1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCHazardRecognizers.h"
20 #include "MCTargetDesc/PPCPredicates.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/MC/MCAsmInfo.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/ADT/STLExtras.h"
32 #define GET_INSTRINFO_CTOR
33 #include "PPCGenInstrInfo.inc"
36 extern cl::opt<bool> DisablePPC32RS;
37 extern cl::opt<bool> DisablePPC64RS;
42 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
43 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
44 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
46 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
47 /// this target when scheduling the DAG.
48 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
49 const TargetMachine *TM,
50 const ScheduleDAG *DAG) const {
51 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
52 if (Directive == PPC::DIR_440) {
53 const InstrItineraryData *II = TM->getInstrItineraryData();
54 return new PPCHazardRecognizer440(II, DAG);
57 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
60 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
61 /// to use for this target when scheduling the DAG.
62 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
63 const InstrItineraryData *II,
64 const ScheduleDAG *DAG) const {
65 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
67 // Most subtargets use a PPC970 recognizer.
68 if (Directive != PPC::DIR_440) {
69 const TargetInstrInfo *TII = TM.getInstrInfo();
70 assert(TII && "No InstrInfo?");
72 return new PPCHazardRecognizer970(*TII);
75 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
77 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
78 int &FrameIndex) const {
79 switch (MI->getOpcode()) {
85 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
86 MI->getOperand(2).isFI()) {
87 FrameIndex = MI->getOperand(2).getIndex();
88 return MI->getOperand(0).getReg();
95 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
96 int &FrameIndex) const {
97 switch (MI->getOpcode()) {
103 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
104 MI->getOperand(2).isFI()) {
105 FrameIndex = MI->getOperand(2).getIndex();
106 return MI->getOperand(0).getReg();
113 // commuteInstruction - We can commute rlwimi instructions, but only if the
114 // rotate amt is zero. We also have to munge the immediates a bit.
116 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
117 MachineFunction &MF = *MI->getParent()->getParent();
119 // Normal instructions can be commuted the obvious way.
120 if (MI->getOpcode() != PPC::RLWIMI)
121 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
123 // Cannot commute if it has a non-zero rotate count.
124 if (MI->getOperand(3).getImm() != 0)
127 // If we have a zero rotate count, we have:
129 // Op0 = (Op1 & ~M) | (Op2 & M)
131 // M = mask((ME+1)&31, (MB-1)&31)
132 // Op0 = (Op2 & ~M) | (Op1 & M)
135 unsigned Reg0 = MI->getOperand(0).getReg();
136 unsigned Reg1 = MI->getOperand(1).getReg();
137 unsigned Reg2 = MI->getOperand(2).getReg();
138 bool Reg1IsKill = MI->getOperand(1).isKill();
139 bool Reg2IsKill = MI->getOperand(2).isKill();
140 bool ChangeReg0 = false;
141 // If machine instrs are no longer in two-address forms, update
142 // destination register as well.
144 // Must be two address instruction!
145 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
146 "Expecting a two-address instruction!");
152 unsigned MB = MI->getOperand(4).getImm();
153 unsigned ME = MI->getOperand(5).getImm();
156 // Create a new instruction.
157 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
158 bool Reg0IsDead = MI->getOperand(0).isDead();
159 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
160 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
161 .addReg(Reg2, getKillRegState(Reg2IsKill))
162 .addReg(Reg1, getKillRegState(Reg1IsKill))
164 .addImm((MB-1) & 31);
168 MI->getOperand(0).setReg(Reg2);
169 MI->getOperand(2).setReg(Reg1);
170 MI->getOperand(1).setReg(Reg2);
171 MI->getOperand(2).setIsKill(Reg1IsKill);
172 MI->getOperand(1).setIsKill(Reg2IsKill);
174 // Swap the mask around.
175 MI->getOperand(4).setImm((ME+1) & 31);
176 MI->getOperand(5).setImm((MB-1) & 31);
180 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
181 MachineBasicBlock::iterator MI) const {
183 BuildMI(MBB, MI, DL, get(PPC::NOP));
188 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
189 MachineBasicBlock *&FBB,
190 SmallVectorImpl<MachineOperand> &Cond,
191 bool AllowModify) const {
192 // If the block has no terminators, it just falls into the block after it.
193 MachineBasicBlock::iterator I = MBB.end();
194 if (I == MBB.begin())
197 while (I->isDebugValue()) {
198 if (I == MBB.begin())
202 if (!isUnpredicatedTerminator(I))
205 // Get the last instruction in the block.
206 MachineInstr *LastInst = I;
208 // If there is only one terminator instruction, process it.
209 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
210 if (LastInst->getOpcode() == PPC::B) {
211 if (!LastInst->getOperand(0).isMBB())
213 TBB = LastInst->getOperand(0).getMBB();
215 } else if (LastInst->getOpcode() == PPC::BCC) {
216 if (!LastInst->getOperand(2).isMBB())
218 // Block ends with fall-through condbranch.
219 TBB = LastInst->getOperand(2).getMBB();
220 Cond.push_back(LastInst->getOperand(0));
221 Cond.push_back(LastInst->getOperand(1));
224 // Otherwise, don't know what this is.
228 // Get the instruction before it if it's a terminator.
229 MachineInstr *SecondLastInst = I;
231 // If there are three terminators, we don't know what sort of block this is.
232 if (SecondLastInst && I != MBB.begin() &&
233 isUnpredicatedTerminator(--I))
236 // If the block ends with PPC::B and PPC:BCC, handle it.
237 if (SecondLastInst->getOpcode() == PPC::BCC &&
238 LastInst->getOpcode() == PPC::B) {
239 if (!SecondLastInst->getOperand(2).isMBB() ||
240 !LastInst->getOperand(0).isMBB())
242 TBB = SecondLastInst->getOperand(2).getMBB();
243 Cond.push_back(SecondLastInst->getOperand(0));
244 Cond.push_back(SecondLastInst->getOperand(1));
245 FBB = LastInst->getOperand(0).getMBB();
249 // If the block ends with two PPC:Bs, handle it. The second one is not
250 // executed, so remove it.
251 if (SecondLastInst->getOpcode() == PPC::B &&
252 LastInst->getOpcode() == PPC::B) {
253 if (!SecondLastInst->getOperand(0).isMBB())
255 TBB = SecondLastInst->getOperand(0).getMBB();
258 I->eraseFromParent();
262 // Otherwise, can't handle this.
266 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
267 MachineBasicBlock::iterator I = MBB.end();
268 if (I == MBB.begin()) return 0;
270 while (I->isDebugValue()) {
271 if (I == MBB.begin())
275 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
278 // Remove the branch.
279 I->eraseFromParent();
283 if (I == MBB.begin()) return 1;
285 if (I->getOpcode() != PPC::BCC)
288 // Remove the branch.
289 I->eraseFromParent();
294 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
295 MachineBasicBlock *FBB,
296 const SmallVectorImpl<MachineOperand> &Cond,
298 // Shouldn't be a fall through.
299 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
300 assert((Cond.size() == 2 || Cond.size() == 0) &&
301 "PPC branch conditions have two components!");
305 if (Cond.empty()) // Unconditional branch
306 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
307 else // Conditional branch
308 BuildMI(&MBB, DL, get(PPC::BCC))
309 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
313 // Two-way Conditional Branch.
314 BuildMI(&MBB, DL, get(PPC::BCC))
315 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
316 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
320 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
321 MachineBasicBlock::iterator I, DebugLoc DL,
322 unsigned DestReg, unsigned SrcReg,
323 bool KillSrc) const {
325 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
327 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
329 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
331 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
333 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
335 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
338 llvm_unreachable("Impossible reg-to-reg copy");
340 const MCInstrDesc &MCID = get(Opc);
341 if (MCID.getNumOperands() == 3)
342 BuildMI(MBB, I, DL, MCID, DestReg)
343 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
345 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
348 // This function returns true if a CR spill is necessary and false otherwise.
350 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
351 unsigned SrcReg, bool isKill,
353 const TargetRegisterClass *RC,
354 SmallVectorImpl<MachineInstr*> &NewMIs) const{
356 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) {
357 if (SrcReg != PPC::LR) {
358 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
360 getKillRegState(isKill)),
363 // FIXME: this spills LR immediately to memory in one step. To do this,
364 // we use R11, which we know cannot be used in the prolog/epilog. This is
366 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
367 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
369 getKillRegState(isKill)),
372 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) {
373 if (SrcReg != PPC::LR8) {
374 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
376 getKillRegState(isKill)),
379 // FIXME: this spills LR immediately to memory in one step. To do this,
380 // we use X11, which we know cannot be used in the prolog/epilog. This is
382 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
383 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
385 getKillRegState(isKill)),
388 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) {
389 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
391 getKillRegState(isKill)),
393 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) {
394 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
396 getKillRegState(isKill)),
398 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) {
399 if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
400 (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
401 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
403 getKillRegState(isKill)),
407 // FIXME: We need a scatch reg here. The trouble with using R0 is that
408 // it's possible for the stack frame to be so big the save location is
409 // out of range of immediate offsets, necessitating another register.
410 // We hack this on Darwin by reserving R2. It's probably broken on Linux
413 bool is64Bit = TM.getSubtargetImpl()->isPPC64();
414 // We need to store the CR in the low 4-bits of the saved value. First,
415 // issue a MFCR to save all of the CRBits.
416 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
417 (is64Bit ? PPC::X2 : PPC::R2) :
418 (is64Bit ? PPC::X0 : PPC::R0);
419 NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::MFCR8pseud :
420 PPC::MFCRpseud), ScratchReg)
421 .addReg(SrcReg, getKillRegState(isKill)));
423 // If the saved register wasn't CR0, shift the bits left so that they are
425 if (SrcReg != PPC::CR0) {
426 unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4;
427 // rlwinm scratch, scratch, ShiftBits, 0, 31.
428 NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::RLWINM8 :
429 PPC::RLWINM), ScratchReg)
430 .addReg(ScratchReg).addImm(ShiftBits)
431 .addImm(0).addImm(31));
434 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(is64Bit ?
435 PPC::STW8 : PPC::STW))
437 getKillRegState(isKill)),
440 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) {
441 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
442 // backend currently only uses CR1EQ as an individual bit, this should
443 // not cause any bug. If we need other uses of CR bits, the following
444 // code may be invalid.
446 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
447 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
449 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
450 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
452 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
453 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
455 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
456 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
458 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
459 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
461 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
462 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
464 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
465 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
467 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
468 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
471 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
472 PPC::CRRCRegisterClass, NewMIs);
474 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) {
475 // We don't have indexed addressing for vector loads. Emit:
479 // FIXME: We use R0 here, because it isn't available for RA.
480 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
482 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
483 .addReg(SrcReg, getKillRegState(isKill))
487 llvm_unreachable("Unknown regclass!");
494 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
495 MachineBasicBlock::iterator MI,
496 unsigned SrcReg, bool isKill, int FrameIdx,
497 const TargetRegisterClass *RC,
498 const TargetRegisterInfo *TRI) const {
499 MachineFunction &MF = *MBB.getParent();
500 SmallVector<MachineInstr*, 4> NewMIs;
502 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
503 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
504 FuncInfo->setSpillsCR();
507 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
508 MBB.insert(MI, NewMIs[i]);
510 const MachineFrameInfo &MFI = *MF.getFrameInfo();
511 MachineMemOperand *MMO =
512 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
513 MachineMemOperand::MOStore,
514 MFI.getObjectSize(FrameIdx),
515 MFI.getObjectAlignment(FrameIdx));
516 NewMIs.back()->addMemOperand(MF, MMO);
520 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
521 unsigned DestReg, int FrameIdx,
522 const TargetRegisterClass *RC,
523 SmallVectorImpl<MachineInstr*> &NewMIs)const{
524 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) {
525 if (DestReg != PPC::LR) {
526 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
527 DestReg), FrameIdx));
529 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
530 PPC::R11), FrameIdx));
531 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
533 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) {
534 if (DestReg != PPC::LR8) {
535 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
538 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
539 PPC::X11), FrameIdx));
540 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::X11));
542 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) {
543 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
545 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) {
546 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
548 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) {
549 if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
550 (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
551 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
552 get(PPC::RESTORE_CR), DestReg)
556 // FIXME: We need a scatch reg here. The trouble with using R0 is that
557 // it's possible for the stack frame to be so big the save location is
558 // out of range of immediate offsets, necessitating another register.
559 // We hack this on Darwin by reserving R2. It's probably broken on Linux
561 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
563 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
564 ScratchReg), FrameIdx));
566 // If the reloaded register isn't CR0, shift the bits right so that they are
567 // in the right CR's slot.
568 if (DestReg != PPC::CR0) {
569 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
570 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
571 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
572 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
576 NewMIs.push_back(BuildMI(MF, DL, get(TM.getSubtargetImpl()->isPPC64() ?
577 PPC::MTCRF8 : PPC::MTCRF), DestReg)
578 .addReg(ScratchReg));
580 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) {
583 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
584 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
586 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
587 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
589 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
590 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
592 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
593 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
595 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
596 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
598 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
599 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
601 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
602 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
604 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
605 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
608 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
609 PPC::CRRCRegisterClass, NewMIs);
611 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) {
612 // We don't have indexed addressing for vector loads. Emit:
616 // FIXME: We use R0 here, because it isn't available for RA.
617 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
619 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
622 llvm_unreachable("Unknown regclass!");
629 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
630 MachineBasicBlock::iterator MI,
631 unsigned DestReg, int FrameIdx,
632 const TargetRegisterClass *RC,
633 const TargetRegisterInfo *TRI) const {
634 MachineFunction &MF = *MBB.getParent();
635 SmallVector<MachineInstr*, 4> NewMIs;
637 if (MI != MBB.end()) DL = MI->getDebugLoc();
638 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs)) {
639 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
640 FuncInfo->setSpillsCR();
642 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
643 MBB.insert(MI, NewMIs[i]);
645 const MachineFrameInfo &MFI = *MF.getFrameInfo();
646 MachineMemOperand *MMO =
647 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
648 MachineMemOperand::MOLoad,
649 MFI.getObjectSize(FrameIdx),
650 MFI.getObjectAlignment(FrameIdx));
651 NewMIs.back()->addMemOperand(MF, MMO);
655 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
656 int FrameIx, uint64_t Offset,
659 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
660 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
665 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
666 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
667 // Leave the CR# the same, but invert the condition.
668 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
672 /// GetInstSize - Return the number of bytes of code the specified
673 /// instruction may be. This returns the maximum number of bytes.
675 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
676 switch (MI->getOpcode()) {
677 case PPC::INLINEASM: { // Inline Asm: Variable size.
678 const MachineFunction *MF = MI->getParent()->getParent();
679 const char *AsmStr = MI->getOperand(0).getSymbolName();
680 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
682 case PPC::PROLOG_LABEL:
688 return 4; // PowerPC instructions are all 4 bytes