1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPredicates.h"
18 #include "PPCGenInstrInfo.inc"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/MC/MCAsmInfo.h"
29 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
30 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
32 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
33 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
34 RI(*TM.getSubtargetImpl(), *this) {}
36 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
39 unsigned& sourceSubIdx,
40 unsigned& destSubIdx) const {
41 sourceSubIdx = destSubIdx = 0; // No sub-registers.
43 unsigned oc = MI.getOpcode();
44 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
45 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
46 assert(MI.getNumOperands() >= 3 &&
47 MI.getOperand(0).isReg() &&
48 MI.getOperand(1).isReg() &&
49 MI.getOperand(2).isReg() &&
50 "invalid PPC OR instruction!");
51 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
52 sourceReg = MI.getOperand(1).getReg();
53 destReg = MI.getOperand(0).getReg();
56 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
57 assert(MI.getNumOperands() >= 3 &&
58 MI.getOperand(0).isReg() &&
59 MI.getOperand(2).isImm() &&
60 "invalid PPC ADDI instruction!");
61 if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
62 sourceReg = MI.getOperand(1).getReg();
63 destReg = MI.getOperand(0).getReg();
66 } else if (oc == PPC::ORI) { // ori r1, r2, 0
67 assert(MI.getNumOperands() >= 3 &&
68 MI.getOperand(0).isReg() &&
69 MI.getOperand(1).isReg() &&
70 MI.getOperand(2).isImm() &&
71 "invalid PPC ORI instruction!");
72 if (MI.getOperand(2).getImm() == 0) {
73 sourceReg = MI.getOperand(1).getReg();
74 destReg = MI.getOperand(0).getReg();
77 } else if (oc == PPC::FMR || oc == PPC::FMRSD) { // fmr r1, r2
78 assert(MI.getNumOperands() >= 2 &&
79 MI.getOperand(0).isReg() &&
80 MI.getOperand(1).isReg() &&
81 "invalid PPC FMR instruction");
82 sourceReg = MI.getOperand(1).getReg();
83 destReg = MI.getOperand(0).getReg();
85 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
86 assert(MI.getNumOperands() >= 2 &&
87 MI.getOperand(0).isReg() &&
88 MI.getOperand(1).isReg() &&
89 "invalid PPC MCRF instruction");
90 sourceReg = MI.getOperand(1).getReg();
91 destReg = MI.getOperand(0).getReg();
97 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
98 int &FrameIndex) const {
99 switch (MI->getOpcode()) {
105 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
106 MI->getOperand(2).isFI()) {
107 FrameIndex = MI->getOperand(2).getIndex();
108 return MI->getOperand(0).getReg();
115 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
116 int &FrameIndex) const {
117 switch (MI->getOpcode()) {
123 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
124 MI->getOperand(2).isFI()) {
125 FrameIndex = MI->getOperand(2).getIndex();
126 return MI->getOperand(0).getReg();
133 // commuteInstruction - We can commute rlwimi instructions, but only if the
134 // rotate amt is zero. We also have to munge the immediates a bit.
136 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
137 MachineFunction &MF = *MI->getParent()->getParent();
139 // Normal instructions can be commuted the obvious way.
140 if (MI->getOpcode() != PPC::RLWIMI)
141 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
143 // Cannot commute if it has a non-zero rotate count.
144 if (MI->getOperand(3).getImm() != 0)
147 // If we have a zero rotate count, we have:
149 // Op0 = (Op1 & ~M) | (Op2 & M)
151 // M = mask((ME+1)&31, (MB-1)&31)
152 // Op0 = (Op2 & ~M) | (Op1 & M)
155 unsigned Reg0 = MI->getOperand(0).getReg();
156 unsigned Reg1 = MI->getOperand(1).getReg();
157 unsigned Reg2 = MI->getOperand(2).getReg();
158 bool Reg1IsKill = MI->getOperand(1).isKill();
159 bool Reg2IsKill = MI->getOperand(2).isKill();
160 bool ChangeReg0 = false;
161 // If machine instrs are no longer in two-address forms, update
162 // destination register as well.
164 // Must be two address instruction!
165 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
166 "Expecting a two-address instruction!");
172 unsigned MB = MI->getOperand(4).getImm();
173 unsigned ME = MI->getOperand(5).getImm();
176 // Create a new instruction.
177 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
178 bool Reg0IsDead = MI->getOperand(0).isDead();
179 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
180 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
181 .addReg(Reg2, getKillRegState(Reg2IsKill))
182 .addReg(Reg1, getKillRegState(Reg1IsKill))
184 .addImm((MB-1) & 31);
188 MI->getOperand(0).setReg(Reg2);
189 MI->getOperand(2).setReg(Reg1);
190 MI->getOperand(1).setReg(Reg2);
191 MI->getOperand(2).setIsKill(Reg1IsKill);
192 MI->getOperand(1).setIsKill(Reg2IsKill);
194 // Swap the mask around.
195 MI->getOperand(4).setImm((ME+1) & 31);
196 MI->getOperand(5).setImm((MB-1) & 31);
200 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
201 MachineBasicBlock::iterator MI) const {
202 DebugLoc DL = DebugLoc::getUnknownLoc();
203 if (MI != MBB.end()) DL = MI->getDebugLoc();
205 BuildMI(MBB, MI, DL, get(PPC::NOP));
210 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
211 MachineBasicBlock *&FBB,
212 SmallVectorImpl<MachineOperand> &Cond,
213 bool AllowModify) const {
214 // If the block has no terminators, it just falls into the block after it.
215 MachineBasicBlock::iterator I = MBB.end();
216 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
219 // Get the last instruction in the block.
220 MachineInstr *LastInst = I;
222 // If there is only one terminator instruction, process it.
223 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
224 if (LastInst->getOpcode() == PPC::B) {
225 if (!LastInst->getOperand(0).isMBB())
227 TBB = LastInst->getOperand(0).getMBB();
229 } else if (LastInst->getOpcode() == PPC::BCC) {
230 if (!LastInst->getOperand(2).isMBB())
232 // Block ends with fall-through condbranch.
233 TBB = LastInst->getOperand(2).getMBB();
234 Cond.push_back(LastInst->getOperand(0));
235 Cond.push_back(LastInst->getOperand(1));
238 // Otherwise, don't know what this is.
242 // Get the instruction before it if it's a terminator.
243 MachineInstr *SecondLastInst = I;
245 // If there are three terminators, we don't know what sort of block this is.
246 if (SecondLastInst && I != MBB.begin() &&
247 isUnpredicatedTerminator(--I))
250 // If the block ends with PPC::B and PPC:BCC, handle it.
251 if (SecondLastInst->getOpcode() == PPC::BCC &&
252 LastInst->getOpcode() == PPC::B) {
253 if (!SecondLastInst->getOperand(2).isMBB() ||
254 !LastInst->getOperand(0).isMBB())
256 TBB = SecondLastInst->getOperand(2).getMBB();
257 Cond.push_back(SecondLastInst->getOperand(0));
258 Cond.push_back(SecondLastInst->getOperand(1));
259 FBB = LastInst->getOperand(0).getMBB();
263 // If the block ends with two PPC:Bs, handle it. The second one is not
264 // executed, so remove it.
265 if (SecondLastInst->getOpcode() == PPC::B &&
266 LastInst->getOpcode() == PPC::B) {
267 if (!SecondLastInst->getOperand(0).isMBB())
269 TBB = SecondLastInst->getOperand(0).getMBB();
272 I->eraseFromParent();
276 // Otherwise, can't handle this.
280 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
281 MachineBasicBlock::iterator I = MBB.end();
282 if (I == MBB.begin()) return 0;
284 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
287 // Remove the branch.
288 I->eraseFromParent();
292 if (I == MBB.begin()) return 1;
294 if (I->getOpcode() != PPC::BCC)
297 // Remove the branch.
298 I->eraseFromParent();
303 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
304 MachineBasicBlock *FBB,
305 const SmallVectorImpl<MachineOperand> &Cond) const {
306 // FIXME this should probably have a DebugLoc argument
307 DebugLoc dl = DebugLoc::getUnknownLoc();
308 // Shouldn't be a fall through.
309 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
310 assert((Cond.size() == 2 || Cond.size() == 0) &&
311 "PPC branch conditions have two components!");
315 if (Cond.empty()) // Unconditional branch
316 BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB);
317 else // Conditional branch
318 BuildMI(&MBB, dl, get(PPC::BCC))
319 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
323 // Two-way Conditional Branch.
324 BuildMI(&MBB, dl, get(PPC::BCC))
325 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
326 BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB);
330 bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
331 MachineBasicBlock::iterator MI,
332 unsigned DestReg, unsigned SrcReg,
333 const TargetRegisterClass *DestRC,
334 const TargetRegisterClass *SrcRC) const {
335 if (DestRC != SrcRC) {
336 // Not yet supported!
340 DebugLoc DL = DebugLoc::getUnknownLoc();
341 if (MI != MBB.end()) DL = MI->getDebugLoc();
343 if (DestRC == PPC::GPRCRegisterClass) {
344 BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
345 } else if (DestRC == PPC::G8RCRegisterClass) {
346 BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
347 } else if (DestRC == PPC::F4RCRegisterClass ||
348 DestRC == PPC::F8RCRegisterClass) {
349 BuildMI(MBB, MI, DL, get(PPC::FMR), DestReg).addReg(SrcReg);
350 } else if (DestRC == PPC::CRRCRegisterClass) {
351 BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg);
352 } else if (DestRC == PPC::VRRCRegisterClass) {
353 BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
354 } else if (DestRC == PPC::CRBITRCRegisterClass) {
355 BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
357 // Attempt to copy register that is not GPR or FPR
365 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
366 unsigned SrcReg, bool isKill,
368 const TargetRegisterClass *RC,
369 SmallVectorImpl<MachineInstr*> &NewMIs) const{
370 DebugLoc DL = DebugLoc::getUnknownLoc();
371 if (RC == PPC::GPRCRegisterClass) {
372 if (SrcReg != PPC::LR) {
373 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
375 getKillRegState(isKill)),
378 // FIXME: this spills LR immediately to memory in one step. To do this,
379 // we use R11, which we know cannot be used in the prolog/epilog. This is
381 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
382 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
384 getKillRegState(isKill)),
387 } else if (RC == PPC::G8RCRegisterClass) {
388 if (SrcReg != PPC::LR8) {
389 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
391 getKillRegState(isKill)),
394 // FIXME: this spills LR immediately to memory in one step. To do this,
395 // we use R11, which we know cannot be used in the prolog/epilog. This is
397 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
398 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
400 getKillRegState(isKill)),
403 } else if (RC == PPC::F8RCRegisterClass) {
404 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
406 getKillRegState(isKill)),
408 } else if (RC == PPC::F4RCRegisterClass) {
409 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
411 getKillRegState(isKill)),
413 } else if (RC == PPC::CRRCRegisterClass) {
414 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
415 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
416 // FIXME (64-bit): Enable
417 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
419 getKillRegState(isKill)),
423 // FIXME: We need a scatch reg here. The trouble with using R0 is that
424 // it's possible for the stack frame to be so big the save location is
425 // out of range of immediate offsets, necessitating another register.
426 // We hack this on Darwin by reserving R2. It's probably broken on Linux
429 // We need to store the CR in the low 4-bits of the saved value. First,
430 // issue a MFCR to save all of the CRBits.
431 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
433 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), ScratchReg));
435 // If the saved register wasn't CR0, shift the bits left so that they are
437 if (SrcReg != PPC::CR0) {
438 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
439 // rlwinm scratch, scratch, ShiftBits, 0, 31.
440 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
441 .addReg(ScratchReg).addImm(ShiftBits)
442 .addImm(0).addImm(31));
445 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
447 getKillRegState(isKill)),
450 } else if (RC == PPC::CRBITRCRegisterClass) {
451 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
452 // backend currently only uses CR1EQ as an individual bit, this should
453 // not cause any bug. If we need other uses of CR bits, the following
454 // code may be invalid.
456 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
457 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
459 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
460 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
462 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
463 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
465 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
466 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
468 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
469 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
471 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
472 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
474 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
475 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
477 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
478 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
481 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
482 PPC::CRRCRegisterClass, NewMIs);
484 } else if (RC == PPC::VRRCRegisterClass) {
485 // We don't have indexed addressing for vector loads. Emit:
489 // FIXME: We use R0 here, because it isn't available for RA.
490 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
492 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
493 .addReg(SrcReg, getKillRegState(isKill))
497 llvm_unreachable("Unknown regclass!");
504 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
505 MachineBasicBlock::iterator MI,
506 unsigned SrcReg, bool isKill, int FrameIdx,
507 const TargetRegisterClass *RC) const {
508 MachineFunction &MF = *MBB.getParent();
509 SmallVector<MachineInstr*, 4> NewMIs;
511 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
512 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
513 FuncInfo->setSpillsCR();
516 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
517 MBB.insert(MI, NewMIs[i]);
521 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
522 unsigned DestReg, int FrameIdx,
523 const TargetRegisterClass *RC,
524 SmallVectorImpl<MachineInstr*> &NewMIs)const{
525 if (RC == PPC::GPRCRegisterClass) {
526 if (DestReg != PPC::LR) {
527 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
528 DestReg), FrameIdx));
530 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
531 PPC::R11), FrameIdx));
532 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
534 } else if (RC == PPC::G8RCRegisterClass) {
535 if (DestReg != PPC::LR8) {
536 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
539 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
540 PPC::R11), FrameIdx));
541 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
543 } else if (RC == PPC::F8RCRegisterClass) {
544 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
546 } else if (RC == PPC::F4RCRegisterClass) {
547 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
549 } else if (RC == PPC::CRRCRegisterClass) {
550 // FIXME: We need a scatch reg here. The trouble with using R0 is that
551 // it's possible for the stack frame to be so big the save location is
552 // out of range of immediate offsets, necessitating another register.
553 // We hack this on Darwin by reserving R2. It's probably broken on Linux
555 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
557 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
558 ScratchReg), FrameIdx));
560 // If the reloaded register isn't CR0, shift the bits right so that they are
561 // in the right CR's slot.
562 if (DestReg != PPC::CR0) {
563 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
564 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
565 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
566 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
570 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg)
571 .addReg(ScratchReg));
572 } else if (RC == PPC::CRBITRCRegisterClass) {
575 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
576 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
578 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
579 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
581 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
582 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
584 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
585 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
587 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
588 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
590 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
591 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
593 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
594 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
596 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
597 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
600 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
601 PPC::CRRCRegisterClass, NewMIs);
603 } else if (RC == PPC::VRRCRegisterClass) {
604 // We don't have indexed addressing for vector loads. Emit:
608 // FIXME: We use R0 here, because it isn't available for RA.
609 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
611 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
614 llvm_unreachable("Unknown regclass!");
619 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
620 MachineBasicBlock::iterator MI,
621 unsigned DestReg, int FrameIdx,
622 const TargetRegisterClass *RC) const {
623 MachineFunction &MF = *MBB.getParent();
624 SmallVector<MachineInstr*, 4> NewMIs;
625 DebugLoc DL = DebugLoc::getUnknownLoc();
626 if (MI != MBB.end()) DL = MI->getDebugLoc();
627 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
628 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
629 MBB.insert(MI, NewMIs[i]);
632 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
633 /// copy instructions, turning them into load/store instructions.
634 MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
636 const SmallVectorImpl<unsigned> &Ops,
637 int FrameIndex) const {
638 if (Ops.size() != 1) return NULL;
640 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
641 // it takes more than one instruction to store it.
642 unsigned Opc = MI->getOpcode();
643 unsigned OpNum = Ops[0];
645 MachineInstr *NewMI = NULL;
646 if ((Opc == PPC::OR &&
647 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
648 if (OpNum == 0) { // move -> store
649 unsigned InReg = MI->getOperand(1).getReg();
650 bool isKill = MI->getOperand(1).isKill();
651 bool isUndef = MI->getOperand(1).isUndef();
652 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
654 getKillRegState(isKill) |
655 getUndefRegState(isUndef)),
657 } else { // move -> load
658 unsigned OutReg = MI->getOperand(0).getReg();
659 bool isDead = MI->getOperand(0).isDead();
660 bool isUndef = MI->getOperand(0).isUndef();
661 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
664 getDeadRegState(isDead) |
665 getUndefRegState(isUndef)),
668 } else if ((Opc == PPC::OR8 &&
669 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
670 if (OpNum == 0) { // move -> store
671 unsigned InReg = MI->getOperand(1).getReg();
672 bool isKill = MI->getOperand(1).isKill();
673 bool isUndef = MI->getOperand(1).isUndef();
674 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
676 getKillRegState(isKill) |
677 getUndefRegState(isUndef)),
679 } else { // move -> load
680 unsigned OutReg = MI->getOperand(0).getReg();
681 bool isDead = MI->getOperand(0).isDead();
682 bool isUndef = MI->getOperand(0).isUndef();
683 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
686 getDeadRegState(isDead) |
687 getUndefRegState(isUndef)),
690 } else if (Opc == PPC::FMR || Opc == PPC::FMRSD) {
691 // The register may be F4RC or F8RC, and that determines the memory op.
692 unsigned OrigReg = MI->getOperand(OpNum).getReg();
693 // We cannot tell the register class from a physreg alone.
694 if (TargetRegisterInfo::isPhysicalRegister(OrigReg))
696 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(OrigReg);
697 const bool is64 = RC == PPC::F8RCRegisterClass;
699 if (OpNum == 0) { // move -> store
700 unsigned InReg = MI->getOperand(1).getReg();
701 bool isKill = MI->getOperand(1).isKill();
702 bool isUndef = MI->getOperand(1).isUndef();
703 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(),
704 get(is64 ? PPC::STFD : PPC::STFS))
706 getKillRegState(isKill) |
707 getUndefRegState(isUndef)),
709 } else { // move -> load
710 unsigned OutReg = MI->getOperand(0).getReg();
711 bool isDead = MI->getOperand(0).isDead();
712 bool isUndef = MI->getOperand(0).isUndef();
713 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(),
714 get(is64 ? PPC::LFD : PPC::LFS))
717 getDeadRegState(isDead) |
718 getUndefRegState(isUndef)),
726 bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
727 const SmallVectorImpl<unsigned> &Ops) const {
728 if (Ops.size() != 1) return false;
730 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
731 // it takes more than one instruction to store it.
732 unsigned Opc = MI->getOpcode();
734 if ((Opc == PPC::OR &&
735 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
737 else if ((Opc == PPC::OR8 &&
738 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
740 else if (Opc == PPC::FMR || Opc == PPC::FMRSD)
748 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
749 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
750 // Leave the CR# the same, but invert the condition.
751 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
755 /// GetInstSize - Return the number of bytes of code the specified
756 /// instruction may be. This returns the maximum number of bytes.
758 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
759 switch (MI->getOpcode()) {
760 case PPC::INLINEASM: { // Inline Asm: Variable size.
761 const MachineFunction *MF = MI->getParent()->getParent();
762 const char *AsmStr = MI->getOperand(0).getSymbolName();
763 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
770 return 4; // PowerPC instructions are all 4 bytes