1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/PseudoSourceValue.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/TargetRegistry.h"
33 #include "llvm/Support/raw_ostream.h"
35 #define GET_INSTRMAP_INFO
36 #define GET_INSTRINFO_CTOR_DTOR
37 #include "PPCGenInstrInfo.inc"
42 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
43 cl::desc("Disable analysis for CTR loops"));
45 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
46 cl::desc("Disable compare instruction optimization"), cl::Hidden);
48 // Pin the vtable to this file.
49 void PPCInstrInfo::anchor() {}
51 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
52 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
53 TM(tm), RI(*TM.getSubtargetImpl()) {}
55 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
56 /// this target when scheduling the DAG.
57 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
58 const TargetMachine *TM,
59 const ScheduleDAG *DAG) const {
60 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
61 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
62 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
63 const InstrItineraryData *II = TM->getInstrItineraryData();
64 return new ScoreboardHazardRecognizer(II, DAG);
67 return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
70 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
71 /// to use for this target when scheduling the DAG.
72 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
73 const InstrItineraryData *II,
74 const ScheduleDAG *DAG) const {
75 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
77 if (Directive == PPC::DIR_PWR7)
78 return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
80 // Most subtargets use a PPC970 recognizer.
81 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
82 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
83 assert(TM.getInstrInfo() && "No InstrInfo?");
85 return new PPCHazardRecognizer970(TM);
88 return new ScoreboardHazardRecognizer(II, DAG);
92 int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
93 const MachineInstr *DefMI, unsigned DefIdx,
94 const MachineInstr *UseMI,
95 unsigned UseIdx) const {
96 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
99 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
100 unsigned Reg = DefMO.getReg();
102 const TargetRegisterInfo *TRI = &getRegisterInfo();
104 if (TRI->isVirtualRegister(Reg)) {
105 const MachineRegisterInfo *MRI =
106 &DefMI->getParent()->getParent()->getRegInfo();
107 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
108 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
110 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
111 PPC::CRBITRCRegClass.contains(Reg);
114 if (UseMI->isBranch() && IsRegCR) {
116 Latency = getInstrLatency(ItinData, DefMI);
118 // On some cores, there is an additional delay between writing to a condition
119 // register, and using it from a branch.
120 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
141 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
142 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
143 unsigned &SrcReg, unsigned &DstReg,
144 unsigned &SubIdx) const {
145 switch (MI.getOpcode()) {
146 default: return false;
148 case PPC::EXTSW_32_64:
149 SrcReg = MI.getOperand(1).getReg();
150 DstReg = MI.getOperand(0).getReg();
151 SubIdx = PPC::sub_32;
156 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
157 int &FrameIndex) const {
158 // Note: This list must be kept consistent with LoadRegFromStackSlot.
159 switch (MI->getOpcode()) {
165 case PPC::RESTORE_CR:
167 case PPC::RESTORE_VRSAVE:
168 // Check for the operands added by addFrameReference (the immediate is the
169 // offset which defaults to 0).
170 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
171 MI->getOperand(2).isFI()) {
172 FrameIndex = MI->getOperand(2).getIndex();
173 return MI->getOperand(0).getReg();
180 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
181 int &FrameIndex) const {
182 // Note: This list must be kept consistent with StoreRegToStackSlot.
183 switch (MI->getOpcode()) {
191 case PPC::SPILL_VRSAVE:
192 // Check for the operands added by addFrameReference (the immediate is the
193 // offset which defaults to 0).
194 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
195 MI->getOperand(2).isFI()) {
196 FrameIndex = MI->getOperand(2).getIndex();
197 return MI->getOperand(0).getReg();
204 // commuteInstruction - We can commute rlwimi instructions, but only if the
205 // rotate amt is zero. We also have to munge the immediates a bit.
207 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
208 MachineFunction &MF = *MI->getParent()->getParent();
210 // Normal instructions can be commuted the obvious way.
211 if (MI->getOpcode() != PPC::RLWIMI &&
212 MI->getOpcode() != PPC::RLWIMIo)
213 return TargetInstrInfo::commuteInstruction(MI, NewMI);
215 // Cannot commute if it has a non-zero rotate count.
216 if (MI->getOperand(3).getImm() != 0)
219 // If we have a zero rotate count, we have:
221 // Op0 = (Op1 & ~M) | (Op2 & M)
223 // M = mask((ME+1)&31, (MB-1)&31)
224 // Op0 = (Op2 & ~M) | (Op1 & M)
227 unsigned Reg0 = MI->getOperand(0).getReg();
228 unsigned Reg1 = MI->getOperand(1).getReg();
229 unsigned Reg2 = MI->getOperand(2).getReg();
230 unsigned SubReg1 = MI->getOperand(1).getSubReg();
231 unsigned SubReg2 = MI->getOperand(2).getSubReg();
232 bool Reg1IsKill = MI->getOperand(1).isKill();
233 bool Reg2IsKill = MI->getOperand(2).isKill();
234 bool ChangeReg0 = false;
235 // If machine instrs are no longer in two-address forms, update
236 // destination register as well.
238 // Must be two address instruction!
239 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
240 "Expecting a two-address instruction!");
241 assert(MI->getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
247 unsigned MB = MI->getOperand(4).getImm();
248 unsigned ME = MI->getOperand(5).getImm();
251 // Create a new instruction.
252 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
253 bool Reg0IsDead = MI->getOperand(0).isDead();
254 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
255 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
256 .addReg(Reg2, getKillRegState(Reg2IsKill))
257 .addReg(Reg1, getKillRegState(Reg1IsKill))
259 .addImm((MB-1) & 31);
263 MI->getOperand(0).setReg(Reg2);
264 MI->getOperand(0).setSubReg(SubReg2);
266 MI->getOperand(2).setReg(Reg1);
267 MI->getOperand(1).setReg(Reg2);
268 MI->getOperand(2).setSubReg(SubReg1);
269 MI->getOperand(1).setSubReg(SubReg2);
270 MI->getOperand(2).setIsKill(Reg1IsKill);
271 MI->getOperand(1).setIsKill(Reg2IsKill);
273 // Swap the mask around.
274 MI->getOperand(4).setImm((ME+1) & 31);
275 MI->getOperand(5).setImm((MB-1) & 31);
279 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
280 MachineBasicBlock::iterator MI) const {
281 // This function is used for scheduling, and the nop wanted here is the type
282 // that terminates dispatch groups on the POWER cores.
283 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
286 default: Opcode = PPC::NOP; break;
287 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
288 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
292 BuildMI(MBB, MI, DL, get(Opcode));
296 // Note: If the condition register is set to CTR or CTR8 then this is a
297 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
298 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
299 MachineBasicBlock *&FBB,
300 SmallVectorImpl<MachineOperand> &Cond,
301 bool AllowModify) const {
302 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
304 // If the block has no terminators, it just falls into the block after it.
305 MachineBasicBlock::iterator I = MBB.end();
306 if (I == MBB.begin())
309 while (I->isDebugValue()) {
310 if (I == MBB.begin())
314 if (!isUnpredicatedTerminator(I))
317 // Get the last instruction in the block.
318 MachineInstr *LastInst = I;
320 // If there is only one terminator instruction, process it.
321 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
322 if (LastInst->getOpcode() == PPC::B) {
323 if (!LastInst->getOperand(0).isMBB())
325 TBB = LastInst->getOperand(0).getMBB();
327 } else if (LastInst->getOpcode() == PPC::BCC) {
328 if (!LastInst->getOperand(2).isMBB())
330 // Block ends with fall-through condbranch.
331 TBB = LastInst->getOperand(2).getMBB();
332 Cond.push_back(LastInst->getOperand(0));
333 Cond.push_back(LastInst->getOperand(1));
335 } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
336 LastInst->getOpcode() == PPC::BDNZ) {
337 if (!LastInst->getOperand(0).isMBB())
339 if (DisableCTRLoopAnal)
341 TBB = LastInst->getOperand(0).getMBB();
342 Cond.push_back(MachineOperand::CreateImm(1));
343 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
346 } else if (LastInst->getOpcode() == PPC::BDZ8 ||
347 LastInst->getOpcode() == PPC::BDZ) {
348 if (!LastInst->getOperand(0).isMBB())
350 if (DisableCTRLoopAnal)
352 TBB = LastInst->getOperand(0).getMBB();
353 Cond.push_back(MachineOperand::CreateImm(0));
354 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
359 // Otherwise, don't know what this is.
363 // Get the instruction before it if it's a terminator.
364 MachineInstr *SecondLastInst = I;
366 // If there are three terminators, we don't know what sort of block this is.
367 if (SecondLastInst && I != MBB.begin() &&
368 isUnpredicatedTerminator(--I))
371 // If the block ends with PPC::B and PPC:BCC, handle it.
372 if (SecondLastInst->getOpcode() == PPC::BCC &&
373 LastInst->getOpcode() == PPC::B) {
374 if (!SecondLastInst->getOperand(2).isMBB() ||
375 !LastInst->getOperand(0).isMBB())
377 TBB = SecondLastInst->getOperand(2).getMBB();
378 Cond.push_back(SecondLastInst->getOperand(0));
379 Cond.push_back(SecondLastInst->getOperand(1));
380 FBB = LastInst->getOperand(0).getMBB();
382 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
383 SecondLastInst->getOpcode() == PPC::BDNZ) &&
384 LastInst->getOpcode() == PPC::B) {
385 if (!SecondLastInst->getOperand(0).isMBB() ||
386 !LastInst->getOperand(0).isMBB())
388 if (DisableCTRLoopAnal)
390 TBB = SecondLastInst->getOperand(0).getMBB();
391 Cond.push_back(MachineOperand::CreateImm(1));
392 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
394 FBB = LastInst->getOperand(0).getMBB();
396 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
397 SecondLastInst->getOpcode() == PPC::BDZ) &&
398 LastInst->getOpcode() == PPC::B) {
399 if (!SecondLastInst->getOperand(0).isMBB() ||
400 !LastInst->getOperand(0).isMBB())
402 if (DisableCTRLoopAnal)
404 TBB = SecondLastInst->getOperand(0).getMBB();
405 Cond.push_back(MachineOperand::CreateImm(0));
406 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
408 FBB = LastInst->getOperand(0).getMBB();
412 // If the block ends with two PPC:Bs, handle it. The second one is not
413 // executed, so remove it.
414 if (SecondLastInst->getOpcode() == PPC::B &&
415 LastInst->getOpcode() == PPC::B) {
416 if (!SecondLastInst->getOperand(0).isMBB())
418 TBB = SecondLastInst->getOperand(0).getMBB();
421 I->eraseFromParent();
425 // Otherwise, can't handle this.
429 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
430 MachineBasicBlock::iterator I = MBB.end();
431 if (I == MBB.begin()) return 0;
433 while (I->isDebugValue()) {
434 if (I == MBB.begin())
438 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
439 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
440 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
443 // Remove the branch.
444 I->eraseFromParent();
448 if (I == MBB.begin()) return 1;
450 if (I->getOpcode() != PPC::BCC &&
451 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
452 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
455 // Remove the branch.
456 I->eraseFromParent();
461 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
462 MachineBasicBlock *FBB,
463 const SmallVectorImpl<MachineOperand> &Cond,
465 // Shouldn't be a fall through.
466 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
467 assert((Cond.size() == 2 || Cond.size() == 0) &&
468 "PPC branch conditions have two components!");
470 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
474 if (Cond.empty()) // Unconditional branch
475 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
476 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
477 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
478 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
479 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
480 else // Conditional branch
481 BuildMI(&MBB, DL, get(PPC::BCC))
482 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
486 // Two-way Conditional Branch.
487 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
488 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
489 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
490 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
492 BuildMI(&MBB, DL, get(PPC::BCC))
493 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
494 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
499 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
500 const SmallVectorImpl<MachineOperand> &Cond,
501 unsigned TrueReg, unsigned FalseReg,
502 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
503 if (!TM.getSubtargetImpl()->hasISEL())
506 if (Cond.size() != 2)
509 // If this is really a bdnz-like condition, then it cannot be turned into a
511 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
514 // Check register classes.
515 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
516 const TargetRegisterClass *RC =
517 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
521 // isel is for regular integer GPRs only.
522 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
523 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
524 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
525 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
528 // FIXME: These numbers are for the A2, how well they work for other cores is
529 // an open question. On the A2, the isel instruction has a 2-cycle latency
530 // but single-cycle throughput. These numbers are used in combination with
531 // the MispredictPenalty setting from the active SchedMachineModel.
539 void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
540 MachineBasicBlock::iterator MI, DebugLoc dl,
542 const SmallVectorImpl<MachineOperand> &Cond,
543 unsigned TrueReg, unsigned FalseReg) const {
544 assert(Cond.size() == 2 &&
545 "PPC branch conditions have two components!");
547 assert(TM.getSubtargetImpl()->hasISEL() &&
548 "Cannot insert select on target without ISEL support");
550 // Get the register classes.
551 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
552 const TargetRegisterClass *RC =
553 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
554 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
556 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
557 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
559 PPC::GPRCRegClass.hasSubClassEq(RC) ||
560 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
561 "isel is for regular integer GPRs only");
563 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
564 unsigned SelectPred = Cond[0].getImm();
568 switch (SelectPred) {
569 default: llvm_unreachable("invalid predicate for isel");
570 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
571 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
572 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
573 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
574 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
575 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
576 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
577 case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
580 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
581 SecondReg = SwapOps ? TrueReg : FalseReg;
583 // The first input register of isel cannot be r0. If it is a member
584 // of a register class that can be r0, then copy it first (the
585 // register allocator should eliminate the copy).
586 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
587 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
588 const TargetRegisterClass *FirstRC =
589 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
590 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
591 unsigned OldFirstReg = FirstReg;
592 FirstReg = MRI.createVirtualRegister(FirstRC);
593 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
594 .addReg(OldFirstReg);
597 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
598 .addReg(FirstReg).addReg(SecondReg)
599 .addReg(Cond[1].getReg(), 0, SubIdx);
602 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
603 MachineBasicBlock::iterator I, DebugLoc DL,
604 unsigned DestReg, unsigned SrcReg,
605 bool KillSrc) const {
607 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
609 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
611 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
613 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
615 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
617 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
620 llvm_unreachable("Impossible reg-to-reg copy");
622 const MCInstrDesc &MCID = get(Opc);
623 if (MCID.getNumOperands() == 3)
624 BuildMI(MBB, I, DL, MCID, DestReg)
625 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
627 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
630 // This function returns true if a CR spill is necessary and false otherwise.
632 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
633 unsigned SrcReg, bool isKill,
635 const TargetRegisterClass *RC,
636 SmallVectorImpl<MachineInstr*> &NewMIs,
637 bool &NonRI, bool &SpillsVRS) const{
638 // Note: If additional store instructions are added here,
639 // update isStoreToStackSlot.
642 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
643 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
644 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
646 getKillRegState(isKill)),
648 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
649 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
650 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
652 getKillRegState(isKill)),
654 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
655 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
657 getKillRegState(isKill)),
659 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
660 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
662 getKillRegState(isKill)),
664 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
665 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
667 getKillRegState(isKill)),
670 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
671 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
672 // backend currently only uses CR1EQ as an individual bit, this should
673 // not cause any bug. If we need other uses of CR bits, the following
674 // code may be invalid.
676 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
677 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
679 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
680 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
682 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
683 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
685 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
686 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
688 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
689 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
691 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
692 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
694 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
695 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
697 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
698 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
701 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
702 &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
704 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
705 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
707 getKillRegState(isKill)),
710 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
711 assert(TM.getSubtargetImpl()->isDarwin() &&
712 "VRSAVE only needs spill/restore on Darwin");
713 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
715 getKillRegState(isKill)),
719 llvm_unreachable("Unknown regclass!");
726 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
727 MachineBasicBlock::iterator MI,
728 unsigned SrcReg, bool isKill, int FrameIdx,
729 const TargetRegisterClass *RC,
730 const TargetRegisterInfo *TRI) const {
731 MachineFunction &MF = *MBB.getParent();
732 SmallVector<MachineInstr*, 4> NewMIs;
734 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
735 FuncInfo->setHasSpills();
737 bool NonRI = false, SpillsVRS = false;
738 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
740 FuncInfo->setSpillsCR();
743 FuncInfo->setSpillsVRSAVE();
746 FuncInfo->setHasNonRISpills();
748 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
749 MBB.insert(MI, NewMIs[i]);
751 const MachineFrameInfo &MFI = *MF.getFrameInfo();
752 MachineMemOperand *MMO =
753 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
754 MachineMemOperand::MOStore,
755 MFI.getObjectSize(FrameIdx),
756 MFI.getObjectAlignment(FrameIdx));
757 NewMIs.back()->addMemOperand(MF, MMO);
761 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
762 unsigned DestReg, int FrameIdx,
763 const TargetRegisterClass *RC,
764 SmallVectorImpl<MachineInstr*> &NewMIs,
765 bool &NonRI, bool &SpillsVRS) const{
766 // Note: If additional load instructions are added here,
767 // update isLoadFromStackSlot.
769 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
770 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
771 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
772 DestReg), FrameIdx));
773 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
774 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
775 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
777 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
778 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
780 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
781 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
783 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
784 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
785 get(PPC::RESTORE_CR), DestReg),
788 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
791 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
792 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
794 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
795 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
797 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
798 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
800 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
801 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
803 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
804 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
806 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
807 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
809 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
810 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
812 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
813 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
816 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
817 &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
819 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
820 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
823 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
824 assert(TM.getSubtargetImpl()->isDarwin() &&
825 "VRSAVE only needs spill/restore on Darwin");
826 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
827 get(PPC::RESTORE_VRSAVE),
832 llvm_unreachable("Unknown regclass!");
839 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
840 MachineBasicBlock::iterator MI,
841 unsigned DestReg, int FrameIdx,
842 const TargetRegisterClass *RC,
843 const TargetRegisterInfo *TRI) const {
844 MachineFunction &MF = *MBB.getParent();
845 SmallVector<MachineInstr*, 4> NewMIs;
847 if (MI != MBB.end()) DL = MI->getDebugLoc();
849 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
850 FuncInfo->setHasSpills();
852 bool NonRI = false, SpillsVRS = false;
853 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
855 FuncInfo->setSpillsCR();
858 FuncInfo->setSpillsVRSAVE();
861 FuncInfo->setHasNonRISpills();
863 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
864 MBB.insert(MI, NewMIs[i]);
866 const MachineFrameInfo &MFI = *MF.getFrameInfo();
867 MachineMemOperand *MMO =
868 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
869 MachineMemOperand::MOLoad,
870 MFI.getObjectSize(FrameIdx),
871 MFI.getObjectAlignment(FrameIdx));
872 NewMIs.back()->addMemOperand(MF, MMO);
876 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
877 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
878 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
879 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
881 // Leave the CR# the same, but invert the condition.
882 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
886 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
887 unsigned Reg, MachineRegisterInfo *MRI) const {
888 // For some instructions, it is legal to fold ZERO into the RA register field.
889 // A zero immediate should always be loaded with a single li.
890 unsigned DefOpc = DefMI->getOpcode();
891 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
893 if (!DefMI->getOperand(1).isImm())
895 if (DefMI->getOperand(1).getImm() != 0)
898 // Note that we cannot here invert the arguments of an isel in order to fold
899 // a ZERO into what is presented as the second argument. All we have here
900 // is the condition bit, and that might come from a CR-logical bit operation.
902 const MCInstrDesc &UseMCID = UseMI->getDesc();
904 // Only fold into real machine instructions.
905 if (UseMCID.isPseudo())
909 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
910 if (UseMI->getOperand(UseIdx).isReg() &&
911 UseMI->getOperand(UseIdx).getReg() == Reg)
914 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
915 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
917 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
919 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
920 // register (which might also be specified as a pointer class kind).
921 if (UseInfo->isLookupPtrRegClass()) {
922 if (UseInfo->RegClass /* Kind */ != 1)
925 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
926 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
930 // Make sure this is not tied to an output register (or otherwise
931 // constrained). This is true for ST?UX registers, for example, which
932 // are tied to their output registers.
933 if (UseInfo->Constraints != 0)
937 if (UseInfo->isLookupPtrRegClass()) {
938 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
939 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
941 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
942 PPC::ZERO8 : PPC::ZERO;
945 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
946 UseMI->getOperand(UseIdx).setReg(ZeroReg);
949 DefMI->eraseFromParent();
954 static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
955 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
957 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
962 // We should make sure that, if we're going to predicate both sides of a
963 // condition (a diamond), that both sides don't define the counter register. We
964 // can predicate counter-decrement-based branches, but while that predicates
965 // the branching, it does not predicate the counter decrement. If we tried to
966 // merge the triangle into one predicated block, we'd decrement the counter
968 bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
969 unsigned NumT, unsigned ExtraT,
970 MachineBasicBlock &FMBB,
971 unsigned NumF, unsigned ExtraF,
972 const BranchProbability &Probability) const {
973 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
977 bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
978 // The predicated branches are identified by their type, not really by the
979 // explicit presence of a predicate. Furthermore, some of them can be
980 // predicated more than once. Because if conversion won't try to predicate
981 // any instruction which already claims to be predicated (by returning true
982 // here), always return false. In doing so, we let isPredicable() be the
983 // final word on whether not the instruction can be (further) predicated.
988 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
989 if (!MI->isTerminator())
992 // Conditional branch is a special case.
993 if (MI->isBranch() && !MI->isBarrier())
996 return !isPredicated(MI);
999 bool PPCInstrInfo::PredicateInstruction(
1001 const SmallVectorImpl<MachineOperand> &Pred) const {
1002 unsigned OpC = MI->getOpcode();
1003 if (OpC == PPC::BLR) {
1004 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1005 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
1006 MI->setDesc(get(Pred[0].getImm() ?
1007 (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
1008 (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1010 MI->setDesc(get(PPC::BCLR));
1011 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1012 .addImm(Pred[0].getImm())
1013 .addReg(Pred[1].getReg());
1017 } else if (OpC == PPC::B) {
1018 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1019 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
1020 MI->setDesc(get(Pred[0].getImm() ?
1021 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1022 (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1024 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1025 MI->RemoveOperand(0);
1027 MI->setDesc(get(PPC::BCC));
1028 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1029 .addImm(Pred[0].getImm())
1030 .addReg(Pred[1].getReg())
1035 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1036 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1037 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1038 llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1040 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1041 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
1042 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
1043 (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1044 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1045 .addImm(Pred[0].getImm())
1046 .addReg(Pred[1].getReg());
1053 bool PPCInstrInfo::SubsumesPredicate(
1054 const SmallVectorImpl<MachineOperand> &Pred1,
1055 const SmallVectorImpl<MachineOperand> &Pred2) const {
1056 assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1057 assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1059 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1061 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1064 // P1 can only subsume P2 if they test the same condition register.
1065 if (Pred1[1].getReg() != Pred2[1].getReg())
1068 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1069 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1074 // Does P1 subsume P2, e.g. GE subsumes GT.
1075 if (P1 == PPC::PRED_LE &&
1076 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1078 if (P1 == PPC::PRED_GE &&
1079 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1085 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
1086 std::vector<MachineOperand> &Pred) const {
1087 // Note: At the present time, the contents of Pred from this function is
1088 // unused by IfConversion. This implementation follows ARM by pushing the
1089 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1090 // predicate, instructions defining CTR or CTR8 are also included as
1091 // predicate-defining instructions.
1093 const TargetRegisterClass *RCs[] =
1094 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1095 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1098 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1099 const MachineOperand &MO = MI->getOperand(i);
1100 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1101 const TargetRegisterClass *RC = RCs[c];
1103 if (MO.isDef() && RC->contains(MO.getReg())) {
1107 } else if (MO.isRegMask()) {
1108 for (TargetRegisterClass::iterator I = RC->begin(),
1109 IE = RC->end(); I != IE; ++I)
1110 if (MO.clobbersPhysReg(*I)) {
1121 bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
1122 unsigned OpC = MI->getOpcode();
1136 bool PPCInstrInfo::analyzeCompare(const MachineInstr *MI,
1137 unsigned &SrcReg, unsigned &SrcReg2,
1138 int &Mask, int &Value) const {
1139 unsigned Opc = MI->getOpcode();
1142 default: return false;
1147 SrcReg = MI->getOperand(1).getReg();
1149 Value = MI->getOperand(2).getImm();
1158 SrcReg = MI->getOperand(1).getReg();
1159 SrcReg2 = MI->getOperand(2).getReg();
1164 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
1165 unsigned SrcReg, unsigned SrcReg2,
1166 int Mask, int Value,
1167 const MachineRegisterInfo *MRI) const {
1171 int OpC = CmpInstr->getOpcode();
1172 unsigned CRReg = CmpInstr->getOperand(0).getReg();
1174 // FP record forms set CR1 based on the execption status bits, not a
1175 // comparison with zero.
1176 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1179 // The record forms set the condition register based on a signed comparison
1180 // with zero (so says the ISA manual). This is not as straightforward as it
1181 // seems, however, because this is always a 64-bit comparison on PPC64, even
1182 // for instructions that are 32-bit in nature (like slw for example).
1183 // So, on PPC32, for unsigned comparisons, we can use the record forms only
1184 // for equality checks (as those don't depend on the sign). On PPC64,
1185 // we are restricted to equality for unsigned 64-bit comparisons and for
1186 // signed 32-bit comparisons the applicability is more restricted.
1187 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
1188 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1189 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1190 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1192 // Get the unique definition of SrcReg.
1193 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1194 if (!MI) return false;
1195 int MIOpC = MI->getOpcode();
1197 bool equalityOnly = false;
1200 if (is32BitSignedCompare) {
1201 // We can perform this optimization only if MI is sign-extending.
1202 if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
1203 MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1204 MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1205 MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1206 MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1210 } else if (is32BitUnsignedCompare) {
1211 // We can perform this optimization, equality only, if MI is
1213 if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1214 MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
1215 MIOpC == PPC::SRW || MIOpC == PPC::SRWo) {
1217 equalityOnly = true;
1221 equalityOnly = is64BitUnsignedCompare;
1223 equalityOnly = is32BitUnsignedCompare;
1226 // We need to check the uses of the condition register in order to reject
1227 // non-equality comparisons.
1228 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(CRReg),
1229 IE = MRI->use_end(); I != IE; ++I) {
1230 MachineInstr *UseMI = &*I;
1231 if (UseMI->getOpcode() == PPC::BCC) {
1232 unsigned Pred = UseMI->getOperand(0).getImm();
1233 if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE)
1235 } else if (UseMI->getOpcode() == PPC::ISEL ||
1236 UseMI->getOpcode() == PPC::ISEL8) {
1237 unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1238 if (SubIdx != PPC::sub_eq)
1245 MachineBasicBlock::iterator I = CmpInstr;
1247 // Scan forward to find the first use of the compare.
1248 for (MachineBasicBlock::iterator EL = CmpInstr->getParent()->end();
1250 bool FoundUse = false;
1251 for (MachineRegisterInfo::use_iterator J = MRI->use_begin(CRReg),
1252 JE = MRI->use_end(); J != JE; ++J)
1262 // There are two possible candidates which can be changed to set CR[01].
1263 // One is MI, the other is a SUB instruction.
1264 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1265 MachineInstr *Sub = NULL;
1267 // MI is not a candidate for CMPrr.
1269 // FIXME: Conservatively refuse to convert an instruction which isn't in the
1270 // same BB as the comparison. This is to allow the check below to avoid calls
1271 // (and other explicit clobbers); instead we should really check for these
1272 // more explicitly (in at least a few predecessors).
1273 else if (MI->getParent() != CmpInstr->getParent() || Value != 0) {
1274 // PPC does not have a record-form SUBri.
1279 const TargetRegisterInfo *TRI = &getRegisterInfo();
1282 // Get ready to iterate backward from CmpInstr.
1283 MachineBasicBlock::iterator E = MI,
1284 B = CmpInstr->getParent()->begin();
1286 for (; I != E && !noSub; --I) {
1287 const MachineInstr &Instr = *I;
1288 unsigned IOpC = Instr.getOpcode();
1290 if (&*I != CmpInstr && (
1291 Instr.modifiesRegister(PPC::CR0, TRI) ||
1292 Instr.readsRegister(PPC::CR0, TRI)))
1293 // This instruction modifies or uses the record condition register after
1294 // the one we want to change. While we could do this transformation, it
1295 // would likely not be profitable. This transformation removes one
1296 // instruction, and so even forcing RA to generate one move probably
1297 // makes it unprofitable.
1300 // Check whether CmpInstr can be made redundant by the current instruction.
1301 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1302 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1303 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1304 ((Instr.getOperand(1).getReg() == SrcReg &&
1305 Instr.getOperand(2).getReg() == SrcReg2) ||
1306 (Instr.getOperand(1).getReg() == SrcReg2 &&
1307 Instr.getOperand(2).getReg() == SrcReg))) {
1313 // The 'and' is below the comparison instruction.
1317 // Return false if no candidates exist.
1321 // The single candidate is called MI.
1325 MIOpC = MI->getOpcode();
1326 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1329 NewOpC = PPC::getRecordFormOpcode(MIOpC);
1330 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1334 // FIXME: On the non-embedded POWER architectures, only some of the record
1335 // forms are fast, and we should use only the fast ones.
1337 // The defining instruction has a record form (or is already a record
1338 // form). It is possible, however, that we'll need to reverse the condition
1339 // code of the users.
1343 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
1344 SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
1346 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1347 // needs to be updated to be based on SUB. Push the condition code
1348 // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1349 // condition code of these operands will be modified.
1350 bool ShouldSwap = false;
1352 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1353 Sub->getOperand(2).getReg() == SrcReg;
1355 // The operands to subf are the opposite of sub, so only in the fixed-point
1356 // case, invert the order.
1357 ShouldSwap = !ShouldSwap;
1361 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(CRReg),
1362 IE = MRI->use_end(); I != IE; ++I) {
1363 MachineInstr *UseMI = &*I;
1364 if (UseMI->getOpcode() == PPC::BCC) {
1365 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1366 assert((!equalityOnly ||
1367 Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) &&
1368 "Invalid predicate for equality-only optimization");
1369 PredsToUpdate.push_back(std::make_pair(&((*I).getOperand(0)),
1370 PPC::getSwappedPredicate(Pred)));
1371 } else if (UseMI->getOpcode() == PPC::ISEL ||
1372 UseMI->getOpcode() == PPC::ISEL8) {
1373 unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1374 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1375 "Invalid CR bit for equality-only optimization");
1377 if (NewSubReg == PPC::sub_lt)
1378 NewSubReg = PPC::sub_gt;
1379 else if (NewSubReg == PPC::sub_gt)
1380 NewSubReg = PPC::sub_lt;
1382 SubRegsToUpdate.push_back(std::make_pair(&((*I).getOperand(3)),
1384 } else // We need to abort on a user we don't understand.
1388 // Create a new virtual register to hold the value of the CR set by the
1389 // record-form instruction. If the instruction was not previously in
1390 // record form, then set the kill flag on the CR.
1391 CmpInstr->eraseFromParent();
1393 MachineBasicBlock::iterator MII = MI;
1394 BuildMI(*MI->getParent(), llvm::next(MII), MI->getDebugLoc(),
1395 get(TargetOpcode::COPY), CRReg)
1396 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1398 if (MIOpC != NewOpC) {
1399 // We need to be careful here: we're replacing one instruction with
1400 // another, and we need to make sure that we get all of the right
1401 // implicit uses and defs. On the other hand, the caller may be holding
1402 // an iterator to this instruction, and so we can't delete it (this is
1403 // specifically the case if this is the instruction directly after the
1406 const MCInstrDesc &NewDesc = get(NewOpC);
1407 MI->setDesc(NewDesc);
1409 if (NewDesc.ImplicitDefs)
1410 for (const uint16_t *ImpDefs = NewDesc.getImplicitDefs();
1411 *ImpDefs; ++ImpDefs)
1412 if (!MI->definesRegister(*ImpDefs))
1413 MI->addOperand(*MI->getParent()->getParent(),
1414 MachineOperand::CreateReg(*ImpDefs, true, true));
1415 if (NewDesc.ImplicitUses)
1416 for (const uint16_t *ImpUses = NewDesc.getImplicitUses();
1417 *ImpUses; ++ImpUses)
1418 if (!MI->readsRegister(*ImpUses))
1419 MI->addOperand(*MI->getParent()->getParent(),
1420 MachineOperand::CreateReg(*ImpUses, false, true));
1423 // Modify the condition code of operands in OperandsToUpdate.
1424 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1425 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1426 for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1427 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1429 for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1430 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1435 /// GetInstSize - Return the number of bytes of code the specified
1436 /// instruction may be. This returns the maximum number of bytes.
1438 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
1439 unsigned Opcode = MI->getOpcode();
1441 if (Opcode == PPC::INLINEASM) {
1442 const MachineFunction *MF = MI->getParent()->getParent();
1443 const char *AsmStr = MI->getOperand(0).getSymbolName();
1444 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1446 const MCInstrDesc &Desc = get(Opcode);
1447 return Desc.getSize();
1452 #define DEBUG_TYPE "ppc-early-ret"
1453 STATISTIC(NumBCLR, "Number of early conditional returns");
1454 STATISTIC(NumBLR, "Number of early returns");
1457 void initializePPCEarlyReturnPass(PassRegistry&);
1461 // PPCEarlyReturn pass - For simple functions without epilogue code, move
1462 // returns up, and create conditional returns, to avoid unnecessary
1463 // branch-to-blr sequences.
1464 struct PPCEarlyReturn : public MachineFunctionPass {
1466 PPCEarlyReturn() : MachineFunctionPass(ID) {
1467 initializePPCEarlyReturnPass(*PassRegistry::getPassRegistry());
1470 const PPCTargetMachine *TM;
1471 const PPCInstrInfo *TII;
1474 bool processBlock(MachineBasicBlock &ReturnMBB) {
1475 bool Changed = false;
1477 MachineBasicBlock::iterator I = ReturnMBB.begin();
1478 I = ReturnMBB.SkipPHIsAndLabels(I);
1480 // The block must be essentially empty except for the blr.
1481 if (I == ReturnMBB.end() || I->getOpcode() != PPC::BLR ||
1482 I != ReturnMBB.getLastNonDebugInstr())
1485 SmallVector<MachineBasicBlock*, 8> PredToRemove;
1486 for (MachineBasicBlock::pred_iterator PI = ReturnMBB.pred_begin(),
1487 PIE = ReturnMBB.pred_end(); PI != PIE; ++PI) {
1488 bool OtherReference = false, BlockChanged = false;
1489 for (MachineBasicBlock::iterator J = (*PI)->getLastNonDebugInstr();;) {
1490 if (J->getOpcode() == PPC::B) {
1491 if (J->getOperand(0).getMBB() == &ReturnMBB) {
1492 // This is an unconditional branch to the return. Replace the
1493 // branch with a blr.
1494 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BLR));
1495 MachineBasicBlock::iterator K = J--;
1496 K->eraseFromParent();
1497 BlockChanged = true;
1501 } else if (J->getOpcode() == PPC::BCC) {
1502 if (J->getOperand(2).getMBB() == &ReturnMBB) {
1503 // This is a conditional branch to the return. Replace the branch
1505 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCLR))
1506 .addImm(J->getOperand(0).getImm())
1507 .addReg(J->getOperand(1).getReg());
1508 MachineBasicBlock::iterator K = J--;
1509 K->eraseFromParent();
1510 BlockChanged = true;
1514 } else if (J->isBranch()) {
1515 if (J->isIndirectBranch()) {
1516 if (ReturnMBB.hasAddressTaken())
1517 OtherReference = true;
1519 for (unsigned i = 0; i < J->getNumOperands(); ++i)
1520 if (J->getOperand(i).isMBB() &&
1521 J->getOperand(i).getMBB() == &ReturnMBB)
1522 OtherReference = true;
1523 } else if (!J->isTerminator() && !J->isDebugValue())
1526 if (J == (*PI)->begin())
1532 if ((*PI)->canFallThrough() && (*PI)->isLayoutSuccessor(&ReturnMBB))
1533 OtherReference = true;
1535 // Predecessors are stored in a vector and can't be removed here.
1536 if (!OtherReference && BlockChanged) {
1537 PredToRemove.push_back(*PI);
1544 for (unsigned i = 0, ie = PredToRemove.size(); i != ie; ++i)
1545 PredToRemove[i]->removeSuccessor(&ReturnMBB);
1547 if (Changed && !ReturnMBB.hasAddressTaken()) {
1548 // We now might be able to merge this blr-only block into its
1549 // by-layout predecessor.
1550 if (ReturnMBB.pred_size() == 1 &&
1551 (*ReturnMBB.pred_begin())->isLayoutSuccessor(&ReturnMBB)) {
1552 // Move the blr into the preceding block.
1553 MachineBasicBlock &PrevMBB = **ReturnMBB.pred_begin();
1554 PrevMBB.splice(PrevMBB.end(), &ReturnMBB, I);
1555 PrevMBB.removeSuccessor(&ReturnMBB);
1558 if (ReturnMBB.pred_empty())
1559 ReturnMBB.eraseFromParent();
1566 virtual bool runOnMachineFunction(MachineFunction &MF) {
1567 TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
1568 TII = TM->getInstrInfo();
1570 bool Changed = false;
1572 // If the function does not have at least two blocks, then there is
1577 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
1578 MachineBasicBlock &B = *I++;
1579 if (processBlock(B))
1586 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1587 MachineFunctionPass::getAnalysisUsage(AU);
1592 INITIALIZE_PASS(PPCEarlyReturn, DEBUG_TYPE,
1593 "PowerPC Early-Return Creation", false, false)
1595 char PPCEarlyReturn::ID = 0;
1597 llvm::createPPCEarlyReturnPass() { return new PPCEarlyReturn(); }