1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPredicates.h"
18 #include "PPCGenInstrInfo.inc"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/MC/MCAsmInfo.h"
29 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
30 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
32 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
33 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
34 RI(*TM.getSubtargetImpl(), *this) {}
36 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
39 unsigned& sourceSubIdx,
40 unsigned& destSubIdx) const {
41 sourceSubIdx = destSubIdx = 0; // No sub-registers.
43 unsigned oc = MI.getOpcode();
44 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
45 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
46 assert(MI.getNumOperands() >= 3 &&
47 MI.getOperand(0).isReg() &&
48 MI.getOperand(1).isReg() &&
49 MI.getOperand(2).isReg() &&
50 "invalid PPC OR instruction!");
51 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
52 sourceReg = MI.getOperand(1).getReg();
53 destReg = MI.getOperand(0).getReg();
56 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
57 assert(MI.getNumOperands() >= 3 &&
58 MI.getOperand(0).isReg() &&
59 MI.getOperand(2).isImm() &&
60 "invalid PPC ADDI instruction!");
61 if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
62 sourceReg = MI.getOperand(1).getReg();
63 destReg = MI.getOperand(0).getReg();
66 } else if (oc == PPC::ORI) { // ori r1, r2, 0
67 assert(MI.getNumOperands() >= 3 &&
68 MI.getOperand(0).isReg() &&
69 MI.getOperand(1).isReg() &&
70 MI.getOperand(2).isImm() &&
71 "invalid PPC ORI instruction!");
72 if (MI.getOperand(2).getImm() == 0) {
73 sourceReg = MI.getOperand(1).getReg();
74 destReg = MI.getOperand(0).getReg();
77 } else if (oc == PPC::FMR || oc == PPC::FMRSD) { // fmr r1, r2
78 assert(MI.getNumOperands() >= 2 &&
79 MI.getOperand(0).isReg() &&
80 MI.getOperand(1).isReg() &&
81 "invalid PPC FMR instruction");
82 sourceReg = MI.getOperand(1).getReg();
83 destReg = MI.getOperand(0).getReg();
85 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
86 assert(MI.getNumOperands() >= 2 &&
87 MI.getOperand(0).isReg() &&
88 MI.getOperand(1).isReg() &&
89 "invalid PPC MCRF instruction");
90 sourceReg = MI.getOperand(1).getReg();
91 destReg = MI.getOperand(0).getReg();
97 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
98 int &FrameIndex) const {
99 switch (MI->getOpcode()) {
105 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
106 MI->getOperand(2).isFI()) {
107 FrameIndex = MI->getOperand(2).getIndex();
108 return MI->getOperand(0).getReg();
115 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
116 int &FrameIndex) const {
117 switch (MI->getOpcode()) {
123 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
124 MI->getOperand(2).isFI()) {
125 FrameIndex = MI->getOperand(2).getIndex();
126 return MI->getOperand(0).getReg();
133 // commuteInstruction - We can commute rlwimi instructions, but only if the
134 // rotate amt is zero. We also have to munge the immediates a bit.
136 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
137 MachineFunction &MF = *MI->getParent()->getParent();
139 // Normal instructions can be commuted the obvious way.
140 if (MI->getOpcode() != PPC::RLWIMI)
141 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
143 // Cannot commute if it has a non-zero rotate count.
144 if (MI->getOperand(3).getImm() != 0)
147 // If we have a zero rotate count, we have:
149 // Op0 = (Op1 & ~M) | (Op2 & M)
151 // M = mask((ME+1)&31, (MB-1)&31)
152 // Op0 = (Op2 & ~M) | (Op1 & M)
155 unsigned Reg0 = MI->getOperand(0).getReg();
156 unsigned Reg1 = MI->getOperand(1).getReg();
157 unsigned Reg2 = MI->getOperand(2).getReg();
158 bool Reg1IsKill = MI->getOperand(1).isKill();
159 bool Reg2IsKill = MI->getOperand(2).isKill();
160 bool ChangeReg0 = false;
161 // If machine instrs are no longer in two-address forms, update
162 // destination register as well.
164 // Must be two address instruction!
165 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
166 "Expecting a two-address instruction!");
172 unsigned MB = MI->getOperand(4).getImm();
173 unsigned ME = MI->getOperand(5).getImm();
176 // Create a new instruction.
177 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
178 bool Reg0IsDead = MI->getOperand(0).isDead();
179 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
180 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
181 .addReg(Reg2, getKillRegState(Reg2IsKill))
182 .addReg(Reg1, getKillRegState(Reg1IsKill))
184 .addImm((MB-1) & 31);
188 MI->getOperand(0).setReg(Reg2);
189 MI->getOperand(2).setReg(Reg1);
190 MI->getOperand(1).setReg(Reg2);
191 MI->getOperand(2).setIsKill(Reg1IsKill);
192 MI->getOperand(1).setIsKill(Reg2IsKill);
194 // Swap the mask around.
195 MI->getOperand(4).setImm((ME+1) & 31);
196 MI->getOperand(5).setImm((MB-1) & 31);
200 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
201 MachineBasicBlock::iterator MI) const {
203 if (MI != MBB.end()) DL = MI->getDebugLoc();
205 BuildMI(MBB, MI, DL, get(PPC::NOP));
210 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
211 MachineBasicBlock *&FBB,
212 SmallVectorImpl<MachineOperand> &Cond,
213 bool AllowModify) const {
214 // If the block has no terminators, it just falls into the block after it.
215 MachineBasicBlock::iterator I = MBB.end();
216 if (I == MBB.begin())
219 while (I->isDebugValue()) {
220 if (I == MBB.begin())
224 if (!isUnpredicatedTerminator(I))
227 // Get the last instruction in the block.
228 MachineInstr *LastInst = I;
230 // If there is only one terminator instruction, process it.
231 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
232 if (LastInst->getOpcode() == PPC::B) {
233 if (!LastInst->getOperand(0).isMBB())
235 TBB = LastInst->getOperand(0).getMBB();
237 } else if (LastInst->getOpcode() == PPC::BCC) {
238 if (!LastInst->getOperand(2).isMBB())
240 // Block ends with fall-through condbranch.
241 TBB = LastInst->getOperand(2).getMBB();
242 Cond.push_back(LastInst->getOperand(0));
243 Cond.push_back(LastInst->getOperand(1));
246 // Otherwise, don't know what this is.
250 // Get the instruction before it if it's a terminator.
251 MachineInstr *SecondLastInst = I;
253 // If there are three terminators, we don't know what sort of block this is.
254 if (SecondLastInst && I != MBB.begin() &&
255 isUnpredicatedTerminator(--I))
258 // If the block ends with PPC::B and PPC:BCC, handle it.
259 if (SecondLastInst->getOpcode() == PPC::BCC &&
260 LastInst->getOpcode() == PPC::B) {
261 if (!SecondLastInst->getOperand(2).isMBB() ||
262 !LastInst->getOperand(0).isMBB())
264 TBB = SecondLastInst->getOperand(2).getMBB();
265 Cond.push_back(SecondLastInst->getOperand(0));
266 Cond.push_back(SecondLastInst->getOperand(1));
267 FBB = LastInst->getOperand(0).getMBB();
271 // If the block ends with two PPC:Bs, handle it. The second one is not
272 // executed, so remove it.
273 if (SecondLastInst->getOpcode() == PPC::B &&
274 LastInst->getOpcode() == PPC::B) {
275 if (!SecondLastInst->getOperand(0).isMBB())
277 TBB = SecondLastInst->getOperand(0).getMBB();
280 I->eraseFromParent();
284 // Otherwise, can't handle this.
288 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
289 MachineBasicBlock::iterator I = MBB.end();
290 if (I == MBB.begin()) return 0;
292 while (I->isDebugValue()) {
293 if (I == MBB.begin())
297 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
300 // Remove the branch.
301 I->eraseFromParent();
305 if (I == MBB.begin()) return 1;
307 if (I->getOpcode() != PPC::BCC)
310 // Remove the branch.
311 I->eraseFromParent();
316 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
317 MachineBasicBlock *FBB,
318 const SmallVectorImpl<MachineOperand> &Cond) const {
319 // FIXME this should probably have a DebugLoc argument
321 // Shouldn't be a fall through.
322 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
323 assert((Cond.size() == 2 || Cond.size() == 0) &&
324 "PPC branch conditions have two components!");
328 if (Cond.empty()) // Unconditional branch
329 BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB);
330 else // Conditional branch
331 BuildMI(&MBB, dl, get(PPC::BCC))
332 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
336 // Two-way Conditional Branch.
337 BuildMI(&MBB, dl, get(PPC::BCC))
338 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
339 BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB);
343 bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
344 MachineBasicBlock::iterator MI,
345 unsigned DestReg, unsigned SrcReg,
346 const TargetRegisterClass *DestRC,
347 const TargetRegisterClass *SrcRC) const {
348 if (DestRC != SrcRC) {
349 // Not yet supported!
354 if (MI != MBB.end()) DL = MI->getDebugLoc();
356 if (DestRC == PPC::GPRCRegisterClass) {
357 BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
358 } else if (DestRC == PPC::G8RCRegisterClass) {
359 BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
360 } else if (DestRC == PPC::F4RCRegisterClass ||
361 DestRC == PPC::F8RCRegisterClass) {
362 BuildMI(MBB, MI, DL, get(PPC::FMR), DestReg).addReg(SrcReg);
363 } else if (DestRC == PPC::CRRCRegisterClass) {
364 BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg);
365 } else if (DestRC == PPC::VRRCRegisterClass) {
366 BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
367 } else if (DestRC == PPC::CRBITRCRegisterClass) {
368 BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
370 // Attempt to copy register that is not GPR or FPR
378 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
379 unsigned SrcReg, bool isKill,
381 const TargetRegisterClass *RC,
382 SmallVectorImpl<MachineInstr*> &NewMIs) const{
384 if (RC == PPC::GPRCRegisterClass) {
385 if (SrcReg != PPC::LR) {
386 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
388 getKillRegState(isKill)),
391 // FIXME: this spills LR immediately to memory in one step. To do this,
392 // we use R11, which we know cannot be used in the prolog/epilog. This is
394 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
395 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
397 getKillRegState(isKill)),
400 } else if (RC == PPC::G8RCRegisterClass) {
401 if (SrcReg != PPC::LR8) {
402 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
404 getKillRegState(isKill)),
407 // FIXME: this spills LR immediately to memory in one step. To do this,
408 // we use R11, which we know cannot be used in the prolog/epilog. This is
410 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
411 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
413 getKillRegState(isKill)),
416 } else if (RC == PPC::F8RCRegisterClass) {
417 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
419 getKillRegState(isKill)),
421 } else if (RC == PPC::F4RCRegisterClass) {
422 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
424 getKillRegState(isKill)),
426 } else if (RC == PPC::CRRCRegisterClass) {
427 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
428 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
429 // FIXME (64-bit): Enable
430 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
432 getKillRegState(isKill)),
436 // FIXME: We need a scatch reg here. The trouble with using R0 is that
437 // it's possible for the stack frame to be so big the save location is
438 // out of range of immediate offsets, necessitating another register.
439 // We hack this on Darwin by reserving R2. It's probably broken on Linux
442 // We need to store the CR in the low 4-bits of the saved value. First,
443 // issue a MFCR to save all of the CRBits.
444 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
446 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), ScratchReg));
448 // If the saved register wasn't CR0, shift the bits left so that they are
450 if (SrcReg != PPC::CR0) {
451 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
452 // rlwinm scratch, scratch, ShiftBits, 0, 31.
453 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
454 .addReg(ScratchReg).addImm(ShiftBits)
455 .addImm(0).addImm(31));
458 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
460 getKillRegState(isKill)),
463 } else if (RC == PPC::CRBITRCRegisterClass) {
464 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
465 // backend currently only uses CR1EQ as an individual bit, this should
466 // not cause any bug. If we need other uses of CR bits, the following
467 // code may be invalid.
469 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
470 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
472 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
473 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
475 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
476 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
478 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
479 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
481 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
482 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
484 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
485 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
487 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
488 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
490 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
491 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
494 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
495 PPC::CRRCRegisterClass, NewMIs);
497 } else if (RC == PPC::VRRCRegisterClass) {
498 // We don't have indexed addressing for vector loads. Emit:
502 // FIXME: We use R0 here, because it isn't available for RA.
503 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
505 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
506 .addReg(SrcReg, getKillRegState(isKill))
510 llvm_unreachable("Unknown regclass!");
517 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
518 MachineBasicBlock::iterator MI,
519 unsigned SrcReg, bool isKill, int FrameIdx,
520 const TargetRegisterClass *RC) const {
521 MachineFunction &MF = *MBB.getParent();
522 SmallVector<MachineInstr*, 4> NewMIs;
524 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
525 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
526 FuncInfo->setSpillsCR();
529 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
530 MBB.insert(MI, NewMIs[i]);
534 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
535 unsigned DestReg, int FrameIdx,
536 const TargetRegisterClass *RC,
537 SmallVectorImpl<MachineInstr*> &NewMIs)const{
538 if (RC == PPC::GPRCRegisterClass) {
539 if (DestReg != PPC::LR) {
540 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
541 DestReg), FrameIdx));
543 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
544 PPC::R11), FrameIdx));
545 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
547 } else if (RC == PPC::G8RCRegisterClass) {
548 if (DestReg != PPC::LR8) {
549 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
552 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
553 PPC::R11), FrameIdx));
554 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
556 } else if (RC == PPC::F8RCRegisterClass) {
557 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
559 } else if (RC == PPC::F4RCRegisterClass) {
560 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
562 } else if (RC == PPC::CRRCRegisterClass) {
563 // FIXME: We need a scatch reg here. The trouble with using R0 is that
564 // it's possible for the stack frame to be so big the save location is
565 // out of range of immediate offsets, necessitating another register.
566 // We hack this on Darwin by reserving R2. It's probably broken on Linux
568 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
570 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
571 ScratchReg), FrameIdx));
573 // If the reloaded register isn't CR0, shift the bits right so that they are
574 // in the right CR's slot.
575 if (DestReg != PPC::CR0) {
576 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
577 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
578 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
579 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
583 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg)
584 .addReg(ScratchReg));
585 } else if (RC == PPC::CRBITRCRegisterClass) {
588 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
589 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
591 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
592 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
594 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
595 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
597 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
598 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
600 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
601 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
603 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
604 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
606 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
607 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
609 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
610 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
613 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
614 PPC::CRRCRegisterClass, NewMIs);
616 } else if (RC == PPC::VRRCRegisterClass) {
617 // We don't have indexed addressing for vector loads. Emit:
621 // FIXME: We use R0 here, because it isn't available for RA.
622 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
624 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
627 llvm_unreachable("Unknown regclass!");
632 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
633 MachineBasicBlock::iterator MI,
634 unsigned DestReg, int FrameIdx,
635 const TargetRegisterClass *RC) const {
636 MachineFunction &MF = *MBB.getParent();
637 SmallVector<MachineInstr*, 4> NewMIs;
639 if (MI != MBB.end()) DL = MI->getDebugLoc();
640 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
641 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
642 MBB.insert(MI, NewMIs[i]);
645 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
646 /// copy instructions, turning them into load/store instructions.
647 MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
649 const SmallVectorImpl<unsigned> &Ops,
650 int FrameIndex) const {
651 if (Ops.size() != 1) return NULL;
653 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
654 // it takes more than one instruction to store it.
655 unsigned Opc = MI->getOpcode();
656 unsigned OpNum = Ops[0];
658 MachineInstr *NewMI = NULL;
659 if ((Opc == PPC::OR &&
660 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
661 if (OpNum == 0) { // move -> store
662 unsigned InReg = MI->getOperand(1).getReg();
663 bool isKill = MI->getOperand(1).isKill();
664 bool isUndef = MI->getOperand(1).isUndef();
665 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
667 getKillRegState(isKill) |
668 getUndefRegState(isUndef)),
670 } else { // move -> load
671 unsigned OutReg = MI->getOperand(0).getReg();
672 bool isDead = MI->getOperand(0).isDead();
673 bool isUndef = MI->getOperand(0).isUndef();
674 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
677 getDeadRegState(isDead) |
678 getUndefRegState(isUndef)),
681 } else if ((Opc == PPC::OR8 &&
682 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
683 if (OpNum == 0) { // move -> store
684 unsigned InReg = MI->getOperand(1).getReg();
685 bool isKill = MI->getOperand(1).isKill();
686 bool isUndef = MI->getOperand(1).isUndef();
687 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
689 getKillRegState(isKill) |
690 getUndefRegState(isUndef)),
692 } else { // move -> load
693 unsigned OutReg = MI->getOperand(0).getReg();
694 bool isDead = MI->getOperand(0).isDead();
695 bool isUndef = MI->getOperand(0).isUndef();
696 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
699 getDeadRegState(isDead) |
700 getUndefRegState(isUndef)),
703 } else if (Opc == PPC::FMR || Opc == PPC::FMRSD) {
704 // The register may be F4RC or F8RC, and that determines the memory op.
705 unsigned OrigReg = MI->getOperand(OpNum).getReg();
706 // We cannot tell the register class from a physreg alone.
707 if (TargetRegisterInfo::isPhysicalRegister(OrigReg))
709 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(OrigReg);
710 const bool is64 = RC == PPC::F8RCRegisterClass;
712 if (OpNum == 0) { // move -> store
713 unsigned InReg = MI->getOperand(1).getReg();
714 bool isKill = MI->getOperand(1).isKill();
715 bool isUndef = MI->getOperand(1).isUndef();
716 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(),
717 get(is64 ? PPC::STFD : PPC::STFS))
719 getKillRegState(isKill) |
720 getUndefRegState(isUndef)),
722 } else { // move -> load
723 unsigned OutReg = MI->getOperand(0).getReg();
724 bool isDead = MI->getOperand(0).isDead();
725 bool isUndef = MI->getOperand(0).isUndef();
726 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(),
727 get(is64 ? PPC::LFD : PPC::LFS))
730 getDeadRegState(isDead) |
731 getUndefRegState(isUndef)),
739 bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
740 const SmallVectorImpl<unsigned> &Ops) const {
741 if (Ops.size() != 1) return false;
743 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
744 // it takes more than one instruction to store it.
745 unsigned Opc = MI->getOpcode();
747 if ((Opc == PPC::OR &&
748 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
750 else if ((Opc == PPC::OR8 &&
751 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
753 else if (Opc == PPC::FMR || Opc == PPC::FMRSD)
761 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
762 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
763 // Leave the CR# the same, but invert the condition.
764 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
768 /// GetInstSize - Return the number of bytes of code the specified
769 /// instruction may be. This returns the maximum number of bytes.
771 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
772 switch (MI->getOpcode()) {
773 case PPC::INLINEASM: { // Inline Asm: Variable size.
774 const MachineFunction *MF = MI->getParent()->getParent();
775 const char *AsmStr = MI->getOperand(0).getSymbolName();
776 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
784 return 4; // PowerPC instructions are all 4 bytes