1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPredicates.h"
18 #include "PPCGenInstrInfo.inc"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/MC/MCAsmInfo.h"
32 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
33 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
38 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
39 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
40 RI(*TM.getSubtargetImpl(), *this) {}
42 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
43 int &FrameIndex) const {
44 switch (MI->getOpcode()) {
50 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
51 MI->getOperand(2).isFI()) {
52 FrameIndex = MI->getOperand(2).getIndex();
53 return MI->getOperand(0).getReg();
60 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
61 int &FrameIndex) const {
62 switch (MI->getOpcode()) {
68 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
69 MI->getOperand(2).isFI()) {
70 FrameIndex = MI->getOperand(2).getIndex();
71 return MI->getOperand(0).getReg();
78 // commuteInstruction - We can commute rlwimi instructions, but only if the
79 // rotate amt is zero. We also have to munge the immediates a bit.
81 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
82 MachineFunction &MF = *MI->getParent()->getParent();
84 // Normal instructions can be commuted the obvious way.
85 if (MI->getOpcode() != PPC::RLWIMI)
86 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
88 // Cannot commute if it has a non-zero rotate count.
89 if (MI->getOperand(3).getImm() != 0)
92 // If we have a zero rotate count, we have:
94 // Op0 = (Op1 & ~M) | (Op2 & M)
96 // M = mask((ME+1)&31, (MB-1)&31)
97 // Op0 = (Op2 & ~M) | (Op1 & M)
100 unsigned Reg0 = MI->getOperand(0).getReg();
101 unsigned Reg1 = MI->getOperand(1).getReg();
102 unsigned Reg2 = MI->getOperand(2).getReg();
103 bool Reg1IsKill = MI->getOperand(1).isKill();
104 bool Reg2IsKill = MI->getOperand(2).isKill();
105 bool ChangeReg0 = false;
106 // If machine instrs are no longer in two-address forms, update
107 // destination register as well.
109 // Must be two address instruction!
110 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
111 "Expecting a two-address instruction!");
117 unsigned MB = MI->getOperand(4).getImm();
118 unsigned ME = MI->getOperand(5).getImm();
121 // Create a new instruction.
122 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
123 bool Reg0IsDead = MI->getOperand(0).isDead();
124 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
125 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
126 .addReg(Reg2, getKillRegState(Reg2IsKill))
127 .addReg(Reg1, getKillRegState(Reg1IsKill))
129 .addImm((MB-1) & 31);
133 MI->getOperand(0).setReg(Reg2);
134 MI->getOperand(2).setReg(Reg1);
135 MI->getOperand(1).setReg(Reg2);
136 MI->getOperand(2).setIsKill(Reg1IsKill);
137 MI->getOperand(1).setIsKill(Reg2IsKill);
139 // Swap the mask around.
140 MI->getOperand(4).setImm((ME+1) & 31);
141 MI->getOperand(5).setImm((MB-1) & 31);
145 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
146 MachineBasicBlock::iterator MI) const {
148 BuildMI(MBB, MI, DL, get(PPC::NOP));
153 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
154 MachineBasicBlock *&FBB,
155 SmallVectorImpl<MachineOperand> &Cond,
156 bool AllowModify) const {
157 // If the block has no terminators, it just falls into the block after it.
158 MachineBasicBlock::iterator I = MBB.end();
159 if (I == MBB.begin())
162 while (I->isDebugValue()) {
163 if (I == MBB.begin())
167 if (!isUnpredicatedTerminator(I))
170 // Get the last instruction in the block.
171 MachineInstr *LastInst = I;
173 // If there is only one terminator instruction, process it.
174 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
175 if (LastInst->getOpcode() == PPC::B) {
176 if (!LastInst->getOperand(0).isMBB())
178 TBB = LastInst->getOperand(0).getMBB();
180 } else if (LastInst->getOpcode() == PPC::BCC) {
181 if (!LastInst->getOperand(2).isMBB())
183 // Block ends with fall-through condbranch.
184 TBB = LastInst->getOperand(2).getMBB();
185 Cond.push_back(LastInst->getOperand(0));
186 Cond.push_back(LastInst->getOperand(1));
189 // Otherwise, don't know what this is.
193 // Get the instruction before it if it's a terminator.
194 MachineInstr *SecondLastInst = I;
196 // If there are three terminators, we don't know what sort of block this is.
197 if (SecondLastInst && I != MBB.begin() &&
198 isUnpredicatedTerminator(--I))
201 // If the block ends with PPC::B and PPC:BCC, handle it.
202 if (SecondLastInst->getOpcode() == PPC::BCC &&
203 LastInst->getOpcode() == PPC::B) {
204 if (!SecondLastInst->getOperand(2).isMBB() ||
205 !LastInst->getOperand(0).isMBB())
207 TBB = SecondLastInst->getOperand(2).getMBB();
208 Cond.push_back(SecondLastInst->getOperand(0));
209 Cond.push_back(SecondLastInst->getOperand(1));
210 FBB = LastInst->getOperand(0).getMBB();
214 // If the block ends with two PPC:Bs, handle it. The second one is not
215 // executed, so remove it.
216 if (SecondLastInst->getOpcode() == PPC::B &&
217 LastInst->getOpcode() == PPC::B) {
218 if (!SecondLastInst->getOperand(0).isMBB())
220 TBB = SecondLastInst->getOperand(0).getMBB();
223 I->eraseFromParent();
227 // Otherwise, can't handle this.
231 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
232 MachineBasicBlock::iterator I = MBB.end();
233 if (I == MBB.begin()) return 0;
235 while (I->isDebugValue()) {
236 if (I == MBB.begin())
240 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
243 // Remove the branch.
244 I->eraseFromParent();
248 if (I == MBB.begin()) return 1;
250 if (I->getOpcode() != PPC::BCC)
253 // Remove the branch.
254 I->eraseFromParent();
259 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
260 MachineBasicBlock *FBB,
261 const SmallVectorImpl<MachineOperand> &Cond,
263 // Shouldn't be a fall through.
264 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
265 assert((Cond.size() == 2 || Cond.size() == 0) &&
266 "PPC branch conditions have two components!");
270 if (Cond.empty()) // Unconditional branch
271 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
272 else // Conditional branch
273 BuildMI(&MBB, DL, get(PPC::BCC))
274 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
278 // Two-way Conditional Branch.
279 BuildMI(&MBB, DL, get(PPC::BCC))
280 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
281 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
285 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
286 MachineBasicBlock::iterator I, DebugLoc DL,
287 unsigned DestReg, unsigned SrcReg,
288 bool KillSrc) const {
290 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
292 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
294 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
296 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
298 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
300 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
303 llvm_unreachable("Impossible reg-to-reg copy");
305 const TargetInstrDesc &TID = get(Opc);
306 if (TID.getNumOperands() == 3)
307 BuildMI(MBB, I, DL, TID, DestReg)
308 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
310 BuildMI(MBB, I, DL, TID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
314 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
315 unsigned SrcReg, bool isKill,
317 const TargetRegisterClass *RC,
318 SmallVectorImpl<MachineInstr*> &NewMIs) const{
320 if (RC == PPC::GPRCRegisterClass) {
321 if (SrcReg != PPC::LR) {
322 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
324 getKillRegState(isKill)),
327 // FIXME: this spills LR immediately to memory in one step. To do this,
328 // we use R11, which we know cannot be used in the prolog/epilog. This is
330 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
331 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
333 getKillRegState(isKill)),
336 } else if (RC == PPC::G8RCRegisterClass) {
337 if (SrcReg != PPC::LR8) {
338 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
340 getKillRegState(isKill)),
343 // FIXME: this spills LR immediately to memory in one step. To do this,
344 // we use R11, which we know cannot be used in the prolog/epilog. This is
346 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
347 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
349 getKillRegState(isKill)),
352 } else if (RC == PPC::F8RCRegisterClass) {
353 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
355 getKillRegState(isKill)),
357 } else if (RC == PPC::F4RCRegisterClass) {
358 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
360 getKillRegState(isKill)),
362 } else if (RC == PPC::CRRCRegisterClass) {
363 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
364 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
365 // FIXME (64-bit): Enable
366 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
368 getKillRegState(isKill)),
372 // FIXME: We need a scatch reg here. The trouble with using R0 is that
373 // it's possible for the stack frame to be so big the save location is
374 // out of range of immediate offsets, necessitating another register.
375 // We hack this on Darwin by reserving R2. It's probably broken on Linux
378 // We need to store the CR in the low 4-bits of the saved value. First,
379 // issue a MFCR to save all of the CRBits.
380 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
382 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg)
383 .addReg(SrcReg, getKillRegState(isKill)));
385 // If the saved register wasn't CR0, shift the bits left so that they are
387 if (SrcReg != PPC::CR0) {
388 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
389 // rlwinm scratch, scratch, ShiftBits, 0, 31.
390 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
391 .addReg(ScratchReg).addImm(ShiftBits)
392 .addImm(0).addImm(31));
395 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
397 getKillRegState(isKill)),
400 } else if (RC == PPC::CRBITRCRegisterClass) {
401 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
402 // backend currently only uses CR1EQ as an individual bit, this should
403 // not cause any bug. If we need other uses of CR bits, the following
404 // code may be invalid.
406 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
407 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
409 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
410 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
412 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
413 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
415 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
416 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
418 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
419 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
421 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
422 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
424 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
425 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
427 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
428 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
431 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
432 PPC::CRRCRegisterClass, NewMIs);
434 } else if (RC == PPC::VRRCRegisterClass) {
435 // We don't have indexed addressing for vector loads. Emit:
439 // FIXME: We use R0 here, because it isn't available for RA.
440 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
442 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
443 .addReg(SrcReg, getKillRegState(isKill))
447 llvm_unreachable("Unknown regclass!");
454 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
455 MachineBasicBlock::iterator MI,
456 unsigned SrcReg, bool isKill, int FrameIdx,
457 const TargetRegisterClass *RC,
458 const TargetRegisterInfo *TRI) const {
459 MachineFunction &MF = *MBB.getParent();
460 SmallVector<MachineInstr*, 4> NewMIs;
462 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
463 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
464 FuncInfo->setSpillsCR();
467 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
468 MBB.insert(MI, NewMIs[i]);
470 const MachineFrameInfo &MFI = *MF.getFrameInfo();
471 MachineMemOperand *MMO =
472 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
473 MachineMemOperand::MOStore, /*Offset=*/0,
474 MFI.getObjectSize(FrameIdx),
475 MFI.getObjectAlignment(FrameIdx));
476 NewMIs.back()->addMemOperand(MF, MMO);
480 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
481 unsigned DestReg, int FrameIdx,
482 const TargetRegisterClass *RC,
483 SmallVectorImpl<MachineInstr*> &NewMIs)const{
484 if (RC == PPC::GPRCRegisterClass) {
485 if (DestReg != PPC::LR) {
486 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
487 DestReg), FrameIdx));
489 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
490 PPC::R11), FrameIdx));
491 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
493 } else if (RC == PPC::G8RCRegisterClass) {
494 if (DestReg != PPC::LR8) {
495 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
498 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
499 PPC::R11), FrameIdx));
500 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
502 } else if (RC == PPC::F8RCRegisterClass) {
503 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
505 } else if (RC == PPC::F4RCRegisterClass) {
506 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
508 } else if (RC == PPC::CRRCRegisterClass) {
509 // FIXME: We need a scatch reg here. The trouble with using R0 is that
510 // it's possible for the stack frame to be so big the save location is
511 // out of range of immediate offsets, necessitating another register.
512 // We hack this on Darwin by reserving R2. It's probably broken on Linux
514 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
516 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
517 ScratchReg), FrameIdx));
519 // If the reloaded register isn't CR0, shift the bits right so that they are
520 // in the right CR's slot.
521 if (DestReg != PPC::CR0) {
522 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
523 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
524 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
525 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
529 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg)
530 .addReg(ScratchReg));
531 } else if (RC == PPC::CRBITRCRegisterClass) {
534 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
535 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
537 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
538 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
540 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
541 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
543 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
544 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
546 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
547 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
549 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
550 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
552 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
553 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
555 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
556 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
559 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
560 PPC::CRRCRegisterClass, NewMIs);
562 } else if (RC == PPC::VRRCRegisterClass) {
563 // We don't have indexed addressing for vector loads. Emit:
567 // FIXME: We use R0 here, because it isn't available for RA.
568 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
570 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
573 llvm_unreachable("Unknown regclass!");
578 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
579 MachineBasicBlock::iterator MI,
580 unsigned DestReg, int FrameIdx,
581 const TargetRegisterClass *RC,
582 const TargetRegisterInfo *TRI) const {
583 MachineFunction &MF = *MBB.getParent();
584 SmallVector<MachineInstr*, 4> NewMIs;
586 if (MI != MBB.end()) DL = MI->getDebugLoc();
587 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
588 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
589 MBB.insert(MI, NewMIs[i]);
591 const MachineFrameInfo &MFI = *MF.getFrameInfo();
592 MachineMemOperand *MMO =
593 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
594 MachineMemOperand::MOLoad, /*Offset=*/0,
595 MFI.getObjectSize(FrameIdx),
596 MFI.getObjectAlignment(FrameIdx));
597 NewMIs.back()->addMemOperand(MF, MMO);
601 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
602 int FrameIx, uint64_t Offset,
605 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
606 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
611 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
612 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
613 // Leave the CR# the same, but invert the condition.
614 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
618 /// GetInstSize - Return the number of bytes of code the specified
619 /// instruction may be. This returns the maximum number of bytes.
621 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
622 switch (MI->getOpcode()) {
623 case PPC::INLINEASM: { // Inline Asm: Variable size.
624 const MachineFunction *MF = MI->getParent()->getParent();
625 const char *AsmStr = MI->getOperand(0).getSymbolName();
626 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
628 case PPC::PROLOG_LABEL:
634 return 4; // PowerPC instructions are all 4 bytes