1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/CodeGen/ScheduleDAG.h"
31 #include "llvm/CodeGen/SlotIndexes.h"
32 #include "llvm/CodeGen/StackMaps.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Support/raw_ostream.h"
43 #define DEBUG_TYPE "ppc-instr-info"
45 #define GET_INSTRMAP_INFO
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "PPCGenInstrInfo.inc"
50 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
51 cl::desc("Disable analysis for CTR loops"));
53 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
54 cl::desc("Disable compare instruction optimization"), cl::Hidden);
56 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
57 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
61 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
62 cl::desc("Use the old (incorrect) instruction latency calculation"));
64 // Pin the vtable to this file.
65 void PPCInstrInfo::anchor() {}
67 PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
68 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
69 Subtarget(STI), RI(STI.getTargetMachine()) {}
71 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
72 /// this target when scheduling the DAG.
73 ScheduleHazardRecognizer *
74 PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
75 const ScheduleDAG *DAG) const {
77 static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
78 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
79 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
80 const InstrItineraryData *II =
81 static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
82 return new ScoreboardHazardRecognizer(II, DAG);
85 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
88 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
89 /// to use for this target when scheduling the DAG.
90 ScheduleHazardRecognizer *
91 PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
92 const ScheduleDAG *DAG) const {
94 DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
96 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
97 return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
99 // Most subtargets use a PPC970 recognizer.
100 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
101 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
102 assert(DAG->TII && "No InstrInfo?");
104 return new PPCHazardRecognizer970(*DAG);
107 return new ScoreboardHazardRecognizer(II, DAG);
110 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
111 const MachineInstr *MI,
112 unsigned *PredCost) const {
113 if (!ItinData || UseOldLatencyCalc)
114 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
116 // The default implementation of getInstrLatency calls getStageLatency, but
117 // getStageLatency does not do the right thing for us. While we have
118 // itinerary, most cores are fully pipelined, and so the itineraries only
119 // express the first part of the pipeline, not every stage. Instead, we need
120 // to use the listed output operand cycle number (using operand 0 here, which
123 unsigned Latency = 1;
124 unsigned DefClass = MI->getDesc().getSchedClass();
125 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
126 const MachineOperand &MO = MI->getOperand(i);
127 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
130 int Cycle = ItinData->getOperandCycle(DefClass, i);
134 Latency = std::max(Latency, (unsigned) Cycle);
140 int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
141 const MachineInstr *DefMI, unsigned DefIdx,
142 const MachineInstr *UseMI,
143 unsigned UseIdx) const {
144 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
147 if (!DefMI->getParent())
150 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
151 unsigned Reg = DefMO.getReg();
154 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
155 const MachineRegisterInfo *MRI =
156 &DefMI->getParent()->getParent()->getRegInfo();
157 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
158 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
160 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
161 PPC::CRBITRCRegClass.contains(Reg);
164 if (UseMI->isBranch() && IsRegCR) {
166 Latency = getInstrLatency(ItinData, DefMI);
168 // On some cores, there is an additional delay between writing to a condition
169 // register, and using it from a branch.
170 unsigned Directive = Subtarget.getDarwinDirective();
192 // This function does not list all associative and commutative operations, but
193 // only those worth feeding through the machine combiner in an attempt to
194 // reduce the critical path. Mostly, this means floating-point operations,
195 // because they have high latencies (compared to other operations, such and
196 // and/or, which are also associative and commutative, but have low latencies).
197 bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
198 switch (Inst.getOpcode()) {
231 bool PPCInstrInfo::getMachineCombinerPatterns(
233 SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
234 // Using the machine combiner in this way is potentially expensive, so
235 // restrict to when aggressive optimizations are desired.
236 if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive)
239 // FP reassociation is only legal when we don't need strict IEEE semantics.
240 if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath)
243 return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
246 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
247 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
248 unsigned &SrcReg, unsigned &DstReg,
249 unsigned &SubIdx) const {
250 switch (MI.getOpcode()) {
251 default: return false;
253 case PPC::EXTSW_32_64:
254 SrcReg = MI.getOperand(1).getReg();
255 DstReg = MI.getOperand(0).getReg();
256 SubIdx = PPC::sub_32;
261 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
262 int &FrameIndex) const {
263 // Note: This list must be kept consistent with LoadRegFromStackSlot.
264 switch (MI->getOpcode()) {
270 case PPC::RESTORE_CR:
271 case PPC::RESTORE_CRBIT:
277 case PPC::RESTORE_VRSAVE:
278 // Check for the operands added by addFrameReference (the immediate is the
279 // offset which defaults to 0).
280 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
281 MI->getOperand(2).isFI()) {
282 FrameIndex = MI->getOperand(2).getIndex();
283 return MI->getOperand(0).getReg();
290 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
291 int &FrameIndex) const {
292 // Note: This list must be kept consistent with StoreRegToStackSlot.
293 switch (MI->getOpcode()) {
300 case PPC::SPILL_CRBIT:
306 case PPC::SPILL_VRSAVE:
307 // Check for the operands added by addFrameReference (the immediate is the
308 // offset which defaults to 0).
309 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
310 MI->getOperand(2).isFI()) {
311 FrameIndex = MI->getOperand(2).getIndex();
312 return MI->getOperand(0).getReg();
319 MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr *MI,
322 unsigned OpIdx2) const {
323 MachineFunction &MF = *MI->getParent()->getParent();
325 // Normal instructions can be commuted the obvious way.
326 if (MI->getOpcode() != PPC::RLWIMI &&
327 MI->getOpcode() != PPC::RLWIMIo)
328 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
329 // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
330 // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
331 // changing the relative order of the mask operands might change what happens
332 // to the high-bits of the mask (and, thus, the result).
334 // Cannot commute if it has a non-zero rotate count.
335 if (MI->getOperand(3).getImm() != 0)
338 // If we have a zero rotate count, we have:
340 // Op0 = (Op1 & ~M) | (Op2 & M)
342 // M = mask((ME+1)&31, (MB-1)&31)
343 // Op0 = (Op2 & ~M) | (Op1 & M)
346 assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
347 "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
348 unsigned Reg0 = MI->getOperand(0).getReg();
349 unsigned Reg1 = MI->getOperand(1).getReg();
350 unsigned Reg2 = MI->getOperand(2).getReg();
351 unsigned SubReg1 = MI->getOperand(1).getSubReg();
352 unsigned SubReg2 = MI->getOperand(2).getSubReg();
353 bool Reg1IsKill = MI->getOperand(1).isKill();
354 bool Reg2IsKill = MI->getOperand(2).isKill();
355 bool ChangeReg0 = false;
356 // If machine instrs are no longer in two-address forms, update
357 // destination register as well.
359 // Must be two address instruction!
360 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
361 "Expecting a two-address instruction!");
362 assert(MI->getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
368 unsigned MB = MI->getOperand(4).getImm();
369 unsigned ME = MI->getOperand(5).getImm();
371 // We can't commute a trivial mask (there is no way to represent an all-zero
373 if (MB == 0 && ME == 31)
377 // Create a new instruction.
378 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
379 bool Reg0IsDead = MI->getOperand(0).isDead();
380 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
381 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
382 .addReg(Reg2, getKillRegState(Reg2IsKill))
383 .addReg(Reg1, getKillRegState(Reg1IsKill))
385 .addImm((MB-1) & 31);
389 MI->getOperand(0).setReg(Reg2);
390 MI->getOperand(0).setSubReg(SubReg2);
392 MI->getOperand(2).setReg(Reg1);
393 MI->getOperand(1).setReg(Reg2);
394 MI->getOperand(2).setSubReg(SubReg1);
395 MI->getOperand(1).setSubReg(SubReg2);
396 MI->getOperand(2).setIsKill(Reg1IsKill);
397 MI->getOperand(1).setIsKill(Reg2IsKill);
399 // Swap the mask around.
400 MI->getOperand(4).setImm((ME+1) & 31);
401 MI->getOperand(5).setImm((MB-1) & 31);
405 bool PPCInstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
406 unsigned &SrcOpIdx2) const {
407 // For VSX A-Type FMA instructions, it is the first two operands that can be
408 // commuted, however, because the non-encoded tied input operand is listed
409 // first, the operands to swap are actually the second and third.
411 int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode());
413 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
415 // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
417 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
420 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
421 MachineBasicBlock::iterator MI) const {
422 // This function is used for scheduling, and the nop wanted here is the type
423 // that terminates dispatch groups on the POWER cores.
424 unsigned Directive = Subtarget.getDarwinDirective();
427 default: Opcode = PPC::NOP; break;
428 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
429 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
430 case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
434 BuildMI(MBB, MI, DL, get(Opcode));
437 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
438 void PPCInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
439 NopInst.setOpcode(PPC::NOP);
443 // Note: If the condition register is set to CTR or CTR8 then this is a
444 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
445 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
446 MachineBasicBlock *&FBB,
447 SmallVectorImpl<MachineOperand> &Cond,
448 bool AllowModify) const {
449 bool isPPC64 = Subtarget.isPPC64();
451 // If the block has no terminators, it just falls into the block after it.
452 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
456 if (!isUnpredicatedTerminator(I))
459 // Get the last instruction in the block.
460 MachineInstr *LastInst = I;
462 // If there is only one terminator instruction, process it.
463 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
464 if (LastInst->getOpcode() == PPC::B) {
465 if (!LastInst->getOperand(0).isMBB())
467 TBB = LastInst->getOperand(0).getMBB();
469 } else if (LastInst->getOpcode() == PPC::BCC) {
470 if (!LastInst->getOperand(2).isMBB())
472 // Block ends with fall-through condbranch.
473 TBB = LastInst->getOperand(2).getMBB();
474 Cond.push_back(LastInst->getOperand(0));
475 Cond.push_back(LastInst->getOperand(1));
477 } else if (LastInst->getOpcode() == PPC::BC) {
478 if (!LastInst->getOperand(1).isMBB())
480 // Block ends with fall-through condbranch.
481 TBB = LastInst->getOperand(1).getMBB();
482 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
483 Cond.push_back(LastInst->getOperand(0));
485 } else if (LastInst->getOpcode() == PPC::BCn) {
486 if (!LastInst->getOperand(1).isMBB())
488 // Block ends with fall-through condbranch.
489 TBB = LastInst->getOperand(1).getMBB();
490 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
491 Cond.push_back(LastInst->getOperand(0));
493 } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
494 LastInst->getOpcode() == PPC::BDNZ) {
495 if (!LastInst->getOperand(0).isMBB())
497 if (DisableCTRLoopAnal)
499 TBB = LastInst->getOperand(0).getMBB();
500 Cond.push_back(MachineOperand::CreateImm(1));
501 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
504 } else if (LastInst->getOpcode() == PPC::BDZ8 ||
505 LastInst->getOpcode() == PPC::BDZ) {
506 if (!LastInst->getOperand(0).isMBB())
508 if (DisableCTRLoopAnal)
510 TBB = LastInst->getOperand(0).getMBB();
511 Cond.push_back(MachineOperand::CreateImm(0));
512 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
517 // Otherwise, don't know what this is.
521 // Get the instruction before it if it's a terminator.
522 MachineInstr *SecondLastInst = I;
524 // If there are three terminators, we don't know what sort of block this is.
525 if (SecondLastInst && I != MBB.begin() &&
526 isUnpredicatedTerminator(--I))
529 // If the block ends with PPC::B and PPC:BCC, handle it.
530 if (SecondLastInst->getOpcode() == PPC::BCC &&
531 LastInst->getOpcode() == PPC::B) {
532 if (!SecondLastInst->getOperand(2).isMBB() ||
533 !LastInst->getOperand(0).isMBB())
535 TBB = SecondLastInst->getOperand(2).getMBB();
536 Cond.push_back(SecondLastInst->getOperand(0));
537 Cond.push_back(SecondLastInst->getOperand(1));
538 FBB = LastInst->getOperand(0).getMBB();
540 } else if (SecondLastInst->getOpcode() == PPC::BC &&
541 LastInst->getOpcode() == PPC::B) {
542 if (!SecondLastInst->getOperand(1).isMBB() ||
543 !LastInst->getOperand(0).isMBB())
545 TBB = SecondLastInst->getOperand(1).getMBB();
546 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
547 Cond.push_back(SecondLastInst->getOperand(0));
548 FBB = LastInst->getOperand(0).getMBB();
550 } else if (SecondLastInst->getOpcode() == PPC::BCn &&
551 LastInst->getOpcode() == PPC::B) {
552 if (!SecondLastInst->getOperand(1).isMBB() ||
553 !LastInst->getOperand(0).isMBB())
555 TBB = SecondLastInst->getOperand(1).getMBB();
556 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
557 Cond.push_back(SecondLastInst->getOperand(0));
558 FBB = LastInst->getOperand(0).getMBB();
560 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
561 SecondLastInst->getOpcode() == PPC::BDNZ) &&
562 LastInst->getOpcode() == PPC::B) {
563 if (!SecondLastInst->getOperand(0).isMBB() ||
564 !LastInst->getOperand(0).isMBB())
566 if (DisableCTRLoopAnal)
568 TBB = SecondLastInst->getOperand(0).getMBB();
569 Cond.push_back(MachineOperand::CreateImm(1));
570 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
572 FBB = LastInst->getOperand(0).getMBB();
574 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
575 SecondLastInst->getOpcode() == PPC::BDZ) &&
576 LastInst->getOpcode() == PPC::B) {
577 if (!SecondLastInst->getOperand(0).isMBB() ||
578 !LastInst->getOperand(0).isMBB())
580 if (DisableCTRLoopAnal)
582 TBB = SecondLastInst->getOperand(0).getMBB();
583 Cond.push_back(MachineOperand::CreateImm(0));
584 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
586 FBB = LastInst->getOperand(0).getMBB();
590 // If the block ends with two PPC:Bs, handle it. The second one is not
591 // executed, so remove it.
592 if (SecondLastInst->getOpcode() == PPC::B &&
593 LastInst->getOpcode() == PPC::B) {
594 if (!SecondLastInst->getOperand(0).isMBB())
596 TBB = SecondLastInst->getOperand(0).getMBB();
599 I->eraseFromParent();
603 // Otherwise, can't handle this.
607 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
608 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
612 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
613 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
614 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
615 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
618 // Remove the branch.
619 I->eraseFromParent();
623 if (I == MBB.begin()) return 1;
625 if (I->getOpcode() != PPC::BCC &&
626 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
627 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
628 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
631 // Remove the branch.
632 I->eraseFromParent();
637 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
638 MachineBasicBlock *FBB,
639 ArrayRef<MachineOperand> Cond,
641 // Shouldn't be a fall through.
642 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
643 assert((Cond.size() == 2 || Cond.size() == 0) &&
644 "PPC branch conditions have two components!");
646 bool isPPC64 = Subtarget.isPPC64();
650 if (Cond.empty()) // Unconditional branch
651 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
652 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
653 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
654 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
655 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
656 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
657 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
658 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
659 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
660 else // Conditional branch
661 BuildMI(&MBB, DL, get(PPC::BCC))
662 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
666 // Two-way Conditional Branch.
667 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
668 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
669 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
670 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
671 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
672 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
673 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
674 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
676 BuildMI(&MBB, DL, get(PPC::BCC))
677 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
678 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
683 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
684 ArrayRef<MachineOperand> Cond,
685 unsigned TrueReg, unsigned FalseReg,
686 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
687 if (!Subtarget.hasISEL())
690 if (Cond.size() != 2)
693 // If this is really a bdnz-like condition, then it cannot be turned into a
695 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
698 // Check register classes.
699 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
700 const TargetRegisterClass *RC =
701 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
705 // isel is for regular integer GPRs only.
706 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
707 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
708 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
709 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
712 // FIXME: These numbers are for the A2, how well they work for other cores is
713 // an open question. On the A2, the isel instruction has a 2-cycle latency
714 // but single-cycle throughput. These numbers are used in combination with
715 // the MispredictPenalty setting from the active SchedMachineModel.
723 void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
724 MachineBasicBlock::iterator MI, DebugLoc dl,
725 unsigned DestReg, ArrayRef<MachineOperand> Cond,
726 unsigned TrueReg, unsigned FalseReg) const {
727 assert(Cond.size() == 2 &&
728 "PPC branch conditions have two components!");
730 assert(Subtarget.hasISEL() &&
731 "Cannot insert select on target without ISEL support");
733 // Get the register classes.
734 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
735 const TargetRegisterClass *RC =
736 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
737 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
739 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
740 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
742 PPC::GPRCRegClass.hasSubClassEq(RC) ||
743 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
744 "isel is for regular integer GPRs only");
746 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
747 auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
751 switch (SelectPred) {
753 case PPC::PRED_EQ_MINUS:
754 case PPC::PRED_EQ_PLUS:
755 SubIdx = PPC::sub_eq; SwapOps = false; break;
757 case PPC::PRED_NE_MINUS:
758 case PPC::PRED_NE_PLUS:
759 SubIdx = PPC::sub_eq; SwapOps = true; break;
761 case PPC::PRED_LT_MINUS:
762 case PPC::PRED_LT_PLUS:
763 SubIdx = PPC::sub_lt; SwapOps = false; break;
765 case PPC::PRED_GE_MINUS:
766 case PPC::PRED_GE_PLUS:
767 SubIdx = PPC::sub_lt; SwapOps = true; break;
769 case PPC::PRED_GT_MINUS:
770 case PPC::PRED_GT_PLUS:
771 SubIdx = PPC::sub_gt; SwapOps = false; break;
773 case PPC::PRED_LE_MINUS:
774 case PPC::PRED_LE_PLUS:
775 SubIdx = PPC::sub_gt; SwapOps = true; break;
777 case PPC::PRED_UN_MINUS:
778 case PPC::PRED_UN_PLUS:
779 SubIdx = PPC::sub_un; SwapOps = false; break;
781 case PPC::PRED_NU_MINUS:
782 case PPC::PRED_NU_PLUS:
783 SubIdx = PPC::sub_un; SwapOps = true; break;
784 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
785 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
788 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
789 SecondReg = SwapOps ? TrueReg : FalseReg;
791 // The first input register of isel cannot be r0. If it is a member
792 // of a register class that can be r0, then copy it first (the
793 // register allocator should eliminate the copy).
794 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
795 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
796 const TargetRegisterClass *FirstRC =
797 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
798 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
799 unsigned OldFirstReg = FirstReg;
800 FirstReg = MRI.createVirtualRegister(FirstRC);
801 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
802 .addReg(OldFirstReg);
805 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
806 .addReg(FirstReg).addReg(SecondReg)
807 .addReg(Cond[1].getReg(), 0, SubIdx);
810 static unsigned getCRBitValue(unsigned CRBit) {
812 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
813 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
814 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
815 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
817 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
818 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
819 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
820 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
822 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
823 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
824 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
825 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
827 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
828 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
829 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
830 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
833 assert(Ret != 4 && "Invalid CR bit register");
837 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
838 MachineBasicBlock::iterator I, DebugLoc DL,
839 unsigned DestReg, unsigned SrcReg,
840 bool KillSrc) const {
841 // We can end up with self copies and similar things as a result of VSX copy
842 // legalization. Promote them here.
843 const TargetRegisterInfo *TRI = &getRegisterInfo();
844 if (PPC::F8RCRegClass.contains(DestReg) &&
845 PPC::VSRCRegClass.contains(SrcReg)) {
847 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
849 if (VSXSelfCopyCrash && SrcReg == SuperReg)
850 llvm_unreachable("nop VSX copy");
853 } else if (PPC::VRRCRegClass.contains(DestReg) &&
854 PPC::VSRCRegClass.contains(SrcReg)) {
856 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass);
858 if (VSXSelfCopyCrash && SrcReg == SuperReg)
859 llvm_unreachable("nop VSX copy");
862 } else if (PPC::F8RCRegClass.contains(SrcReg) &&
863 PPC::VSRCRegClass.contains(DestReg)) {
865 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
867 if (VSXSelfCopyCrash && DestReg == SuperReg)
868 llvm_unreachable("nop VSX copy");
871 } else if (PPC::VRRCRegClass.contains(SrcReg) &&
872 PPC::VSRCRegClass.contains(DestReg)) {
874 TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass);
876 if (VSXSelfCopyCrash && DestReg == SuperReg)
877 llvm_unreachable("nop VSX copy");
882 // Different class register copy
883 if (PPC::CRBITRCRegClass.contains(SrcReg) &&
884 PPC::GPRCRegClass.contains(DestReg)) {
885 unsigned CRReg = getCRFromCRBit(SrcReg);
886 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
887 .addReg(CRReg), getKillRegState(KillSrc);
888 // Rotate the CR bit in the CR fields to be the least significant bit and
889 // then mask with 0x1 (MB = ME = 31).
890 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
891 .addReg(DestReg, RegState::Kill)
892 .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
896 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
897 PPC::G8RCRegClass.contains(DestReg)) {
898 BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg)
899 .addReg(SrcReg), getKillRegState(KillSrc);
901 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
902 PPC::GPRCRegClass.contains(DestReg)) {
903 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
904 .addReg(SrcReg), getKillRegState(KillSrc);
909 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
911 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
913 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
915 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
917 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
919 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
920 // There are two different ways this can be done:
921 // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
922 // issue in VSU pipeline 0.
923 // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
924 // can go to either pipeline.
925 // We'll always use xxlor here, because in practically all cases where
926 // copies are generated, they are close enough to some use that the
927 // lower-latency form is preferable.
929 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
930 PPC::VSSRCRegClass.contains(DestReg, SrcReg))
932 else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
934 else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
936 else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
938 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
941 llvm_unreachable("Impossible reg-to-reg copy");
943 const MCInstrDesc &MCID = get(Opc);
944 if (MCID.getNumOperands() == 3)
945 BuildMI(MBB, I, DL, MCID, DestReg)
946 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
948 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
951 // This function returns true if a CR spill is necessary and false otherwise.
953 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
954 unsigned SrcReg, bool isKill,
956 const TargetRegisterClass *RC,
957 SmallVectorImpl<MachineInstr*> &NewMIs,
958 bool &NonRI, bool &SpillsVRS) const{
959 // Note: If additional store instructions are added here,
960 // update isStoreToStackSlot.
963 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
964 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
965 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
967 getKillRegState(isKill)),
969 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
970 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
971 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
973 getKillRegState(isKill)),
975 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
976 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
978 getKillRegState(isKill)),
980 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
981 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
983 getKillRegState(isKill)),
985 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
986 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
988 getKillRegState(isKill)),
991 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
992 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
994 getKillRegState(isKill)),
997 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
998 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
1000 getKillRegState(isKill)),
1003 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1004 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X))
1006 getKillRegState(isKill)),
1009 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1010 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSDX))
1012 getKillRegState(isKill)),
1015 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1016 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSSPX))
1018 getKillRegState(isKill)),
1021 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1022 assert(Subtarget.isDarwin() &&
1023 "VRSAVE only needs spill/restore on Darwin");
1024 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
1026 getKillRegState(isKill)),
1029 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1030 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX))
1032 getKillRegState(isKill)),
1035 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1036 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs))
1038 getKillRegState(isKill)),
1041 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1042 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb))
1044 getKillRegState(isKill)),
1048 llvm_unreachable("Unknown regclass!");
1055 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1056 MachineBasicBlock::iterator MI,
1057 unsigned SrcReg, bool isKill, int FrameIdx,
1058 const TargetRegisterClass *RC,
1059 const TargetRegisterInfo *TRI) const {
1060 MachineFunction &MF = *MBB.getParent();
1061 SmallVector<MachineInstr*, 4> NewMIs;
1063 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1064 FuncInfo->setHasSpills();
1066 bool NonRI = false, SpillsVRS = false;
1067 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
1069 FuncInfo->setSpillsCR();
1072 FuncInfo->setSpillsVRSAVE();
1075 FuncInfo->setHasNonRISpills();
1077 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1078 MBB.insert(MI, NewMIs[i]);
1080 const MachineFrameInfo &MFI = *MF.getFrameInfo();
1081 MachineMemOperand *MMO = MF.getMachineMemOperand(
1082 MachinePointerInfo::getFixedStack(MF, FrameIdx),
1083 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx),
1084 MFI.getObjectAlignment(FrameIdx));
1085 NewMIs.back()->addMemOperand(MF, MMO);
1089 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
1090 unsigned DestReg, int FrameIdx,
1091 const TargetRegisterClass *RC,
1092 SmallVectorImpl<MachineInstr*> &NewMIs,
1093 bool &NonRI, bool &SpillsVRS) const{
1094 // Note: If additional load instructions are added here,
1095 // update isLoadFromStackSlot.
1097 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1098 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1099 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
1100 DestReg), FrameIdx));
1101 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1102 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1103 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
1105 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1106 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
1108 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1109 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
1111 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1112 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1113 get(PPC::RESTORE_CR), DestReg),
1116 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1117 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1118 get(PPC::RESTORE_CRBIT), DestReg),
1121 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1122 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
1125 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1126 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXVD2X), DestReg),
1129 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1130 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSDX), DestReg),
1133 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1134 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSSPX), DestReg),
1137 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1138 assert(Subtarget.isDarwin() &&
1139 "VRSAVE only needs spill/restore on Darwin");
1140 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1141 get(PPC::RESTORE_VRSAVE),
1145 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1146 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDX), DestReg),
1149 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1150 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFSXs), DestReg),
1153 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1154 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDXb), DestReg),
1158 llvm_unreachable("Unknown regclass!");
1165 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1166 MachineBasicBlock::iterator MI,
1167 unsigned DestReg, int FrameIdx,
1168 const TargetRegisterClass *RC,
1169 const TargetRegisterInfo *TRI) const {
1170 MachineFunction &MF = *MBB.getParent();
1171 SmallVector<MachineInstr*, 4> NewMIs;
1173 if (MI != MBB.end()) DL = MI->getDebugLoc();
1175 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1176 FuncInfo->setHasSpills();
1178 bool NonRI = false, SpillsVRS = false;
1179 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
1181 FuncInfo->setSpillsCR();
1184 FuncInfo->setSpillsVRSAVE();
1187 FuncInfo->setHasNonRISpills();
1189 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1190 MBB.insert(MI, NewMIs[i]);
1192 const MachineFrameInfo &MFI = *MF.getFrameInfo();
1193 MachineMemOperand *MMO = MF.getMachineMemOperand(
1194 MachinePointerInfo::getFixedStack(MF, FrameIdx),
1195 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx),
1196 MFI.getObjectAlignment(FrameIdx));
1197 NewMIs.back()->addMemOperand(MF, MMO);
1201 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1202 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1203 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1204 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1206 // Leave the CR# the same, but invert the condition.
1207 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1211 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
1212 unsigned Reg, MachineRegisterInfo *MRI) const {
1213 // For some instructions, it is legal to fold ZERO into the RA register field.
1214 // A zero immediate should always be loaded with a single li.
1215 unsigned DefOpc = DefMI->getOpcode();
1216 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1218 if (!DefMI->getOperand(1).isImm())
1220 if (DefMI->getOperand(1).getImm() != 0)
1223 // Note that we cannot here invert the arguments of an isel in order to fold
1224 // a ZERO into what is presented as the second argument. All we have here
1225 // is the condition bit, and that might come from a CR-logical bit operation.
1227 const MCInstrDesc &UseMCID = UseMI->getDesc();
1229 // Only fold into real machine instructions.
1230 if (UseMCID.isPseudo())
1234 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
1235 if (UseMI->getOperand(UseIdx).isReg() &&
1236 UseMI->getOperand(UseIdx).getReg() == Reg)
1239 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
1240 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1242 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1244 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1245 // register (which might also be specified as a pointer class kind).
1246 if (UseInfo->isLookupPtrRegClass()) {
1247 if (UseInfo->RegClass /* Kind */ != 1)
1250 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1251 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1255 // Make sure this is not tied to an output register (or otherwise
1256 // constrained). This is true for ST?UX registers, for example, which
1257 // are tied to their output registers.
1258 if (UseInfo->Constraints != 0)
1262 if (UseInfo->isLookupPtrRegClass()) {
1263 bool isPPC64 = Subtarget.isPPC64();
1264 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1266 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1267 PPC::ZERO8 : PPC::ZERO;
1270 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1271 UseMI->getOperand(UseIdx).setReg(ZeroReg);
1274 DefMI->eraseFromParent();
1279 static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
1280 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1282 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1287 // We should make sure that, if we're going to predicate both sides of a
1288 // condition (a diamond), that both sides don't define the counter register. We
1289 // can predicate counter-decrement-based branches, but while that predicates
1290 // the branching, it does not predicate the counter decrement. If we tried to
1291 // merge the triangle into one predicated block, we'd decrement the counter
1293 bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
1294 unsigned NumT, unsigned ExtraT,
1295 MachineBasicBlock &FMBB,
1296 unsigned NumF, unsigned ExtraF,
1297 BranchProbability Probability) const {
1298 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1302 bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
1303 // The predicated branches are identified by their type, not really by the
1304 // explicit presence of a predicate. Furthermore, some of them can be
1305 // predicated more than once. Because if conversion won't try to predicate
1306 // any instruction which already claims to be predicated (by returning true
1307 // here), always return false. In doing so, we let isPredicable() be the
1308 // final word on whether not the instruction can be (further) predicated.
1313 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1314 if (!MI->isTerminator())
1317 // Conditional branch is a special case.
1318 if (MI->isBranch() && !MI->isBarrier())
1321 return !isPredicated(MI);
1324 bool PPCInstrInfo::PredicateInstruction(MachineInstr *MI,
1325 ArrayRef<MachineOperand> Pred) const {
1326 unsigned OpC = MI->getOpcode();
1327 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1328 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1329 bool isPPC64 = Subtarget.isPPC64();
1330 MI->setDesc(get(Pred[0].getImm() ?
1331 (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
1332 (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1333 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1334 MI->setDesc(get(PPC::BCLR));
1335 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1336 .addReg(Pred[1].getReg());
1337 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1338 MI->setDesc(get(PPC::BCLRn));
1339 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1340 .addReg(Pred[1].getReg());
1342 MI->setDesc(get(PPC::BCCLR));
1343 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1344 .addImm(Pred[0].getImm())
1345 .addReg(Pred[1].getReg());
1349 } else if (OpC == PPC::B) {
1350 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1351 bool isPPC64 = Subtarget.isPPC64();
1352 MI->setDesc(get(Pred[0].getImm() ?
1353 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1354 (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1355 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1356 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1357 MI->RemoveOperand(0);
1359 MI->setDesc(get(PPC::BC));
1360 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1361 .addReg(Pred[1].getReg())
1363 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1364 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1365 MI->RemoveOperand(0);
1367 MI->setDesc(get(PPC::BCn));
1368 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1369 .addReg(Pred[1].getReg())
1372 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1373 MI->RemoveOperand(0);
1375 MI->setDesc(get(PPC::BCC));
1376 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1377 .addImm(Pred[0].getImm())
1378 .addReg(Pred[1].getReg())
1383 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1384 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1385 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1386 llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1388 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1389 bool isPPC64 = Subtarget.isPPC64();
1391 if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1392 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
1393 (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1394 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1395 .addReg(Pred[1].getReg());
1397 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1398 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) :
1399 (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1400 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1401 .addReg(Pred[1].getReg());
1405 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) :
1406 (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1407 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1408 .addImm(Pred[0].getImm())
1409 .addReg(Pred[1].getReg());
1416 bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1417 ArrayRef<MachineOperand> Pred2) const {
1418 assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1419 assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1421 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1423 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1426 // P1 can only subsume P2 if they test the same condition register.
1427 if (Pred1[1].getReg() != Pred2[1].getReg())
1430 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1431 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1436 // Does P1 subsume P2, e.g. GE subsumes GT.
1437 if (P1 == PPC::PRED_LE &&
1438 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1440 if (P1 == PPC::PRED_GE &&
1441 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1447 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
1448 std::vector<MachineOperand> &Pred) const {
1449 // Note: At the present time, the contents of Pred from this function is
1450 // unused by IfConversion. This implementation follows ARM by pushing the
1451 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1452 // predicate, instructions defining CTR or CTR8 are also included as
1453 // predicate-defining instructions.
1455 const TargetRegisterClass *RCs[] =
1456 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1457 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1460 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1461 const MachineOperand &MO = MI->getOperand(i);
1462 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1463 const TargetRegisterClass *RC = RCs[c];
1465 if (MO.isDef() && RC->contains(MO.getReg())) {
1469 } else if (MO.isRegMask()) {
1470 for (TargetRegisterClass::iterator I = RC->begin(),
1471 IE = RC->end(); I != IE; ++I)
1472 if (MO.clobbersPhysReg(*I)) {
1483 bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
1484 unsigned OpC = MI->getOpcode();
1499 bool PPCInstrInfo::analyzeCompare(const MachineInstr *MI,
1500 unsigned &SrcReg, unsigned &SrcReg2,
1501 int &Mask, int &Value) const {
1502 unsigned Opc = MI->getOpcode();
1505 default: return false;
1510 SrcReg = MI->getOperand(1).getReg();
1512 Value = MI->getOperand(2).getImm();
1521 SrcReg = MI->getOperand(1).getReg();
1522 SrcReg2 = MI->getOperand(2).getReg();
1527 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
1528 unsigned SrcReg, unsigned SrcReg2,
1529 int Mask, int Value,
1530 const MachineRegisterInfo *MRI) const {
1534 int OpC = CmpInstr->getOpcode();
1535 unsigned CRReg = CmpInstr->getOperand(0).getReg();
1537 // FP record forms set CR1 based on the execption status bits, not a
1538 // comparison with zero.
1539 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1542 // The record forms set the condition register based on a signed comparison
1543 // with zero (so says the ISA manual). This is not as straightforward as it
1544 // seems, however, because this is always a 64-bit comparison on PPC64, even
1545 // for instructions that are 32-bit in nature (like slw for example).
1546 // So, on PPC32, for unsigned comparisons, we can use the record forms only
1547 // for equality checks (as those don't depend on the sign). On PPC64,
1548 // we are restricted to equality for unsigned 64-bit comparisons and for
1549 // signed 32-bit comparisons the applicability is more restricted.
1550 bool isPPC64 = Subtarget.isPPC64();
1551 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1552 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1553 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1555 // Get the unique definition of SrcReg.
1556 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1557 if (!MI) return false;
1558 int MIOpC = MI->getOpcode();
1560 bool equalityOnly = false;
1563 if (is32BitSignedCompare) {
1564 // We can perform this optimization only if MI is sign-extending.
1565 if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
1566 MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1567 MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1568 MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1569 MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1573 } else if (is32BitUnsignedCompare) {
1574 // We can perform this optimization, equality only, if MI is
1576 if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1577 MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
1578 MIOpC == PPC::SRW || MIOpC == PPC::SRWo) {
1580 equalityOnly = true;
1584 equalityOnly = is64BitUnsignedCompare;
1586 equalityOnly = is32BitUnsignedCompare;
1589 // We need to check the uses of the condition register in order to reject
1590 // non-equality comparisons.
1591 for (MachineRegisterInfo::use_instr_iterator I =MRI->use_instr_begin(CRReg),
1592 IE = MRI->use_instr_end(); I != IE; ++I) {
1593 MachineInstr *UseMI = &*I;
1594 if (UseMI->getOpcode() == PPC::BCC) {
1595 unsigned Pred = UseMI->getOperand(0).getImm();
1596 if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE)
1598 } else if (UseMI->getOpcode() == PPC::ISEL ||
1599 UseMI->getOpcode() == PPC::ISEL8) {
1600 unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1601 if (SubIdx != PPC::sub_eq)
1608 MachineBasicBlock::iterator I = CmpInstr;
1610 // Scan forward to find the first use of the compare.
1611 for (MachineBasicBlock::iterator EL = CmpInstr->getParent()->end();
1613 bool FoundUse = false;
1614 for (MachineRegisterInfo::use_instr_iterator J =MRI->use_instr_begin(CRReg),
1615 JE = MRI->use_instr_end(); J != JE; ++J)
1625 // There are two possible candidates which can be changed to set CR[01].
1626 // One is MI, the other is a SUB instruction.
1627 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1628 MachineInstr *Sub = nullptr;
1630 // MI is not a candidate for CMPrr.
1632 // FIXME: Conservatively refuse to convert an instruction which isn't in the
1633 // same BB as the comparison. This is to allow the check below to avoid calls
1634 // (and other explicit clobbers); instead we should really check for these
1635 // more explicitly (in at least a few predecessors).
1636 else if (MI->getParent() != CmpInstr->getParent() || Value != 0) {
1637 // PPC does not have a record-form SUBri.
1642 const TargetRegisterInfo *TRI = &getRegisterInfo();
1645 // Get ready to iterate backward from CmpInstr.
1646 MachineBasicBlock::iterator E = MI,
1647 B = CmpInstr->getParent()->begin();
1649 for (; I != E && !noSub; --I) {
1650 const MachineInstr &Instr = *I;
1651 unsigned IOpC = Instr.getOpcode();
1653 if (&*I != CmpInstr && (
1654 Instr.modifiesRegister(PPC::CR0, TRI) ||
1655 Instr.readsRegister(PPC::CR0, TRI)))
1656 // This instruction modifies or uses the record condition register after
1657 // the one we want to change. While we could do this transformation, it
1658 // would likely not be profitable. This transformation removes one
1659 // instruction, and so even forcing RA to generate one move probably
1660 // makes it unprofitable.
1663 // Check whether CmpInstr can be made redundant by the current instruction.
1664 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1665 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1666 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1667 ((Instr.getOperand(1).getReg() == SrcReg &&
1668 Instr.getOperand(2).getReg() == SrcReg2) ||
1669 (Instr.getOperand(1).getReg() == SrcReg2 &&
1670 Instr.getOperand(2).getReg() == SrcReg))) {
1676 // The 'and' is below the comparison instruction.
1680 // Return false if no candidates exist.
1684 // The single candidate is called MI.
1688 MIOpC = MI->getOpcode();
1689 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1692 NewOpC = PPC::getRecordFormOpcode(MIOpC);
1693 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1697 // FIXME: On the non-embedded POWER architectures, only some of the record
1698 // forms are fast, and we should use only the fast ones.
1700 // The defining instruction has a record form (or is already a record
1701 // form). It is possible, however, that we'll need to reverse the condition
1702 // code of the users.
1706 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
1707 SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
1709 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1710 // needs to be updated to be based on SUB. Push the condition code
1711 // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1712 // condition code of these operands will be modified.
1713 bool ShouldSwap = false;
1715 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1716 Sub->getOperand(2).getReg() == SrcReg;
1718 // The operands to subf are the opposite of sub, so only in the fixed-point
1719 // case, invert the order.
1720 ShouldSwap = !ShouldSwap;
1724 for (MachineRegisterInfo::use_instr_iterator
1725 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1727 MachineInstr *UseMI = &*I;
1728 if (UseMI->getOpcode() == PPC::BCC) {
1729 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1730 assert((!equalityOnly ||
1731 Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) &&
1732 "Invalid predicate for equality-only optimization");
1733 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1734 PPC::getSwappedPredicate(Pred)));
1735 } else if (UseMI->getOpcode() == PPC::ISEL ||
1736 UseMI->getOpcode() == PPC::ISEL8) {
1737 unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1738 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1739 "Invalid CR bit for equality-only optimization");
1741 if (NewSubReg == PPC::sub_lt)
1742 NewSubReg = PPC::sub_gt;
1743 else if (NewSubReg == PPC::sub_gt)
1744 NewSubReg = PPC::sub_lt;
1746 SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1748 } else // We need to abort on a user we don't understand.
1752 // Create a new virtual register to hold the value of the CR set by the
1753 // record-form instruction. If the instruction was not previously in
1754 // record form, then set the kill flag on the CR.
1755 CmpInstr->eraseFromParent();
1757 MachineBasicBlock::iterator MII = MI;
1758 BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1759 get(TargetOpcode::COPY), CRReg)
1760 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1762 if (MIOpC != NewOpC) {
1763 // We need to be careful here: we're replacing one instruction with
1764 // another, and we need to make sure that we get all of the right
1765 // implicit uses and defs. On the other hand, the caller may be holding
1766 // an iterator to this instruction, and so we can't delete it (this is
1767 // specifically the case if this is the instruction directly after the
1770 const MCInstrDesc &NewDesc = get(NewOpC);
1771 MI->setDesc(NewDesc);
1773 if (NewDesc.ImplicitDefs)
1774 for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1775 *ImpDefs; ++ImpDefs)
1776 if (!MI->definesRegister(*ImpDefs))
1777 MI->addOperand(*MI->getParent()->getParent(),
1778 MachineOperand::CreateReg(*ImpDefs, true, true));
1779 if (NewDesc.ImplicitUses)
1780 for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1781 *ImpUses; ++ImpUses)
1782 if (!MI->readsRegister(*ImpUses))
1783 MI->addOperand(*MI->getParent()->getParent(),
1784 MachineOperand::CreateReg(*ImpUses, false, true));
1787 // Modify the condition code of operands in OperandsToUpdate.
1788 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1789 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1790 for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1791 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1793 for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1794 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1799 /// GetInstSize - Return the number of bytes of code the specified
1800 /// instruction may be. This returns the maximum number of bytes.
1802 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
1803 unsigned Opcode = MI->getOpcode();
1805 if (Opcode == PPC::INLINEASM) {
1806 const MachineFunction *MF = MI->getParent()->getParent();
1807 const char *AsmStr = MI->getOperand(0).getSymbolName();
1808 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1809 } else if (Opcode == TargetOpcode::STACKMAP) {
1810 return MI->getOperand(1).getImm();
1811 } else if (Opcode == TargetOpcode::PATCHPOINT) {
1812 PatchPointOpers Opers(MI);
1813 return Opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
1815 const MCInstrDesc &Desc = get(Opcode);
1816 return Desc.getSize();
1820 std::pair<unsigned, unsigned>
1821 PPCInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
1822 const unsigned Mask = PPCII::MO_ACCESS_MASK;
1823 return std::make_pair(TF & Mask, TF & ~Mask);
1826 ArrayRef<std::pair<unsigned, const char *>>
1827 PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
1828 using namespace PPCII;
1829 static const std::pair<unsigned, const char *> TargetFlags[] = {
1832 {MO_TPREL_LO, "ppc-tprel-lo"},
1833 {MO_TPREL_HA, "ppc-tprel-ha"},
1834 {MO_DTPREL_LO, "ppc-dtprel-lo"},
1835 {MO_TLSLD_LO, "ppc-tlsld-lo"},
1836 {MO_TOC_LO, "ppc-toc-lo"},
1837 {MO_TLS, "ppc-tls"}};
1838 return makeArrayRef(TargetFlags);
1841 ArrayRef<std::pair<unsigned, const char *>>
1842 PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
1843 using namespace PPCII;
1844 static const std::pair<unsigned, const char *> TargetFlags[] = {
1845 {MO_PLT_OR_STUB, "ppc-plt-or-stub"},
1846 {MO_PIC_FLAG, "ppc-pic"},
1847 {MO_NLP_FLAG, "ppc-nlp"},
1848 {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
1849 return makeArrayRef(TargetFlags);