1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPredicates.h"
18 #include "PPCGenInstrInfo.inc"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Target/TargetAsmInfo.h"
26 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
27 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
29 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
30 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
31 RI(*TM.getSubtargetImpl(), *this) {}
33 /// getPointerRegClass - Return the register class to use to hold pointers.
34 /// This is used for addressing modes.
35 const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
36 if (TM.getSubtargetImpl()->isPPC64())
37 return &PPC::G8RCRegClass;
39 return &PPC::GPRCRegClass;
43 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
45 unsigned& destReg) const {
46 unsigned oc = MI.getOpcode();
47 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
48 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
49 assert(MI.getNumOperands() >= 3 &&
50 MI.getOperand(0).isReg() &&
51 MI.getOperand(1).isReg() &&
52 MI.getOperand(2).isReg() &&
53 "invalid PPC OR instruction!");
54 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
55 sourceReg = MI.getOperand(1).getReg();
56 destReg = MI.getOperand(0).getReg();
59 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
60 assert(MI.getNumOperands() >= 3 &&
61 MI.getOperand(0).isReg() &&
62 MI.getOperand(2).isImm() &&
63 "invalid PPC ADDI instruction!");
64 if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
65 sourceReg = MI.getOperand(1).getReg();
66 destReg = MI.getOperand(0).getReg();
69 } else if (oc == PPC::ORI) { // ori r1, r2, 0
70 assert(MI.getNumOperands() >= 3 &&
71 MI.getOperand(0).isReg() &&
72 MI.getOperand(1).isReg() &&
73 MI.getOperand(2).isImm() &&
74 "invalid PPC ORI instruction!");
75 if (MI.getOperand(2).getImm() == 0) {
76 sourceReg = MI.getOperand(1).getReg();
77 destReg = MI.getOperand(0).getReg();
80 } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
81 oc == PPC::FMRSD) { // fmr r1, r2
82 assert(MI.getNumOperands() >= 2 &&
83 MI.getOperand(0).isReg() &&
84 MI.getOperand(1).isReg() &&
85 "invalid PPC FMR instruction");
86 sourceReg = MI.getOperand(1).getReg();
87 destReg = MI.getOperand(0).getReg();
89 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
90 assert(MI.getNumOperands() >= 2 &&
91 MI.getOperand(0).isReg() &&
92 MI.getOperand(1).isReg() &&
93 "invalid PPC MCRF instruction");
94 sourceReg = MI.getOperand(1).getReg();
95 destReg = MI.getOperand(0).getReg();
101 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
102 int &FrameIndex) const {
103 switch (MI->getOpcode()) {
109 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
110 MI->getOperand(2).isFI()) {
111 FrameIndex = MI->getOperand(2).getIndex();
112 return MI->getOperand(0).getReg();
119 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
120 int &FrameIndex) const {
121 switch (MI->getOpcode()) {
127 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
128 MI->getOperand(2).isFI()) {
129 FrameIndex = MI->getOperand(2).getIndex();
130 return MI->getOperand(0).getReg();
137 // commuteInstruction - We can commute rlwimi instructions, but only if the
138 // rotate amt is zero. We also have to munge the immediates a bit.
140 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
141 MachineFunction &MF = *MI->getParent()->getParent();
143 // Normal instructions can be commuted the obvious way.
144 if (MI->getOpcode() != PPC::RLWIMI)
145 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
147 // Cannot commute if it has a non-zero rotate count.
148 if (MI->getOperand(3).getImm() != 0)
151 // If we have a zero rotate count, we have:
153 // Op0 = (Op1 & ~M) | (Op2 & M)
155 // M = mask((ME+1)&31, (MB-1)&31)
156 // Op0 = (Op2 & ~M) | (Op1 & M)
159 unsigned Reg0 = MI->getOperand(0).getReg();
160 unsigned Reg1 = MI->getOperand(1).getReg();
161 unsigned Reg2 = MI->getOperand(2).getReg();
162 bool Reg1IsKill = MI->getOperand(1).isKill();
163 bool Reg2IsKill = MI->getOperand(2).isKill();
164 bool ChangeReg0 = false;
165 // If machine instrs are no longer in two-address forms, update
166 // destination register as well.
168 // Must be two address instruction!
169 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
170 "Expecting a two-address instruction!");
176 unsigned MB = MI->getOperand(4).getImm();
177 unsigned ME = MI->getOperand(5).getImm();
180 // Create a new instruction.
181 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
182 bool Reg0IsDead = MI->getOperand(0).isDead();
183 return BuildMI(MF, MI->getDesc())
184 .addReg(Reg0, true, false, false, Reg0IsDead)
185 .addReg(Reg2, false, false, Reg2IsKill)
186 .addReg(Reg1, false, false, Reg1IsKill)
188 .addImm((MB-1) & 31);
192 MI->getOperand(0).setReg(Reg2);
193 MI->getOperand(2).setReg(Reg1);
194 MI->getOperand(1).setReg(Reg2);
195 MI->getOperand(2).setIsKill(Reg1IsKill);
196 MI->getOperand(1).setIsKill(Reg2IsKill);
198 // Swap the mask around.
199 MI->getOperand(4).setImm((ME+1) & 31);
200 MI->getOperand(5).setImm((MB-1) & 31);
204 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
205 MachineBasicBlock::iterator MI) const {
206 BuildMI(MBB, MI, get(PPC::NOP));
211 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
212 MachineBasicBlock *&FBB,
213 SmallVectorImpl<MachineOperand> &Cond) const {
214 // If the block has no terminators, it just falls into the block after it.
215 MachineBasicBlock::iterator I = MBB.end();
216 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
219 // Get the last instruction in the block.
220 MachineInstr *LastInst = I;
222 // If there is only one terminator instruction, process it.
223 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
224 if (LastInst->getOpcode() == PPC::B) {
225 TBB = LastInst->getOperand(0).getMBB();
227 } else if (LastInst->getOpcode() == PPC::BCC) {
228 // Block ends with fall-through condbranch.
229 TBB = LastInst->getOperand(2).getMBB();
230 Cond.push_back(LastInst->getOperand(0));
231 Cond.push_back(LastInst->getOperand(1));
234 // Otherwise, don't know what this is.
238 // Get the instruction before it if it's a terminator.
239 MachineInstr *SecondLastInst = I;
241 // If there are three terminators, we don't know what sort of block this is.
242 if (SecondLastInst && I != MBB.begin() &&
243 isUnpredicatedTerminator(--I))
246 // If the block ends with PPC::B and PPC:BCC, handle it.
247 if (SecondLastInst->getOpcode() == PPC::BCC &&
248 LastInst->getOpcode() == PPC::B) {
249 TBB = SecondLastInst->getOperand(2).getMBB();
250 Cond.push_back(SecondLastInst->getOperand(0));
251 Cond.push_back(SecondLastInst->getOperand(1));
252 FBB = LastInst->getOperand(0).getMBB();
256 // If the block ends with two PPC:Bs, handle it. The second one is not
257 // executed, so remove it.
258 if (SecondLastInst->getOpcode() == PPC::B &&
259 LastInst->getOpcode() == PPC::B) {
260 TBB = SecondLastInst->getOperand(0).getMBB();
262 I->eraseFromParent();
266 // Otherwise, can't handle this.
270 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
271 MachineBasicBlock::iterator I = MBB.end();
272 if (I == MBB.begin()) return 0;
274 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
277 // Remove the branch.
278 I->eraseFromParent();
282 if (I == MBB.begin()) return 1;
284 if (I->getOpcode() != PPC::BCC)
287 // Remove the branch.
288 I->eraseFromParent();
293 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
294 MachineBasicBlock *FBB,
295 const SmallVectorImpl<MachineOperand> &Cond) const {
296 // Shouldn't be a fall through.
297 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
298 assert((Cond.size() == 2 || Cond.size() == 0) &&
299 "PPC branch conditions have two components!");
303 if (Cond.empty()) // Unconditional branch
304 BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
305 else // Conditional branch
306 BuildMI(&MBB, get(PPC::BCC))
307 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
311 // Two-way Conditional Branch.
312 BuildMI(&MBB, get(PPC::BCC))
313 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
314 BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
318 bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
319 MachineBasicBlock::iterator MI,
320 unsigned DestReg, unsigned SrcReg,
321 const TargetRegisterClass *DestRC,
322 const TargetRegisterClass *SrcRC) const {
323 if (DestRC != SrcRC) {
324 // Not yet supported!
328 if (DestRC == PPC::GPRCRegisterClass) {
329 BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
330 } else if (DestRC == PPC::G8RCRegisterClass) {
331 BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
332 } else if (DestRC == PPC::F4RCRegisterClass) {
333 BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg);
334 } else if (DestRC == PPC::F8RCRegisterClass) {
335 BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg);
336 } else if (DestRC == PPC::CRRCRegisterClass) {
337 BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg);
338 } else if (DestRC == PPC::VRRCRegisterClass) {
339 BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
340 } else if (DestRC == PPC::CRBITRCRegisterClass) {
341 BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
343 // Attempt to copy register that is not GPR or FPR
351 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
352 unsigned SrcReg, bool isKill,
354 const TargetRegisterClass *RC,
355 SmallVectorImpl<MachineInstr*> &NewMIs) const{
356 if (RC == PPC::GPRCRegisterClass) {
357 if (SrcReg != PPC::LR) {
358 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
359 .addReg(SrcReg, false, false, isKill),
362 // FIXME: this spills LR immediately to memory in one step. To do this,
363 // we use R11, which we know cannot be used in the prolog/epilog. This is
365 NewMIs.push_back(BuildMI(MF, get(PPC::MFLR), PPC::R11));
366 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
367 .addReg(PPC::R11, false, false, isKill),
370 } else if (RC == PPC::G8RCRegisterClass) {
371 if (SrcReg != PPC::LR8) {
372 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
373 .addReg(SrcReg, false, false, isKill), FrameIdx));
375 // FIXME: this spills LR immediately to memory in one step. To do this,
376 // we use R11, which we know cannot be used in the prolog/epilog. This is
378 NewMIs.push_back(BuildMI(MF, get(PPC::MFLR8), PPC::X11));
379 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
380 .addReg(PPC::X11, false, false, isKill), FrameIdx));
382 } else if (RC == PPC::F8RCRegisterClass) {
383 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFD))
384 .addReg(SrcReg, false, false, isKill), FrameIdx));
385 } else if (RC == PPC::F4RCRegisterClass) {
386 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFS))
387 .addReg(SrcReg, false, false, isKill), FrameIdx));
388 } else if (RC == PPC::CRRCRegisterClass) {
389 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
390 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
391 // FIXME (64-bit): Enable
392 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::SPILL_CR))
393 .addReg(SrcReg, false, false, isKill),
397 // FIXME: We use R0 here, because it isn't available for RA. We need to
398 // store the CR in the low 4-bits of the saved value. First, issue a MFCR
399 // to save all of the CRBits.
400 NewMIs.push_back(BuildMI(MF, get(PPC::MFCR), PPC::R0));
402 // If the saved register wasn't CR0, shift the bits left so that they are
404 if (SrcReg != PPC::CR0) {
405 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
406 // rlwinm r0, r0, ShiftBits, 0, 31.
407 NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
408 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
411 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
412 .addReg(PPC::R0, false, false, isKill),
415 } else if (RC == PPC::CRBITRCRegisterClass) {
416 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
417 // backend currently only uses CR1EQ as an individual bit, this should
418 // not cause any bug. If we need other uses of CR bits, the following
419 // code may be invalid.
421 if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
423 else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
425 else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
427 else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
429 else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
431 else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
433 else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
435 else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
438 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
439 PPC::CRRCRegisterClass, NewMIs);
441 } else if (RC == PPC::VRRCRegisterClass) {
442 // We don't have indexed addressing for vector loads. Emit:
446 // FIXME: We use R0 here, because it isn't available for RA.
447 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
449 NewMIs.push_back(BuildMI(MF, get(PPC::STVX))
450 .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
452 assert(0 && "Unknown regclass!");
460 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
461 MachineBasicBlock::iterator MI,
462 unsigned SrcReg, bool isKill, int FrameIdx,
463 const TargetRegisterClass *RC) const {
464 MachineFunction &MF = *MBB.getParent();
465 SmallVector<MachineInstr*, 4> NewMIs;
467 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
468 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
469 FuncInfo->setSpillsCR();
472 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
473 MBB.insert(MI, NewMIs[i]);
476 void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
478 SmallVectorImpl<MachineOperand> &Addr,
479 const TargetRegisterClass *RC,
480 SmallVectorImpl<MachineInstr*> &NewMIs) const{
481 if (Addr[0].isFI()) {
482 if (StoreRegToStackSlot(MF, SrcReg, isKill,
483 Addr[0].getIndex(), RC, NewMIs)) {
484 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
485 FuncInfo->setSpillsCR();
492 if (RC == PPC::GPRCRegisterClass) {
494 } else if (RC == PPC::G8RCRegisterClass) {
496 } else if (RC == PPC::F8RCRegisterClass) {
498 } else if (RC == PPC::F4RCRegisterClass) {
500 } else if (RC == PPC::VRRCRegisterClass) {
503 assert(0 && "Unknown regclass!");
506 MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
507 .addReg(SrcReg, false, false, isKill);
508 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
509 MachineOperand &MO = Addr[i];
511 MIB.addReg(MO.getReg());
513 MIB.addImm(MO.getImm());
515 MIB.addFrameIndex(MO.getIndex());
517 NewMIs.push_back(MIB);
522 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF,
523 unsigned DestReg, int FrameIdx,
524 const TargetRegisterClass *RC,
525 SmallVectorImpl<MachineInstr*> &NewMIs)const{
526 if (RC == PPC::GPRCRegisterClass) {
527 if (DestReg != PPC::LR) {
528 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), DestReg),
531 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R11),
533 NewMIs.push_back(BuildMI(MF, get(PPC::MTLR)).addReg(PPC::R11));
535 } else if (RC == PPC::G8RCRegisterClass) {
536 if (DestReg != PPC::LR8) {
537 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), DestReg),
540 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), PPC::R11),
542 NewMIs.push_back(BuildMI(MF, get(PPC::MTLR8)).addReg(PPC::R11));
544 } else if (RC == PPC::F8RCRegisterClass) {
545 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFD), DestReg),
547 } else if (RC == PPC::F4RCRegisterClass) {
548 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFS), DestReg),
550 } else if (RC == PPC::CRRCRegisterClass) {
551 // FIXME: We use R0 here, because it isn't available for RA.
552 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R0),
555 // If the reloaded register isn't CR0, shift the bits right so that they are
556 // in the right CR's slot.
557 if (DestReg != PPC::CR0) {
558 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
559 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
560 NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
561 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
564 NewMIs.push_back(BuildMI(MF, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
565 } else if (RC == PPC::CRBITRCRegisterClass) {
568 if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
570 else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
572 else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
574 else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
576 else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
578 else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
580 else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
582 else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
585 return LoadRegFromStackSlot(MF, Reg, FrameIdx,
586 PPC::CRRCRegisterClass, NewMIs);
588 } else if (RC == PPC::VRRCRegisterClass) {
589 // We don't have indexed addressing for vector loads. Emit:
593 // FIXME: We use R0 here, because it isn't available for RA.
594 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
596 NewMIs.push_back(BuildMI(MF, get(PPC::LVX),DestReg).addReg(PPC::R0)
599 assert(0 && "Unknown regclass!");
605 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
606 MachineBasicBlock::iterator MI,
607 unsigned DestReg, int FrameIdx,
608 const TargetRegisterClass *RC) const {
609 MachineFunction &MF = *MBB.getParent();
610 SmallVector<MachineInstr*, 4> NewMIs;
611 LoadRegFromStackSlot(MF, DestReg, FrameIdx, RC, NewMIs);
612 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
613 MBB.insert(MI, NewMIs[i]);
616 void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
617 SmallVectorImpl<MachineOperand> &Addr,
618 const TargetRegisterClass *RC,
619 SmallVectorImpl<MachineInstr*> &NewMIs)const{
620 if (Addr[0].isFI()) {
621 LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs);
626 if (RC == PPC::GPRCRegisterClass) {
627 assert(DestReg != PPC::LR && "Can't handle this yet!");
629 } else if (RC == PPC::G8RCRegisterClass) {
630 assert(DestReg != PPC::LR8 && "Can't handle this yet!");
632 } else if (RC == PPC::F8RCRegisterClass) {
634 } else if (RC == PPC::F4RCRegisterClass) {
636 } else if (RC == PPC::VRRCRegisterClass) {
639 assert(0 && "Unknown regclass!");
642 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
643 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
644 MachineOperand &MO = Addr[i];
646 MIB.addReg(MO.getReg());
648 MIB.addImm(MO.getImm());
650 MIB.addFrameIndex(MO.getIndex());
652 NewMIs.push_back(MIB);
656 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
657 /// copy instructions, turning them into load/store instructions.
658 MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
660 const SmallVectorImpl<unsigned> &Ops,
661 int FrameIndex) const {
662 if (Ops.size() != 1) return NULL;
664 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
665 // it takes more than one instruction to store it.
666 unsigned Opc = MI->getOpcode();
667 unsigned OpNum = Ops[0];
669 MachineInstr *NewMI = NULL;
670 if ((Opc == PPC::OR &&
671 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
672 if (OpNum == 0) { // move -> store
673 unsigned InReg = MI->getOperand(1).getReg();
674 bool isKill = MI->getOperand(1).isKill();
675 NewMI = addFrameReference(BuildMI(MF, get(PPC::STW))
676 .addReg(InReg, false, false, isKill),
678 } else { // move -> load
679 unsigned OutReg = MI->getOperand(0).getReg();
680 bool isDead = MI->getOperand(0).isDead();
681 NewMI = addFrameReference(BuildMI(MF, get(PPC::LWZ))
682 .addReg(OutReg, true, false, false, isDead),
685 } else if ((Opc == PPC::OR8 &&
686 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
687 if (OpNum == 0) { // move -> store
688 unsigned InReg = MI->getOperand(1).getReg();
689 bool isKill = MI->getOperand(1).isKill();
690 NewMI = addFrameReference(BuildMI(MF, get(PPC::STD))
691 .addReg(InReg, false, false, isKill),
693 } else { // move -> load
694 unsigned OutReg = MI->getOperand(0).getReg();
695 bool isDead = MI->getOperand(0).isDead();
696 NewMI = addFrameReference(BuildMI(MF, get(PPC::LD))
697 .addReg(OutReg, true, false, false, isDead),
700 } else if (Opc == PPC::FMRD) {
701 if (OpNum == 0) { // move -> store
702 unsigned InReg = MI->getOperand(1).getReg();
703 bool isKill = MI->getOperand(1).isKill();
704 NewMI = addFrameReference(BuildMI(MF, get(PPC::STFD))
705 .addReg(InReg, false, false, isKill),
707 } else { // move -> load
708 unsigned OutReg = MI->getOperand(0).getReg();
709 bool isDead = MI->getOperand(0).isDead();
710 NewMI = addFrameReference(BuildMI(MF, get(PPC::LFD))
711 .addReg(OutReg, true, false, false, isDead),
714 } else if (Opc == PPC::FMRS) {
715 if (OpNum == 0) { // move -> store
716 unsigned InReg = MI->getOperand(1).getReg();
717 bool isKill = MI->getOperand(1).isKill();
718 NewMI = addFrameReference(BuildMI(MF, get(PPC::STFS))
719 .addReg(InReg, false, false, isKill),
721 } else { // move -> load
722 unsigned OutReg = MI->getOperand(0).getReg();
723 bool isDead = MI->getOperand(0).isDead();
724 NewMI = addFrameReference(BuildMI(MF, get(PPC::LFS))
725 .addReg(OutReg, true, false, false, isDead),
733 bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
734 const SmallVectorImpl<unsigned> &Ops) const {
735 if (Ops.size() != 1) return false;
737 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
738 // it takes more than one instruction to store it.
739 unsigned Opc = MI->getOpcode();
741 if ((Opc == PPC::OR &&
742 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
744 else if ((Opc == PPC::OR8 &&
745 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
747 else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
754 bool PPCInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
755 if (MBB.empty()) return false;
757 switch (MBB.back().getOpcode()) {
758 case PPC::BLR: // Return.
759 case PPC::B: // Uncond branch.
760 case PPC::BCTR: // Indirect branch.
762 default: return false;
767 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
768 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
769 // Leave the CR# the same, but invert the condition.
770 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
774 /// GetInstSize - Return the number of bytes of code the specified
775 /// instruction may be. This returns the maximum number of bytes.
777 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
778 switch (MI->getOpcode()) {
779 case PPC::INLINEASM: { // Inline Asm: Variable size.
780 const MachineFunction *MF = MI->getParent()->getParent();
781 const char *AsmStr = MI->getOperand(0).getSymbolName();
782 return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
789 return 4; // PowerPC instructions are all 4 bytes