1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPredicates.h"
18 #include "PPCGenInstrInfo.inc"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/Support/CommandLine.h"
25 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
26 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
28 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
29 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
30 RI(*TM.getSubtargetImpl(), *this) {}
32 /// getPointerRegClass - Return the register class to use to hold pointers.
33 /// This is used for addressing modes.
34 const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
35 if (TM.getSubtargetImpl()->isPPC64())
36 return &PPC::G8RCRegClass;
38 return &PPC::GPRCRegClass;
42 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
44 unsigned& destReg) const {
45 unsigned oc = MI.getOpcode();
46 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
47 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
48 assert(MI.getNumOperands() >= 3 &&
49 MI.getOperand(0).isRegister() &&
50 MI.getOperand(1).isRegister() &&
51 MI.getOperand(2).isRegister() &&
52 "invalid PPC OR instruction!");
53 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
54 sourceReg = MI.getOperand(1).getReg();
55 destReg = MI.getOperand(0).getReg();
58 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
59 assert(MI.getNumOperands() >= 3 &&
60 MI.getOperand(0).isRegister() &&
61 MI.getOperand(2).isImmediate() &&
62 "invalid PPC ADDI instruction!");
63 if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) {
64 sourceReg = MI.getOperand(1).getReg();
65 destReg = MI.getOperand(0).getReg();
68 } else if (oc == PPC::ORI) { // ori r1, r2, 0
69 assert(MI.getNumOperands() >= 3 &&
70 MI.getOperand(0).isRegister() &&
71 MI.getOperand(1).isRegister() &&
72 MI.getOperand(2).isImmediate() &&
73 "invalid PPC ORI instruction!");
74 if (MI.getOperand(2).getImm() == 0) {
75 sourceReg = MI.getOperand(1).getReg();
76 destReg = MI.getOperand(0).getReg();
79 } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
80 oc == PPC::FMRSD) { // fmr r1, r2
81 assert(MI.getNumOperands() >= 2 &&
82 MI.getOperand(0).isRegister() &&
83 MI.getOperand(1).isRegister() &&
84 "invalid PPC FMR instruction");
85 sourceReg = MI.getOperand(1).getReg();
86 destReg = MI.getOperand(0).getReg();
88 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
89 assert(MI.getNumOperands() >= 2 &&
90 MI.getOperand(0).isRegister() &&
91 MI.getOperand(1).isRegister() &&
92 "invalid PPC MCRF instruction");
93 sourceReg = MI.getOperand(1).getReg();
94 destReg = MI.getOperand(0).getReg();
100 unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
101 int &FrameIndex) const {
102 switch (MI->getOpcode()) {
108 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
109 MI->getOperand(2).isFI()) {
110 FrameIndex = MI->getOperand(2).getIndex();
111 return MI->getOperand(0).getReg();
118 unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
119 int &FrameIndex) const {
120 switch (MI->getOpcode()) {
126 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
127 MI->getOperand(2).isFI()) {
128 FrameIndex = MI->getOperand(2).getIndex();
129 return MI->getOperand(0).getReg();
136 // commuteInstruction - We can commute rlwimi instructions, but only if the
137 // rotate amt is zero. We also have to munge the immediates a bit.
138 MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
139 // Normal instructions can be commuted the obvious way.
140 if (MI->getOpcode() != PPC::RLWIMI)
141 return TargetInstrInfoImpl::commuteInstruction(MI);
143 // Cannot commute if it has a non-zero rotate count.
144 if (MI->getOperand(3).getImm() != 0)
147 // If we have a zero rotate count, we have:
149 // Op0 = (Op1 & ~M) | (Op2 & M)
151 // M = mask((ME+1)&31, (MB-1)&31)
152 // Op0 = (Op2 & ~M) | (Op1 & M)
155 unsigned Reg0 = MI->getOperand(0).getReg();
156 unsigned Reg1 = MI->getOperand(1).getReg();
157 unsigned Reg2 = MI->getOperand(2).getReg();
158 bool Reg1IsKill = MI->getOperand(1).isKill();
159 bool Reg2IsKill = MI->getOperand(2).isKill();
160 // If machine instrs are no longer in two-address forms, update
161 // destination register as well.
163 // Must be two address instruction!
164 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
165 "Expecting a two-address instruction!");
166 MI->getOperand(0).setReg(Reg2);
169 MI->getOperand(2).setReg(Reg1);
170 MI->getOperand(1).setReg(Reg2);
171 MI->getOperand(2).setIsKill(Reg1IsKill);
172 MI->getOperand(1).setIsKill(Reg2IsKill);
174 // Swap the mask around.
175 unsigned MB = MI->getOperand(4).getImm();
176 unsigned ME = MI->getOperand(5).getImm();
177 MI->getOperand(4).setImm((ME+1) & 31);
178 MI->getOperand(5).setImm((MB-1) & 31);
182 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
183 MachineBasicBlock::iterator MI) const {
184 BuildMI(MBB, MI, get(PPC::NOP));
189 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
190 MachineBasicBlock *&FBB,
191 std::vector<MachineOperand> &Cond) const {
192 // If the block has no terminators, it just falls into the block after it.
193 MachineBasicBlock::iterator I = MBB.end();
194 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
197 // Get the last instruction in the block.
198 MachineInstr *LastInst = I;
200 // If there is only one terminator instruction, process it.
201 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
202 if (LastInst->getOpcode() == PPC::B) {
203 TBB = LastInst->getOperand(0).getMBB();
205 } else if (LastInst->getOpcode() == PPC::BCC) {
206 // Block ends with fall-through condbranch.
207 TBB = LastInst->getOperand(2).getMBB();
208 Cond.push_back(LastInst->getOperand(0));
209 Cond.push_back(LastInst->getOperand(1));
212 // Otherwise, don't know what this is.
216 // Get the instruction before it if it's a terminator.
217 MachineInstr *SecondLastInst = I;
219 // If there are three terminators, we don't know what sort of block this is.
220 if (SecondLastInst && I != MBB.begin() &&
221 isUnpredicatedTerminator(--I))
224 // If the block ends with PPC::B and PPC:BCC, handle it.
225 if (SecondLastInst->getOpcode() == PPC::BCC &&
226 LastInst->getOpcode() == PPC::B) {
227 TBB = SecondLastInst->getOperand(2).getMBB();
228 Cond.push_back(SecondLastInst->getOperand(0));
229 Cond.push_back(SecondLastInst->getOperand(1));
230 FBB = LastInst->getOperand(0).getMBB();
234 // If the block ends with two PPC:Bs, handle it. The second one is not
235 // executed, so remove it.
236 if (SecondLastInst->getOpcode() == PPC::B &&
237 LastInst->getOpcode() == PPC::B) {
238 TBB = SecondLastInst->getOperand(0).getMBB();
240 I->eraseFromParent();
244 // Otherwise, can't handle this.
248 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
249 MachineBasicBlock::iterator I = MBB.end();
250 if (I == MBB.begin()) return 0;
252 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
255 // Remove the branch.
256 I->eraseFromParent();
260 if (I == MBB.begin()) return 1;
262 if (I->getOpcode() != PPC::BCC)
265 // Remove the branch.
266 I->eraseFromParent();
271 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
272 MachineBasicBlock *FBB,
273 const std::vector<MachineOperand> &Cond) const {
274 // Shouldn't be a fall through.
275 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
276 assert((Cond.size() == 2 || Cond.size() == 0) &&
277 "PPC branch conditions have two components!");
281 if (Cond.empty()) // Unconditional branch
282 BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
283 else // Conditional branch
284 BuildMI(&MBB, get(PPC::BCC))
285 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
289 // Two-way Conditional Branch.
290 BuildMI(&MBB, get(PPC::BCC))
291 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
292 BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
296 void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
297 MachineBasicBlock::iterator MI,
298 unsigned DestReg, unsigned SrcReg,
299 const TargetRegisterClass *DestRC,
300 const TargetRegisterClass *SrcRC) const {
301 if (DestRC != SrcRC) {
302 cerr << "Not yet supported!";
306 if (DestRC == PPC::GPRCRegisterClass) {
307 BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
308 } else if (DestRC == PPC::G8RCRegisterClass) {
309 BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
310 } else if (DestRC == PPC::F4RCRegisterClass) {
311 BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg);
312 } else if (DestRC == PPC::F8RCRegisterClass) {
313 BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg);
314 } else if (DestRC == PPC::CRRCRegisterClass) {
315 BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg);
316 } else if (DestRC == PPC::VRRCRegisterClass) {
317 BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
318 } else if (DestRC == PPC::CRBITRCRegisterClass) {
319 BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
321 cerr << "Attempt to copy register that is not GPR or FPR";
327 PPCInstrInfo::StoreRegToStackSlot(unsigned SrcReg, bool isKill,
329 const TargetRegisterClass *RC,
330 SmallVectorImpl<MachineInstr*> &NewMIs) const{
331 if (RC == PPC::GPRCRegisterClass) {
332 if (SrcReg != PPC::LR) {
333 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW))
334 .addReg(SrcReg, false, false, isKill),
337 // FIXME: this spills LR immediately to memory in one step. To do this,
338 // we use R11, which we know cannot be used in the prolog/epilog. This is
340 NewMIs.push_back(BuildMI(get(PPC::MFLR), PPC::R11));
341 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW))
342 .addReg(PPC::R11, false, false, isKill),
345 } else if (RC == PPC::G8RCRegisterClass) {
346 if (SrcReg != PPC::LR8) {
347 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STD))
348 .addReg(SrcReg, false, false, isKill), FrameIdx));
350 // FIXME: this spills LR immediately to memory in one step. To do this,
351 // we use R11, which we know cannot be used in the prolog/epilog. This is
353 NewMIs.push_back(BuildMI(get(PPC::MFLR8), PPC::X11));
354 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STD))
355 .addReg(PPC::X11, false, false, isKill), FrameIdx));
357 } else if (RC == PPC::F8RCRegisterClass) {
358 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STFD))
359 .addReg(SrcReg, false, false, isKill), FrameIdx));
360 } else if (RC == PPC::F4RCRegisterClass) {
361 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STFS))
362 .addReg(SrcReg, false, false, isKill), FrameIdx));
363 } else if (RC == PPC::CRRCRegisterClass) {
364 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
365 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
366 // FIXME (64-bit): Enable
367 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::SPILL_CR))
368 .addReg(SrcReg, false, false, isKill),
372 // FIXME: We use R0 here, because it isn't available for RA. We need to
373 // store the CR in the low 4-bits of the saved value. First, issue a MFCR
374 // to save all of the CRBits.
375 NewMIs.push_back(BuildMI(get(PPC::MFCR), PPC::R0));
377 // If the saved register wasn't CR0, shift the bits left so that they are
379 if (SrcReg != PPC::CR0) {
380 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
381 // rlwinm r0, r0, ShiftBits, 0, 31.
382 NewMIs.push_back(BuildMI(get(PPC::RLWINM), PPC::R0)
383 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
386 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW))
387 .addReg(PPC::R0, false, false, isKill),
390 } else if (RC == PPC::CRBITRCRegisterClass) {
391 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
392 // backend currently only uses CR1EQ as an individual bit, this should
393 // not cause any bug. If we need other uses of CR bits, the following
394 // code may be invalid.
396 if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
398 else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
400 else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
402 else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
404 else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
406 else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
408 else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
410 else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
413 return StoreRegToStackSlot(Reg, isKill, FrameIdx,
414 PPC::CRRCRegisterClass, NewMIs);
416 } else if (RC == PPC::VRRCRegisterClass) {
417 // We don't have indexed addressing for vector loads. Emit:
421 // FIXME: We use R0 here, because it isn't available for RA.
422 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::ADDI), PPC::R0),
424 NewMIs.push_back(BuildMI(get(PPC::STVX))
425 .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
427 assert(0 && "Unknown regclass!");
435 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
436 MachineBasicBlock::iterator MI,
437 unsigned SrcReg, bool isKill, int FrameIdx,
438 const TargetRegisterClass *RC) const {
439 SmallVector<MachineInstr*, 4> NewMIs;
441 if (StoreRegToStackSlot(SrcReg, isKill, FrameIdx, RC, NewMIs)) {
442 PPCFunctionInfo *FuncInfo = MBB.getParent()->getInfo<PPCFunctionInfo>();
443 FuncInfo->setSpillsCR();
446 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
447 MBB.insert(MI, NewMIs[i]);
450 void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
452 SmallVectorImpl<MachineOperand> &Addr,
453 const TargetRegisterClass *RC,
454 SmallVectorImpl<MachineInstr*> &NewMIs) const{
455 if (Addr[0].isFrameIndex()) {
456 if (StoreRegToStackSlot(SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs)) {
457 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
458 FuncInfo->setSpillsCR();
465 if (RC == PPC::GPRCRegisterClass) {
467 } else if (RC == PPC::G8RCRegisterClass) {
469 } else if (RC == PPC::F8RCRegisterClass) {
471 } else if (RC == PPC::F4RCRegisterClass) {
473 } else if (RC == PPC::VRRCRegisterClass) {
476 assert(0 && "Unknown regclass!");
479 MachineInstrBuilder MIB = BuildMI(get(Opc))
480 .addReg(SrcReg, false, false, isKill);
481 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
482 MachineOperand &MO = Addr[i];
484 MIB.addReg(MO.getReg());
485 else if (MO.isImmediate())
486 MIB.addImm(MO.getImm());
488 MIB.addFrameIndex(MO.getIndex());
490 NewMIs.push_back(MIB);
495 PPCInstrInfo::LoadRegFromStackSlot(unsigned DestReg, int FrameIdx,
496 const TargetRegisterClass *RC,
497 SmallVectorImpl<MachineInstr*> &NewMIs)const{
498 if (RC == PPC::GPRCRegisterClass) {
499 if (DestReg != PPC::LR) {
500 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), DestReg),
503 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), PPC::R11),
505 NewMIs.push_back(BuildMI(get(PPC::MTLR)).addReg(PPC::R11));
507 } else if (RC == PPC::G8RCRegisterClass) {
508 if (DestReg != PPC::LR8) {
509 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LD), DestReg),
512 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LD), PPC::R11),
514 NewMIs.push_back(BuildMI(get(PPC::MTLR8)).addReg(PPC::R11));
516 } else if (RC == PPC::F8RCRegisterClass) {
517 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LFD), DestReg),
519 } else if (RC == PPC::F4RCRegisterClass) {
520 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LFS), DestReg),
522 } else if (RC == PPC::CRRCRegisterClass) {
523 // FIXME: We use R0 here, because it isn't available for RA.
524 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), PPC::R0),
527 // If the reloaded register isn't CR0, shift the bits right so that they are
528 // in the right CR's slot.
529 if (DestReg != PPC::CR0) {
530 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
531 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
532 NewMIs.push_back(BuildMI(get(PPC::RLWINM), PPC::R0)
533 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
536 NewMIs.push_back(BuildMI(get(PPC::MTCRF), DestReg).addReg(PPC::R0));
537 } else if (RC == PPC::CRBITRCRegisterClass) {
540 if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
542 else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
544 else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
546 else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
548 else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
550 else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
552 else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
554 else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
557 return LoadRegFromStackSlot(Reg, FrameIdx,
558 PPC::CRRCRegisterClass, NewMIs);
560 } else if (RC == PPC::VRRCRegisterClass) {
561 // We don't have indexed addressing for vector loads. Emit:
565 // FIXME: We use R0 here, because it isn't available for RA.
566 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::ADDI), PPC::R0),
568 NewMIs.push_back(BuildMI(get(PPC::LVX),DestReg).addReg(PPC::R0)
571 assert(0 && "Unknown regclass!");
577 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
578 MachineBasicBlock::iterator MI,
579 unsigned DestReg, int FrameIdx,
580 const TargetRegisterClass *RC) const {
581 SmallVector<MachineInstr*, 4> NewMIs;
582 LoadRegFromStackSlot(DestReg, FrameIdx, RC, NewMIs);
583 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
584 MBB.insert(MI, NewMIs[i]);
587 void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
588 SmallVectorImpl<MachineOperand> &Addr,
589 const TargetRegisterClass *RC,
590 SmallVectorImpl<MachineInstr*> &NewMIs)const{
591 if (Addr[0].isFrameIndex()) {
592 LoadRegFromStackSlot(DestReg, Addr[0].getIndex(), RC, NewMIs);
597 if (RC == PPC::GPRCRegisterClass) {
598 assert(DestReg != PPC::LR && "Can't handle this yet!");
600 } else if (RC == PPC::G8RCRegisterClass) {
601 assert(DestReg != PPC::LR8 && "Can't handle this yet!");
603 } else if (RC == PPC::F8RCRegisterClass) {
605 } else if (RC == PPC::F4RCRegisterClass) {
607 } else if (RC == PPC::VRRCRegisterClass) {
610 assert(0 && "Unknown regclass!");
613 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
614 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
615 MachineOperand &MO = Addr[i];
617 MIB.addReg(MO.getReg());
618 else if (MO.isImmediate())
619 MIB.addImm(MO.getImm());
621 MIB.addFrameIndex(MO.getIndex());
623 NewMIs.push_back(MIB);
627 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
628 /// copy instructions, turning them into load/store instructions.
629 MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF,
631 SmallVectorImpl<unsigned> &Ops,
632 int FrameIndex) const {
633 if (Ops.size() != 1) return NULL;
635 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
636 // it takes more than one instruction to store it.
637 unsigned Opc = MI->getOpcode();
638 unsigned OpNum = Ops[0];
640 MachineInstr *NewMI = NULL;
641 if ((Opc == PPC::OR &&
642 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
643 if (OpNum == 0) { // move -> store
644 unsigned InReg = MI->getOperand(1).getReg();
645 NewMI = addFrameReference(BuildMI(get(PPC::STW)).addReg(InReg),
647 } else { // move -> load
648 unsigned OutReg = MI->getOperand(0).getReg();
649 NewMI = addFrameReference(BuildMI(get(PPC::LWZ), OutReg),
652 } else if ((Opc == PPC::OR8 &&
653 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
654 if (OpNum == 0) { // move -> store
655 unsigned InReg = MI->getOperand(1).getReg();
656 NewMI = addFrameReference(BuildMI(get(PPC::STD)).addReg(InReg),
658 } else { // move -> load
659 unsigned OutReg = MI->getOperand(0).getReg();
660 NewMI = addFrameReference(BuildMI(get(PPC::LD), OutReg), FrameIndex);
662 } else if (Opc == PPC::FMRD) {
663 if (OpNum == 0) { // move -> store
664 unsigned InReg = MI->getOperand(1).getReg();
665 NewMI = addFrameReference(BuildMI(get(PPC::STFD)).addReg(InReg),
667 } else { // move -> load
668 unsigned OutReg = MI->getOperand(0).getReg();
669 NewMI = addFrameReference(BuildMI(get(PPC::LFD), OutReg), FrameIndex);
671 } else if (Opc == PPC::FMRS) {
672 if (OpNum == 0) { // move -> store
673 unsigned InReg = MI->getOperand(1).getReg();
674 NewMI = addFrameReference(BuildMI(get(PPC::STFS)).addReg(InReg),
676 } else { // move -> load
677 unsigned OutReg = MI->getOperand(0).getReg();
678 NewMI = addFrameReference(BuildMI(get(PPC::LFS), OutReg), FrameIndex);
683 NewMI->copyKillDeadInfo(MI);
687 bool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
688 SmallVectorImpl<unsigned> &Ops) const {
689 if (Ops.size() != 1) return false;
691 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
692 // it takes more than one instruction to store it.
693 unsigned Opc = MI->getOpcode();
695 if ((Opc == PPC::OR &&
696 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
698 else if ((Opc == PPC::OR8 &&
699 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
701 else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
708 bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
709 if (MBB.empty()) return false;
711 switch (MBB.back().getOpcode()) {
712 case PPC::BLR: // Return.
713 case PPC::B: // Uncond branch.
714 case PPC::BCTR: // Indirect branch.
716 default: return false;
721 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
722 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
723 // Leave the CR# the same, but invert the condition.
724 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));