1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "PPCGenInstrInfo.inc"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 PPCInstrInfo::PPCInstrInfo()
22 : TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])) {}
24 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
26 unsigned& destReg) const {
27 MachineOpCode oc = MI.getOpcode();
28 if (oc == PPC::OR) { // or r1, r2, r2
29 assert(MI.getNumOperands() == 3 &&
30 MI.getOperand(0).isRegister() &&
31 MI.getOperand(1).isRegister() &&
32 MI.getOperand(2).isRegister() &&
33 "invalid PPC OR instruction!");
34 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
35 sourceReg = MI.getOperand(1).getReg();
36 destReg = MI.getOperand(0).getReg();
39 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
40 assert(MI.getNumOperands() == 3 &&
41 MI.getOperand(0).isRegister() &&
42 MI.getOperand(2).isImmediate() &&
43 "invalid PPC ADDI instruction!");
44 if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
45 sourceReg = MI.getOperand(1).getReg();
46 destReg = MI.getOperand(0).getReg();
49 } else if (oc == PPC::ORI) { // ori r1, r2, 0
50 assert(MI.getNumOperands() == 3 &&
51 MI.getOperand(0).isRegister() &&
52 MI.getOperand(1).isRegister() &&
53 MI.getOperand(2).isImmediate() &&
54 "invalid PPC ORI instruction!");
55 if (MI.getOperand(2).getImmedValue()==0) {
56 sourceReg = MI.getOperand(1).getReg();
57 destReg = MI.getOperand(0).getReg();
60 } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
61 oc == PPC::FMRSD) { // fmr r1, r2
62 assert(MI.getNumOperands() == 2 &&
63 MI.getOperand(0).isRegister() &&
64 MI.getOperand(1).isRegister() &&
65 "invalid PPC FMR instruction");
66 sourceReg = MI.getOperand(1).getReg();
67 destReg = MI.getOperand(0).getReg();
69 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
70 assert(MI.getNumOperands() == 2 &&
71 MI.getOperand(0).isRegister() &&
72 MI.getOperand(1).isRegister() &&
73 "invalid PPC MCRF instruction");
74 sourceReg = MI.getOperand(1).getReg();
75 destReg = MI.getOperand(0).getReg();
81 // commuteInstruction - We can commute rlwimi instructions, but only if the
82 // rotate amt is zero. We also have to munge the immediates a bit.
83 MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
84 // Normal instructions can be commuted the obvious way.
85 if (MI->getOpcode() != PPC::RLWIMI)
86 return TargetInstrInfo::commuteInstruction(MI);
88 // Cannot commute if it has a non-zero rotate count.
89 if (MI->getOperand(3).getImmedValue() != 0)
92 // If we have a zero rotate count, we have:
94 // Op0 = (Op1 & ~M) | (Op2 & M)
96 // M = mask((ME+1)&31, (MB-1)&31)
97 // Op0 = (Op2 & ~M) | (Op1 & M)
100 unsigned Reg1 = MI->getOperand(1).getReg();
101 unsigned Reg2 = MI->getOperand(2).getReg();
102 MI->SetMachineOperandReg(2, Reg1);
103 MI->SetMachineOperandReg(1, Reg2);
105 // Swap the mask around.
106 unsigned MB = MI->getOperand(4).getImmedValue();
107 unsigned ME = MI->getOperand(5).getImmedValue();
108 MI->getOperand(4).setImmedValue((ME+1) & 31);
109 MI->getOperand(5).setImmedValue((MB-1) & 31);