1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/PseudoSourceValue.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/TargetRegistry.h"
33 #include "llvm/Support/raw_ostream.h"
35 #define GET_INSTRINFO_CTOR
36 #include "PPCGenInstrInfo.inc"
41 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
42 cl::desc("Disable analysis for CTR loops"));
44 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
45 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
46 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
48 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
49 /// this target when scheduling the DAG.
50 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
51 const TargetMachine *TM,
52 const ScheduleDAG *DAG) const {
53 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
54 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
55 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
56 const InstrItineraryData *II = TM->getInstrItineraryData();
57 return new PPCScoreboardHazardRecognizer(II, DAG);
60 return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
63 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
64 /// to use for this target when scheduling the DAG.
65 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
66 const InstrItineraryData *II,
67 const ScheduleDAG *DAG) const {
68 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
70 // Most subtargets use a PPC970 recognizer.
71 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
72 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
73 const TargetInstrInfo *TII = TM.getInstrInfo();
74 assert(TII && "No InstrInfo?");
76 return new PPCHazardRecognizer970(*TII);
79 return new PPCScoreboardHazardRecognizer(II, DAG);
82 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
83 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
84 unsigned &SrcReg, unsigned &DstReg,
85 unsigned &SubIdx) const {
86 switch (MI.getOpcode()) {
87 default: return false;
89 case PPC::EXTSW_32_64:
90 SrcReg = MI.getOperand(1).getReg();
91 DstReg = MI.getOperand(0).getReg();
97 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
98 int &FrameIndex) const {
99 // Note: This list must be kept consistent with LoadRegFromStackSlot.
100 switch (MI->getOpcode()) {
106 case PPC::RESTORE_CR:
108 case PPC::RESTORE_VRSAVE:
109 // Check for the operands added by addFrameReference (the immediate is the
110 // offset which defaults to 0).
111 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
112 MI->getOperand(2).isFI()) {
113 FrameIndex = MI->getOperand(2).getIndex();
114 return MI->getOperand(0).getReg();
121 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
122 int &FrameIndex) const {
123 // Note: This list must be kept consistent with StoreRegToStackSlot.
124 switch (MI->getOpcode()) {
132 case PPC::SPILL_VRSAVE:
133 // Check for the operands added by addFrameReference (the immediate is the
134 // offset which defaults to 0).
135 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
136 MI->getOperand(2).isFI()) {
137 FrameIndex = MI->getOperand(2).getIndex();
138 return MI->getOperand(0).getReg();
145 // commuteInstruction - We can commute rlwimi instructions, but only if the
146 // rotate amt is zero. We also have to munge the immediates a bit.
148 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
149 MachineFunction &MF = *MI->getParent()->getParent();
151 // Normal instructions can be commuted the obvious way.
152 if (MI->getOpcode() != PPC::RLWIMI)
153 return TargetInstrInfo::commuteInstruction(MI, NewMI);
155 // Cannot commute if it has a non-zero rotate count.
156 if (MI->getOperand(3).getImm() != 0)
159 // If we have a zero rotate count, we have:
161 // Op0 = (Op1 & ~M) | (Op2 & M)
163 // M = mask((ME+1)&31, (MB-1)&31)
164 // Op0 = (Op2 & ~M) | (Op1 & M)
167 unsigned Reg0 = MI->getOperand(0).getReg();
168 unsigned Reg1 = MI->getOperand(1).getReg();
169 unsigned Reg2 = MI->getOperand(2).getReg();
170 bool Reg1IsKill = MI->getOperand(1).isKill();
171 bool Reg2IsKill = MI->getOperand(2).isKill();
172 bool ChangeReg0 = false;
173 // If machine instrs are no longer in two-address forms, update
174 // destination register as well.
176 // Must be two address instruction!
177 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
178 "Expecting a two-address instruction!");
184 unsigned MB = MI->getOperand(4).getImm();
185 unsigned ME = MI->getOperand(5).getImm();
188 // Create a new instruction.
189 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
190 bool Reg0IsDead = MI->getOperand(0).isDead();
191 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
192 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
193 .addReg(Reg2, getKillRegState(Reg2IsKill))
194 .addReg(Reg1, getKillRegState(Reg1IsKill))
196 .addImm((MB-1) & 31);
200 MI->getOperand(0).setReg(Reg2);
201 MI->getOperand(2).setReg(Reg1);
202 MI->getOperand(1).setReg(Reg2);
203 MI->getOperand(2).setIsKill(Reg1IsKill);
204 MI->getOperand(1).setIsKill(Reg2IsKill);
206 // Swap the mask around.
207 MI->getOperand(4).setImm((ME+1) & 31);
208 MI->getOperand(5).setImm((MB-1) & 31);
212 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
213 MachineBasicBlock::iterator MI) const {
215 BuildMI(MBB, MI, DL, get(PPC::NOP));
220 // Note: If the condition register is set to CTR or CTR8 then this is a
221 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
222 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
223 MachineBasicBlock *&FBB,
224 SmallVectorImpl<MachineOperand> &Cond,
225 bool AllowModify) const {
226 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
228 // If the block has no terminators, it just falls into the block after it.
229 MachineBasicBlock::iterator I = MBB.end();
230 if (I == MBB.begin())
233 while (I->isDebugValue()) {
234 if (I == MBB.begin())
238 if (!isUnpredicatedTerminator(I))
241 // Get the last instruction in the block.
242 MachineInstr *LastInst = I;
244 // If there is only one terminator instruction, process it.
245 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
246 if (LastInst->getOpcode() == PPC::B) {
247 if (!LastInst->getOperand(0).isMBB())
249 TBB = LastInst->getOperand(0).getMBB();
251 } else if (LastInst->getOpcode() == PPC::BCC) {
252 if (!LastInst->getOperand(2).isMBB())
254 // Block ends with fall-through condbranch.
255 TBB = LastInst->getOperand(2).getMBB();
256 Cond.push_back(LastInst->getOperand(0));
257 Cond.push_back(LastInst->getOperand(1));
259 } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
260 LastInst->getOpcode() == PPC::BDNZ) {
261 if (!LastInst->getOperand(0).isMBB())
263 if (DisableCTRLoopAnal)
265 TBB = LastInst->getOperand(0).getMBB();
266 Cond.push_back(MachineOperand::CreateImm(1));
267 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
270 } else if (LastInst->getOpcode() == PPC::BDZ8 ||
271 LastInst->getOpcode() == PPC::BDZ) {
272 if (!LastInst->getOperand(0).isMBB())
274 if (DisableCTRLoopAnal)
276 TBB = LastInst->getOperand(0).getMBB();
277 Cond.push_back(MachineOperand::CreateImm(0));
278 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
283 // Otherwise, don't know what this is.
287 // Get the instruction before it if it's a terminator.
288 MachineInstr *SecondLastInst = I;
290 // If there are three terminators, we don't know what sort of block this is.
291 if (SecondLastInst && I != MBB.begin() &&
292 isUnpredicatedTerminator(--I))
295 // If the block ends with PPC::B and PPC:BCC, handle it.
296 if (SecondLastInst->getOpcode() == PPC::BCC &&
297 LastInst->getOpcode() == PPC::B) {
298 if (!SecondLastInst->getOperand(2).isMBB() ||
299 !LastInst->getOperand(0).isMBB())
301 TBB = SecondLastInst->getOperand(2).getMBB();
302 Cond.push_back(SecondLastInst->getOperand(0));
303 Cond.push_back(SecondLastInst->getOperand(1));
304 FBB = LastInst->getOperand(0).getMBB();
306 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
307 SecondLastInst->getOpcode() == PPC::BDNZ) &&
308 LastInst->getOpcode() == PPC::B) {
309 if (!SecondLastInst->getOperand(0).isMBB() ||
310 !LastInst->getOperand(0).isMBB())
312 if (DisableCTRLoopAnal)
314 TBB = SecondLastInst->getOperand(0).getMBB();
315 Cond.push_back(MachineOperand::CreateImm(1));
316 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
318 FBB = LastInst->getOperand(0).getMBB();
320 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
321 SecondLastInst->getOpcode() == PPC::BDZ) &&
322 LastInst->getOpcode() == PPC::B) {
323 if (!SecondLastInst->getOperand(0).isMBB() ||
324 !LastInst->getOperand(0).isMBB())
326 if (DisableCTRLoopAnal)
328 TBB = SecondLastInst->getOperand(0).getMBB();
329 Cond.push_back(MachineOperand::CreateImm(0));
330 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
332 FBB = LastInst->getOperand(0).getMBB();
336 // If the block ends with two PPC:Bs, handle it. The second one is not
337 // executed, so remove it.
338 if (SecondLastInst->getOpcode() == PPC::B &&
339 LastInst->getOpcode() == PPC::B) {
340 if (!SecondLastInst->getOperand(0).isMBB())
342 TBB = SecondLastInst->getOperand(0).getMBB();
345 I->eraseFromParent();
349 // Otherwise, can't handle this.
353 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
354 MachineBasicBlock::iterator I = MBB.end();
355 if (I == MBB.begin()) return 0;
357 while (I->isDebugValue()) {
358 if (I == MBB.begin())
362 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
363 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
364 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
367 // Remove the branch.
368 I->eraseFromParent();
372 if (I == MBB.begin()) return 1;
374 if (I->getOpcode() != PPC::BCC &&
375 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
376 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
379 // Remove the branch.
380 I->eraseFromParent();
385 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
386 MachineBasicBlock *FBB,
387 const SmallVectorImpl<MachineOperand> &Cond,
389 // Shouldn't be a fall through.
390 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
391 assert((Cond.size() == 2 || Cond.size() == 0) &&
392 "PPC branch conditions have two components!");
394 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
398 if (Cond.empty()) // Unconditional branch
399 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
400 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
401 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
402 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
403 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
404 else // Conditional branch
405 BuildMI(&MBB, DL, get(PPC::BCC))
406 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
410 // Two-way Conditional Branch.
411 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
412 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
413 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
414 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
416 BuildMI(&MBB, DL, get(PPC::BCC))
417 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
418 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
423 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
424 const SmallVectorImpl<MachineOperand> &Cond,
425 unsigned TrueReg, unsigned FalseReg,
426 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
427 if (!TM.getSubtargetImpl()->hasISEL())
430 if (Cond.size() != 2)
433 // If this is really a bdnz-like condition, then it cannot be turned into a
435 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
438 // Check register classes.
439 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
440 const TargetRegisterClass *RC =
441 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
445 // isel is for regular integer GPRs only.
446 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
447 !PPC::G8RCRegClass.hasSubClassEq(RC))
450 // FIXME: These numbers are for the A2, how well they work for other cores is
451 // an open question. On the A2, the isel instruction has a 2-cycle latency
452 // but single-cycle throughput. These numbers are used in combination with
453 // the MispredictPenalty setting from the active SchedMachineModel.
461 void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
462 MachineBasicBlock::iterator MI, DebugLoc dl,
464 const SmallVectorImpl<MachineOperand> &Cond,
465 unsigned TrueReg, unsigned FalseReg) const {
466 assert(Cond.size() == 2 &&
467 "PPC branch conditions have two components!");
469 assert(TM.getSubtargetImpl()->hasISEL() &&
470 "Cannot insert select on target without ISEL support");
472 // Get the register classes.
473 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
474 const TargetRegisterClass *RC =
475 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
476 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
477 assert((PPC::GPRCRegClass.hasSubClassEq(RC) ||
478 PPC::G8RCRegClass.hasSubClassEq(RC)) &&
479 "isel is for regular integer GPRs only");
482 PPC::GPRCRegClass.hasSubClassEq(RC) ? PPC::ISEL : PPC::ISEL8;
483 unsigned SelectPred = Cond[0].getImm();
487 switch (SelectPred) {
488 default: llvm_unreachable("invalid predicate for isel");
489 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
490 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
491 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
492 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
493 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
494 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
495 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
496 case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
499 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
500 SecondReg = SwapOps ? TrueReg : FalseReg;
502 // The first input register of isel cannot be r0. If it is a member
503 // of a register class that can be r0, then copy it first (the
504 // register allocator should eliminate the copy).
505 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
506 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
507 const TargetRegisterClass *FirstRC =
508 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
509 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
510 unsigned OldFirstReg = FirstReg;
511 FirstReg = MRI.createVirtualRegister(FirstRC);
512 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
513 .addReg(OldFirstReg);
516 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
517 .addReg(FirstReg).addReg(SecondReg)
518 .addReg(Cond[1].getReg(), 0, SubIdx);
521 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
522 MachineBasicBlock::iterator I, DebugLoc DL,
523 unsigned DestReg, unsigned SrcReg,
524 bool KillSrc) const {
526 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
528 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
530 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
532 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
534 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
536 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
539 llvm_unreachable("Impossible reg-to-reg copy");
541 const MCInstrDesc &MCID = get(Opc);
542 if (MCID.getNumOperands() == 3)
543 BuildMI(MBB, I, DL, MCID, DestReg)
544 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
546 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
549 // This function returns true if a CR spill is necessary and false otherwise.
551 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
552 unsigned SrcReg, bool isKill,
554 const TargetRegisterClass *RC,
555 SmallVectorImpl<MachineInstr*> &NewMIs,
556 bool &NonRI, bool &SpillsVRS) const{
557 // Note: If additional store instructions are added here,
558 // update isStoreToStackSlot.
561 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
562 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
564 getKillRegState(isKill)),
566 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
567 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
569 getKillRegState(isKill)),
571 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
572 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
574 getKillRegState(isKill)),
576 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
577 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
579 getKillRegState(isKill)),
581 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
582 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
584 getKillRegState(isKill)),
587 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
588 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
589 // backend currently only uses CR1EQ as an individual bit, this should
590 // not cause any bug. If we need other uses of CR bits, the following
591 // code may be invalid.
593 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
594 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
596 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
597 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
599 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
600 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
602 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
603 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
605 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
606 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
608 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
609 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
611 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
612 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
614 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
615 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
618 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
619 &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
621 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
622 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
624 getKillRegState(isKill)),
627 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
628 assert(TM.getSubtargetImpl()->isDarwin() &&
629 "VRSAVE only needs spill/restore on Darwin");
630 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
632 getKillRegState(isKill)),
636 llvm_unreachable("Unknown regclass!");
643 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
644 MachineBasicBlock::iterator MI,
645 unsigned SrcReg, bool isKill, int FrameIdx,
646 const TargetRegisterClass *RC,
647 const TargetRegisterInfo *TRI) const {
648 MachineFunction &MF = *MBB.getParent();
649 SmallVector<MachineInstr*, 4> NewMIs;
651 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
652 FuncInfo->setHasSpills();
654 bool NonRI = false, SpillsVRS = false;
655 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
657 FuncInfo->setSpillsCR();
660 FuncInfo->setSpillsVRSAVE();
663 FuncInfo->setHasNonRISpills();
665 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
666 MBB.insert(MI, NewMIs[i]);
668 const MachineFrameInfo &MFI = *MF.getFrameInfo();
669 MachineMemOperand *MMO =
670 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
671 MachineMemOperand::MOStore,
672 MFI.getObjectSize(FrameIdx),
673 MFI.getObjectAlignment(FrameIdx));
674 NewMIs.back()->addMemOperand(MF, MMO);
678 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
679 unsigned DestReg, int FrameIdx,
680 const TargetRegisterClass *RC,
681 SmallVectorImpl<MachineInstr*> &NewMIs,
682 bool &NonRI, bool &SpillsVRS) const{
683 // Note: If additional load instructions are added here,
684 // update isLoadFromStackSlot.
686 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
687 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
688 DestReg), FrameIdx));
689 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
690 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
692 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
693 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
695 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
696 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
698 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
699 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
700 get(PPC::RESTORE_CR), DestReg),
703 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
706 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
707 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
709 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
710 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
712 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
713 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
715 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
716 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
718 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
719 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
721 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
722 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
724 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
725 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
727 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
728 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
731 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
732 &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
734 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
735 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
738 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
739 assert(TM.getSubtargetImpl()->isDarwin() &&
740 "VRSAVE only needs spill/restore on Darwin");
741 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
742 get(PPC::RESTORE_VRSAVE),
747 llvm_unreachable("Unknown regclass!");
754 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
755 MachineBasicBlock::iterator MI,
756 unsigned DestReg, int FrameIdx,
757 const TargetRegisterClass *RC,
758 const TargetRegisterInfo *TRI) const {
759 MachineFunction &MF = *MBB.getParent();
760 SmallVector<MachineInstr*, 4> NewMIs;
762 if (MI != MBB.end()) DL = MI->getDebugLoc();
764 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
765 FuncInfo->setHasSpills();
767 bool NonRI = false, SpillsVRS = false;
768 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
770 FuncInfo->setSpillsCR();
773 FuncInfo->setSpillsVRSAVE();
776 FuncInfo->setHasNonRISpills();
778 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
779 MBB.insert(MI, NewMIs[i]);
781 const MachineFrameInfo &MFI = *MF.getFrameInfo();
782 MachineMemOperand *MMO =
783 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
784 MachineMemOperand::MOLoad,
785 MFI.getObjectSize(FrameIdx),
786 MFI.getObjectAlignment(FrameIdx));
787 NewMIs.back()->addMemOperand(MF, MMO);
791 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
792 int FrameIx, uint64_t Offset,
795 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
796 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
801 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
802 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
803 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
804 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
806 // Leave the CR# the same, but invert the condition.
807 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
811 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
812 unsigned Reg, MachineRegisterInfo *MRI) const {
813 // For some instructions, it is legal to fold ZERO into the RA register field.
814 // A zero immediate should always be loaded with a single li.
815 unsigned DefOpc = DefMI->getOpcode();
816 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
818 if (!DefMI->getOperand(1).isImm())
820 if (DefMI->getOperand(1).getImm() != 0)
823 // Note that we cannot here invert the arguments of an isel in order to fold
824 // a ZERO into what is presented as the second argument. All we have here
825 // is the condition bit, and that might come from a CR-logical bit operation.
827 const MCInstrDesc &UseMCID = UseMI->getDesc();
829 // Only fold into real machine instructions.
830 if (UseMCID.isPseudo())
834 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
835 if (UseMI->getOperand(UseIdx).isReg() &&
836 UseMI->getOperand(UseIdx).getReg() == Reg)
839 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
840 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
842 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
844 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
845 // register (which might also be specified as a pointer class kind).
846 if (UseInfo->isLookupPtrRegClass()) {
847 if (UseInfo->RegClass /* Kind */ != 1)
850 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
851 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
855 // Make sure this is not tied to an output register (or otherwise
856 // constrained). This is true for ST?UX registers, for example, which
857 // are tied to their output registers.
858 if (UseInfo->Constraints != 0)
862 if (UseInfo->isLookupPtrRegClass()) {
863 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
864 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
866 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
867 PPC::ZERO8 : PPC::ZERO;
870 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
871 UseMI->getOperand(UseIdx).setReg(ZeroReg);
874 DefMI->eraseFromParent();
879 static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
880 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
882 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
887 // We should make sure that, if we're going to predicate both sides of a
888 // condition (a diamond), that both sides don't define the counter register. We
889 // can predicate counter-decrement-based branches, but while that predicates
890 // the branching, it does not predicate the counter decrement. If we tried to
891 // merge the triangle into one predicated block, we'd decrement the counter
893 bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
894 unsigned NumT, unsigned ExtraT,
895 MachineBasicBlock &FMBB,
896 unsigned NumF, unsigned ExtraF,
897 const BranchProbability &Probability) const {
898 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
902 bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
903 // The predicated branches are identified by their type, not really by the
904 // explicit presence of a predicate. Furthermore, some of them can be
905 // predicated more than once. Because if conversion won't try to predicate
906 // any instruction which already claims to be predicated (by returning true
907 // here), always return false. In doing so, we let isPredicable() be the
908 // final word on whether not the instruction can be (further) predicated.
913 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
914 if (!MI->isTerminator())
917 // Conditional branch is a special case.
918 if (MI->isBranch() && !MI->isBarrier())
921 return !isPredicated(MI);
924 bool PPCInstrInfo::PredicateInstruction(
926 const SmallVectorImpl<MachineOperand> &Pred) const {
927 unsigned OpC = MI->getOpcode();
928 if (OpC == PPC::BLR) {
929 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
930 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
931 MI->setDesc(get(Pred[0].getImm() ?
932 (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
933 (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
935 MI->setDesc(get(PPC::BCLR));
936 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
937 .addImm(Pred[0].getImm())
938 .addReg(Pred[1].getReg());
942 } else if (OpC == PPC::B) {
943 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
944 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
945 MI->setDesc(get(Pred[0].getImm() ?
946 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
947 (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
949 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
950 MI->RemoveOperand(0);
952 MI->setDesc(get(PPC::BCC));
953 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
954 .addImm(Pred[0].getImm())
955 .addReg(Pred[1].getReg())
960 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
961 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
962 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
963 llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
965 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
966 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
967 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
968 (setLR ? PPC::BCCTRL : PPC::BCCTR)));
969 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
970 .addImm(Pred[0].getImm())
971 .addReg(Pred[1].getReg());
978 bool PPCInstrInfo::SubsumesPredicate(
979 const SmallVectorImpl<MachineOperand> &Pred1,
980 const SmallVectorImpl<MachineOperand> &Pred2) const {
981 assert(Pred1.size() == 2 && "Invalid PPC first predicate");
982 assert(Pred2.size() == 2 && "Invalid PPC second predicate");
984 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
986 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
989 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
990 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
995 // Does P1 subsume P2, e.g. GE subsumes GT.
996 if (P1 == PPC::PRED_LE &&
997 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
999 if (P1 == PPC::PRED_GE &&
1000 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1006 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
1007 std::vector<MachineOperand> &Pred) const {
1008 // Note: At the present time, the contents of Pred from this function is
1009 // unused by IfConversion. This implementation follows ARM by pushing the
1010 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1011 // predicate, instructions defining CTR or CTR8 are also included as
1012 // predicate-defining instructions.
1014 const TargetRegisterClass *RCs[] =
1015 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1016 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1019 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1020 const MachineOperand &MO = MI->getOperand(i);
1021 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1022 const TargetRegisterClass *RC = RCs[c];
1024 if (MO.isDef() && RC->contains(MO.getReg())) {
1028 } else if (MO.isRegMask()) {
1029 for (TargetRegisterClass::iterator I = RC->begin(),
1030 IE = RC->end(); I != IE; ++I)
1031 if (MO.clobbersPhysReg(*I)) {
1042 bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
1043 unsigned OpC = MI->getOpcode();
1057 /// GetInstSize - Return the number of bytes of code the specified
1058 /// instruction may be. This returns the maximum number of bytes.
1060 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
1061 switch (MI->getOpcode()) {
1062 case PPC::INLINEASM: { // Inline Asm: Variable size.
1063 const MachineFunction *MF = MI->getParent()->getParent();
1064 const char *AsmStr = MI->getOperand(0).getSymbolName();
1065 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1067 case PPC::PROLOG_LABEL:
1070 case PPC::DBG_VALUE:
1076 return 4; // PowerPC instructions are all 4 bytes
1081 #define DEBUG_TYPE "ppc-early-ret"
1082 STATISTIC(NumBCLR, "Number of early conditional returns");
1083 STATISTIC(NumBLR, "Number of early returns");
1086 void initializePPCEarlyReturnPass(PassRegistry&);
1090 // PPCEarlyReturn pass - For simple functions without epilogue code, move
1091 // returns up, and create conditional returns, to avoid unnecessary
1092 // branch-to-blr sequences.
1093 struct PPCEarlyReturn : public MachineFunctionPass {
1095 PPCEarlyReturn() : MachineFunctionPass(ID) {
1096 initializePPCEarlyReturnPass(*PassRegistry::getPassRegistry());
1099 const PPCTargetMachine *TM;
1100 const PPCInstrInfo *TII;
1103 bool processBlock(MachineBasicBlock &ReturnMBB) {
1104 bool Changed = false;
1106 MachineBasicBlock::iterator I = ReturnMBB.begin();
1107 I = ReturnMBB.SkipPHIsAndLabels(I);
1109 // The block must be essentially empty except for the blr.
1110 if (I == ReturnMBB.end() || I->getOpcode() != PPC::BLR ||
1111 I != ReturnMBB.getLastNonDebugInstr())
1114 SmallVector<MachineBasicBlock*, 8> PredToRemove;
1115 for (MachineBasicBlock::pred_iterator PI = ReturnMBB.pred_begin(),
1116 PIE = ReturnMBB.pred_end(); PI != PIE; ++PI) {
1117 bool OtherReference = false, BlockChanged = false;
1118 for (MachineBasicBlock::iterator J = (*PI)->getLastNonDebugInstr();;) {
1119 if (J->getOpcode() == PPC::B) {
1120 if (J->getOperand(0).getMBB() == &ReturnMBB) {
1121 // This is an unconditional branch to the return. Replace the
1122 // branch with a blr.
1123 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BLR));
1124 MachineBasicBlock::iterator K = J--;
1125 K->eraseFromParent();
1126 BlockChanged = true;
1130 } else if (J->getOpcode() == PPC::BCC) {
1131 if (J->getOperand(2).getMBB() == &ReturnMBB) {
1132 // This is a conditional branch to the return. Replace the branch
1134 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCLR))
1135 .addImm(J->getOperand(0).getImm())
1136 .addReg(J->getOperand(1).getReg());
1137 MachineBasicBlock::iterator K = J--;
1138 K->eraseFromParent();
1139 BlockChanged = true;
1143 } else if (J->isBranch()) {
1144 if (J->isIndirectBranch()) {
1145 if (ReturnMBB.hasAddressTaken())
1146 OtherReference = true;
1148 for (unsigned i = 0; i < J->getNumOperands(); ++i)
1149 if (J->getOperand(i).isMBB() &&
1150 J->getOperand(i).getMBB() == &ReturnMBB)
1151 OtherReference = true;
1152 } else if (!J->isTerminator() && !J->isDebugValue())
1155 if (J == (*PI)->begin())
1161 if ((*PI)->canFallThrough() && (*PI)->isLayoutSuccessor(&ReturnMBB))
1162 OtherReference = true;
1164 // Predecessors are stored in a vector and can't be removed here.
1165 if (!OtherReference && BlockChanged) {
1166 PredToRemove.push_back(*PI);
1173 for (unsigned i = 0, ie = PredToRemove.size(); i != ie; ++i)
1174 PredToRemove[i]->removeSuccessor(&ReturnMBB);
1176 if (Changed && !ReturnMBB.hasAddressTaken()) {
1177 // We now might be able to merge this blr-only block into its
1178 // by-layout predecessor.
1179 if (ReturnMBB.pred_size() == 1 &&
1180 (*ReturnMBB.pred_begin())->isLayoutSuccessor(&ReturnMBB)) {
1181 // Move the blr into the preceding block.
1182 MachineBasicBlock &PrevMBB = **ReturnMBB.pred_begin();
1183 PrevMBB.splice(PrevMBB.end(), &ReturnMBB, I);
1184 PrevMBB.removeSuccessor(&ReturnMBB);
1187 if (ReturnMBB.pred_empty())
1188 ReturnMBB.eraseFromParent();
1195 virtual bool runOnMachineFunction(MachineFunction &MF) {
1196 TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
1197 TII = TM->getInstrInfo();
1199 bool Changed = false;
1201 // If the function does not have at least two blocks, then there is
1206 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
1207 MachineBasicBlock &B = *I++;
1208 if (processBlock(B))
1215 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1216 MachineFunctionPass::getAnalysisUsage(AU);
1221 INITIALIZE_PASS(PPCEarlyReturn, DEBUG_TYPE,
1222 "PowerPC Early-Return Creation", false, false)
1224 char PPCEarlyReturn::ID = 0;
1226 llvm::createPPCEarlyReturnPass() { return new PPCEarlyReturn(); }