1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
33 #define GET_INSTRINFO_CTOR
34 #include "PPCGenInstrInfo.inc"
39 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
40 cl::desc("Disable analysis for CTR loops"));
42 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
43 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
44 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
46 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
47 /// this target when scheduling the DAG.
48 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
49 const TargetMachine *TM,
50 const ScheduleDAG *DAG) const {
51 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
52 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
53 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
54 const InstrItineraryData *II = TM->getInstrItineraryData();
55 return new PPCScoreboardHazardRecognizer(II, DAG);
58 return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
61 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
62 /// to use for this target when scheduling the DAG.
63 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
64 const InstrItineraryData *II,
65 const ScheduleDAG *DAG) const {
66 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
68 // Most subtargets use a PPC970 recognizer.
69 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
70 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
71 const TargetInstrInfo *TII = TM.getInstrInfo();
72 assert(TII && "No InstrInfo?");
74 return new PPCHazardRecognizer970(*TII);
77 return new PPCScoreboardHazardRecognizer(II, DAG);
80 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
81 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
82 unsigned &SrcReg, unsigned &DstReg,
83 unsigned &SubIdx) const {
84 switch (MI.getOpcode()) {
85 default: return false;
87 case PPC::EXTSW_32_64:
88 SrcReg = MI.getOperand(1).getReg();
89 DstReg = MI.getOperand(0).getReg();
95 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
96 int &FrameIndex) const {
97 // Note: This list must be kept consistent with LoadRegFromStackSlot.
98 switch (MI->getOpcode()) {
104 case PPC::RESTORE_CR:
106 case PPC::RESTORE_VRSAVE:
107 // Check for the operands added by addFrameReference (the immediate is the
108 // offset which defaults to 0).
109 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
110 MI->getOperand(2).isFI()) {
111 FrameIndex = MI->getOperand(2).getIndex();
112 return MI->getOperand(0).getReg();
119 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
120 int &FrameIndex) const {
121 // Note: This list must be kept consistent with StoreRegToStackSlot.
122 switch (MI->getOpcode()) {
130 case PPC::SPILL_VRSAVE:
131 // Check for the operands added by addFrameReference (the immediate is the
132 // offset which defaults to 0).
133 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
134 MI->getOperand(2).isFI()) {
135 FrameIndex = MI->getOperand(2).getIndex();
136 return MI->getOperand(0).getReg();
143 // commuteInstruction - We can commute rlwimi instructions, but only if the
144 // rotate amt is zero. We also have to munge the immediates a bit.
146 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
147 MachineFunction &MF = *MI->getParent()->getParent();
149 // Normal instructions can be commuted the obvious way.
150 if (MI->getOpcode() != PPC::RLWIMI)
151 return TargetInstrInfo::commuteInstruction(MI, NewMI);
153 // Cannot commute if it has a non-zero rotate count.
154 if (MI->getOperand(3).getImm() != 0)
157 // If we have a zero rotate count, we have:
159 // Op0 = (Op1 & ~M) | (Op2 & M)
161 // M = mask((ME+1)&31, (MB-1)&31)
162 // Op0 = (Op2 & ~M) | (Op1 & M)
165 unsigned Reg0 = MI->getOperand(0).getReg();
166 unsigned Reg1 = MI->getOperand(1).getReg();
167 unsigned Reg2 = MI->getOperand(2).getReg();
168 bool Reg1IsKill = MI->getOperand(1).isKill();
169 bool Reg2IsKill = MI->getOperand(2).isKill();
170 bool ChangeReg0 = false;
171 // If machine instrs are no longer in two-address forms, update
172 // destination register as well.
174 // Must be two address instruction!
175 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
176 "Expecting a two-address instruction!");
182 unsigned MB = MI->getOperand(4).getImm();
183 unsigned ME = MI->getOperand(5).getImm();
186 // Create a new instruction.
187 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
188 bool Reg0IsDead = MI->getOperand(0).isDead();
189 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
190 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
191 .addReg(Reg2, getKillRegState(Reg2IsKill))
192 .addReg(Reg1, getKillRegState(Reg1IsKill))
194 .addImm((MB-1) & 31);
198 MI->getOperand(0).setReg(Reg2);
199 MI->getOperand(2).setReg(Reg1);
200 MI->getOperand(1).setReg(Reg2);
201 MI->getOperand(2).setIsKill(Reg1IsKill);
202 MI->getOperand(1).setIsKill(Reg2IsKill);
204 // Swap the mask around.
205 MI->getOperand(4).setImm((ME+1) & 31);
206 MI->getOperand(5).setImm((MB-1) & 31);
210 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
211 MachineBasicBlock::iterator MI) const {
213 BuildMI(MBB, MI, DL, get(PPC::NOP));
218 // Note: If the condition register is set to CTR or CTR8 then this is a
219 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
220 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
221 MachineBasicBlock *&FBB,
222 SmallVectorImpl<MachineOperand> &Cond,
223 bool AllowModify) const {
224 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
226 // If the block has no terminators, it just falls into the block after it.
227 MachineBasicBlock::iterator I = MBB.end();
228 if (I == MBB.begin())
231 while (I->isDebugValue()) {
232 if (I == MBB.begin())
236 if (!isUnpredicatedTerminator(I))
239 // Get the last instruction in the block.
240 MachineInstr *LastInst = I;
242 // If there is only one terminator instruction, process it.
243 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
244 if (LastInst->getOpcode() == PPC::B) {
245 if (!LastInst->getOperand(0).isMBB())
247 TBB = LastInst->getOperand(0).getMBB();
249 } else if (LastInst->getOpcode() == PPC::BCC) {
250 if (!LastInst->getOperand(2).isMBB())
252 // Block ends with fall-through condbranch.
253 TBB = LastInst->getOperand(2).getMBB();
254 Cond.push_back(LastInst->getOperand(0));
255 Cond.push_back(LastInst->getOperand(1));
257 } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
258 LastInst->getOpcode() == PPC::BDNZ) {
259 if (!LastInst->getOperand(0).isMBB())
261 if (DisableCTRLoopAnal)
263 TBB = LastInst->getOperand(0).getMBB();
264 Cond.push_back(MachineOperand::CreateImm(1));
265 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
268 } else if (LastInst->getOpcode() == PPC::BDZ8 ||
269 LastInst->getOpcode() == PPC::BDZ) {
270 if (!LastInst->getOperand(0).isMBB())
272 if (DisableCTRLoopAnal)
274 TBB = LastInst->getOperand(0).getMBB();
275 Cond.push_back(MachineOperand::CreateImm(0));
276 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
281 // Otherwise, don't know what this is.
285 // Get the instruction before it if it's a terminator.
286 MachineInstr *SecondLastInst = I;
288 // If there are three terminators, we don't know what sort of block this is.
289 if (SecondLastInst && I != MBB.begin() &&
290 isUnpredicatedTerminator(--I))
293 // If the block ends with PPC::B and PPC:BCC, handle it.
294 if (SecondLastInst->getOpcode() == PPC::BCC &&
295 LastInst->getOpcode() == PPC::B) {
296 if (!SecondLastInst->getOperand(2).isMBB() ||
297 !LastInst->getOperand(0).isMBB())
299 TBB = SecondLastInst->getOperand(2).getMBB();
300 Cond.push_back(SecondLastInst->getOperand(0));
301 Cond.push_back(SecondLastInst->getOperand(1));
302 FBB = LastInst->getOperand(0).getMBB();
304 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
305 SecondLastInst->getOpcode() == PPC::BDNZ) &&
306 LastInst->getOpcode() == PPC::B) {
307 if (!SecondLastInst->getOperand(0).isMBB() ||
308 !LastInst->getOperand(0).isMBB())
310 if (DisableCTRLoopAnal)
312 TBB = SecondLastInst->getOperand(0).getMBB();
313 Cond.push_back(MachineOperand::CreateImm(1));
314 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
316 FBB = LastInst->getOperand(0).getMBB();
318 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
319 SecondLastInst->getOpcode() == PPC::BDZ) &&
320 LastInst->getOpcode() == PPC::B) {
321 if (!SecondLastInst->getOperand(0).isMBB() ||
322 !LastInst->getOperand(0).isMBB())
324 if (DisableCTRLoopAnal)
326 TBB = SecondLastInst->getOperand(0).getMBB();
327 Cond.push_back(MachineOperand::CreateImm(0));
328 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
330 FBB = LastInst->getOperand(0).getMBB();
334 // If the block ends with two PPC:Bs, handle it. The second one is not
335 // executed, so remove it.
336 if (SecondLastInst->getOpcode() == PPC::B &&
337 LastInst->getOpcode() == PPC::B) {
338 if (!SecondLastInst->getOperand(0).isMBB())
340 TBB = SecondLastInst->getOperand(0).getMBB();
343 I->eraseFromParent();
347 // Otherwise, can't handle this.
351 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
352 MachineBasicBlock::iterator I = MBB.end();
353 if (I == MBB.begin()) return 0;
355 while (I->isDebugValue()) {
356 if (I == MBB.begin())
360 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
361 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
362 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
365 // Remove the branch.
366 I->eraseFromParent();
370 if (I == MBB.begin()) return 1;
372 if (I->getOpcode() != PPC::BCC &&
373 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
374 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
377 // Remove the branch.
378 I->eraseFromParent();
383 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
384 MachineBasicBlock *FBB,
385 const SmallVectorImpl<MachineOperand> &Cond,
387 // Shouldn't be a fall through.
388 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
389 assert((Cond.size() == 2 || Cond.size() == 0) &&
390 "PPC branch conditions have two components!");
392 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
396 if (Cond.empty()) // Unconditional branch
397 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
398 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
399 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
400 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
401 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
402 else // Conditional branch
403 BuildMI(&MBB, DL, get(PPC::BCC))
404 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
408 // Two-way Conditional Branch.
409 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
410 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
411 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
412 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
414 BuildMI(&MBB, DL, get(PPC::BCC))
415 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
416 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
421 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
422 const SmallVectorImpl<MachineOperand> &Cond,
423 unsigned TrueReg, unsigned FalseReg,
424 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
425 if (!TM.getSubtargetImpl()->hasISEL())
428 if (Cond.size() != 2)
431 // If this is really a bdnz-like condition, then it cannot be turned into a
433 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
436 // Check register classes.
437 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
438 const TargetRegisterClass *RC =
439 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
443 // isel is for regular integer GPRs only.
444 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
445 !PPC::G8RCRegClass.hasSubClassEq(RC))
448 // FIXME: These numbers are for the A2, how well they work for other cores is
449 // an open question. On the A2, the isel instruction has a 2-cycle latency
450 // but single-cycle throughput. These numbers are used in combination with
451 // the MispredictPenalty setting from the active SchedMachineModel.
459 void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
460 MachineBasicBlock::iterator MI, DebugLoc dl,
462 const SmallVectorImpl<MachineOperand> &Cond,
463 unsigned TrueReg, unsigned FalseReg) const {
464 assert(Cond.size() == 2 &&
465 "PPC branch conditions have two components!");
467 assert(TM.getSubtargetImpl()->hasISEL() &&
468 "Cannot insert select on target without ISEL support");
470 // Get the register classes.
471 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
472 const TargetRegisterClass *RC =
473 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
474 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
475 assert((PPC::GPRCRegClass.hasSubClassEq(RC) ||
476 PPC::G8RCRegClass.hasSubClassEq(RC)) &&
477 "isel is for regular integer GPRs only");
480 PPC::GPRCRegClass.hasSubClassEq(RC) ? PPC::ISEL : PPC::ISEL8;
481 unsigned SelectPred = Cond[0].getImm();
485 switch (SelectPred) {
486 default: llvm_unreachable("invalid predicate for isel");
487 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
488 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
489 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
490 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
491 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
492 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
493 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
494 case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
497 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
498 SecondReg = SwapOps ? TrueReg : FalseReg;
500 // The first input register of isel cannot be r0. If it is a member
501 // of a register class that can be r0, then copy it first (the
502 // register allocator should eliminate the copy).
503 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
504 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
505 const TargetRegisterClass *FirstRC =
506 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
507 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
508 unsigned OldFirstReg = FirstReg;
509 FirstReg = MRI.createVirtualRegister(FirstRC);
510 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
511 .addReg(OldFirstReg);
514 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
515 .addReg(FirstReg).addReg(SecondReg)
516 .addReg(Cond[1].getReg(), 0, SubIdx);
519 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
520 MachineBasicBlock::iterator I, DebugLoc DL,
521 unsigned DestReg, unsigned SrcReg,
522 bool KillSrc) const {
524 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
526 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
528 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
530 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
532 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
534 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
537 llvm_unreachable("Impossible reg-to-reg copy");
539 const MCInstrDesc &MCID = get(Opc);
540 if (MCID.getNumOperands() == 3)
541 BuildMI(MBB, I, DL, MCID, DestReg)
542 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
544 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
547 // This function returns true if a CR spill is necessary and false otherwise.
549 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
550 unsigned SrcReg, bool isKill,
552 const TargetRegisterClass *RC,
553 SmallVectorImpl<MachineInstr*> &NewMIs,
554 bool &NonRI, bool &SpillsVRS) const{
555 // Note: If additional store instructions are added here,
556 // update isStoreToStackSlot.
559 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
560 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
562 getKillRegState(isKill)),
564 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
565 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
567 getKillRegState(isKill)),
569 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
570 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
572 getKillRegState(isKill)),
574 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
575 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
577 getKillRegState(isKill)),
579 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
580 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
582 getKillRegState(isKill)),
585 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
586 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
587 // backend currently only uses CR1EQ as an individual bit, this should
588 // not cause any bug. If we need other uses of CR bits, the following
589 // code may be invalid.
591 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
592 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
594 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
595 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
597 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
598 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
600 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
601 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
603 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
604 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
606 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
607 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
609 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
610 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
612 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
613 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
616 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
617 &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
619 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
620 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
622 getKillRegState(isKill)),
625 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
626 assert(TM.getSubtargetImpl()->isDarwin() &&
627 "VRSAVE only needs spill/restore on Darwin");
628 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
630 getKillRegState(isKill)),
634 llvm_unreachable("Unknown regclass!");
641 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
642 MachineBasicBlock::iterator MI,
643 unsigned SrcReg, bool isKill, int FrameIdx,
644 const TargetRegisterClass *RC,
645 const TargetRegisterInfo *TRI) const {
646 MachineFunction &MF = *MBB.getParent();
647 SmallVector<MachineInstr*, 4> NewMIs;
649 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
650 FuncInfo->setHasSpills();
652 bool NonRI = false, SpillsVRS = false;
653 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
655 FuncInfo->setSpillsCR();
658 FuncInfo->setSpillsVRSAVE();
661 FuncInfo->setHasNonRISpills();
663 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
664 MBB.insert(MI, NewMIs[i]);
666 const MachineFrameInfo &MFI = *MF.getFrameInfo();
667 MachineMemOperand *MMO =
668 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
669 MachineMemOperand::MOStore,
670 MFI.getObjectSize(FrameIdx),
671 MFI.getObjectAlignment(FrameIdx));
672 NewMIs.back()->addMemOperand(MF, MMO);
676 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
677 unsigned DestReg, int FrameIdx,
678 const TargetRegisterClass *RC,
679 SmallVectorImpl<MachineInstr*> &NewMIs,
680 bool &NonRI, bool &SpillsVRS) const{
681 // Note: If additional load instructions are added here,
682 // update isLoadFromStackSlot.
684 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
685 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
686 DestReg), FrameIdx));
687 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
688 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
690 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
691 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
693 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
694 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
696 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
697 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
698 get(PPC::RESTORE_CR), DestReg),
701 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
704 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
705 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
707 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
708 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
710 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
711 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
713 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
714 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
716 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
717 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
719 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
720 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
722 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
723 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
725 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
726 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
729 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
730 &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
732 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
733 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
736 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
737 assert(TM.getSubtargetImpl()->isDarwin() &&
738 "VRSAVE only needs spill/restore on Darwin");
739 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
740 get(PPC::RESTORE_VRSAVE),
745 llvm_unreachable("Unknown regclass!");
752 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
753 MachineBasicBlock::iterator MI,
754 unsigned DestReg, int FrameIdx,
755 const TargetRegisterClass *RC,
756 const TargetRegisterInfo *TRI) const {
757 MachineFunction &MF = *MBB.getParent();
758 SmallVector<MachineInstr*, 4> NewMIs;
760 if (MI != MBB.end()) DL = MI->getDebugLoc();
762 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
763 FuncInfo->setHasSpills();
765 bool NonRI = false, SpillsVRS = false;
766 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
768 FuncInfo->setSpillsCR();
771 FuncInfo->setSpillsVRSAVE();
774 FuncInfo->setHasNonRISpills();
776 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
777 MBB.insert(MI, NewMIs[i]);
779 const MachineFrameInfo &MFI = *MF.getFrameInfo();
780 MachineMemOperand *MMO =
781 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
782 MachineMemOperand::MOLoad,
783 MFI.getObjectSize(FrameIdx),
784 MFI.getObjectAlignment(FrameIdx));
785 NewMIs.back()->addMemOperand(MF, MMO);
789 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
790 int FrameIx, uint64_t Offset,
793 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
794 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
799 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
800 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
801 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
802 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
804 // Leave the CR# the same, but invert the condition.
805 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
809 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
810 unsigned Reg, MachineRegisterInfo *MRI) const {
811 // For some instructions, it is legal to fold ZERO into the RA register field.
812 // A zero immediate should always be loaded with a single li.
813 unsigned DefOpc = DefMI->getOpcode();
814 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
816 if (!DefMI->getOperand(1).isImm())
818 if (DefMI->getOperand(1).getImm() != 0)
821 // Note that we cannot here invert the arguments of an isel in order to fold
822 // a ZERO into what is presented as the second argument. All we have here
823 // is the condition bit, and that might come from a CR-logical bit operation.
825 const MCInstrDesc &UseMCID = UseMI->getDesc();
827 // Only fold into real machine instructions.
828 if (UseMCID.isPseudo())
832 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
833 if (UseMI->getOperand(UseIdx).isReg() &&
834 UseMI->getOperand(UseIdx).getReg() == Reg)
837 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
838 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
840 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
842 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
843 // register (which might also be specified as a pointer class kind).
844 if (UseInfo->isLookupPtrRegClass()) {
845 if (UseInfo->RegClass /* Kind */ != 1)
848 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
849 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
853 // Make sure this is not tied to an output register (or otherwise
854 // constrained). This is true for ST?UX registers, for example, which
855 // are tied to their output registers.
856 if (UseInfo->Constraints != 0)
860 if (UseInfo->isLookupPtrRegClass()) {
861 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
862 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
864 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
865 PPC::ZERO8 : PPC::ZERO;
868 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
869 UseMI->getOperand(UseIdx).setReg(ZeroReg);
872 DefMI->eraseFromParent();
877 /// GetInstSize - Return the number of bytes of code the specified
878 /// instruction may be. This returns the maximum number of bytes.
880 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
881 switch (MI->getOpcode()) {
882 case PPC::INLINEASM: { // Inline Asm: Variable size.
883 const MachineFunction *MF = MI->getParent()->getParent();
884 const char *AsmStr = MI->getOperand(0).getSymbolName();
885 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
887 case PPC::PROLOG_LABEL:
896 return 4; // PowerPC instructions are all 4 bytes