1 //===- PPCInstrInfo.h - PowerPC Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef POWERPC32_INSTRUCTIONINFO_H
15 #define POWERPC32_INSTRUCTIONINFO_H
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "PPCRegisterInfo.h"
23 /// PPCII - This namespace holds all of the PowerPC target-specific
24 /// per-instruction flags. These must match the corresponding definitions in
25 /// PPC.td and PPCInstrFormats.td.
28 // PPC970 Instruction Flags. These flags describe the characteristics of the
29 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
30 // raw machine instructions.
32 /// PPC970_First - This instruction starts a new dispatch group, so it will
33 /// always be the first one in the group.
36 /// PPC970_Single - This instruction starts a new dispatch group and
37 /// terminates it, so it will be the sole instruction in the group.
40 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
41 /// two dispatch pipes to be available to issue.
44 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
45 /// an instruction is issued to.
47 PPC970_Mask = 0x07 << PPC970_Shift
50 /// These are the various PPC970 execution unit pipelines. Each instruction
52 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
53 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
54 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
55 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
56 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
57 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
58 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
59 PPC970_BRU = 7 << PPC970_Shift // Branch Unit
64 class PPCInstrInfo : public TargetInstrInfoImpl {
66 const PPCRegisterInfo RI;
68 bool StoreRegToStackSlot(MachineFunction &MF,
69 unsigned SrcReg, bool isKill, int FrameIdx,
70 const TargetRegisterClass *RC,
71 SmallVectorImpl<MachineInstr*> &NewMIs) const;
72 void LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
73 unsigned DestReg, int FrameIdx,
74 const TargetRegisterClass *RC,
75 SmallVectorImpl<MachineInstr*> &NewMIs) const;
77 explicit PPCInstrInfo(PPCTargetMachine &TM);
79 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
80 /// such, whenever a client has an instance of instruction info, it should
81 /// always be able to get register info as well (through this method).
83 virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
85 /// Return true if the instruction is a register to register move and return
86 /// the source and dest operands and their sub-register indices by reference.
87 virtual bool isMoveInstr(const MachineInstr &MI,
88 unsigned &SrcReg, unsigned &DstReg,
89 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
91 unsigned isLoadFromStackSlot(const MachineInstr *MI,
92 int &FrameIndex) const;
93 unsigned isStoreToStackSlot(const MachineInstr *MI,
94 int &FrameIndex) const;
96 // commuteInstruction - We can commute rlwimi instructions, but only if the
97 // rotate amt is zero. We also have to munge the immediates a bit.
98 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
100 virtual void insertNoop(MachineBasicBlock &MBB,
101 MachineBasicBlock::iterator MI) const;
105 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
106 MachineBasicBlock *&FBB,
107 SmallVectorImpl<MachineOperand> &Cond,
108 bool AllowModify) const;
109 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
110 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
111 MachineBasicBlock *FBB,
112 const SmallVectorImpl<MachineOperand> &Cond) const;
113 virtual bool copyRegToReg(MachineBasicBlock &MBB,
114 MachineBasicBlock::iterator MI,
115 unsigned DestReg, unsigned SrcReg,
116 const TargetRegisterClass *DestRC,
117 const TargetRegisterClass *SrcRC) const;
119 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
120 MachineBasicBlock::iterator MBBI,
121 unsigned SrcReg, bool isKill, int FrameIndex,
122 const TargetRegisterClass *RC) const;
124 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
125 MachineBasicBlock::iterator MBBI,
126 unsigned DestReg, int FrameIndex,
127 const TargetRegisterClass *RC) const;
129 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
130 /// copy instructions, turning them into load/store instructions.
131 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
133 const SmallVectorImpl<unsigned> &Ops,
134 int FrameIndex) const;
136 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
138 const SmallVectorImpl<unsigned> &Ops,
139 MachineInstr* LoadMI) const {
143 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
144 const SmallVectorImpl<unsigned> &Ops) const;
147 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
149 /// GetInstSize - Return the number of bytes of code the specified
150 /// instruction may be. This returns the maximum number of bytes.
152 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;