1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef POWERPC_INSTRUCTIONINFO_H
15 #define POWERPC_INSTRUCTIONINFO_H
18 #include "PPCRegisterInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
21 #define GET_INSTRINFO_HEADER
22 #include "PPCGenInstrInfo.inc"
26 /// PPCII - This namespace holds all of the PowerPC target-specific
27 /// per-instruction flags. These must match the corresponding definitions in
28 /// PPC.td and PPCInstrFormats.td.
31 // PPC970 Instruction Flags. These flags describe the characteristics of the
32 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
33 // raw machine instructions.
35 /// PPC970_First - This instruction starts a new dispatch group, so it will
36 /// always be the first one in the group.
39 /// PPC970_Single - This instruction starts a new dispatch group and
40 /// terminates it, so it will be the sole instruction in the group.
43 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
44 /// two dispatch pipes to be available to issue.
47 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
48 /// an instruction is issued to.
50 PPC970_Mask = 0x07 << PPC970_Shift
53 /// These are the various PPC970 execution unit pipelines. Each instruction
55 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
56 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
57 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
58 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
59 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
60 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
61 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
62 PPC970_BRU = 7 << PPC970_Shift // Branch Unit
64 } // end namespace PPCII
67 class PPCInstrInfo : public PPCGenInstrInfo {
69 const PPCRegisterInfo RI;
71 bool StoreRegToStackSlot(MachineFunction &MF,
72 unsigned SrcReg, bool isKill, int FrameIdx,
73 const TargetRegisterClass *RC,
74 SmallVectorImpl<MachineInstr*> &NewMIs,
75 bool &NonRI, bool &SpillsVRS) const;
76 bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
77 unsigned DestReg, int FrameIdx,
78 const TargetRegisterClass *RC,
79 SmallVectorImpl<MachineInstr*> &NewMIs,
80 bool &NonRI, bool &SpillsVRS) const;
81 virtual void anchor();
83 explicit PPCInstrInfo(PPCTargetMachine &TM);
85 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
86 /// such, whenever a client has an instance of instruction info, it should
87 /// always be able to get register info as well (through this method).
89 virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
91 ScheduleHazardRecognizer *
92 CreateTargetHazardRecognizer(const TargetMachine *TM,
93 const ScheduleDAG *DAG) const;
94 ScheduleHazardRecognizer *
95 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
96 const ScheduleDAG *DAG) const;
99 int getOperandLatency(const InstrItineraryData *ItinData,
100 const MachineInstr *DefMI, unsigned DefIdx,
101 const MachineInstr *UseMI, unsigned UseIdx) const;
103 int getOperandLatency(const InstrItineraryData *ItinData,
104 SDNode *DefNode, unsigned DefIdx,
105 SDNode *UseNode, unsigned UseIdx) const {
106 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
110 bool isCoalescableExtInstr(const MachineInstr &MI,
111 unsigned &SrcReg, unsigned &DstReg,
112 unsigned &SubIdx) const;
113 unsigned isLoadFromStackSlot(const MachineInstr *MI,
114 int &FrameIndex) const;
115 unsigned isStoreToStackSlot(const MachineInstr *MI,
116 int &FrameIndex) const;
118 // commuteInstruction - We can commute rlwimi instructions, but only if the
119 // rotate amt is zero. We also have to munge the immediates a bit.
120 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
122 virtual void insertNoop(MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator MI) const;
127 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
128 MachineBasicBlock *&FBB,
129 SmallVectorImpl<MachineOperand> &Cond,
130 bool AllowModify) const;
131 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
132 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
133 MachineBasicBlock *FBB,
134 const SmallVectorImpl<MachineOperand> &Cond,
138 virtual bool canInsertSelect(const MachineBasicBlock&,
139 const SmallVectorImpl<MachineOperand> &Cond,
140 unsigned, unsigned, int&, int&, int&) const;
141 virtual void insertSelect(MachineBasicBlock &MBB,
142 MachineBasicBlock::iterator MI, DebugLoc DL,
144 const SmallVectorImpl<MachineOperand> &Cond,
145 unsigned TrueReg, unsigned FalseReg) const;
147 virtual void copyPhysReg(MachineBasicBlock &MBB,
148 MachineBasicBlock::iterator I, DebugLoc DL,
149 unsigned DestReg, unsigned SrcReg,
152 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
153 MachineBasicBlock::iterator MBBI,
154 unsigned SrcReg, bool isKill, int FrameIndex,
155 const TargetRegisterClass *RC,
156 const TargetRegisterInfo *TRI) const;
158 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
159 MachineBasicBlock::iterator MBBI,
160 unsigned DestReg, int FrameIndex,
161 const TargetRegisterClass *RC,
162 const TargetRegisterInfo *TRI) const;
165 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
167 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
168 unsigned Reg, MachineRegisterInfo *MRI) const;
170 // If conversion by predication (only supported by some branch instructions).
171 // All of the profitability checks always return true; it is always
172 // profitable to use the predicated branches.
173 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
174 unsigned NumCycles, unsigned ExtraPredCycles,
175 const BranchProbability &Probability) const {
179 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
180 unsigned NumT, unsigned ExtraT,
181 MachineBasicBlock &FMBB,
182 unsigned NumF, unsigned ExtraF,
183 const BranchProbability &Probability) const;
185 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
187 const BranchProbability
188 &Probability) const {
192 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
193 MachineBasicBlock &FMBB) const {
197 // Predication support.
198 bool isPredicated(const MachineInstr *MI) const;
200 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
203 bool PredicateInstruction(MachineInstr *MI,
204 const SmallVectorImpl<MachineOperand> &Pred) const;
207 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
208 const SmallVectorImpl<MachineOperand> &Pred2) const;
210 virtual bool DefinesPredicate(MachineInstr *MI,
211 std::vector<MachineOperand> &Pred) const;
213 virtual bool isPredicable(MachineInstr *MI) const;
215 // Comparison optimization.
218 virtual bool analyzeCompare(const MachineInstr *MI,
219 unsigned &SrcReg, unsigned &SrcReg2,
220 int &Mask, int &Value) const;
222 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr,
223 unsigned SrcReg, unsigned SrcReg2,
225 const MachineRegisterInfo *MRI) const;
227 /// GetInstSize - Return the number of bytes of code the specified
228 /// instruction may be. This returns the maximum number of bytes.
230 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;