1 //===- PPCInstrInfo.h - PowerPC Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef POWERPC32_INSTRUCTIONINFO_H
15 #define POWERPC32_INSTRUCTIONINFO_H
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "PPCRegisterInfo.h"
23 /// PPCII - This namespace holds all of the PowerPC target-specific
24 /// per-instruction flags. These must match the corresponding definitions in
25 /// PPC.td and PPCInstrFormats.td.
28 // PPC970 Instruction Flags. These flags describe the characteristics of the
29 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
30 // raw machine instructions.
32 /// PPC970_First - This instruction starts a new dispatch group, so it will
33 /// always be the first one in the group.
36 /// PPC970_Single - This instruction starts a new dispatch group and
37 /// terminates it, so it will be the sole instruction in the group.
40 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
41 /// two dispatch pipes to be available to issue.
44 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
45 /// an instruction is issued to.
47 PPC970_Mask = 0x07 << PPC970_Shift,
50 /// These are the various PPC970 execution unit pipelines. Each instruction
52 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
53 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
54 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
55 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
56 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
57 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
58 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
59 PPC970_BRU = 7 << PPC970_Shift, // Branch Unit
64 class PPCInstrInfo : public TargetInstrInfo {
65 const PPCRegisterInfo RI;
69 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
70 /// such, whenever a client has an instance of instruction info, it should
71 /// always be able to get register info as well (through this method).
73 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
76 // Return true if the instruction is a register to register move and
77 // leave the source and dest operands in the passed parameters.
79 virtual bool isMoveInstr(const MachineInstr& MI,
81 unsigned& destReg) const;
83 unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
84 unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
86 // commuteInstruction - We can commute rlwimi instructions, but only if the
87 // rotate amt is zero. We also have to munge the immediates a bit.
88 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
90 virtual void insertNoop(MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator MI) const;
93 static unsigned invertPPCBranchOpcode(unsigned Opcode) {
95 default: assert(0 && "Unknown PPC branch opcode!");
96 case PPC::BEQ: return PPC::BNE;
97 case PPC::BNE: return PPC::BEQ;
98 case PPC::BLT: return PPC::BGE;
99 case PPC::BGE: return PPC::BLT;
100 case PPC::BGT: return PPC::BLE;
101 case PPC::BLE: return PPC::BGT;
102 case PPC::BNU: return PPC::BUN;
103 case PPC::BUN: return PPC::BNU;