1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 3, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 4, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
46 def SDT_PPClarx : SDTypeProfile<1, 2, [
47 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>
49 def SDT_PPCstcx : SDTypeProfile<0, 3, [
50 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>
52 def SDT_PPCcmp_unres : SDTypeProfile<0, 3, [
53 SDTCisSameAs<0, 1>, SDTCisInt<1>, SDTCisVT<2, i32>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
60 //===----------------------------------------------------------------------===//
61 // PowerPC specific DAG Nodes.
64 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
65 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
66 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
67 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
68 [SDNPHasChain, SDNPMayStore]>;
70 // This sequence is used for long double->int conversions. It changes the
71 // bits in the FPSCR which is not modelled.
72 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
74 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
75 [SDNPInFlag, SDNPOutFlag]>;
76 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
77 [SDNPInFlag, SDNPOutFlag]>;
78 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
79 [SDNPInFlag, SDNPOutFlag]>;
80 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
81 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
85 def PPCfsel : SDNode<"PPCISD::FSEL",
86 // Type constraint for fsel.
87 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
88 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
90 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
91 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
92 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
93 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
95 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
97 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
98 // amounts. These nodes are generated by the multi-precision shift code.
99 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
100 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
101 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
103 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
104 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
105 [SDNPHasChain, SDNPMayStore]>;
107 // These are target-independent nodes, but have target-specific formats.
108 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
109 [SDNPHasChain, SDNPOutFlag]>;
110 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
111 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
113 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
114 def PPCcall_Macho : SDNode<"PPCISD::CALL_Macho", SDT_PPCCall,
115 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
116 def PPCcall_ELF : SDNode<"PPCISD::CALL_ELF", SDT_PPCCall,
117 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
118 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
119 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
120 def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTNone,
121 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
123 def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTNone,
124 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
126 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
127 [SDNPHasChain, SDNPOptInFlag]>;
129 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
130 [SDNPHasChain, SDNPOptInFlag]>;
132 def PPCtailcall : SDNode<"PPCISD::TAILCALL", SDT_PPCCall,
133 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
135 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
136 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
138 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
139 [SDNPHasChain, SDNPOptInFlag]>;
141 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
142 [SDNPHasChain, SDNPMayLoad]>;
143 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
144 [SDNPHasChain, SDNPMayStore]>;
146 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
147 [SDNPHasChain, SDNPMayLoad]>;
148 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
149 [SDNPHasChain, SDNPMayStore]>;
150 def PPCcmp_unres : SDNode<"PPCISD::CMP_UNRESERVE", SDT_PPCcmp_unres,
153 // Instructions to support dynamic alloca.
154 def SDTDynOp : SDTypeProfile<1, 2, []>;
155 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
157 //===----------------------------------------------------------------------===//
158 // PowerPC specific transformation functions and pattern fragments.
161 def SHL32 : SDNodeXForm<imm, [{
162 // Transformation function: 31 - imm
163 return getI32Imm(31 - N->getValue());
166 def SRL32 : SDNodeXForm<imm, [{
167 // Transformation function: 32 - imm
168 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
171 def LO16 : SDNodeXForm<imm, [{
172 // Transformation function: get the low 16 bits.
173 return getI32Imm((unsigned short)N->getValue());
176 def HI16 : SDNodeXForm<imm, [{
177 // Transformation function: shift the immediate value down into the low bits.
178 return getI32Imm((unsigned)N->getValue() >> 16);
181 def HA16 : SDNodeXForm<imm, [{
182 // Transformation function: shift the immediate value down into the low bits.
183 signed int Val = N->getValue();
184 return getI32Imm((Val - (signed short)Val) >> 16);
186 def MB : SDNodeXForm<imm, [{
187 // Transformation function: get the start bit of a mask
189 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
190 return getI32Imm(mb);
193 def ME : SDNodeXForm<imm, [{
194 // Transformation function: get the end bit of a mask
196 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
197 return getI32Imm(me);
199 def maskimm32 : PatLeaf<(imm), [{
200 // maskImm predicate - True if immediate is a run of ones.
202 if (N->getValueType(0) == MVT::i32)
203 return isRunOfOnes((unsigned)N->getValue(), mb, me);
208 def immSExt16 : PatLeaf<(imm), [{
209 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
210 // field. Used by instructions like 'addi'.
211 if (N->getValueType(0) == MVT::i32)
212 return (int32_t)N->getValue() == (short)N->getValue();
214 return (int64_t)N->getValue() == (short)N->getValue();
216 def immZExt16 : PatLeaf<(imm), [{
217 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
218 // field. Used by instructions like 'ori'.
219 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
222 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
223 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
224 // identical in 32-bit mode, but in 64-bit mode, they return true if the
225 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
227 def imm16ShiftedZExt : PatLeaf<(imm), [{
228 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
229 // immediate are set. Used by instructions like 'xoris'.
230 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
233 def imm16ShiftedSExt : PatLeaf<(imm), [{
234 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
235 // immediate are set. Used by instructions like 'addis'. Identical to
236 // imm16ShiftedZExt in 32-bit mode.
237 if (N->getValue() & 0xFFFF) return false;
238 if (N->getValueType(0) == MVT::i32)
240 // For 64-bit, make sure it is sext right.
241 return N->getValue() == (uint64_t)(int)N->getValue();
245 //===----------------------------------------------------------------------===//
246 // PowerPC Flag Definitions.
248 class isPPC64 { bit PPC64 = 1; }
250 list<Register> Defs = [CR0];
254 class RegConstraint<string C> {
255 string Constraints = C;
257 class NoEncode<string E> {
258 string DisableEncoding = E;
262 //===----------------------------------------------------------------------===//
263 // PowerPC Operand Definitions.
265 def s5imm : Operand<i32> {
266 let PrintMethod = "printS5ImmOperand";
268 def u5imm : Operand<i32> {
269 let PrintMethod = "printU5ImmOperand";
271 def u6imm : Operand<i32> {
272 let PrintMethod = "printU6ImmOperand";
274 def s16imm : Operand<i32> {
275 let PrintMethod = "printS16ImmOperand";
277 def u16imm : Operand<i32> {
278 let PrintMethod = "printU16ImmOperand";
280 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
281 let PrintMethod = "printS16X4ImmOperand";
283 def target : Operand<OtherVT> {
284 let PrintMethod = "printBranchOperand";
286 def calltarget : Operand<iPTR> {
287 let PrintMethod = "printCallOperand";
289 def aaddr : Operand<iPTR> {
290 let PrintMethod = "printAbsAddrOperand";
292 def piclabel: Operand<iPTR> {
293 let PrintMethod = "printPICLabel";
295 def symbolHi: Operand<i32> {
296 let PrintMethod = "printSymbolHi";
298 def symbolLo: Operand<i32> {
299 let PrintMethod = "printSymbolLo";
301 def crbitm: Operand<i8> {
302 let PrintMethod = "printcrbitm";
305 def memri : Operand<iPTR> {
306 let PrintMethod = "printMemRegImm";
307 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
309 def memrr : Operand<iPTR> {
310 let PrintMethod = "printMemRegReg";
311 let MIOperandInfo = (ops ptr_rc, ptr_rc);
313 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
314 let PrintMethod = "printMemRegImmShifted";
315 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
318 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
319 // that doesn't matter.
320 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
321 (ops (i32 20), (i32 zero_reg))> {
322 let PrintMethod = "printPredicateOperand";
325 // Define PowerPC specific addressing mode.
326 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
327 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
328 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
329 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
331 /// This is just the offset part of iaddr, used for preinc.
332 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
334 //===----------------------------------------------------------------------===//
335 // PowerPC Instruction Predicate Definitions.
336 def FPContractions : Predicate<"!NoExcessFPPrecision">;
337 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
338 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
341 //===----------------------------------------------------------------------===//
342 // PowerPC Instruction Definitions.
344 // Pseudo-instructions:
346 let hasCtrlDep = 1 in {
347 let Defs = [R1], Uses = [R1] in {
348 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
349 "${:comment} ADJCALLSTACKDOWN",
350 [(callseq_start imm:$amt)]>;
351 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
352 "${:comment} ADJCALLSTACKUP",
353 [(callseq_end imm:$amt1, imm:$amt2)]>;
356 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
357 "UPDATE_VRSAVE $rD, $rS", []>;
360 let Defs = [R1], Uses = [R1] in
361 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
362 "${:comment} DYNALLOC $result, $negsize, $fpsi",
364 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
366 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
367 // scheduler into a branch sequence.
368 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
369 PPC970_Single = 1 in {
370 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
371 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
373 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
374 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
376 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
377 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
379 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
380 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
382 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
383 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
387 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
388 // scavenge a register for it.
389 def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F),
390 "${:comment} SPILL_CR $cond $F", []>;
392 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
394 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
395 "b${p:cc}lr ${p:reg}", BrB,
397 let isBranch = 1, isIndirectBranch = 1 in
398 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
402 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
405 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
406 let isBarrier = 1 in {
407 def B : IForm<18, 0, 0, (outs), (ins target:$dst),
412 // BCC represents an arbitrary conditional branch on a predicate.
413 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
414 // a two-value operand where a dag node expects two operands. :(
415 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst),
416 "b${cond:cc} ${cond:reg}, $dst"
417 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
421 let isCall = 1, PPC970_Unit = 7,
422 // All calls clobber the non-callee saved registers...
423 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
424 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
425 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
428 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
429 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
430 // Convenient aliases for call instructions
431 def BL_Macho : IForm<18, 0, 1,
432 (outs), (ins calltarget:$func, variable_ops),
433 "bl $func", BrB, []>; // See Pat patterns below.
434 def BLA_Macho : IForm<18, 1, 1,
435 (outs), (ins aaddr:$func, variable_ops),
436 "bla $func", BrB, [(PPCcall_Macho (i32 imm:$func))]>;
437 def BCTRL_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
438 (outs), (ins variable_ops),
440 [(PPCbctrl_Macho)]>, Requires<[In32BitMode]>;
444 let isCall = 1, PPC970_Unit = 7,
445 // All calls clobber the non-callee saved registers...
446 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
447 F0,F1,F2,F3,F4,F5,F6,F7,F8,
448 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
451 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
452 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
453 // Convenient aliases for call instructions
454 def BL_ELF : IForm<18, 0, 1,
455 (outs), (ins calltarget:$func, variable_ops),
456 "bl $func", BrB, []>; // See Pat patterns below.
457 def BLA_ELF : IForm<18, 1, 1,
458 (outs), (ins aaddr:$func, variable_ops),
460 [(PPCcall_ELF (i32 imm:$func))]>;
461 def BCTRL_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
462 (outs), (ins variable_ops),
464 [(PPCbctrl_ELF)]>, Requires<[In32BitMode]>;
468 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
469 def TCRETURNdi :Pseudo< (outs),
470 (ins calltarget:$dst, i32imm:$offset, variable_ops),
471 "#TC_RETURNd $dst $offset",
475 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
476 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
477 "#TC_RETURNa $func $offset",
478 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
480 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
481 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops),
482 "#TC_RETURNr $dst $offset",
486 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
487 isIndirectBranch = 1, isCall = 1, isReturn = 1 in
488 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
489 Requires<[In32BitMode]>;
493 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
494 isBarrier = 1, isCall = 1, isReturn = 1 in
495 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
500 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
501 isBarrier = 1, isCall = 1, isReturn = 1 in
502 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
507 // DCB* instructions.
508 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
509 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
510 PPC970_DGroup_Single;
511 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
512 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
513 PPC970_DGroup_Single;
514 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
515 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
516 PPC970_DGroup_Single;
517 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
518 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
519 PPC970_DGroup_Single;
520 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
521 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
522 PPC970_DGroup_Single;
523 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
524 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
525 PPC970_DGroup_Single;
526 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
527 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
528 PPC970_DGroup_Single;
529 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
530 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
531 PPC970_DGroup_Single;
533 // Atomic operations.
534 def LWARX : Pseudo<(outs GPRC:$rD), (ins memrr:$ptr, i32imm:$label),
535 "\nLa${label}_entry:\n\tlwarx $rD, $ptr",
536 [(set GPRC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>;
538 let Defs = [CR0] in {
539 def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label),
540 "stwcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:",
541 [(PPCstcx GPRC:$rS, xoaddr:$dst, imm:$label)]>;
543 def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm:$label),
544 "cmpw $rA, $rB\n\tbne- La${label}_exit",
545 [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm:$label)]>;
546 def CMP_UNRESwi : Pseudo<(outs), (ins GPRC:$rA, s16imm:$imm, i32imm:$label),
547 "cmpwi $rA, $imm\n\tbne- La${label}_exit",
548 [(PPCcmp_unres GPRC:$rA, immSExt16:$imm, imm:$label)]>;
551 //===----------------------------------------------------------------------===//
552 // PPC32 Load Instructions.
555 // Unindexed (r+i) Loads.
556 let isSimpleLoad = 1, PPC970_Unit = 2 in {
557 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
558 "lbz $rD, $src", LdStGeneral,
559 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
560 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
561 "lha $rD, $src", LdStLHA,
562 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
563 PPC970_DGroup_Cracked;
564 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
565 "lhz $rD, $src", LdStGeneral,
566 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
567 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
568 "lwz $rD, $src", LdStGeneral,
569 [(set GPRC:$rD, (load iaddr:$src))]>;
571 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
572 "lfs $rD, $src", LdStLFDU,
573 [(set F4RC:$rD, (load iaddr:$src))]>;
574 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
575 "lfd $rD, $src", LdStLFD,
576 [(set F8RC:$rD, (load iaddr:$src))]>;
579 // Unindexed (r+i) Loads with Update (preinc).
580 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
581 "lbzu $rD, $addr", LdStGeneral,
582 []>, RegConstraint<"$addr.reg = $ea_result">,
583 NoEncode<"$ea_result">;
585 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
586 "lhau $rD, $addr", LdStGeneral,
587 []>, RegConstraint<"$addr.reg = $ea_result">,
588 NoEncode<"$ea_result">;
590 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
591 "lhzu $rD, $addr", LdStGeneral,
592 []>, RegConstraint<"$addr.reg = $ea_result">,
593 NoEncode<"$ea_result">;
595 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
596 "lwzu $rD, $addr", LdStGeneral,
597 []>, RegConstraint<"$addr.reg = $ea_result">,
598 NoEncode<"$ea_result">;
600 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
601 "lfs $rD, $addr", LdStLFDU,
602 []>, RegConstraint<"$addr.reg = $ea_result">,
603 NoEncode<"$ea_result">;
605 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
606 "lfd $rD, $addr", LdStLFD,
607 []>, RegConstraint<"$addr.reg = $ea_result">,
608 NoEncode<"$ea_result">;
611 // Indexed (r+r) Loads.
613 let isSimpleLoad = 1, PPC970_Unit = 2 in {
614 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
615 "lbzx $rD, $src", LdStGeneral,
616 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
617 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
618 "lhax $rD, $src", LdStLHA,
619 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
620 PPC970_DGroup_Cracked;
621 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
622 "lhzx $rD, $src", LdStGeneral,
623 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
624 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
625 "lwzx $rD, $src", LdStGeneral,
626 [(set GPRC:$rD, (load xaddr:$src))]>;
629 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
630 "lhbrx $rD, $src", LdStGeneral,
631 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
632 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
633 "lwbrx $rD, $src", LdStGeneral,
634 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
636 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
637 "lfsx $frD, $src", LdStLFDU,
638 [(set F4RC:$frD, (load xaddr:$src))]>;
639 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
640 "lfdx $frD, $src", LdStLFDU,
641 [(set F8RC:$frD, (load xaddr:$src))]>;
644 //===----------------------------------------------------------------------===//
645 // PPC32 Store Instructions.
648 // Unindexed (r+i) Stores.
649 let PPC970_Unit = 2 in {
650 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
651 "stb $rS, $src", LdStGeneral,
652 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
653 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
654 "sth $rS, $src", LdStGeneral,
655 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
656 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
657 "stw $rS, $src", LdStGeneral,
658 [(store GPRC:$rS, iaddr:$src)]>;
659 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
660 "stfs $rS, $dst", LdStUX,
661 [(store F4RC:$rS, iaddr:$dst)]>;
662 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
663 "stfd $rS, $dst", LdStUX,
664 [(store F8RC:$rS, iaddr:$dst)]>;
667 // Unindexed (r+i) Stores with Update (preinc).
668 let PPC970_Unit = 2 in {
669 def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
670 symbolLo:$ptroff, ptr_rc:$ptrreg),
671 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
672 [(set ptr_rc:$ea_res,
673 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
674 iaddroff:$ptroff))]>,
675 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
676 def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
677 symbolLo:$ptroff, ptr_rc:$ptrreg),
678 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
679 [(set ptr_rc:$ea_res,
680 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
681 iaddroff:$ptroff))]>,
682 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
683 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
684 symbolLo:$ptroff, ptr_rc:$ptrreg),
685 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
686 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
687 iaddroff:$ptroff))]>,
688 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
689 def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
690 symbolLo:$ptroff, ptr_rc:$ptrreg),
691 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
692 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
693 iaddroff:$ptroff))]>,
694 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
695 def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
696 symbolLo:$ptroff, ptr_rc:$ptrreg),
697 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
698 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
699 iaddroff:$ptroff))]>,
700 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
704 // Indexed (r+r) Stores.
706 let PPC970_Unit = 2 in {
707 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
708 "stbx $rS, $dst", LdStGeneral,
709 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
710 PPC970_DGroup_Cracked;
711 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
712 "sthx $rS, $dst", LdStGeneral,
713 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
714 PPC970_DGroup_Cracked;
715 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
716 "stwx $rS, $dst", LdStGeneral,
717 [(store GPRC:$rS, xaddr:$dst)]>,
718 PPC970_DGroup_Cracked;
720 let mayStore = 1 in {
721 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
722 "stwux $rS, $rA, $rB", LdStGeneral,
725 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
726 "sthbrx $rS, $dst", LdStGeneral,
727 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
728 PPC970_DGroup_Cracked;
729 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
730 "stwbrx $rS, $dst", LdStGeneral,
731 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
732 PPC970_DGroup_Cracked;
734 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
735 "stfiwx $frS, $dst", LdStUX,
736 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
738 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
739 "stfsx $frS, $dst", LdStUX,
740 [(store F4RC:$frS, xaddr:$dst)]>;
741 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
742 "stfdx $frS, $dst", LdStUX,
743 [(store F8RC:$frS, xaddr:$dst)]>;
747 //===----------------------------------------------------------------------===//
748 // PPC32 Arithmetic Instructions.
751 let PPC970_Unit = 1 in { // FXU Operations.
752 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
753 "addi $rD, $rA, $imm", IntGeneral,
754 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
755 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
756 "addic $rD, $rA, $imm", IntGeneral,
757 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
758 PPC970_DGroup_Cracked;
759 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
760 "addic. $rD, $rA, $imm", IntGeneral,
762 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
763 "addis $rD, $rA, $imm", IntGeneral,
764 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
765 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
766 "la $rD, $sym($rA)", IntGeneral,
767 [(set GPRC:$rD, (add GPRC:$rA,
768 (PPClo tglobaladdr:$sym, 0)))]>;
769 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
770 "mulli $rD, $rA, $imm", IntMulLI,
771 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
772 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
773 "subfic $rD, $rA, $imm", IntGeneral,
774 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
776 let isReMaterializable = 1 in {
777 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
778 "li $rD, $imm", IntGeneral,
779 [(set GPRC:$rD, immSExt16:$imm)]>;
780 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
781 "lis $rD, $imm", IntGeneral,
782 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
786 let PPC970_Unit = 1 in { // FXU Operations.
787 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
788 "andi. $dst, $src1, $src2", IntGeneral,
789 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
791 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
792 "andis. $dst, $src1, $src2", IntGeneral,
793 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
795 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
796 "ori $dst, $src1, $src2", IntGeneral,
797 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
798 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
799 "oris $dst, $src1, $src2", IntGeneral,
800 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
801 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
802 "xori $dst, $src1, $src2", IntGeneral,
803 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
804 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
805 "xoris $dst, $src1, $src2", IntGeneral,
806 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
807 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
809 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
810 "cmpwi $crD, $rA, $imm", IntCompare>;
811 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
812 "cmplwi $dst, $src1, $src2", IntCompare>;
816 let PPC970_Unit = 1 in { // FXU Operations.
817 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
818 "nand $rA, $rS, $rB", IntGeneral,
819 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
820 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
821 "and $rA, $rS, $rB", IntGeneral,
822 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
823 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
824 "andc $rA, $rS, $rB", IntGeneral,
825 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
826 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
827 "or $rA, $rS, $rB", IntGeneral,
828 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
829 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
830 "nor $rA, $rS, $rB", IntGeneral,
831 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
832 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
833 "orc $rA, $rS, $rB", IntGeneral,
834 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
835 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
836 "eqv $rA, $rS, $rB", IntGeneral,
837 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
838 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
839 "xor $rA, $rS, $rB", IntGeneral,
840 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
841 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
842 "slw $rA, $rS, $rB", IntGeneral,
843 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
844 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
845 "srw $rA, $rS, $rB", IntGeneral,
846 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
847 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
848 "sraw $rA, $rS, $rB", IntShift,
849 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
852 let PPC970_Unit = 1 in { // FXU Operations.
853 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
854 "srawi $rA, $rS, $SH", IntShift,
855 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
856 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
857 "cntlzw $rA, $rS", IntGeneral,
858 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
859 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
860 "extsb $rA, $rS", IntGeneral,
861 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
862 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
863 "extsh $rA, $rS", IntGeneral,
864 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
866 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
867 "cmpw $crD, $rA, $rB", IntCompare>;
868 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
869 "cmplw $crD, $rA, $rB", IntCompare>;
871 let PPC970_Unit = 3 in { // FPU Operations.
872 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
873 // "fcmpo $crD, $fA, $fB", FPCompare>;
874 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
875 "fcmpu $crD, $fA, $fB", FPCompare>;
876 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
877 "fcmpu $crD, $fA, $fB", FPCompare>;
879 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
880 "fctiwz $frD, $frB", FPGeneral,
881 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
882 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
883 "frsp $frD, $frB", FPGeneral,
884 [(set F4RC:$frD, (fround F8RC:$frB))]>;
885 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
886 "fsqrt $frD, $frB", FPSqrt,
887 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
888 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
889 "fsqrts $frD, $frB", FPSqrt,
890 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
893 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
895 /// Note that these are defined as pseudo-ops on the PPC970 because they are
896 /// often coalesced away and we don't want the dispatch group builder to think
897 /// that they will fill slots (which could cause the load of a LSU reject to
898 /// sneak into a d-group with a store).
899 def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
900 "fmr $frD, $frB", FPGeneral,
901 []>, // (set F4RC:$frD, F4RC:$frB)
903 def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB),
904 "fmr $frD, $frB", FPGeneral,
905 []>, // (set F8RC:$frD, F8RC:$frB)
907 def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB),
908 "fmr $frD, $frB", FPGeneral,
909 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
912 let PPC970_Unit = 3 in { // FPU Operations.
913 // These are artificially split into two different forms, for 4/8 byte FP.
914 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
915 "fabs $frD, $frB", FPGeneral,
916 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
917 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
918 "fabs $frD, $frB", FPGeneral,
919 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
920 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
921 "fnabs $frD, $frB", FPGeneral,
922 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
923 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
924 "fnabs $frD, $frB", FPGeneral,
925 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
926 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
927 "fneg $frD, $frB", FPGeneral,
928 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
929 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
930 "fneg $frD, $frB", FPGeneral,
931 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
935 // XL-Form instructions. condition register logical ops.
937 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
938 "mcrf $BF, $BFA", BrMCR>,
939 PPC970_DGroup_First, PPC970_Unit_CRU;
941 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
942 (ins CRBITRC:$CRA, CRBITRC:$CRB),
943 "creqv $CRD, $CRA, $CRB", BrCR,
946 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
947 (ins CRBITRC:$CRA, CRBITRC:$CRB),
948 "cror $CRD, $CRA, $CRB", BrCR,
951 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
952 "creqv $dst, $dst, $dst", BrCR,
955 // XFX-Form instructions. Instructions that deal with SPRs.
957 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
958 "mfctr $rT", SprMFSPR>,
959 PPC970_DGroup_First, PPC970_Unit_FXU;
960 let Pattern = [(PPCmtctr GPRC:$rS)] in {
961 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
962 "mtctr $rS", SprMTSPR>,
963 PPC970_DGroup_First, PPC970_Unit_FXU;
966 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
967 "mtlr $rS", SprMTSPR>,
968 PPC970_DGroup_First, PPC970_Unit_FXU;
969 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
970 "mflr $rT", SprMFSPR>,
971 PPC970_DGroup_First, PPC970_Unit_FXU;
973 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
974 // a GPR on the PPC970. As such, copies in and out have the same performance
975 // characteristics as an OR instruction.
976 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
977 "mtspr 256, $rS", IntGeneral>,
978 PPC970_DGroup_Single, PPC970_Unit_FXU;
979 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
980 "mfspr $rT, 256", IntGeneral>,
981 PPC970_DGroup_First, PPC970_Unit_FXU;
983 def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
984 "mtcrf $FXM, $rS", BrMCRX>,
985 PPC970_MicroCode, PPC970_Unit_CRU;
986 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>,
987 PPC970_MicroCode, PPC970_Unit_CRU;
988 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
989 "mfcr $rT, $FXM", SprMFCR>,
990 PPC970_DGroup_First, PPC970_Unit_CRU;
992 // Instructions to manipulate FPSCR. Only long double handling uses these.
993 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
995 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
997 [(set F8RC:$rT, (PPCmffs))]>,
998 PPC970_DGroup_Single, PPC970_Unit_FPU;
999 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1000 "mtfsb0 $FM", IntMTFSB0,
1001 [(PPCmtfsb0 (i32 imm:$FM))]>,
1002 PPC970_DGroup_Single, PPC970_Unit_FPU;
1003 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1004 "mtfsb1 $FM", IntMTFSB0,
1005 [(PPCmtfsb1 (i32 imm:$FM))]>,
1006 PPC970_DGroup_Single, PPC970_Unit_FPU;
1007 def FADDrtz: AForm_2<63, 21,
1008 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1009 "fadd $FRT, $FRA, $FRB", FPGeneral,
1010 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1011 PPC970_DGroup_Single, PPC970_Unit_FPU;
1012 // MTFSF does not actually produce an FP result. We pretend it copies
1013 // input reg B to the output. If we didn't do this it would look like the
1014 // instruction had no outputs (because we aren't modelling the FPSCR) and
1015 // it would be deleted.
1016 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1017 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1018 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1019 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1020 F8RC:$rT, F8RC:$FRB))]>,
1021 PPC970_DGroup_Single, PPC970_Unit_FPU;
1023 let PPC970_Unit = 1 in { // FXU Operations.
1025 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1027 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1028 "add $rT, $rA, $rB", IntGeneral,
1029 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1030 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1031 "addc $rT, $rA, $rB", IntGeneral,
1032 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1033 PPC970_DGroup_Cracked;
1034 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1035 "adde $rT, $rA, $rB", IntGeneral,
1036 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1037 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1038 "divw $rT, $rA, $rB", IntDivW,
1039 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1040 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1041 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1042 "divwu $rT, $rA, $rB", IntDivW,
1043 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1044 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1045 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1046 "mulhw $rT, $rA, $rB", IntMulHW,
1047 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1048 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1049 "mulhwu $rT, $rA, $rB", IntMulHWU,
1050 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1051 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1052 "mullw $rT, $rA, $rB", IntMulHW,
1053 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1054 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1055 "subf $rT, $rA, $rB", IntGeneral,
1056 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1057 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1058 "subfc $rT, $rA, $rB", IntGeneral,
1059 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1060 PPC970_DGroup_Cracked;
1061 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1062 "subfe $rT, $rA, $rB", IntGeneral,
1063 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1064 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1065 "addme $rT, $rA", IntGeneral,
1066 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
1067 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1068 "addze $rT, $rA", IntGeneral,
1069 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1070 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1071 "neg $rT, $rA", IntGeneral,
1072 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1073 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1074 "subfme $rT, $rA", IntGeneral,
1075 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
1076 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1077 "subfze $rT, $rA", IntGeneral,
1078 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1081 // A-Form instructions. Most of the instructions executed in the FPU are of
1084 let PPC970_Unit = 3 in { // FPU Operations.
1085 def FMADD : AForm_1<63, 29,
1086 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1087 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1088 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1090 Requires<[FPContractions]>;
1091 def FMADDS : AForm_1<59, 29,
1092 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1093 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1094 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1096 Requires<[FPContractions]>;
1097 def FMSUB : AForm_1<63, 28,
1098 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1099 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1100 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1102 Requires<[FPContractions]>;
1103 def FMSUBS : AForm_1<59, 28,
1104 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1105 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1106 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1108 Requires<[FPContractions]>;
1109 def FNMADD : AForm_1<63, 31,
1110 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1111 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1112 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1114 Requires<[FPContractions]>;
1115 def FNMADDS : AForm_1<59, 31,
1116 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1117 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1118 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1120 Requires<[FPContractions]>;
1121 def FNMSUB : AForm_1<63, 30,
1122 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1123 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1124 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1126 Requires<[FPContractions]>;
1127 def FNMSUBS : AForm_1<59, 30,
1128 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1129 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1130 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1132 Requires<[FPContractions]>;
1133 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1134 // having 4 of these, force the comparison to always be an 8-byte double (code
1135 // should use an FMRSD if the input comparison value really wants to be a float)
1136 // and 4/8 byte forms for the result and operand type..
1137 def FSELD : AForm_1<63, 23,
1138 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1139 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1140 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1141 def FSELS : AForm_1<63, 23,
1142 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1143 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1144 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1145 def FADD : AForm_2<63, 21,
1146 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1147 "fadd $FRT, $FRA, $FRB", FPGeneral,
1148 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1149 def FADDS : AForm_2<59, 21,
1150 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1151 "fadds $FRT, $FRA, $FRB", FPGeneral,
1152 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1153 def FDIV : AForm_2<63, 18,
1154 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1155 "fdiv $FRT, $FRA, $FRB", FPDivD,
1156 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1157 def FDIVS : AForm_2<59, 18,
1158 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1159 "fdivs $FRT, $FRA, $FRB", FPDivS,
1160 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1161 def FMUL : AForm_3<63, 25,
1162 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1163 "fmul $FRT, $FRA, $FRB", FPFused,
1164 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1165 def FMULS : AForm_3<59, 25,
1166 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1167 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1168 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1169 def FSUB : AForm_2<63, 20,
1170 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1171 "fsub $FRT, $FRA, $FRB", FPGeneral,
1172 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1173 def FSUBS : AForm_2<59, 20,
1174 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1175 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1176 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1179 let PPC970_Unit = 1 in { // FXU Operations.
1180 // M-Form instructions. rotate and mask instructions.
1182 let isCommutable = 1 in {
1183 // RLWIMI can be commuted if the rotate amount is zero.
1184 def RLWIMI : MForm_2<20,
1185 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1186 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1187 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1190 def RLWINM : MForm_2<21,
1191 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1192 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1194 def RLWINMo : MForm_2<21,
1195 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1196 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1197 []>, isDOT, PPC970_DGroup_Cracked;
1198 def RLWNM : MForm_2<23,
1199 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1200 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1205 //===----------------------------------------------------------------------===//
1206 // DWARF Pseudo Instructions
1209 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
1210 "${:comment} .loc $file, $line, $col",
1211 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
1214 //===----------------------------------------------------------------------===//
1215 // PowerPC Instruction Patterns
1218 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1219 def : Pat<(i32 imm:$imm),
1220 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1222 // Implement the 'not' operation with the NOR instruction.
1223 def NOT : Pat<(not GPRC:$in),
1224 (NOR GPRC:$in, GPRC:$in)>;
1226 // ADD an arbitrary immediate.
1227 def : Pat<(add GPRC:$in, imm:$imm),
1228 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1229 // OR an arbitrary immediate.
1230 def : Pat<(or GPRC:$in, imm:$imm),
1231 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1232 // XOR an arbitrary immediate.
1233 def : Pat<(xor GPRC:$in, imm:$imm),
1234 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1236 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1237 (SUBFIC GPRC:$in, imm:$imm)>;
1240 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1241 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1242 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1243 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1246 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1247 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1248 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1249 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1252 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1253 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1256 def : Pat<(PPCcall_Macho (i32 tglobaladdr:$dst)),
1257 (BL_Macho tglobaladdr:$dst)>;
1258 def : Pat<(PPCcall_Macho (i32 texternalsym:$dst)),
1259 (BL_Macho texternalsym:$dst)>;
1260 def : Pat<(PPCcall_ELF (i32 tglobaladdr:$dst)),
1261 (BL_ELF tglobaladdr:$dst)>;
1262 def : Pat<(PPCcall_ELF (i32 texternalsym:$dst)),
1263 (BL_ELF texternalsym:$dst)>;
1266 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1267 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1269 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1270 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1272 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1273 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1277 // Hi and Lo for Darwin Global Addresses.
1278 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1279 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1280 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1281 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1282 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1283 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1284 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1285 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1286 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1287 (ADDIS GPRC:$in, tconstpool:$g)>;
1288 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1289 (ADDIS GPRC:$in, tjumptable:$g)>;
1291 // Fused negative multiply subtract, alternate pattern
1292 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1293 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1294 Requires<[FPContractions]>;
1295 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1296 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1297 Requires<[FPContractions]>;
1299 // Standard shifts. These are represented separately from the real shifts above
1300 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1302 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1303 (SRAW GPRC:$rS, GPRC:$rB)>;
1304 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1305 (SRW GPRC:$rS, GPRC:$rB)>;
1306 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1307 (SLW GPRC:$rS, GPRC:$rB)>;
1309 def : Pat<(zextloadi1 iaddr:$src),
1311 def : Pat<(zextloadi1 xaddr:$src),
1313 def : Pat<(extloadi1 iaddr:$src),
1315 def : Pat<(extloadi1 xaddr:$src),
1317 def : Pat<(extloadi8 iaddr:$src),
1319 def : Pat<(extloadi8 xaddr:$src),
1321 def : Pat<(extloadi16 iaddr:$src),
1323 def : Pat<(extloadi16 xaddr:$src),
1325 def : Pat<(extloadf32 iaddr:$src),
1326 (FMRSD (LFS iaddr:$src))>;
1327 def : Pat<(extloadf32 xaddr:$src),
1328 (FMRSD (LFSX xaddr:$src))>;
1330 // Atomic operations
1331 def : Pat<(PPCcmp_unres immSExt16:$imm, GPRC:$rA, imm:$label),
1332 (CMP_UNRESwi GPRC:$rA, immSExt16:$imm, imm:$label)>;
1334 include "PPCInstrAltivec.td"
1335 include "PPCInstr64Bit.td"