1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
61 //===----------------------------------------------------------------------===//
62 // PowerPC specific DAG Nodes.
65 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
66 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
68 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
69 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
70 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
71 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
72 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
73 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
74 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
75 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
76 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
77 [SDNPHasChain, SDNPMayStore]>;
78 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
79 [SDNPHasChain, SDNPMayLoad]>;
80 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
81 [SDNPHasChain, SDNPMayLoad]>;
83 // Extract FPSCR (not modeled at the DAG level).
84 def PPCmffs : SDNode<"PPCISD::MFFS",
85 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
87 // Perform FADD in round-to-zero mode.
88 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
91 def PPCfsel : SDNode<"PPCISD::FSEL",
92 // Type constraint for fsel.
93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
96 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
97 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
98 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
99 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
100 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
102 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
104 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
105 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
107 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
108 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
109 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
110 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
111 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
112 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
113 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
114 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
116 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
118 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
120 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
121 // amounts. These nodes are generated by the multi-precision shift code.
122 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
123 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
124 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
126 // These are target-independent nodes, but have target-specific formats.
127 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
128 [SDNPHasChain, SDNPOutGlue]>;
129 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
132 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
133 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
134 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
136 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
139 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
141 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
142 [SDNPHasChain, SDNPSideEffect,
143 SDNPInGlue, SDNPOutGlue]>;
144 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
145 [SDNPHasChain, SDNPSideEffect,
146 SDNPInGlue, SDNPOutGlue]>;
147 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
149 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
150 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
153 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
154 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
156 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
157 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
159 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
160 SDTypeProfile<1, 1, [SDTCisInt<0>,
162 [SDNPHasChain, SDNPSideEffect]>;
163 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
164 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
165 [SDNPHasChain, SDNPSideEffect]>;
167 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
168 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
169 [SDNPHasChain, SDNPSideEffect]>;
171 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
172 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
174 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
175 [SDNPHasChain, SDNPOptInGlue]>;
177 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
178 [SDNPHasChain, SDNPMayLoad]>;
179 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
180 [SDNPHasChain, SDNPMayStore]>;
182 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
183 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
186 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
188 // Instructions to support atomic operations
189 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
190 [SDNPHasChain, SDNPMayLoad]>;
191 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
192 [SDNPHasChain, SDNPMayStore]>;
194 // Instructions to support medium and large code model
195 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
196 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
197 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
200 // Instructions to support dynamic alloca.
201 def SDTDynOp : SDTypeProfile<1, 2, []>;
202 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
204 //===----------------------------------------------------------------------===//
205 // PowerPC specific transformation functions and pattern fragments.
208 def SHL32 : SDNodeXForm<imm, [{
209 // Transformation function: 31 - imm
210 return getI32Imm(31 - N->getZExtValue());
213 def SRL32 : SDNodeXForm<imm, [{
214 // Transformation function: 32 - imm
215 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
218 def LO16 : SDNodeXForm<imm, [{
219 // Transformation function: get the low 16 bits.
220 return getI32Imm((unsigned short)N->getZExtValue());
223 def HI16 : SDNodeXForm<imm, [{
224 // Transformation function: shift the immediate value down into the low bits.
225 return getI32Imm((unsigned)N->getZExtValue() >> 16);
228 def HA16 : SDNodeXForm<imm, [{
229 // Transformation function: shift the immediate value down into the low bits.
230 signed int Val = N->getZExtValue();
231 return getI32Imm((Val - (signed short)Val) >> 16);
233 def MB : SDNodeXForm<imm, [{
234 // Transformation function: get the start bit of a mask
236 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
237 return getI32Imm(mb);
240 def ME : SDNodeXForm<imm, [{
241 // Transformation function: get the end bit of a mask
243 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
244 return getI32Imm(me);
246 def maskimm32 : PatLeaf<(imm), [{
247 // maskImm predicate - True if immediate is a run of ones.
249 if (N->getValueType(0) == MVT::i32)
250 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
255 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
256 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
257 // sign extended field. Used by instructions like 'addi'.
258 return (int32_t)Imm == (short)Imm;
260 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
261 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
262 // sign extended field. Used by instructions like 'addi'.
263 return (int64_t)Imm == (short)Imm;
265 def immZExt16 : PatLeaf<(imm), [{
266 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
267 // field. Used by instructions like 'ori'.
268 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
271 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
272 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
273 // identical in 32-bit mode, but in 64-bit mode, they return true if the
274 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
276 def imm16ShiftedZExt : PatLeaf<(imm), [{
277 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
278 // immediate are set. Used by instructions like 'xoris'.
279 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
282 def imm16ShiftedSExt : PatLeaf<(imm), [{
283 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
284 // immediate are set. Used by instructions like 'addis'. Identical to
285 // imm16ShiftedZExt in 32-bit mode.
286 if (N->getZExtValue() & 0xFFFF) return false;
287 if (N->getValueType(0) == MVT::i32)
289 // For 64-bit, make sure it is sext right.
290 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
293 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
294 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
295 // zero extended field.
296 return isUInt<32>(Imm);
299 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
300 // restricted memrix (4-aligned) constants are alignment sensitive. If these
301 // offsets are hidden behind TOC entries than the values of the lower-order
302 // bits cannot be checked directly. As a result, we need to also incorporate
303 // an alignment check into the relevant patterns.
305 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
306 return cast<LoadSDNode>(N)->getAlignment() >= 4;
308 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
309 (store node:$val, node:$ptr), [{
310 return cast<StoreSDNode>(N)->getAlignment() >= 4;
312 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
313 return cast<LoadSDNode>(N)->getAlignment() >= 4;
315 def aligned4pre_store : PatFrag<
316 (ops node:$val, node:$base, node:$offset),
317 (pre_store node:$val, node:$base, node:$offset), [{
318 return cast<StoreSDNode>(N)->getAlignment() >= 4;
321 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
322 return cast<LoadSDNode>(N)->getAlignment() < 4;
324 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
325 (store node:$val, node:$ptr), [{
326 return cast<StoreSDNode>(N)->getAlignment() < 4;
328 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
329 return cast<LoadSDNode>(N)->getAlignment() < 4;
332 //===----------------------------------------------------------------------===//
333 // PowerPC Flag Definitions.
335 class isPPC64 { bit PPC64 = 1; }
336 class isDOT { bit RC = 1; }
338 class RegConstraint<string C> {
339 string Constraints = C;
341 class NoEncode<string E> {
342 string DisableEncoding = E;
346 //===----------------------------------------------------------------------===//
347 // PowerPC Operand Definitions.
349 // In the default PowerPC assembler syntax, registers are specified simply
350 // by number, so they cannot be distinguished from immediate values (without
351 // looking at the opcode). This means that the default operand matching logic
352 // for the asm parser does not work, and we need to specify custom matchers.
353 // Since those can only be specified with RegisterOperand classes and not
354 // directly on the RegisterClass, all instructions patterns used by the asm
355 // parser need to use a RegisterOperand (instead of a RegisterClass) for
356 // all their register operands.
357 // For this purpose, we define one RegisterOperand for each RegisterClass,
358 // using the same name as the class, just in lower case.
360 def PPCRegGPRCAsmOperand : AsmOperandClass {
361 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
363 def gprc : RegisterOperand<GPRC> {
364 let ParserMatchClass = PPCRegGPRCAsmOperand;
366 def PPCRegG8RCAsmOperand : AsmOperandClass {
367 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
369 def g8rc : RegisterOperand<G8RC> {
370 let ParserMatchClass = PPCRegG8RCAsmOperand;
372 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
373 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
375 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
376 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
378 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
379 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
381 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
382 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
384 def PPCRegF8RCAsmOperand : AsmOperandClass {
385 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
387 def f8rc : RegisterOperand<F8RC> {
388 let ParserMatchClass = PPCRegF8RCAsmOperand;
390 def PPCRegF4RCAsmOperand : AsmOperandClass {
391 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
393 def f4rc : RegisterOperand<F4RC> {
394 let ParserMatchClass = PPCRegF4RCAsmOperand;
396 def PPCRegVRRCAsmOperand : AsmOperandClass {
397 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
399 def vrrc : RegisterOperand<VRRC> {
400 let ParserMatchClass = PPCRegVRRCAsmOperand;
402 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
403 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
405 def crbitrc : RegisterOperand<CRBITRC> {
406 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
408 def PPCRegCRRCAsmOperand : AsmOperandClass {
409 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
411 def crrc : RegisterOperand<CRRC> {
412 let ParserMatchClass = PPCRegCRRCAsmOperand;
415 def PPCS5ImmAsmOperand : AsmOperandClass {
416 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
417 let RenderMethod = "addImmOperands";
419 def s5imm : Operand<i32> {
420 let PrintMethod = "printS5ImmOperand";
421 let ParserMatchClass = PPCS5ImmAsmOperand;
422 let DecoderMethod = "decodeSImmOperand<5>";
424 def PPCU5ImmAsmOperand : AsmOperandClass {
425 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
426 let RenderMethod = "addImmOperands";
428 def u5imm : Operand<i32> {
429 let PrintMethod = "printU5ImmOperand";
430 let ParserMatchClass = PPCU5ImmAsmOperand;
431 let DecoderMethod = "decodeUImmOperand<5>";
433 def PPCU6ImmAsmOperand : AsmOperandClass {
434 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
435 let RenderMethod = "addImmOperands";
437 def u6imm : Operand<i32> {
438 let PrintMethod = "printU6ImmOperand";
439 let ParserMatchClass = PPCU6ImmAsmOperand;
440 let DecoderMethod = "decodeUImmOperand<6>";
442 def PPCS16ImmAsmOperand : AsmOperandClass {
443 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
444 let RenderMethod = "addImmOperands";
446 def s16imm : Operand<i32> {
447 let PrintMethod = "printS16ImmOperand";
448 let EncoderMethod = "getImm16Encoding";
449 let ParserMatchClass = PPCS16ImmAsmOperand;
450 let DecoderMethod = "decodeSImmOperand<16>";
452 def PPCU16ImmAsmOperand : AsmOperandClass {
453 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
454 let RenderMethod = "addImmOperands";
456 def u16imm : Operand<i32> {
457 let PrintMethod = "printU16ImmOperand";
458 let EncoderMethod = "getImm16Encoding";
459 let ParserMatchClass = PPCU16ImmAsmOperand;
460 let DecoderMethod = "decodeUImmOperand<16>";
462 def PPCS17ImmAsmOperand : AsmOperandClass {
463 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
464 let RenderMethod = "addImmOperands";
466 def s17imm : Operand<i32> {
467 // This operand type is used for addis/lis to allow the assembler parser
468 // to accept immediates in the range -65536..65535 for compatibility with
469 // the GNU assembler. The operand is treated as 16-bit otherwise.
470 let PrintMethod = "printS16ImmOperand";
471 let EncoderMethod = "getImm16Encoding";
472 let ParserMatchClass = PPCS17ImmAsmOperand;
473 let DecoderMethod = "decodeSImmOperand<16>";
475 def PPCDirectBrAsmOperand : AsmOperandClass {
476 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
477 let RenderMethod = "addBranchTargetOperands";
479 def directbrtarget : Operand<OtherVT> {
480 let PrintMethod = "printBranchOperand";
481 let EncoderMethod = "getDirectBrEncoding";
482 let ParserMatchClass = PPCDirectBrAsmOperand;
484 def absdirectbrtarget : Operand<OtherVT> {
485 let PrintMethod = "printAbsBranchOperand";
486 let EncoderMethod = "getAbsDirectBrEncoding";
487 let ParserMatchClass = PPCDirectBrAsmOperand;
489 def PPCCondBrAsmOperand : AsmOperandClass {
490 let Name = "CondBr"; let PredicateMethod = "isCondBr";
491 let RenderMethod = "addBranchTargetOperands";
493 def condbrtarget : Operand<OtherVT> {
494 let PrintMethod = "printBranchOperand";
495 let EncoderMethod = "getCondBrEncoding";
496 let ParserMatchClass = PPCCondBrAsmOperand;
498 def abscondbrtarget : Operand<OtherVT> {
499 let PrintMethod = "printAbsBranchOperand";
500 let EncoderMethod = "getAbsCondBrEncoding";
501 let ParserMatchClass = PPCCondBrAsmOperand;
503 def calltarget : Operand<iPTR> {
504 let PrintMethod = "printBranchOperand";
505 let EncoderMethod = "getDirectBrEncoding";
506 let ParserMatchClass = PPCDirectBrAsmOperand;
508 def abscalltarget : Operand<iPTR> {
509 let PrintMethod = "printAbsBranchOperand";
510 let EncoderMethod = "getAbsDirectBrEncoding";
511 let ParserMatchClass = PPCDirectBrAsmOperand;
513 def PPCCRBitMaskOperand : AsmOperandClass {
514 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
516 def crbitm: Operand<i8> {
517 let PrintMethod = "printcrbitm";
518 let EncoderMethod = "get_crbitm_encoding";
519 let DecoderMethod = "decodeCRBitMOperand";
520 let ParserMatchClass = PPCCRBitMaskOperand;
523 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
524 def PPCRegGxRCNoR0Operand : AsmOperandClass {
525 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
527 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
528 let ParserMatchClass = PPCRegGxRCNoR0Operand;
530 // A version of ptr_rc usable with the asm parser.
531 def PPCRegGxRCOperand : AsmOperandClass {
532 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
534 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
535 let ParserMatchClass = PPCRegGxRCOperand;
538 def PPCDispRIOperand : AsmOperandClass {
539 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
540 let RenderMethod = "addImmOperands";
542 def dispRI : Operand<iPTR> {
543 let ParserMatchClass = PPCDispRIOperand;
545 def PPCDispRIXOperand : AsmOperandClass {
546 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
547 let RenderMethod = "addImmOperands";
549 def dispRIX : Operand<iPTR> {
550 let ParserMatchClass = PPCDispRIXOperand;
553 def memri : Operand<iPTR> {
554 let PrintMethod = "printMemRegImm";
555 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
556 let EncoderMethod = "getMemRIEncoding";
557 let DecoderMethod = "decodeMemRIOperands";
559 def memrr : Operand<iPTR> {
560 let PrintMethod = "printMemRegReg";
561 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
563 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
564 let PrintMethod = "printMemRegImm";
565 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
566 let EncoderMethod = "getMemRIXEncoding";
567 let DecoderMethod = "decodeMemRIXOperands";
570 // A single-register address. This is used with the SjLj
571 // pseudo-instructions.
572 def memr : Operand<iPTR> {
573 let MIOperandInfo = (ops ptr_rc:$ptrreg);
575 def PPCTLSRegOperand : AsmOperandClass {
576 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
577 let RenderMethod = "addTLSRegOperands";
579 def tlsreg32 : Operand<i32> {
580 let EncoderMethod = "getTLSRegEncoding";
581 let ParserMatchClass = PPCTLSRegOperand;
584 // PowerPC Predicate operand.
585 def pred : Operand<OtherVT> {
586 let PrintMethod = "printPredicateOperand";
587 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
590 // Define PowerPC specific addressing mode.
591 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
592 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
593 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
594 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
596 // The address in a single register. This is used with the SjLj
597 // pseudo-instructions.
598 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
600 /// This is just the offset part of iaddr, used for preinc.
601 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
603 //===----------------------------------------------------------------------===//
604 // PowerPC Instruction Predicate Definitions.
605 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
606 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
607 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
608 def IsNotBookE : Predicate<"!PPCSubTarget.isBookE()">;
610 //===----------------------------------------------------------------------===//
611 // PowerPC Multiclass Definitions.
613 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
614 string asmbase, string asmstr, InstrItinClass itin,
616 let BaseName = asmbase in {
617 def NAME : XForm_6<opcode, xo, OOL, IOL,
618 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
619 pattern>, RecFormRel;
621 def o : XForm_6<opcode, xo, OOL, IOL,
622 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
623 []>, isDOT, RecFormRel;
627 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
628 string asmbase, string asmstr, InstrItinClass itin,
630 let BaseName = asmbase in {
631 let Defs = [CARRY] in
632 def NAME : XForm_6<opcode, xo, OOL, IOL,
633 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
634 pattern>, RecFormRel;
635 let Defs = [CARRY, CR0] in
636 def o : XForm_6<opcode, xo, OOL, IOL,
637 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
638 []>, isDOT, RecFormRel;
642 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
643 string asmbase, string asmstr, InstrItinClass itin,
645 let BaseName = asmbase in {
646 let Defs = [CARRY] in
647 def NAME : XForm_10<opcode, xo, OOL, IOL,
648 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
649 pattern>, RecFormRel;
650 let Defs = [CARRY, CR0] in
651 def o : XForm_10<opcode, xo, OOL, IOL,
652 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
653 []>, isDOT, RecFormRel;
657 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
658 string asmbase, string asmstr, InstrItinClass itin,
660 let BaseName = asmbase in {
661 def NAME : XForm_11<opcode, xo, OOL, IOL,
662 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
663 pattern>, RecFormRel;
665 def o : XForm_11<opcode, xo, OOL, IOL,
666 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
667 []>, isDOT, RecFormRel;
671 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
672 string asmbase, string asmstr, InstrItinClass itin,
674 let BaseName = asmbase in {
675 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
676 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
677 pattern>, RecFormRel;
679 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
680 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
681 []>, isDOT, RecFormRel;
685 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
686 string asmbase, string asmstr, InstrItinClass itin,
688 let BaseName = asmbase in {
689 let Defs = [CARRY] in
690 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
691 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
692 pattern>, RecFormRel;
693 let Defs = [CARRY, CR0] in
694 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
695 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
696 []>, isDOT, RecFormRel;
700 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
701 string asmbase, string asmstr, InstrItinClass itin,
703 let BaseName = asmbase in {
704 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
705 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
706 pattern>, RecFormRel;
708 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
709 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
710 []>, isDOT, RecFormRel;
714 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
715 string asmbase, string asmstr, InstrItinClass itin,
717 let BaseName = asmbase in {
718 let Defs = [CARRY] in
719 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
720 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
721 pattern>, RecFormRel;
722 let Defs = [CARRY, CR0] in
723 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
724 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
725 []>, isDOT, RecFormRel;
729 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
730 string asmbase, string asmstr, InstrItinClass itin,
732 let BaseName = asmbase in {
733 def NAME : MForm_2<opcode, OOL, IOL,
734 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
735 pattern>, RecFormRel;
737 def o : MForm_2<opcode, OOL, IOL,
738 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
739 []>, isDOT, RecFormRel;
743 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
744 string asmbase, string asmstr, InstrItinClass itin,
746 let BaseName = asmbase in {
747 def NAME : MDForm_1<opcode, xo, OOL, IOL,
748 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
749 pattern>, RecFormRel;
751 def o : MDForm_1<opcode, xo, OOL, IOL,
752 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
753 []>, isDOT, RecFormRel;
757 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
758 string asmbase, string asmstr, InstrItinClass itin,
760 let BaseName = asmbase in {
761 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
762 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
763 pattern>, RecFormRel;
765 def o : MDSForm_1<opcode, xo, OOL, IOL,
766 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
767 []>, isDOT, RecFormRel;
771 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
772 string asmbase, string asmstr, InstrItinClass itin,
774 let BaseName = asmbase in {
775 let Defs = [CARRY] in
776 def NAME : XSForm_1<opcode, xo, OOL, IOL,
777 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
778 pattern>, RecFormRel;
779 let Defs = [CARRY, CR0] in
780 def o : XSForm_1<opcode, xo, OOL, IOL,
781 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
782 []>, isDOT, RecFormRel;
786 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
787 string asmbase, string asmstr, InstrItinClass itin,
789 let BaseName = asmbase in {
790 def NAME : XForm_26<opcode, xo, OOL, IOL,
791 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
792 pattern>, RecFormRel;
794 def o : XForm_26<opcode, xo, OOL, IOL,
795 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
796 []>, isDOT, RecFormRel;
800 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
801 string asmbase, string asmstr, InstrItinClass itin,
803 let BaseName = asmbase in {
804 def NAME : XForm_28<opcode, xo, OOL, IOL,
805 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
806 pattern>, RecFormRel;
808 def o : XForm_28<opcode, xo, OOL, IOL,
809 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
810 []>, isDOT, RecFormRel;
814 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
815 string asmbase, string asmstr, InstrItinClass itin,
817 let BaseName = asmbase in {
818 def NAME : AForm_1<opcode, xo, OOL, IOL,
819 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
820 pattern>, RecFormRel;
822 def o : AForm_1<opcode, xo, OOL, IOL,
823 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
824 []>, isDOT, RecFormRel;
828 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
829 string asmbase, string asmstr, InstrItinClass itin,
831 let BaseName = asmbase in {
832 def NAME : AForm_2<opcode, xo, OOL, IOL,
833 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
834 pattern>, RecFormRel;
836 def o : AForm_2<opcode, xo, OOL, IOL,
837 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
838 []>, isDOT, RecFormRel;
842 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
843 string asmbase, string asmstr, InstrItinClass itin,
845 let BaseName = asmbase in {
846 def NAME : AForm_3<opcode, xo, OOL, IOL,
847 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
848 pattern>, RecFormRel;
850 def o : AForm_3<opcode, xo, OOL, IOL,
851 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
852 []>, isDOT, RecFormRel;
856 //===----------------------------------------------------------------------===//
857 // PowerPC Instruction Definitions.
859 // Pseudo-instructions:
861 let hasCtrlDep = 1 in {
862 let Defs = [R1], Uses = [R1] in {
863 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
864 [(callseq_start timm:$amt)]>;
865 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
866 [(callseq_end timm:$amt1, timm:$amt2)]>;
869 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
870 "UPDATE_VRSAVE $rD, $rS", []>;
873 let Defs = [R1], Uses = [R1] in
874 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
876 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
878 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
879 // instruction selection into a branch sequence.
880 let usesCustomInserter = 1, // Expanded after instruction selection.
881 PPC970_Single = 1 in {
882 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
883 // because either operand might become the first operand in an isel, and
884 // that operand cannot be r0.
885 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
886 gprc_nor0:$T, gprc_nor0:$F,
887 i32imm:$BROPC), "#SELECT_CC_I4",
889 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
890 g8rc_nox0:$T, g8rc_nox0:$F,
891 i32imm:$BROPC), "#SELECT_CC_I8",
893 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
894 i32imm:$BROPC), "#SELECT_CC_F4",
896 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
897 i32imm:$BROPC), "#SELECT_CC_F8",
899 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
900 i32imm:$BROPC), "#SELECT_CC_VRRC",
903 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
904 // register bit directly.
905 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
906 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
907 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
908 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
909 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
910 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
911 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
912 f4rc:$T, f4rc:$F), "#SELECT_F4",
913 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
914 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
915 f8rc:$T, f8rc:$F), "#SELECT_F8",
916 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
917 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
918 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
920 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
923 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
924 // scavenge a register for it.
925 let mayStore = 1 in {
926 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
928 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
932 // RESTORE_CR - Indicate that we're restoring the CR register (previously
933 // spilled), so we'll need to scavenge a register for it.
935 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
937 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
938 "#RESTORE_CRBIT", []>;
941 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
942 let isReturn = 1, Uses = [LR, RM] in
943 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
945 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
946 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
949 let isCodeGenOnly = 1 in {
950 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
951 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
954 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
955 "bcctr 12, $bi, 0", IIC_BrB, []>;
956 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
957 "bcctr 4, $bi, 0", IIC_BrB, []>;
963 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
966 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
967 let isBarrier = 1 in {
968 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
971 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
972 "ba $dst", IIC_BrB, []>;
975 // BCC represents an arbitrary conditional branch on a predicate.
976 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
977 // a two-value operand where a dag node expects two operands. :(
978 let isCodeGenOnly = 1 in {
979 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
980 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
981 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
982 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
983 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
985 let isReturn = 1, Uses = [LR, RM] in
986 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
987 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
990 let isCodeGenOnly = 1 in {
991 let Pattern = [(brcond i1:$bi, bb:$dst)] in
992 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
995 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
996 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
999 let isReturn = 1, Uses = [LR, RM] in
1000 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1001 "bclr 12, $bi, 0", IIC_BrB, []>;
1002 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1003 "bclr 4, $bi, 0", IIC_BrB, []>;
1006 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1007 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1008 "bdzlr", IIC_BrB, []>;
1009 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1010 "bdnzlr", IIC_BrB, []>;
1011 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1012 "bdzlr+", IIC_BrB, []>;
1013 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1014 "bdnzlr+", IIC_BrB, []>;
1015 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1016 "bdzlr-", IIC_BrB, []>;
1017 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1018 "bdnzlr-", IIC_BrB, []>;
1021 let Defs = [CTR], Uses = [CTR] in {
1022 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1024 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1026 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1028 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1030 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1032 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1034 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1036 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1038 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1040 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1042 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1044 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1049 // The unconditional BCL used by the SjLj setjmp code.
1050 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1051 let Defs = [LR], Uses = [RM] in {
1052 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1053 "bcl 20, 31, $dst">;
1057 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1058 // Convenient aliases for call instructions
1059 let Uses = [RM] in {
1060 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1061 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1062 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1063 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1065 let isCodeGenOnly = 1 in {
1066 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1067 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1068 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1069 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1071 def BCL : BForm_4<16, 12, 0, 1, (outs),
1072 (ins crbitrc:$bi, condbrtarget:$dst),
1073 "bcl 12, $bi, $dst">;
1074 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1075 (ins crbitrc:$bi, condbrtarget:$dst),
1076 "bcl 4, $bi, $dst">;
1079 let Uses = [CTR, RM] in {
1080 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1081 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1082 Requires<[In32BitMode]>;
1084 let isCodeGenOnly = 1 in {
1085 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1086 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1089 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1090 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1091 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1092 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1095 let Uses = [LR, RM] in {
1096 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1097 "blrl", IIC_BrB, []>;
1099 let isCodeGenOnly = 1 in {
1100 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1101 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1104 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1105 "bclrl 12, $bi, 0", IIC_BrB, []>;
1106 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1107 "bclrl 4, $bi, 0", IIC_BrB, []>;
1110 let Defs = [CTR], Uses = [CTR, RM] in {
1111 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1113 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1115 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1117 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1119 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1121 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1123 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1125 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1127 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1129 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1131 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1133 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1136 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1137 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1138 "bdzlrl", IIC_BrB, []>;
1139 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1140 "bdnzlrl", IIC_BrB, []>;
1141 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1142 "bdzlrl+", IIC_BrB, []>;
1143 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1144 "bdnzlrl+", IIC_BrB, []>;
1145 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1146 "bdzlrl-", IIC_BrB, []>;
1147 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1148 "bdnzlrl-", IIC_BrB, []>;
1152 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1153 def TCRETURNdi :Pseudo< (outs),
1154 (ins calltarget:$dst, i32imm:$offset),
1155 "#TC_RETURNd $dst $offset",
1159 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1160 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1161 "#TC_RETURNa $func $offset",
1162 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1164 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1165 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1166 "#TC_RETURNr $dst $offset",
1170 let isCodeGenOnly = 1 in {
1172 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1173 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1174 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1175 []>, Requires<[In32BitMode]>;
1177 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1178 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1179 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1183 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1184 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1185 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1191 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1193 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1194 "#EH_SJLJ_SETJMP32",
1195 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1196 Requires<[In32BitMode]>;
1197 let isTerminator = 1 in
1198 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1199 "#EH_SJLJ_LONGJMP32",
1200 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1201 Requires<[In32BitMode]>;
1204 let isBranch = 1, isTerminator = 1 in {
1205 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1206 "#EH_SjLj_Setup\t$dst", []>;
1210 let PPC970_Unit = 7 in {
1211 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1212 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1215 // DCB* instructions.
1216 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1217 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1218 PPC970_DGroup_Single;
1219 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1220 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1221 PPC970_DGroup_Single;
1222 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1223 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1224 PPC970_DGroup_Single;
1225 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1226 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1227 PPC970_DGroup_Single;
1228 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1229 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1230 PPC970_DGroup_Single;
1231 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1232 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1233 PPC970_DGroup_Single;
1234 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1235 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1236 PPC970_DGroup_Single;
1237 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1238 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1239 PPC970_DGroup_Single;
1241 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1242 (DCBT xoaddr:$dst)>;
1244 // Atomic operations
1245 let usesCustomInserter = 1 in {
1246 let Defs = [CR0] in {
1247 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1248 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1249 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1250 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1251 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1252 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1253 def ATOMIC_LOAD_AND_I8 : Pseudo<
1254 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1255 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1256 def ATOMIC_LOAD_OR_I8 : Pseudo<
1257 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1258 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1259 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1260 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1261 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1262 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1263 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1264 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1265 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1266 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1267 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1268 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1269 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1270 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1271 def ATOMIC_LOAD_AND_I16 : Pseudo<
1272 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1273 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1274 def ATOMIC_LOAD_OR_I16 : Pseudo<
1275 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1276 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1277 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1278 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1279 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1280 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1281 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1282 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1283 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1284 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1285 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1286 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1287 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1288 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1289 def ATOMIC_LOAD_AND_I32 : Pseudo<
1290 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1291 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1292 def ATOMIC_LOAD_OR_I32 : Pseudo<
1293 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1294 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1295 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1296 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1297 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1298 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1299 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1300 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1302 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1303 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1304 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1305 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1306 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1307 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1308 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1309 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1310 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1312 def ATOMIC_SWAP_I8 : Pseudo<
1313 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1314 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1315 def ATOMIC_SWAP_I16 : Pseudo<
1316 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1317 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1318 def ATOMIC_SWAP_I32 : Pseudo<
1319 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1320 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1324 // Instructions to support atomic operations
1325 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1326 "lwarx $rD, $src", IIC_LdStLWARX,
1327 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1330 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1331 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1332 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1335 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1336 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1338 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1339 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1340 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1341 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1342 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1343 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1344 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1345 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1347 //===----------------------------------------------------------------------===//
1348 // PPC32 Load Instructions.
1351 // Unindexed (r+i) Loads.
1352 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1353 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1354 "lbz $rD, $src", IIC_LdStLoad,
1355 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1356 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1357 "lha $rD, $src", IIC_LdStLHA,
1358 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1359 PPC970_DGroup_Cracked;
1360 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1361 "lhz $rD, $src", IIC_LdStLoad,
1362 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1363 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1364 "lwz $rD, $src", IIC_LdStLoad,
1365 [(set i32:$rD, (load iaddr:$src))]>;
1367 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1368 "lfs $rD, $src", IIC_LdStLFD,
1369 [(set f32:$rD, (load iaddr:$src))]>;
1370 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1371 "lfd $rD, $src", IIC_LdStLFD,
1372 [(set f64:$rD, (load iaddr:$src))]>;
1375 // Unindexed (r+i) Loads with Update (preinc).
1376 let mayLoad = 1, neverHasSideEffects = 1 in {
1377 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1378 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1379 []>, RegConstraint<"$addr.reg = $ea_result">,
1380 NoEncode<"$ea_result">;
1382 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1383 "lhau $rD, $addr", IIC_LdStLHAU,
1384 []>, RegConstraint<"$addr.reg = $ea_result">,
1385 NoEncode<"$ea_result">;
1387 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1388 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1389 []>, RegConstraint<"$addr.reg = $ea_result">,
1390 NoEncode<"$ea_result">;
1392 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1393 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1394 []>, RegConstraint<"$addr.reg = $ea_result">,
1395 NoEncode<"$ea_result">;
1397 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1398 "lfsu $rD, $addr", IIC_LdStLFDU,
1399 []>, RegConstraint<"$addr.reg = $ea_result">,
1400 NoEncode<"$ea_result">;
1402 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1403 "lfdu $rD, $addr", IIC_LdStLFDU,
1404 []>, RegConstraint<"$addr.reg = $ea_result">,
1405 NoEncode<"$ea_result">;
1408 // Indexed (r+r) Loads with Update (preinc).
1409 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1411 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1412 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1413 NoEncode<"$ea_result">;
1415 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1417 "lhaux $rD, $addr", IIC_LdStLHAUX,
1418 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1419 NoEncode<"$ea_result">;
1421 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1423 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1424 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1425 NoEncode<"$ea_result">;
1427 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1429 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1430 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1431 NoEncode<"$ea_result">;
1433 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1435 "lfsux $rD, $addr", IIC_LdStLFDUX,
1436 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1437 NoEncode<"$ea_result">;
1439 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1441 "lfdux $rD, $addr", IIC_LdStLFDUX,
1442 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1443 NoEncode<"$ea_result">;
1447 // Indexed (r+r) Loads.
1449 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1450 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1451 "lbzx $rD, $src", IIC_LdStLoad,
1452 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1453 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1454 "lhax $rD, $src", IIC_LdStLHA,
1455 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1456 PPC970_DGroup_Cracked;
1457 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1458 "lhzx $rD, $src", IIC_LdStLoad,
1459 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1460 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1461 "lwzx $rD, $src", IIC_LdStLoad,
1462 [(set i32:$rD, (load xaddr:$src))]>;
1465 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1466 "lhbrx $rD, $src", IIC_LdStLoad,
1467 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1468 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1469 "lwbrx $rD, $src", IIC_LdStLoad,
1470 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1472 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1473 "lfsx $frD, $src", IIC_LdStLFD,
1474 [(set f32:$frD, (load xaddr:$src))]>;
1475 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1476 "lfdx $frD, $src", IIC_LdStLFD,
1477 [(set f64:$frD, (load xaddr:$src))]>;
1479 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1480 "lfiwax $frD, $src", IIC_LdStLFD,
1481 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1482 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1483 "lfiwzx $frD, $src", IIC_LdStLFD,
1484 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1488 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1489 "lmw $rD, $src", IIC_LdStLMW, []>;
1491 //===----------------------------------------------------------------------===//
1492 // PPC32 Store Instructions.
1495 // Unindexed (r+i) Stores.
1496 let PPC970_Unit = 2 in {
1497 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1498 "stb $rS, $src", IIC_LdStStore,
1499 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1500 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1501 "sth $rS, $src", IIC_LdStStore,
1502 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1503 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1504 "stw $rS, $src", IIC_LdStStore,
1505 [(store i32:$rS, iaddr:$src)]>;
1506 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1507 "stfs $rS, $dst", IIC_LdStSTFD,
1508 [(store f32:$rS, iaddr:$dst)]>;
1509 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1510 "stfd $rS, $dst", IIC_LdStSTFD,
1511 [(store f64:$rS, iaddr:$dst)]>;
1514 // Unindexed (r+i) Stores with Update (preinc).
1515 let PPC970_Unit = 2, mayStore = 1 in {
1516 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1517 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1518 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1519 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1520 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1521 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1522 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1523 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1524 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1525 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1526 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1527 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1528 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1529 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1530 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1533 // Patterns to match the pre-inc stores. We can't put the patterns on
1534 // the instruction definitions directly as ISel wants the address base
1535 // and offset to be separate operands, not a single complex operand.
1536 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1537 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1538 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1539 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1540 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1541 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1542 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1543 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1544 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1545 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1547 // Indexed (r+r) Stores.
1548 let PPC970_Unit = 2 in {
1549 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1550 "stbx $rS, $dst", IIC_LdStStore,
1551 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1552 PPC970_DGroup_Cracked;
1553 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1554 "sthx $rS, $dst", IIC_LdStStore,
1555 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1556 PPC970_DGroup_Cracked;
1557 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1558 "stwx $rS, $dst", IIC_LdStStore,
1559 [(store i32:$rS, xaddr:$dst)]>,
1560 PPC970_DGroup_Cracked;
1562 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1563 "sthbrx $rS, $dst", IIC_LdStStore,
1564 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1565 PPC970_DGroup_Cracked;
1566 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1567 "stwbrx $rS, $dst", IIC_LdStStore,
1568 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1569 PPC970_DGroup_Cracked;
1571 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1572 "stfiwx $frS, $dst", IIC_LdStSTFD,
1573 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1575 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1576 "stfsx $frS, $dst", IIC_LdStSTFD,
1577 [(store f32:$frS, xaddr:$dst)]>;
1578 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1579 "stfdx $frS, $dst", IIC_LdStSTFD,
1580 [(store f64:$frS, xaddr:$dst)]>;
1583 // Indexed (r+r) Stores with Update (preinc).
1584 let PPC970_Unit = 2, mayStore = 1 in {
1585 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1586 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1587 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1588 PPC970_DGroup_Cracked;
1589 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1590 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1591 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1592 PPC970_DGroup_Cracked;
1593 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1594 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1595 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1596 PPC970_DGroup_Cracked;
1597 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1598 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1599 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1600 PPC970_DGroup_Cracked;
1601 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1602 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1603 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1604 PPC970_DGroup_Cracked;
1607 // Patterns to match the pre-inc stores. We can't put the patterns on
1608 // the instruction definitions directly as ISel wants the address base
1609 // and offset to be separate operands, not a single complex operand.
1610 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1611 (STBUX $rS, $ptrreg, $ptroff)>;
1612 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1613 (STHUX $rS, $ptrreg, $ptroff)>;
1614 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1615 (STWUX $rS, $ptrreg, $ptroff)>;
1616 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1617 (STFSUX $rS, $ptrreg, $ptroff)>;
1618 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1619 (STFDUX $rS, $ptrreg, $ptroff)>;
1622 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1623 "stmw $rS, $dst", IIC_LdStLMW, []>;
1625 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1626 "sync $L", IIC_LdStSync, []>, Requires<[IsNotBookE]>;
1628 let isCodeGenOnly = 1 in {
1629 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1630 "msync", IIC_LdStSync, []>, Requires<[IsBookE]> {
1635 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[IsNotBookE]>;
1636 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[IsBookE]>;
1638 //===----------------------------------------------------------------------===//
1639 // PPC32 Arithmetic Instructions.
1642 let PPC970_Unit = 1 in { // FXU Operations.
1643 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1644 "addi $rD, $rA, $imm", IIC_IntSimple,
1645 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1646 let BaseName = "addic" in {
1647 let Defs = [CARRY] in
1648 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1649 "addic $rD, $rA, $imm", IIC_IntGeneral,
1650 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1651 RecFormRel, PPC970_DGroup_Cracked;
1652 let Defs = [CARRY, CR0] in
1653 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1654 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1655 []>, isDOT, RecFormRel;
1657 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1658 "addis $rD, $rA, $imm", IIC_IntSimple,
1659 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1660 let isCodeGenOnly = 1 in
1661 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1662 "la $rD, $sym($rA)", IIC_IntGeneral,
1663 [(set i32:$rD, (add i32:$rA,
1664 (PPClo tglobaladdr:$sym, 0)))]>;
1665 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1666 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1667 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1668 let Defs = [CARRY] in
1669 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1670 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1671 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1673 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1674 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1675 "li $rD, $imm", IIC_IntSimple,
1676 [(set i32:$rD, imm32SExt16:$imm)]>;
1677 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1678 "lis $rD, $imm", IIC_IntSimple,
1679 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1683 let PPC970_Unit = 1 in { // FXU Operations.
1684 let Defs = [CR0] in {
1685 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1686 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1687 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1689 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1690 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1691 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1694 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1695 "ori $dst, $src1, $src2", IIC_IntSimple,
1696 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1697 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1698 "oris $dst, $src1, $src2", IIC_IntSimple,
1699 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1700 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1701 "xori $dst, $src1, $src2", IIC_IntSimple,
1702 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1703 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1704 "xoris $dst, $src1, $src2", IIC_IntSimple,
1705 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1707 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1709 let isCodeGenOnly = 1 in {
1710 // The POWER6 and POWER7 have special group-terminating nops.
1711 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1712 "ori 1, 1, 0", IIC_IntSimple, []>;
1713 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1714 "ori 2, 2, 0", IIC_IntSimple, []>;
1717 let isCompare = 1, neverHasSideEffects = 1 in {
1718 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1719 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1720 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1721 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1725 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1726 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1727 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1728 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1729 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1730 "and", "$rA, $rS, $rB", IIC_IntSimple,
1731 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1732 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1733 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1734 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1735 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1736 "or", "$rA, $rS, $rB", IIC_IntSimple,
1737 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1738 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1739 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1740 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1741 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1742 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1743 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1744 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1745 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1746 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1747 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1748 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1749 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1750 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1751 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1752 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1753 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1754 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1755 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1756 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1757 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1758 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1761 let PPC970_Unit = 1 in { // FXU Operations.
1762 let neverHasSideEffects = 1 in {
1763 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1764 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1765 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1766 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1767 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1768 [(set i32:$rA, (ctlz i32:$rS))]>;
1769 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1770 "extsb", "$rA, $rS", IIC_IntSimple,
1771 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1772 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1773 "extsh", "$rA, $rS", IIC_IntSimple,
1774 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1776 let isCompare = 1, neverHasSideEffects = 1 in {
1777 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1778 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1779 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1780 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1783 let PPC970_Unit = 3 in { // FPU Operations.
1784 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1785 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1786 let isCompare = 1, neverHasSideEffects = 1 in {
1787 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1788 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1789 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1790 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1791 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1794 let Uses = [RM] in {
1795 let neverHasSideEffects = 1 in {
1796 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1797 "fctiw", "$frD, $frB", IIC_FPGeneral,
1799 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1800 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1801 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1803 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1804 "frsp", "$frD, $frB", IIC_FPGeneral,
1805 [(set f32:$frD, (fround f64:$frB))]>;
1807 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1808 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1809 "frin", "$frD, $frB", IIC_FPGeneral,
1810 [(set f64:$frD, (frnd f64:$frB))]>;
1811 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1812 "frin", "$frD, $frB", IIC_FPGeneral,
1813 [(set f32:$frD, (frnd f32:$frB))]>;
1816 let neverHasSideEffects = 1 in {
1817 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1818 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1819 "frip", "$frD, $frB", IIC_FPGeneral,
1820 [(set f64:$frD, (fceil f64:$frB))]>;
1821 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1822 "frip", "$frD, $frB", IIC_FPGeneral,
1823 [(set f32:$frD, (fceil f32:$frB))]>;
1824 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1825 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1826 "friz", "$frD, $frB", IIC_FPGeneral,
1827 [(set f64:$frD, (ftrunc f64:$frB))]>;
1828 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1829 "friz", "$frD, $frB", IIC_FPGeneral,
1830 [(set f32:$frD, (ftrunc f32:$frB))]>;
1831 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1832 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1833 "frim", "$frD, $frB", IIC_FPGeneral,
1834 [(set f64:$frD, (ffloor f64:$frB))]>;
1835 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1836 "frim", "$frD, $frB", IIC_FPGeneral,
1837 [(set f32:$frD, (ffloor f32:$frB))]>;
1839 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1840 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1841 [(set f64:$frD, (fsqrt f64:$frB))]>;
1842 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1843 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1844 [(set f32:$frD, (fsqrt f32:$frB))]>;
1849 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1850 /// often coalesced away and we don't want the dispatch group builder to think
1851 /// that they will fill slots (which could cause the load of a LSU reject to
1852 /// sneak into a d-group with a store).
1853 let neverHasSideEffects = 1 in
1854 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1855 "fmr", "$frD, $frB", IIC_FPGeneral,
1856 []>, // (set f32:$frD, f32:$frB)
1859 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1860 // These are artificially split into two different forms, for 4/8 byte FP.
1861 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1862 "fabs", "$frD, $frB", IIC_FPGeneral,
1863 [(set f32:$frD, (fabs f32:$frB))]>;
1864 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1865 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1866 "fabs", "$frD, $frB", IIC_FPGeneral,
1867 [(set f64:$frD, (fabs f64:$frB))]>;
1868 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1869 "fnabs", "$frD, $frB", IIC_FPGeneral,
1870 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1871 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1872 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1873 "fnabs", "$frD, $frB", IIC_FPGeneral,
1874 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1875 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1876 "fneg", "$frD, $frB", IIC_FPGeneral,
1877 [(set f32:$frD, (fneg f32:$frB))]>;
1878 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1879 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1880 "fneg", "$frD, $frB", IIC_FPGeneral,
1881 [(set f64:$frD, (fneg f64:$frB))]>;
1883 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1884 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1885 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1886 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1887 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1888 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1889 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1891 // Reciprocal estimates.
1892 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1893 "fre", "$frD, $frB", IIC_FPGeneral,
1894 [(set f64:$frD, (PPCfre f64:$frB))]>;
1895 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1896 "fres", "$frD, $frB", IIC_FPGeneral,
1897 [(set f32:$frD, (PPCfre f32:$frB))]>;
1898 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1899 "frsqrte", "$frD, $frB", IIC_FPGeneral,
1900 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1901 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1902 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
1903 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1906 // XL-Form instructions. condition register logical ops.
1908 let neverHasSideEffects = 1 in
1909 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1910 "mcrf $BF, $BFA", IIC_BrMCR>,
1911 PPC970_DGroup_First, PPC970_Unit_CRU;
1913 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
1914 (ins crbitrc:$CRA, crbitrc:$CRB),
1915 "crand $CRD, $CRA, $CRB", IIC_BrCR,
1916 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
1918 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
1919 (ins crbitrc:$CRA, crbitrc:$CRB),
1920 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
1921 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
1923 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
1924 (ins crbitrc:$CRA, crbitrc:$CRB),
1925 "cror $CRD, $CRA, $CRB", IIC_BrCR,
1926 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
1928 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
1929 (ins crbitrc:$CRA, crbitrc:$CRB),
1930 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
1931 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
1933 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
1934 (ins crbitrc:$CRA, crbitrc:$CRB),
1935 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
1936 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
1938 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
1939 (ins crbitrc:$CRA, crbitrc:$CRB),
1940 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
1941 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
1943 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
1944 (ins crbitrc:$CRA, crbitrc:$CRB),
1945 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
1946 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
1948 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
1949 (ins crbitrc:$CRA, crbitrc:$CRB),
1950 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
1951 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
1953 let isCodeGenOnly = 1 in {
1954 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
1955 "creqv $dst, $dst, $dst", IIC_BrCR,
1956 [(set i1:$dst, 1)]>;
1958 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
1959 "crxor $dst, $dst, $dst", IIC_BrCR,
1960 [(set i1:$dst, 0)]>;
1962 let Defs = [CR1EQ], CRD = 6 in {
1963 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1964 "creqv 6, 6, 6", IIC_BrCR,
1967 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1968 "crxor 6, 6, 6", IIC_BrCR,
1973 // XFX-Form instructions. Instructions that deal with SPRs.
1976 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
1977 "mfspr $RT, $SPR", IIC_SprMFSPR>;
1978 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
1979 "mtspr $SPR, $RT", IIC_SprMTSPR>;
1981 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
1982 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
1984 let Uses = [CTR] in {
1985 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
1986 "mfctr $rT", IIC_SprMFSPR>,
1987 PPC970_DGroup_First, PPC970_Unit_FXU;
1989 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1990 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1991 "mtctr $rS", IIC_SprMTSPR>,
1992 PPC970_DGroup_First, PPC970_Unit_FXU;
1994 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
1995 let Pattern = [(int_ppc_mtctr i32:$rS)] in
1996 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1997 "mtctr $rS", IIC_SprMTSPR>,
1998 PPC970_DGroup_First, PPC970_Unit_FXU;
2001 let Defs = [LR] in {
2002 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2003 "mtlr $rS", IIC_SprMTSPR>,
2004 PPC970_DGroup_First, PPC970_Unit_FXU;
2006 let Uses = [LR] in {
2007 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2008 "mflr $rT", IIC_SprMFSPR>,
2009 PPC970_DGroup_First, PPC970_Unit_FXU;
2012 let isCodeGenOnly = 1 in {
2013 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2014 // like a GPR on the PPC970. As such, copies in and out have the same
2015 // performance characteristics as an OR instruction.
2016 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2017 "mtspr 256, $rS", IIC_IntGeneral>,
2018 PPC970_DGroup_Single, PPC970_Unit_FXU;
2019 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2020 "mfspr $rT, 256", IIC_IntGeneral>,
2021 PPC970_DGroup_First, PPC970_Unit_FXU;
2023 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2024 (outs VRSAVERC:$reg), (ins gprc:$rS),
2025 "mtspr 256, $rS", IIC_IntGeneral>,
2026 PPC970_DGroup_Single, PPC970_Unit_FXU;
2027 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2028 (ins VRSAVERC:$reg),
2029 "mfspr $rT, 256", IIC_IntGeneral>,
2030 PPC970_DGroup_First, PPC970_Unit_FXU;
2033 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2034 // so we'll need to scavenge a register for it.
2036 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2037 "#SPILL_VRSAVE", []>;
2039 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2040 // spilled), so we'll need to scavenge a register for it.
2042 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2043 "#RESTORE_VRSAVE", []>;
2045 let neverHasSideEffects = 1 in {
2046 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2047 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2048 PPC970_DGroup_First, PPC970_Unit_CRU;
2050 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2051 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2052 PPC970_MicroCode, PPC970_Unit_CRU;
2054 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2055 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2056 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2057 PPC970_DGroup_First, PPC970_Unit_CRU;
2059 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2060 "mfcr $rT", IIC_SprMFCR>,
2061 PPC970_MicroCode, PPC970_Unit_CRU;
2062 } // neverHasSideEffects = 1
2064 // Pseudo instruction to perform FADD in round-to-zero mode.
2065 let usesCustomInserter = 1, Uses = [RM] in {
2066 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2067 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2070 // The above pseudo gets expanded to make use of the following instructions
2071 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2072 let Uses = [RM], Defs = [RM] in {
2073 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2074 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2075 PPC970_DGroup_Single, PPC970_Unit_FPU;
2076 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2077 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2078 PPC970_DGroup_Single, PPC970_Unit_FPU;
2079 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2080 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2081 PPC970_DGroup_Single, PPC970_Unit_FPU;
2083 let Uses = [RM] in {
2084 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2085 "mffs $rT", IIC_IntMFFS,
2086 [(set f64:$rT, (PPCmffs))]>,
2087 PPC970_DGroup_Single, PPC970_Unit_FPU;
2091 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
2092 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2094 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2095 "add", "$rT, $rA, $rB", IIC_IntSimple,
2096 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2097 let isCodeGenOnly = 1 in
2098 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2099 "add $rT, $rA, $rB", IIC_IntSimple,
2100 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2101 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2102 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2103 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2104 PPC970_DGroup_Cracked;
2105 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2106 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2107 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2108 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2109 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2110 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2111 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2112 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2113 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2114 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2115 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2116 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2117 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2118 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2119 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2120 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2121 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2122 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2123 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2124 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2125 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2126 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2127 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2128 PPC970_DGroup_Cracked;
2129 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2130 "neg", "$rT, $rA", IIC_IntSimple,
2131 [(set i32:$rT, (ineg i32:$rA))]>;
2132 let Uses = [CARRY] in {
2133 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2134 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2135 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2136 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2137 "addme", "$rT, $rA", IIC_IntGeneral,
2138 [(set i32:$rT, (adde i32:$rA, -1))]>;
2139 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2140 "addze", "$rT, $rA", IIC_IntGeneral,
2141 [(set i32:$rT, (adde i32:$rA, 0))]>;
2142 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2143 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2144 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2145 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2146 "subfme", "$rT, $rA", IIC_IntGeneral,
2147 [(set i32:$rT, (sube -1, i32:$rA))]>;
2148 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2149 "subfze", "$rT, $rA", IIC_IntGeneral,
2150 [(set i32:$rT, (sube 0, i32:$rA))]>;
2154 // A-Form instructions. Most of the instructions executed in the FPU are of
2157 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
2158 let Uses = [RM] in {
2159 defm FMADD : AForm_1r<63, 29,
2160 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2161 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2162 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2163 defm FMADDS : AForm_1r<59, 29,
2164 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2165 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2166 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2167 defm FMSUB : AForm_1r<63, 28,
2168 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2169 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2171 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2172 defm FMSUBS : AForm_1r<59, 28,
2173 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2174 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2176 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2177 defm FNMADD : AForm_1r<63, 31,
2178 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2179 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2181 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2182 defm FNMADDS : AForm_1r<59, 31,
2183 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2184 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2186 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2187 defm FNMSUB : AForm_1r<63, 30,
2188 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2189 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2190 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2191 (fneg f64:$FRB))))]>;
2192 defm FNMSUBS : AForm_1r<59, 30,
2193 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2194 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2195 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2196 (fneg f32:$FRB))))]>;
2198 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2199 // having 4 of these, force the comparison to always be an 8-byte double (code
2200 // should use an FMRSD if the input comparison value really wants to be a float)
2201 // and 4/8 byte forms for the result and operand type..
2202 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2203 defm FSELD : AForm_1r<63, 23,
2204 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2205 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2206 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2207 defm FSELS : AForm_1r<63, 23,
2208 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2209 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2210 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2211 let Uses = [RM] in {
2212 defm FADD : AForm_2r<63, 21,
2213 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2214 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2215 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2216 defm FADDS : AForm_2r<59, 21,
2217 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2218 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2219 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2220 defm FDIV : AForm_2r<63, 18,
2221 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2222 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2223 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2224 defm FDIVS : AForm_2r<59, 18,
2225 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2226 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2227 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2228 defm FMUL : AForm_3r<63, 25,
2229 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2230 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2231 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2232 defm FMULS : AForm_3r<59, 25,
2233 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2234 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2235 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2236 defm FSUB : AForm_2r<63, 20,
2237 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2238 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2239 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2240 defm FSUBS : AForm_2r<59, 20,
2241 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2242 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2243 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2247 let neverHasSideEffects = 1 in {
2248 let PPC970_Unit = 1 in { // FXU Operations.
2250 def ISEL : AForm_4<31, 15,
2251 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2252 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
2256 let PPC970_Unit = 1 in { // FXU Operations.
2257 // M-Form instructions. rotate and mask instructions.
2259 let isCommutable = 1 in {
2260 // RLWIMI can be commuted if the rotate amount is zero.
2261 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2262 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2263 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2264 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2265 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2267 let BaseName = "rlwinm" in {
2268 def RLWINM : MForm_2<21,
2269 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2270 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2273 def RLWINMo : MForm_2<21,
2274 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2275 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2276 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2278 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2279 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2280 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2283 } // neverHasSideEffects = 1
2285 //===----------------------------------------------------------------------===//
2286 // PowerPC Instruction Patterns
2289 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2290 def : Pat<(i32 imm:$imm),
2291 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2293 // Implement the 'not' operation with the NOR instruction.
2294 def i32not : OutPatFrag<(ops node:$in),
2296 def : Pat<(not i32:$in),
2299 // ADD an arbitrary immediate.
2300 def : Pat<(add i32:$in, imm:$imm),
2301 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2302 // OR an arbitrary immediate.
2303 def : Pat<(or i32:$in, imm:$imm),
2304 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2305 // XOR an arbitrary immediate.
2306 def : Pat<(xor i32:$in, imm:$imm),
2307 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2309 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2310 (SUBFIC $in, imm:$imm)>;
2313 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2314 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2315 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2316 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2319 def : Pat<(rotl i32:$in, i32:$sh),
2320 (RLWNM $in, $sh, 0, 31)>;
2321 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2322 (RLWINM $in, imm:$imm, 0, 31)>;
2325 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2326 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2329 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2330 (BL tglobaladdr:$dst)>;
2331 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2332 (BL texternalsym:$dst)>;
2335 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2336 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2338 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2339 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2341 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2342 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2346 // Hi and Lo for Darwin Global Addresses.
2347 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2348 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2349 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2350 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2351 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2352 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2353 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2354 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2355 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2356 (ADDIS $in, tglobaltlsaddr:$g)>;
2357 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2358 (ADDI $in, tglobaltlsaddr:$g)>;
2359 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2360 (ADDIS $in, tglobaladdr:$g)>;
2361 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2362 (ADDIS $in, tconstpool:$g)>;
2363 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2364 (ADDIS $in, tjumptable:$g)>;
2365 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2366 (ADDIS $in, tblockaddress:$g)>;
2368 // Support for thread-local storage.
2369 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2370 [(set i32:$rD, (PPCppc32GOT))]>;
2372 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2375 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2376 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2377 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2379 // Standard shifts. These are represented separately from the real shifts above
2380 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2382 def : Pat<(sra i32:$rS, i32:$rB),
2384 def : Pat<(srl i32:$rS, i32:$rB),
2386 def : Pat<(shl i32:$rS, i32:$rB),
2389 def : Pat<(zextloadi1 iaddr:$src),
2391 def : Pat<(zextloadi1 xaddr:$src),
2393 def : Pat<(extloadi1 iaddr:$src),
2395 def : Pat<(extloadi1 xaddr:$src),
2397 def : Pat<(extloadi8 iaddr:$src),
2399 def : Pat<(extloadi8 xaddr:$src),
2401 def : Pat<(extloadi16 iaddr:$src),
2403 def : Pat<(extloadi16 xaddr:$src),
2405 def : Pat<(f64 (extloadf32 iaddr:$src)),
2406 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2407 def : Pat<(f64 (extloadf32 xaddr:$src)),
2408 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2410 def : Pat<(f64 (fextend f32:$src)),
2411 (COPY_TO_REGCLASS $src, F8RC)>;
2413 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[IsNotBookE]>;
2414 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[IsBookE]>;
2416 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2417 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2418 (FNMSUB $A, $C, $B)>;
2419 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2420 (FNMSUB $A, $C, $B)>;
2421 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2422 (FNMSUBS $A, $C, $B)>;
2423 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2424 (FNMSUBS $A, $C, $B)>;
2426 // FCOPYSIGN's operand types need not agree.
2427 def : Pat<(fcopysign f64:$frB, f32:$frA),
2428 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2429 def : Pat<(fcopysign f32:$frB, f64:$frA),
2430 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2432 include "PPCInstrAltivec.td"
2433 include "PPCInstr64Bit.td"
2435 def crnot : OutPatFrag<(ops node:$in),
2437 def : Pat<(not i1:$in),
2440 // Patterns for arithmetic i1 operations.
2441 def : Pat<(add i1:$a, i1:$b),
2443 def : Pat<(sub i1:$a, i1:$b),
2445 def : Pat<(mul i1:$a, i1:$b),
2448 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2449 // (-1 is used to mean all bits set).
2450 def : Pat<(i1 -1), (CRSET)>;
2452 // i1 extensions, implemented in terms of isel.
2453 def : Pat<(i32 (zext i1:$in)),
2454 (SELECT_I4 $in, (LI 1), (LI 0))>;
2455 def : Pat<(i32 (sext i1:$in)),
2456 (SELECT_I4 $in, (LI -1), (LI 0))>;
2458 def : Pat<(i64 (zext i1:$in)),
2459 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2460 def : Pat<(i64 (sext i1:$in)),
2461 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2463 // FIXME: We should choose either a zext or a sext based on other constants
2465 def : Pat<(i32 (anyext i1:$in)),
2466 (SELECT_I4 $in, (LI 1), (LI 0))>;
2467 def : Pat<(i64 (anyext i1:$in)),
2468 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2470 // match setcc on i1 variables.
2471 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2473 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2475 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2477 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2479 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2481 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2483 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2485 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2487 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2489 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2492 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2493 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2494 // floating-point types.
2496 multiclass CRNotPat<dag pattern, dag result> {
2497 def : Pat<pattern, (crnot result)>;
2498 def : Pat<(not pattern), result>;
2500 // We can also fold the crnot into an extension:
2501 def : Pat<(i32 (zext pattern)),
2502 (SELECT_I4 result, (LI 0), (LI 1))>;
2503 def : Pat<(i32 (sext pattern)),
2504 (SELECT_I4 result, (LI 0), (LI -1))>;
2506 // We can also fold the crnot into an extension:
2507 def : Pat<(i64 (zext pattern)),
2508 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2509 def : Pat<(i64 (sext pattern)),
2510 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2512 // FIXME: We should choose either a zext or a sext based on other constants
2514 def : Pat<(i32 (anyext pattern)),
2515 (SELECT_I4 result, (LI 0), (LI 1))>;
2517 def : Pat<(i64 (anyext pattern)),
2518 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2521 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2522 // we need to write imm:$imm in the output patterns below, not just $imm, or
2523 // else the resulting matcher will not correctly add the immediate operand
2524 // (making it a register operand instead).
2527 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2528 OutPatFrag rfrag, OutPatFrag rfrag8> {
2529 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2531 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2533 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2534 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2535 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2536 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2538 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2540 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2542 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2543 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2544 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2545 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2548 // Note that we do all inversions below with i(32|64)not, instead of using
2549 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2550 // has 2-cycle latency.
2552 defm : ExtSetCCPat<SETEQ,
2553 PatFrag<(ops node:$in, node:$cc),
2554 (setcc $in, 0, $cc)>,
2555 OutPatFrag<(ops node:$in),
2556 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2557 OutPatFrag<(ops node:$in),
2558 (RLDICL (CNTLZD $in), 58, 63)> >;
2560 defm : ExtSetCCPat<SETNE,
2561 PatFrag<(ops node:$in, node:$cc),
2562 (setcc $in, 0, $cc)>,
2563 OutPatFrag<(ops node:$in),
2564 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2565 OutPatFrag<(ops node:$in),
2566 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2568 defm : ExtSetCCPat<SETLT,
2569 PatFrag<(ops node:$in, node:$cc),
2570 (setcc $in, 0, $cc)>,
2571 OutPatFrag<(ops node:$in),
2572 (RLWINM $in, 1, 31, 31)>,
2573 OutPatFrag<(ops node:$in),
2574 (RLDICL $in, 1, 63)> >;
2576 defm : ExtSetCCPat<SETGE,
2577 PatFrag<(ops node:$in, node:$cc),
2578 (setcc $in, 0, $cc)>,
2579 OutPatFrag<(ops node:$in),
2580 (RLWINM (i32not $in), 1, 31, 31)>,
2581 OutPatFrag<(ops node:$in),
2582 (RLDICL (i64not $in), 1, 63)> >;
2584 defm : ExtSetCCPat<SETGT,
2585 PatFrag<(ops node:$in, node:$cc),
2586 (setcc $in, 0, $cc)>,
2587 OutPatFrag<(ops node:$in),
2588 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2589 OutPatFrag<(ops node:$in),
2590 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2592 defm : ExtSetCCPat<SETLE,
2593 PatFrag<(ops node:$in, node:$cc),
2594 (setcc $in, 0, $cc)>,
2595 OutPatFrag<(ops node:$in),
2596 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2597 OutPatFrag<(ops node:$in),
2598 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2600 defm : ExtSetCCPat<SETLT,
2601 PatFrag<(ops node:$in, node:$cc),
2602 (setcc $in, -1, $cc)>,
2603 OutPatFrag<(ops node:$in),
2604 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2605 OutPatFrag<(ops node:$in),
2606 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2608 defm : ExtSetCCPat<SETGE,
2609 PatFrag<(ops node:$in, node:$cc),
2610 (setcc $in, -1, $cc)>,
2611 OutPatFrag<(ops node:$in),
2612 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2613 OutPatFrag<(ops node:$in),
2614 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2616 defm : ExtSetCCPat<SETGT,
2617 PatFrag<(ops node:$in, node:$cc),
2618 (setcc $in, -1, $cc)>,
2619 OutPatFrag<(ops node:$in),
2620 (RLWINM (i32not $in), 1, 31, 31)>,
2621 OutPatFrag<(ops node:$in),
2622 (RLDICL (i64not $in), 1, 63)> >;
2624 defm : ExtSetCCPat<SETLE,
2625 PatFrag<(ops node:$in, node:$cc),
2626 (setcc $in, -1, $cc)>,
2627 OutPatFrag<(ops node:$in),
2628 (RLWINM $in, 1, 31, 31)>,
2629 OutPatFrag<(ops node:$in),
2630 (RLDICL $in, 1, 63)> >;
2633 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2634 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2635 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2636 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2637 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2638 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2639 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2640 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2641 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2642 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2643 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2644 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2646 // For non-equality comparisons, the default code would materialize the
2647 // constant, then compare against it, like this:
2649 // ori r2, r2, 22136
2652 // Since we are just comparing for equality, we can emit this instead:
2653 // xoris r0,r3,0x1234
2654 // cmplwi cr0,r0,0x5678
2657 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2658 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2659 (LO16 imm:$imm)), sub_eq)>;
2661 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2662 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2663 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2664 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2665 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2666 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2667 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2668 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2669 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2670 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2671 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2672 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2674 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2675 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2676 (LO16 imm:$imm)), sub_eq)>;
2678 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
2679 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2680 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2681 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2682 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2683 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2684 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
2685 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2686 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2687 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2689 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2690 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2691 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
2692 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2693 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2694 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2695 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
2696 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2697 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2698 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2701 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
2702 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2703 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2704 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2705 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2706 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2707 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
2708 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2709 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
2710 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2711 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
2712 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2714 // For non-equality comparisons, the default code would materialize the
2715 // constant, then compare against it, like this:
2717 // ori r2, r2, 22136
2720 // Since we are just comparing for equality, we can emit this instead:
2721 // xoris r0,r3,0x1234
2722 // cmpldi cr0,r0,0x5678
2725 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
2726 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2727 (LO16 imm:$imm)), sub_eq)>;
2729 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
2730 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2731 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
2732 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2733 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
2734 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2735 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
2736 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2737 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
2738 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2739 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
2740 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2742 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
2743 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2744 (LO16 imm:$imm)), sub_eq)>;
2746 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
2747 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2748 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
2749 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2750 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
2751 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2752 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
2753 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2754 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
2755 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2757 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
2758 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2759 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
2760 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2761 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
2762 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2763 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
2764 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2765 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
2766 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2769 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
2770 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2771 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
2772 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2773 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
2774 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2775 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
2776 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2777 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
2778 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2779 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
2780 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2781 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
2782 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2784 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
2785 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2786 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
2787 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2788 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
2789 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2790 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
2791 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2792 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
2793 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2794 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
2795 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2796 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
2797 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2800 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
2801 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2802 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
2803 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2804 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
2805 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2806 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
2807 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2808 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
2809 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2810 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
2811 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2812 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
2813 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2815 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
2816 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2817 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
2818 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2819 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
2820 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2821 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
2822 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2823 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
2824 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2825 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
2826 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2827 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
2828 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2830 // match select on i1 variables:
2831 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
2832 (CROR (CRAND $cond , $tval),
2833 (CRAND (crnot $cond), $fval))>;
2835 // match selectcc on i1 variables:
2836 // select (lhs == rhs), tval, fval is:
2837 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
2838 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
2839 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
2840 (CRAND (CRORC $lhs, $rhs), $fval))>;
2841 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
2842 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
2843 (CRAND (CRANDC $lhs, $rhs), $fval))>;
2844 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
2845 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
2846 (CRAND (CRXOR $lhs, $rhs), $fval))>;
2847 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
2848 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
2849 (CRAND (CRANDC $rhs, $lhs), $fval))>;
2850 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
2851 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
2852 (CRAND (CRORC $rhs, $lhs), $fval))>;
2853 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
2854 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
2855 (CRAND (CRXOR $lhs, $rhs), $tval))>;
2857 // match selectcc on i1 variables with non-i1 output.
2858 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
2859 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
2860 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
2861 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
2862 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
2863 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
2864 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
2865 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
2866 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
2867 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
2868 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
2869 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
2871 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
2872 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
2873 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
2874 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
2875 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
2876 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
2877 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
2878 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
2879 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
2880 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
2881 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
2882 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
2884 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
2885 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
2886 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
2887 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
2888 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
2889 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
2890 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
2891 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
2892 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
2893 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
2894 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
2895 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
2897 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
2898 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
2899 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
2900 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
2901 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
2902 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
2903 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
2904 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
2905 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
2906 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
2907 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
2908 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
2910 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
2911 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
2912 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
2913 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
2914 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
2915 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
2916 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
2917 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
2918 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
2919 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
2920 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
2921 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
2923 let usesCustomInserter = 1 in {
2924 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
2926 [(set i1:$dst, (trunc (not i32:$in)))]>;
2927 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
2929 [(set i1:$dst, (trunc i32:$in))]>;
2931 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
2933 [(set i1:$dst, (trunc (not i64:$in)))]>;
2934 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
2936 [(set i1:$dst, (trunc i64:$in))]>;
2939 def : Pat<(i1 (not (trunc i32:$in))),
2940 (ANDIo_1_EQ_BIT $in)>;
2941 def : Pat<(i1 (not (trunc i64:$in))),
2942 (ANDIo_1_EQ_BIT8 $in)>;
2944 //===----------------------------------------------------------------------===//
2945 // PowerPC Instructions used for assembler/disassembler only
2948 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
2949 "isync", IIC_SprISYNC, []>;
2951 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
2952 "icbi $src", IIC_LdStICBI, []>;
2954 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
2955 "eieio", IIC_LdStLoad, []>;
2957 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
2958 "wait $L", IIC_LdStLoad, []>;
2960 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
2961 "mtmsr $RS, $L", IIC_SprMTMSR>;
2963 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
2964 "mfmsr $RT", IIC_SprMFMSR, []>;
2966 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
2967 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
2969 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
2970 "slbie $RB", IIC_SprSLBIE, []>;
2972 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
2973 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
2975 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
2976 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
2978 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
2980 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
2981 "tlbsync", IIC_SprTLBSYNC, []>;
2983 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
2984 "tlbiel $RB", IIC_SprTLBIEL, []>;
2986 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
2987 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
2989 //===----------------------------------------------------------------------===//
2990 // PowerPC Assembler Instruction Aliases
2993 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
2994 // These are aliases that require C++ handling to convert to the target
2995 // instruction, while InstAliases can be handled directly by tblgen.
2996 class PPCAsmPseudo<string asm, dag iops>
2998 let Namespace = "PPC";
2999 bit PPC64 = 0; // Default value, override with isPPC64
3001 let OutOperandList = (outs);
3002 let InOperandList = iops;
3004 let AsmString = asm;
3005 let isAsmParserOnly = 1;
3009 def : InstAlias<"sc", (SC 0)>;
3011 def : InstAlias<"sync", (SYNC 0)>, Requires<[IsNotBookE]>;
3012 def : InstAlias<"msync", (SYNC 0)>, Requires<[IsNotBookE]>;
3013 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[IsNotBookE]>;
3014 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[IsNotBookE]>;
3016 def : InstAlias<"wait", (WAIT 0)>;
3017 def : InstAlias<"waitrsv", (WAIT 1)>;
3018 def : InstAlias<"waitimpl", (WAIT 2)>;
3020 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3021 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3022 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3023 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3025 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3026 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3028 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3029 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3031 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3033 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3034 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3036 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3037 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3039 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3041 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3043 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3044 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3045 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3046 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3047 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3048 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3049 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3050 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3052 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3053 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3054 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3055 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3057 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3058 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3060 def : InstAlias<"mfsprg $RT, 0", (MFSPR gprc:$RT, 272)>;
3061 def : InstAlias<"mfsprg $RT, 1", (MFSPR gprc:$RT, 273)>;
3062 def : InstAlias<"mfsprg $RT, 2", (MFSPR gprc:$RT, 274)>;
3063 def : InstAlias<"mfsprg $RT, 3", (MFSPR gprc:$RT, 275)>;
3065 def : InstAlias<"mfsprg0 $RT", (MFSPR gprc:$RT, 272)>;
3066 def : InstAlias<"mfsprg1 $RT", (MFSPR gprc:$RT, 273)>;
3067 def : InstAlias<"mfsprg2 $RT", (MFSPR gprc:$RT, 274)>;
3068 def : InstAlias<"mfsprg3 $RT", (MFSPR gprc:$RT, 275)>;
3070 def : InstAlias<"mtsprg 0, $RT", (MTSPR 272, gprc:$RT)>;
3071 def : InstAlias<"mtsprg 1, $RT", (MTSPR 273, gprc:$RT)>;
3072 def : InstAlias<"mtsprg 2, $RT", (MTSPR 274, gprc:$RT)>;
3073 def : InstAlias<"mtsprg 3, $RT", (MTSPR 275, gprc:$RT)>;
3075 def : InstAlias<"mtsprg0 $RT", (MTSPR 272, gprc:$RT)>;
3076 def : InstAlias<"mtsprg1 $RT", (MTSPR 273, gprc:$RT)>;
3077 def : InstAlias<"mtsprg2 $RT", (MTSPR 274, gprc:$RT)>;
3078 def : InstAlias<"mtsprg3 $RT", (MTSPR 275, gprc:$RT)>;
3080 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3082 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3083 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3085 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3087 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3088 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3090 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3091 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3092 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3093 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3095 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3097 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3098 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3099 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3100 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3101 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3102 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3103 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3104 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3105 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3106 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3107 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3108 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3109 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3110 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3111 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3112 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3113 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3114 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3115 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3116 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3117 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3118 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3119 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3120 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3121 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3122 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3123 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3124 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3125 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3126 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3127 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3128 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3129 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3130 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3131 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3132 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3134 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3135 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3136 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3137 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3138 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3139 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3141 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3142 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3143 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3144 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3145 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3146 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3147 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3148 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3149 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3150 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3151 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3152 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3153 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3154 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3155 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3156 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3157 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3158 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3159 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3160 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3161 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3162 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3163 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3164 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3165 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3166 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3167 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3168 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3169 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3170 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3171 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3172 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3174 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3175 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3176 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3177 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3178 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3179 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3181 // These generic branch instruction forms are used for the assembler parser only.
3182 // Defs and Uses are conservative, since we don't know the BO value.
3183 let PPC970_Unit = 7 in {
3184 let Defs = [CTR], Uses = [CTR, RM] in {
3185 def gBC : BForm_3<16, 0, 0, (outs),
3186 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3187 "bc $bo, $bi, $dst">;
3188 def gBCA : BForm_3<16, 1, 0, (outs),
3189 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3190 "bca $bo, $bi, $dst">;
3192 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3193 def gBCL : BForm_3<16, 0, 1, (outs),
3194 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3195 "bcl $bo, $bi, $dst">;
3196 def gBCLA : BForm_3<16, 1, 1, (outs),
3197 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3198 "bcla $bo, $bi, $dst">;
3200 let Defs = [CTR], Uses = [CTR, LR, RM] in
3201 def gBCLR : XLForm_2<19, 16, 0, (outs),
3202 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3203 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3204 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3205 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3206 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3207 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3208 let Defs = [CTR], Uses = [CTR, LR, RM] in
3209 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3210 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3211 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3212 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3213 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3214 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3215 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3217 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3218 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3219 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3220 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3222 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3223 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3224 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3225 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3226 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3227 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3228 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3230 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3231 : BranchSimpleMnemonic1<name, pm, bo> {
3232 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3233 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3235 defm : BranchSimpleMnemonic2<"t", "", 12>;
3236 defm : BranchSimpleMnemonic2<"f", "", 4>;
3237 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3238 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3239 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3240 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3241 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3242 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3243 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3244 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3246 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3247 def : InstAlias<"b"#name#pm#" $cc, $dst",
3248 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3249 def : InstAlias<"b"#name#pm#" $dst",
3250 (BCC bibo, CR0, condbrtarget:$dst)>;
3252 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3253 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3254 def : InstAlias<"b"#name#"a"#pm#" $dst",
3255 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3257 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3258 (BCCLR bibo, crrc:$cc)>;
3259 def : InstAlias<"b"#name#"lr"#pm,
3262 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3263 (BCCCTR bibo, crrc:$cc)>;
3264 def : InstAlias<"b"#name#"ctr"#pm,
3265 (BCCCTR bibo, CR0)>;
3267 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3268 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3269 def : InstAlias<"b"#name#"l"#pm#" $dst",
3270 (BCCL bibo, CR0, condbrtarget:$dst)>;
3272 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3273 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3274 def : InstAlias<"b"#name#"la"#pm#" $dst",
3275 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3277 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3278 (BCCLRL bibo, crrc:$cc)>;
3279 def : InstAlias<"b"#name#"lrl"#pm,
3280 (BCCLRL bibo, CR0)>;
3282 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3283 (BCCCTRL bibo, crrc:$cc)>;
3284 def : InstAlias<"b"#name#"ctrl"#pm,
3285 (BCCCTRL bibo, CR0)>;
3287 multiclass BranchExtendedMnemonic<string name, int bibo> {
3288 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3289 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3290 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3292 defm : BranchExtendedMnemonic<"lt", 12>;
3293 defm : BranchExtendedMnemonic<"gt", 44>;
3294 defm : BranchExtendedMnemonic<"eq", 76>;
3295 defm : BranchExtendedMnemonic<"un", 108>;
3296 defm : BranchExtendedMnemonic<"so", 108>;
3297 defm : BranchExtendedMnemonic<"ge", 4>;
3298 defm : BranchExtendedMnemonic<"nl", 4>;
3299 defm : BranchExtendedMnemonic<"le", 36>;
3300 defm : BranchExtendedMnemonic<"ng", 36>;
3301 defm : BranchExtendedMnemonic<"ne", 68>;
3302 defm : BranchExtendedMnemonic<"nu", 100>;
3303 defm : BranchExtendedMnemonic<"ns", 100>;
3305 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3306 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3307 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3308 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3309 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3310 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3311 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3312 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3314 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3315 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3316 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3317 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3318 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3319 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3320 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3321 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3323 multiclass TrapExtendedMnemonic<string name, int to> {
3324 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3325 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3326 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3327 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3329 defm : TrapExtendedMnemonic<"lt", 16>;
3330 defm : TrapExtendedMnemonic<"le", 20>;
3331 defm : TrapExtendedMnemonic<"eq", 4>;
3332 defm : TrapExtendedMnemonic<"ge", 12>;
3333 defm : TrapExtendedMnemonic<"gt", 8>;
3334 defm : TrapExtendedMnemonic<"nl", 12>;
3335 defm : TrapExtendedMnemonic<"ne", 24>;
3336 defm : TrapExtendedMnemonic<"ng", 20>;
3337 defm : TrapExtendedMnemonic<"llt", 2>;
3338 defm : TrapExtendedMnemonic<"lle", 6>;
3339 defm : TrapExtendedMnemonic<"lge", 5>;
3340 defm : TrapExtendedMnemonic<"lgt", 1>;
3341 defm : TrapExtendedMnemonic<"lnl", 5>;
3342 defm : TrapExtendedMnemonic<"lng", 6>;
3343 defm : TrapExtendedMnemonic<"u", 31>;