1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
50 SDTCisPtrTy<0>, SDTCisVT<1, i32>
53 def tocentry32 : Operand<iPTR> {
54 let MIOperandInfo = (ops i32imm:$imm);
57 def SDT_PPCqvfperm : SDTypeProfile<1, 3, [
58 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>
60 def SDT_PPCqvgpci : SDTypeProfile<1, 1, [
61 SDTCisVec<0>, SDTCisInt<1>
63 def SDT_PPCqvaligni : SDTypeProfile<1, 3, [
64 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>
66 def SDT_PPCqvesplati : SDTypeProfile<1, 2, [
67 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
70 def SDT_PPCqbflt : SDTypeProfile<1, 1, [
71 SDTCisVec<0>, SDTCisVec<1>
74 def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
75 SDTCisVec<0>, SDTCisPtrTy<1>
78 //===----------------------------------------------------------------------===//
79 // PowerPC specific DAG Nodes.
82 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
83 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
85 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
86 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
87 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
88 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
89 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
90 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
91 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
92 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
93 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
94 [SDNPHasChain, SDNPMayStore]>;
95 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
96 [SDNPHasChain, SDNPMayLoad]>;
97 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
98 [SDNPHasChain, SDNPMayLoad]>;
100 // Extract FPSCR (not modeled at the DAG level).
101 def PPCmffs : SDNode<"PPCISD::MFFS",
102 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
104 // Perform FADD in round-to-zero mode.
105 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
108 def PPCfsel : SDNode<"PPCISD::FSEL",
109 // Type constraint for fsel.
110 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
111 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
113 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
114 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
115 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp,
116 [SDNPMayLoad, SDNPMemOperand]>;
117 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
118 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
120 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
122 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
123 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
125 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
126 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
127 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
128 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
129 def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
130 SDTypeProfile<1, 3, [
131 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
132 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
133 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
134 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
135 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
136 def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
137 SDTypeProfile<1, 3, [
138 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
139 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
140 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
141 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
143 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
145 def PPCqvfperm : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
146 def PPCqvgpci : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
147 def PPCqvaligni : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
148 def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;
150 def PPCqbflt : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>;
152 def PPCqvlfsb : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb,
153 [SDNPHasChain, SDNPMayLoad]>;
155 def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
157 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
158 // amounts. These nodes are generated by the multi-precision shift code.
159 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
160 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
161 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
163 // These are target-independent nodes, but have target-specific formats.
164 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
165 [SDNPHasChain, SDNPOutGlue]>;
166 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
167 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
169 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
170 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
171 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
173 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
174 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
176 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
177 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
178 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
179 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
181 def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
182 SDTypeProfile<0, 1, []>,
183 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
186 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
187 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
189 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
190 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
192 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
193 SDTypeProfile<1, 1, [SDTCisInt<0>,
195 [SDNPHasChain, SDNPSideEffect]>;
196 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
197 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
198 [SDNPHasChain, SDNPSideEffect]>;
200 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
201 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
202 [SDNPHasChain, SDNPSideEffect]>;
204 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
205 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
207 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
208 [SDNPHasChain, SDNPOptInGlue]>;
210 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
211 [SDNPHasChain, SDNPMayLoad]>;
212 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
213 [SDNPHasChain, SDNPMayStore]>;
215 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
216 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
217 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
218 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
219 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
221 // Instructions to support dynamic alloca.
222 def SDTDynOp : SDTypeProfile<1, 2, []>;
223 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
225 //===----------------------------------------------------------------------===//
226 // PowerPC specific transformation functions and pattern fragments.
229 def SHL32 : SDNodeXForm<imm, [{
230 // Transformation function: 31 - imm
231 return getI32Imm(31 - N->getZExtValue(), SDLoc(N));
234 def SRL32 : SDNodeXForm<imm, [{
235 // Transformation function: 32 - imm
236 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N))
237 : getI32Imm(0, SDLoc(N));
240 def LO16 : SDNodeXForm<imm, [{
241 // Transformation function: get the low 16 bits.
242 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N));
245 def HI16 : SDNodeXForm<imm, [{
246 // Transformation function: shift the immediate value down into the low bits.
247 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N));
250 def HA16 : SDNodeXForm<imm, [{
251 // Transformation function: shift the immediate value down into the low bits.
252 signed int Val = N->getZExtValue();
253 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
255 def MB : SDNodeXForm<imm, [{
256 // Transformation function: get the start bit of a mask
258 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
259 return getI32Imm(mb, SDLoc(N));
262 def ME : SDNodeXForm<imm, [{
263 // Transformation function: get the end bit of a mask
265 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
266 return getI32Imm(me, SDLoc(N));
268 def maskimm32 : PatLeaf<(imm), [{
269 // maskImm predicate - True if immediate is a run of ones.
271 if (N->getValueType(0) == MVT::i32)
272 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
277 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
278 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
279 // sign extended field. Used by instructions like 'addi'.
280 return (int32_t)Imm == (short)Imm;
282 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
283 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
284 // sign extended field. Used by instructions like 'addi'.
285 return (int64_t)Imm == (short)Imm;
287 def immZExt16 : PatLeaf<(imm), [{
288 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
289 // field. Used by instructions like 'ori'.
290 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
293 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
294 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
295 // identical in 32-bit mode, but in 64-bit mode, they return true if the
296 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
298 def imm16ShiftedZExt : PatLeaf<(imm), [{
299 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
300 // immediate are set. Used by instructions like 'xoris'.
301 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
304 def imm16ShiftedSExt : PatLeaf<(imm), [{
305 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
306 // immediate are set. Used by instructions like 'addis'. Identical to
307 // imm16ShiftedZExt in 32-bit mode.
308 if (N->getZExtValue() & 0xFFFF) return false;
309 if (N->getValueType(0) == MVT::i32)
311 // For 64-bit, make sure it is sext right.
312 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
315 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
316 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
317 // zero extended field.
318 return isUInt<32>(Imm);
321 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
322 // restricted memrix (4-aligned) constants are alignment sensitive. If these
323 // offsets are hidden behind TOC entries than the values of the lower-order
324 // bits cannot be checked directly. As a result, we need to also incorporate
325 // an alignment check into the relevant patterns.
327 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
328 return cast<LoadSDNode>(N)->getAlignment() >= 4;
330 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
331 (store node:$val, node:$ptr), [{
332 return cast<StoreSDNode>(N)->getAlignment() >= 4;
334 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
335 return cast<LoadSDNode>(N)->getAlignment() >= 4;
337 def aligned4pre_store : PatFrag<
338 (ops node:$val, node:$base, node:$offset),
339 (pre_store node:$val, node:$base, node:$offset), [{
340 return cast<StoreSDNode>(N)->getAlignment() >= 4;
343 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
344 return cast<LoadSDNode>(N)->getAlignment() < 4;
346 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
347 (store node:$val, node:$ptr), [{
348 return cast<StoreSDNode>(N)->getAlignment() < 4;
350 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
351 return cast<LoadSDNode>(N)->getAlignment() < 4;
354 //===----------------------------------------------------------------------===//
355 // PowerPC Flag Definitions.
357 class isPPC64 { bit PPC64 = 1; }
358 class isDOT { bit RC = 1; }
360 class RegConstraint<string C> {
361 string Constraints = C;
363 class NoEncode<string E> {
364 string DisableEncoding = E;
368 //===----------------------------------------------------------------------===//
369 // PowerPC Operand Definitions.
371 // In the default PowerPC assembler syntax, registers are specified simply
372 // by number, so they cannot be distinguished from immediate values (without
373 // looking at the opcode). This means that the default operand matching logic
374 // for the asm parser does not work, and we need to specify custom matchers.
375 // Since those can only be specified with RegisterOperand classes and not
376 // directly on the RegisterClass, all instructions patterns used by the asm
377 // parser need to use a RegisterOperand (instead of a RegisterClass) for
378 // all their register operands.
379 // For this purpose, we define one RegisterOperand for each RegisterClass,
380 // using the same name as the class, just in lower case.
382 def PPCRegGPRCAsmOperand : AsmOperandClass {
383 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
385 def gprc : RegisterOperand<GPRC> {
386 let ParserMatchClass = PPCRegGPRCAsmOperand;
388 def PPCRegG8RCAsmOperand : AsmOperandClass {
389 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
391 def g8rc : RegisterOperand<G8RC> {
392 let ParserMatchClass = PPCRegG8RCAsmOperand;
394 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
395 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
397 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
398 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
400 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
401 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
403 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
404 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
406 def PPCRegF8RCAsmOperand : AsmOperandClass {
407 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
409 def f8rc : RegisterOperand<F8RC> {
410 let ParserMatchClass = PPCRegF8RCAsmOperand;
412 def PPCRegF4RCAsmOperand : AsmOperandClass {
413 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
415 def f4rc : RegisterOperand<F4RC> {
416 let ParserMatchClass = PPCRegF4RCAsmOperand;
418 def PPCRegVRRCAsmOperand : AsmOperandClass {
419 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
421 def vrrc : RegisterOperand<VRRC> {
422 let ParserMatchClass = PPCRegVRRCAsmOperand;
424 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
425 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
427 def crbitrc : RegisterOperand<CRBITRC> {
428 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
430 def PPCRegCRRCAsmOperand : AsmOperandClass {
431 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
433 def crrc : RegisterOperand<CRRC> {
434 let ParserMatchClass = PPCRegCRRCAsmOperand;
436 def crrc0 : RegisterOperand<CRRC0> {
437 let ParserMatchClass = PPCRegCRRCAsmOperand;
440 def PPCU1ImmAsmOperand : AsmOperandClass {
441 let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
442 let RenderMethod = "addImmOperands";
444 def u1imm : Operand<i32> {
445 let PrintMethod = "printU1ImmOperand";
446 let ParserMatchClass = PPCU1ImmAsmOperand;
449 def PPCU2ImmAsmOperand : AsmOperandClass {
450 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
451 let RenderMethod = "addImmOperands";
453 def u2imm : Operand<i32> {
454 let PrintMethod = "printU2ImmOperand";
455 let ParserMatchClass = PPCU2ImmAsmOperand;
458 def PPCU3ImmAsmOperand : AsmOperandClass {
459 let Name = "U3Imm"; let PredicateMethod = "isU3Imm";
460 let RenderMethod = "addImmOperands";
462 def u3imm : Operand<i32> {
463 let PrintMethod = "printU3ImmOperand";
464 let ParserMatchClass = PPCU3ImmAsmOperand;
467 def PPCU4ImmAsmOperand : AsmOperandClass {
468 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
469 let RenderMethod = "addImmOperands";
471 def u4imm : Operand<i32> {
472 let PrintMethod = "printU4ImmOperand";
473 let ParserMatchClass = PPCU4ImmAsmOperand;
475 def PPCS5ImmAsmOperand : AsmOperandClass {
476 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
477 let RenderMethod = "addImmOperands";
479 def s5imm : Operand<i32> {
480 let PrintMethod = "printS5ImmOperand";
481 let ParserMatchClass = PPCS5ImmAsmOperand;
482 let DecoderMethod = "decodeSImmOperand<5>";
484 def PPCU5ImmAsmOperand : AsmOperandClass {
485 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
486 let RenderMethod = "addImmOperands";
488 def u5imm : Operand<i32> {
489 let PrintMethod = "printU5ImmOperand";
490 let ParserMatchClass = PPCU5ImmAsmOperand;
491 let DecoderMethod = "decodeUImmOperand<5>";
493 def PPCU6ImmAsmOperand : AsmOperandClass {
494 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
495 let RenderMethod = "addImmOperands";
497 def u6imm : Operand<i32> {
498 let PrintMethod = "printU6ImmOperand";
499 let ParserMatchClass = PPCU6ImmAsmOperand;
500 let DecoderMethod = "decodeUImmOperand<6>";
502 def PPCU12ImmAsmOperand : AsmOperandClass {
503 let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
504 let RenderMethod = "addImmOperands";
506 def u12imm : Operand<i32> {
507 let PrintMethod = "printU12ImmOperand";
508 let ParserMatchClass = PPCU12ImmAsmOperand;
509 let DecoderMethod = "decodeUImmOperand<12>";
511 def PPCS16ImmAsmOperand : AsmOperandClass {
512 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
513 let RenderMethod = "addS16ImmOperands";
515 def s16imm : Operand<i32> {
516 let PrintMethod = "printS16ImmOperand";
517 let EncoderMethod = "getImm16Encoding";
518 let ParserMatchClass = PPCS16ImmAsmOperand;
519 let DecoderMethod = "decodeSImmOperand<16>";
521 def PPCU16ImmAsmOperand : AsmOperandClass {
522 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
523 let RenderMethod = "addU16ImmOperands";
525 def u16imm : Operand<i32> {
526 let PrintMethod = "printU16ImmOperand";
527 let EncoderMethod = "getImm16Encoding";
528 let ParserMatchClass = PPCU16ImmAsmOperand;
529 let DecoderMethod = "decodeUImmOperand<16>";
531 def PPCS17ImmAsmOperand : AsmOperandClass {
532 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
533 let RenderMethod = "addS16ImmOperands";
535 def s17imm : Operand<i32> {
536 // This operand type is used for addis/lis to allow the assembler parser
537 // to accept immediates in the range -65536..65535 for compatibility with
538 // the GNU assembler. The operand is treated as 16-bit otherwise.
539 let PrintMethod = "printS16ImmOperand";
540 let EncoderMethod = "getImm16Encoding";
541 let ParserMatchClass = PPCS17ImmAsmOperand;
542 let DecoderMethod = "decodeSImmOperand<16>";
544 def PPCDirectBrAsmOperand : AsmOperandClass {
545 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
546 let RenderMethod = "addBranchTargetOperands";
548 def directbrtarget : Operand<OtherVT> {
549 let PrintMethod = "printBranchOperand";
550 let EncoderMethod = "getDirectBrEncoding";
551 let ParserMatchClass = PPCDirectBrAsmOperand;
553 def absdirectbrtarget : Operand<OtherVT> {
554 let PrintMethod = "printAbsBranchOperand";
555 let EncoderMethod = "getAbsDirectBrEncoding";
556 let ParserMatchClass = PPCDirectBrAsmOperand;
558 def PPCCondBrAsmOperand : AsmOperandClass {
559 let Name = "CondBr"; let PredicateMethod = "isCondBr";
560 let RenderMethod = "addBranchTargetOperands";
562 def condbrtarget : Operand<OtherVT> {
563 let PrintMethod = "printBranchOperand";
564 let EncoderMethod = "getCondBrEncoding";
565 let ParserMatchClass = PPCCondBrAsmOperand;
567 def abscondbrtarget : Operand<OtherVT> {
568 let PrintMethod = "printAbsBranchOperand";
569 let EncoderMethod = "getAbsCondBrEncoding";
570 let ParserMatchClass = PPCCondBrAsmOperand;
572 def calltarget : Operand<iPTR> {
573 let PrintMethod = "printBranchOperand";
574 let EncoderMethod = "getDirectBrEncoding";
575 let ParserMatchClass = PPCDirectBrAsmOperand;
577 def abscalltarget : Operand<iPTR> {
578 let PrintMethod = "printAbsBranchOperand";
579 let EncoderMethod = "getAbsDirectBrEncoding";
580 let ParserMatchClass = PPCDirectBrAsmOperand;
582 def PPCCRBitMaskOperand : AsmOperandClass {
583 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
585 def crbitm: Operand<i8> {
586 let PrintMethod = "printcrbitm";
587 let EncoderMethod = "get_crbitm_encoding";
588 let DecoderMethod = "decodeCRBitMOperand";
589 let ParserMatchClass = PPCCRBitMaskOperand;
592 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
593 def PPCRegGxRCNoR0Operand : AsmOperandClass {
594 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
596 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
597 let ParserMatchClass = PPCRegGxRCNoR0Operand;
599 // A version of ptr_rc usable with the asm parser.
600 def PPCRegGxRCOperand : AsmOperandClass {
601 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
603 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
604 let ParserMatchClass = PPCRegGxRCOperand;
607 def PPCDispRIOperand : AsmOperandClass {
608 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
609 let RenderMethod = "addS16ImmOperands";
611 def dispRI : Operand<iPTR> {
612 let ParserMatchClass = PPCDispRIOperand;
614 def PPCDispRIXOperand : AsmOperandClass {
615 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
616 let RenderMethod = "addImmOperands";
618 def dispRIX : Operand<iPTR> {
619 let ParserMatchClass = PPCDispRIXOperand;
621 def PPCDispSPE8Operand : AsmOperandClass {
622 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
623 let RenderMethod = "addImmOperands";
625 def dispSPE8 : Operand<iPTR> {
626 let ParserMatchClass = PPCDispSPE8Operand;
628 def PPCDispSPE4Operand : AsmOperandClass {
629 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
630 let RenderMethod = "addImmOperands";
632 def dispSPE4 : Operand<iPTR> {
633 let ParserMatchClass = PPCDispSPE4Operand;
635 def PPCDispSPE2Operand : AsmOperandClass {
636 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
637 let RenderMethod = "addImmOperands";
639 def dispSPE2 : Operand<iPTR> {
640 let ParserMatchClass = PPCDispSPE2Operand;
643 def memri : Operand<iPTR> {
644 let PrintMethod = "printMemRegImm";
645 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
646 let EncoderMethod = "getMemRIEncoding";
647 let DecoderMethod = "decodeMemRIOperands";
649 def memrr : Operand<iPTR> {
650 let PrintMethod = "printMemRegReg";
651 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
653 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
654 let PrintMethod = "printMemRegImm";
655 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
656 let EncoderMethod = "getMemRIXEncoding";
657 let DecoderMethod = "decodeMemRIXOperands";
659 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
660 let PrintMethod = "printMemRegImm";
661 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
662 let EncoderMethod = "getSPE8DisEncoding";
664 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
665 let PrintMethod = "printMemRegImm";
666 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
667 let EncoderMethod = "getSPE4DisEncoding";
669 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
670 let PrintMethod = "printMemRegImm";
671 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
672 let EncoderMethod = "getSPE2DisEncoding";
675 // A single-register address. This is used with the SjLj
676 // pseudo-instructions.
677 def memr : Operand<iPTR> {
678 let MIOperandInfo = (ops ptr_rc:$ptrreg);
680 def PPCTLSRegOperand : AsmOperandClass {
681 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
682 let RenderMethod = "addTLSRegOperands";
684 def tlsreg32 : Operand<i32> {
685 let EncoderMethod = "getTLSRegEncoding";
686 let ParserMatchClass = PPCTLSRegOperand;
688 def tlsgd32 : Operand<i32> {}
689 def tlscall32 : Operand<i32> {
690 let PrintMethod = "printTLSCall";
691 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
692 let EncoderMethod = "getTLSCallEncoding";
695 // PowerPC Predicate operand.
696 def pred : Operand<OtherVT> {
697 let PrintMethod = "printPredicateOperand";
698 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
701 // Define PowerPC specific addressing mode.
702 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
703 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
704 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
705 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
707 // The address in a single register. This is used with the SjLj
708 // pseudo-instructions.
709 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
711 /// This is just the offset part of iaddr, used for preinc.
712 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
714 //===----------------------------------------------------------------------===//
715 // PowerPC Instruction Predicate Definitions.
716 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
717 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
718 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
719 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
720 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
721 def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
722 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
723 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
724 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
725 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
726 def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
727 def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
728 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
729 def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">;
730 def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
731 def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
733 //===----------------------------------------------------------------------===//
734 // PowerPC Multiclass Definitions.
736 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
737 string asmbase, string asmstr, InstrItinClass itin,
739 let BaseName = asmbase in {
740 def NAME : XForm_6<opcode, xo, OOL, IOL,
741 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
742 pattern>, RecFormRel;
744 def o : XForm_6<opcode, xo, OOL, IOL,
745 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
746 []>, isDOT, RecFormRel;
750 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
751 string asmbase, string asmstr, InstrItinClass itin,
753 let BaseName = asmbase in {
754 let Defs = [CARRY] in
755 def NAME : XForm_6<opcode, xo, OOL, IOL,
756 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
757 pattern>, RecFormRel;
758 let Defs = [CARRY, CR0] in
759 def o : XForm_6<opcode, xo, OOL, IOL,
760 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
761 []>, isDOT, RecFormRel;
765 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
766 string asmbase, string asmstr, InstrItinClass itin,
768 let BaseName = asmbase in {
769 let Defs = [CARRY] in
770 def NAME : XForm_10<opcode, xo, OOL, IOL,
771 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
772 pattern>, RecFormRel;
773 let Defs = [CARRY, CR0] in
774 def o : XForm_10<opcode, xo, OOL, IOL,
775 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
776 []>, isDOT, RecFormRel;
780 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
781 string asmbase, string asmstr, InstrItinClass itin,
783 let BaseName = asmbase in {
784 def NAME : XForm_11<opcode, xo, OOL, IOL,
785 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
786 pattern>, RecFormRel;
788 def o : XForm_11<opcode, xo, OOL, IOL,
789 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
790 []>, isDOT, RecFormRel;
794 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
795 string asmbase, string asmstr, InstrItinClass itin,
797 let BaseName = asmbase in {
798 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
799 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
800 pattern>, RecFormRel;
802 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
803 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
804 []>, isDOT, RecFormRel;
808 // Multiclass for instructions for which the non record form is not cracked
809 // and the record form is cracked (i.e. divw, mullw, etc.)
810 multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
811 string asmbase, string asmstr, InstrItinClass itin,
813 let BaseName = asmbase in {
814 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
815 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
816 pattern>, RecFormRel;
818 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
819 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
820 []>, isDOT, RecFormRel, PPC970_DGroup_First,
821 PPC970_DGroup_Cracked;
825 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
826 string asmbase, string asmstr, InstrItinClass itin,
828 let BaseName = asmbase in {
829 let Defs = [CARRY] in
830 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
831 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
832 pattern>, RecFormRel;
833 let Defs = [CARRY, CR0] in
834 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
835 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
836 []>, isDOT, RecFormRel;
840 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
841 string asmbase, string asmstr, InstrItinClass itin,
843 let BaseName = asmbase in {
844 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
845 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
846 pattern>, RecFormRel;
848 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
849 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
850 []>, isDOT, RecFormRel;
854 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
855 string asmbase, string asmstr, InstrItinClass itin,
857 let BaseName = asmbase in {
858 let Defs = [CARRY] in
859 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
860 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
861 pattern>, RecFormRel;
862 let Defs = [CARRY, CR0] in
863 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
864 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
865 []>, isDOT, RecFormRel;
869 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
870 string asmbase, string asmstr, InstrItinClass itin,
872 let BaseName = asmbase in {
873 def NAME : MForm_2<opcode, OOL, IOL,
874 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
875 pattern>, RecFormRel;
877 def o : MForm_2<opcode, OOL, IOL,
878 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
879 []>, isDOT, RecFormRel;
883 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
884 string asmbase, string asmstr, InstrItinClass itin,
886 let BaseName = asmbase in {
887 def NAME : MDForm_1<opcode, xo, OOL, IOL,
888 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
889 pattern>, RecFormRel;
891 def o : MDForm_1<opcode, xo, OOL, IOL,
892 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
893 []>, isDOT, RecFormRel;
897 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
898 string asmbase, string asmstr, InstrItinClass itin,
900 let BaseName = asmbase in {
901 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
902 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
903 pattern>, RecFormRel;
905 def o : MDSForm_1<opcode, xo, OOL, IOL,
906 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
907 []>, isDOT, RecFormRel;
911 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
912 string asmbase, string asmstr, InstrItinClass itin,
914 let BaseName = asmbase in {
915 let Defs = [CARRY] in
916 def NAME : XSForm_1<opcode, xo, OOL, IOL,
917 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
918 pattern>, RecFormRel;
919 let Defs = [CARRY, CR0] in
920 def o : XSForm_1<opcode, xo, OOL, IOL,
921 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
922 []>, isDOT, RecFormRel;
926 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
927 string asmbase, string asmstr, InstrItinClass itin,
929 let BaseName = asmbase in {
930 def NAME : XForm_26<opcode, xo, OOL, IOL,
931 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
932 pattern>, RecFormRel;
934 def o : XForm_26<opcode, xo, OOL, IOL,
935 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
936 []>, isDOT, RecFormRel;
940 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
941 string asmbase, string asmstr, InstrItinClass itin,
943 let BaseName = asmbase in {
944 def NAME : XForm_28<opcode, xo, OOL, IOL,
945 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
946 pattern>, RecFormRel;
948 def o : XForm_28<opcode, xo, OOL, IOL,
949 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
950 []>, isDOT, RecFormRel;
954 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
955 string asmbase, string asmstr, InstrItinClass itin,
957 let BaseName = asmbase in {
958 def NAME : AForm_1<opcode, xo, OOL, IOL,
959 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
960 pattern>, RecFormRel;
962 def o : AForm_1<opcode, xo, OOL, IOL,
963 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
964 []>, isDOT, RecFormRel;
968 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
969 string asmbase, string asmstr, InstrItinClass itin,
971 let BaseName = asmbase in {
972 def NAME : AForm_2<opcode, xo, OOL, IOL,
973 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
974 pattern>, RecFormRel;
976 def o : AForm_2<opcode, xo, OOL, IOL,
977 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
978 []>, isDOT, RecFormRel;
982 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
983 string asmbase, string asmstr, InstrItinClass itin,
985 let BaseName = asmbase in {
986 def NAME : AForm_3<opcode, xo, OOL, IOL,
987 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
988 pattern>, RecFormRel;
990 def o : AForm_3<opcode, xo, OOL, IOL,
991 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
992 []>, isDOT, RecFormRel;
996 //===----------------------------------------------------------------------===//
997 // PowerPC Instruction Definitions.
999 // Pseudo-instructions:
1001 let hasCtrlDep = 1 in {
1002 let Defs = [R1], Uses = [R1] in {
1003 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
1004 [(callseq_start timm:$amt)]>;
1005 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
1006 [(callseq_end timm:$amt1, timm:$amt2)]>;
1009 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1010 "UPDATE_VRSAVE $rD, $rS", []>;
1013 let Defs = [R1], Uses = [R1] in
1014 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1016 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
1018 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
1019 // instruction selection into a branch sequence.
1020 let usesCustomInserter = 1, // Expanded after instruction selection.
1021 PPC970_Single = 1 in {
1022 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
1023 // because either operand might become the first operand in an isel, and
1024 // that operand cannot be r0.
1025 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1026 gprc_nor0:$T, gprc_nor0:$F,
1027 i32imm:$BROPC), "#SELECT_CC_I4",
1029 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1030 g8rc_nox0:$T, g8rc_nox0:$F,
1031 i32imm:$BROPC), "#SELECT_CC_I8",
1033 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1034 i32imm:$BROPC), "#SELECT_CC_F4",
1036 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1037 i32imm:$BROPC), "#SELECT_CC_F8",
1039 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1040 i32imm:$BROPC), "#SELECT_CC_VRRC",
1043 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
1044 // register bit directly.
1045 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1046 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
1047 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
1048 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1049 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
1050 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
1051 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1052 f4rc:$T, f4rc:$F), "#SELECT_F4",
1053 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
1054 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1055 f8rc:$T, f8rc:$F), "#SELECT_F8",
1056 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1057 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1058 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
1060 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
1063 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
1064 // scavenge a register for it.
1065 let mayStore = 1 in {
1066 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1068 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1069 "#SPILL_CRBIT", []>;
1072 // RESTORE_CR - Indicate that we're restoring the CR register (previously
1073 // spilled), so we'll need to scavenge a register for it.
1074 let mayLoad = 1 in {
1075 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1077 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1078 "#RESTORE_CRBIT", []>;
1081 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1082 let isReturn = 1, Uses = [LR, RM] in
1083 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1084 [(retflag)]>, Requires<[In32BitMode]>;
1085 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1086 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1089 let isCodeGenOnly = 1 in {
1090 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1091 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1094 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1095 "bcctr 12, $bi, 0", IIC_BrB, []>;
1096 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1097 "bcctr 4, $bi, 0", IIC_BrB, []>;
1103 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1106 def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1109 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1110 let isBarrier = 1 in {
1111 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1114 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1115 "ba $dst", IIC_BrB, []>;
1118 // BCC represents an arbitrary conditional branch on a predicate.
1119 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1120 // a two-value operand where a dag node expects two operands. :(
1121 let isCodeGenOnly = 1 in {
1122 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1123 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1124 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1125 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1126 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1128 let isReturn = 1, Uses = [LR, RM] in
1129 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1130 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1133 let isCodeGenOnly = 1 in {
1134 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1135 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1136 "bc 12, $bi, $dst">;
1138 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1139 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1142 let isReturn = 1, Uses = [LR, RM] in
1143 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1144 "bclr 12, $bi, 0", IIC_BrB, []>;
1145 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1146 "bclr 4, $bi, 0", IIC_BrB, []>;
1149 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1150 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1151 "bdzlr", IIC_BrB, []>;
1152 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1153 "bdnzlr", IIC_BrB, []>;
1154 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1155 "bdzlr+", IIC_BrB, []>;
1156 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1157 "bdnzlr+", IIC_BrB, []>;
1158 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1159 "bdzlr-", IIC_BrB, []>;
1160 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1161 "bdnzlr-", IIC_BrB, []>;
1164 let Defs = [CTR], Uses = [CTR] in {
1165 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1167 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1169 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1171 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1173 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1175 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1177 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1179 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1181 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1183 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1185 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1187 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1192 // The unconditional BCL used by the SjLj setjmp code.
1193 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1194 let Defs = [LR], Uses = [RM] in {
1195 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1196 "bcl 20, 31, $dst">;
1200 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1201 // Convenient aliases for call instructions
1202 let Uses = [RM] in {
1203 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1204 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1205 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1206 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1208 let isCodeGenOnly = 1 in {
1209 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1210 "bl $func", IIC_BrB, []>;
1211 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1212 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1213 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1214 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1216 def BCL : BForm_4<16, 12, 0, 1, (outs),
1217 (ins crbitrc:$bi, condbrtarget:$dst),
1218 "bcl 12, $bi, $dst">;
1219 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1220 (ins crbitrc:$bi, condbrtarget:$dst),
1221 "bcl 4, $bi, $dst">;
1224 let Uses = [CTR, RM] in {
1225 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1226 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1227 Requires<[In32BitMode]>;
1229 let isCodeGenOnly = 1 in {
1230 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1231 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1234 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1235 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1236 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1237 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1240 let Uses = [LR, RM] in {
1241 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1242 "blrl", IIC_BrB, []>;
1244 let isCodeGenOnly = 1 in {
1245 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1246 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1249 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1250 "bclrl 12, $bi, 0", IIC_BrB, []>;
1251 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1252 "bclrl 4, $bi, 0", IIC_BrB, []>;
1255 let Defs = [CTR], Uses = [CTR, RM] in {
1256 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1258 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1260 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1262 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1264 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1266 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1268 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1270 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1272 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1274 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1276 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1278 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1281 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1282 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1283 "bdzlrl", IIC_BrB, []>;
1284 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1285 "bdnzlrl", IIC_BrB, []>;
1286 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1287 "bdzlrl+", IIC_BrB, []>;
1288 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1289 "bdnzlrl+", IIC_BrB, []>;
1290 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1291 "bdzlrl-", IIC_BrB, []>;
1292 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1293 "bdnzlrl-", IIC_BrB, []>;
1297 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1298 def TCRETURNdi :Pseudo< (outs),
1299 (ins calltarget:$dst, i32imm:$offset),
1300 "#TC_RETURNd $dst $offset",
1304 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1305 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1306 "#TC_RETURNa $func $offset",
1307 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1309 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1310 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1311 "#TC_RETURNr $dst $offset",
1315 let isCodeGenOnly = 1 in {
1317 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1318 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1319 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1320 []>, Requires<[In32BitMode]>;
1322 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1323 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1324 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1328 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1329 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1330 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1336 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1338 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1339 "#EH_SJLJ_SETJMP32",
1340 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1341 Requires<[In32BitMode]>;
1342 let isTerminator = 1 in
1343 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1344 "#EH_SJLJ_LONGJMP32",
1345 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1346 Requires<[In32BitMode]>;
1349 let isBranch = 1, isTerminator = 1 in {
1350 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1351 "#EH_SjLj_Setup\t$dst", []>;
1355 let PPC970_Unit = 7 in {
1356 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1357 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1360 // DCB* instructions.
1361 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1362 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1363 PPC970_DGroup_Single;
1364 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1365 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1366 PPC970_DGroup_Single;
1367 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1368 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1369 PPC970_DGroup_Single;
1370 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1371 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1372 PPC970_DGroup_Single;
1373 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1374 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1375 PPC970_DGroup_Single;
1376 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1377 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1378 PPC970_DGroup_Single;
1380 let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
1381 def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst),
1382 "dcbt $dst, $TH", IIC_LdStDCBF, []>,
1383 PPC970_DGroup_Single;
1384 def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst),
1385 "dcbtst $dst, $TH", IIC_LdStDCBF, []>,
1386 PPC970_DGroup_Single;
1387 } // hasSideEffects = 0
1389 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1390 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1392 def : Pat<(int_ppc_dcbt xoaddr:$dst),
1393 (DCBT 0, xoaddr:$dst)>;
1394 def : Pat<(int_ppc_dcbtst xoaddr:$dst),
1395 (DCBTST 0, xoaddr:$dst)>;
1397 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1398 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads
1399 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1400 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores
1401 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1402 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1404 // Atomic operations
1405 let usesCustomInserter = 1 in {
1406 let Defs = [CR0] in {
1407 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1408 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1409 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1410 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1411 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1412 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1413 def ATOMIC_LOAD_AND_I8 : Pseudo<
1414 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1415 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1416 def ATOMIC_LOAD_OR_I8 : Pseudo<
1417 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1418 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1419 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1420 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1421 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1422 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1423 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1424 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1425 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1426 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1427 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1428 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1429 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1430 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1431 def ATOMIC_LOAD_AND_I16 : Pseudo<
1432 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1433 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1434 def ATOMIC_LOAD_OR_I16 : Pseudo<
1435 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1436 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1437 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1438 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1439 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1440 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1441 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1442 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1443 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1444 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1445 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1446 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1447 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1448 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1449 def ATOMIC_LOAD_AND_I32 : Pseudo<
1450 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1451 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1452 def ATOMIC_LOAD_OR_I32 : Pseudo<
1453 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1454 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1455 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1456 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1457 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1458 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1459 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1460 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1462 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1463 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1464 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1465 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1466 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1467 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1468 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1469 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1470 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1472 def ATOMIC_SWAP_I8 : Pseudo<
1473 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1474 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1475 def ATOMIC_SWAP_I16 : Pseudo<
1476 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1477 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1478 def ATOMIC_SWAP_I32 : Pseudo<
1479 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1480 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1484 // Instructions to support atomic operations
1485 let mayLoad = 1, hasSideEffects = 0 in {
1486 def LBARX : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
1487 "lbarx $rD, $src", IIC_LdStLWARX, []>,
1488 Requires<[HasPartwordAtomics]>;
1490 def LHARX : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src),
1491 "lharx $rD, $src", IIC_LdStLWARX, []>,
1492 Requires<[HasPartwordAtomics]>;
1494 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1495 "lwarx $rD, $src", IIC_LdStLWARX, []>;
1497 // Instructions to support lock versions of atomics
1498 // (EH=1 - see Power ISA 2.07 Book II 4.4.2)
1499 def LBARXL : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
1500 "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1501 Requires<[HasPartwordAtomics]>;
1503 def LHARXL : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src),
1504 "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1505 Requires<[HasPartwordAtomics]>;
1507 def LWARXL : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1508 "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
1511 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {
1512 def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
1513 "stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
1514 isDOT, Requires<[HasPartwordAtomics]>;
1516 def STHCX : XForm_1<31, 726, (outs), (ins gprc:$rS, memrr:$dst),
1517 "sthcx. $rS, $dst", IIC_LdStSTWCX, []>,
1518 isDOT, Requires<[HasPartwordAtomics]>;
1520 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1521 "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
1524 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1525 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1527 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1528 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1529 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1530 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1531 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1532 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1533 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1534 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1536 //===----------------------------------------------------------------------===//
1537 // PPC32 Load Instructions.
1540 // Unindexed (r+i) Loads.
1541 let PPC970_Unit = 2 in {
1542 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1543 "lbz $rD, $src", IIC_LdStLoad,
1544 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1545 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1546 "lha $rD, $src", IIC_LdStLHA,
1547 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1548 PPC970_DGroup_Cracked;
1549 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1550 "lhz $rD, $src", IIC_LdStLoad,
1551 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1552 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1553 "lwz $rD, $src", IIC_LdStLoad,
1554 [(set i32:$rD, (load iaddr:$src))]>;
1556 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1557 "lfs $rD, $src", IIC_LdStLFD,
1558 [(set f32:$rD, (load iaddr:$src))]>;
1559 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1560 "lfd $rD, $src", IIC_LdStLFD,
1561 [(set f64:$rD, (load iaddr:$src))]>;
1564 // Unindexed (r+i) Loads with Update (preinc).
1565 let mayLoad = 1, hasSideEffects = 0 in {
1566 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1567 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1568 []>, RegConstraint<"$addr.reg = $ea_result">,
1569 NoEncode<"$ea_result">;
1571 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1572 "lhau $rD, $addr", IIC_LdStLHAU,
1573 []>, RegConstraint<"$addr.reg = $ea_result">,
1574 NoEncode<"$ea_result">;
1576 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1577 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1578 []>, RegConstraint<"$addr.reg = $ea_result">,
1579 NoEncode<"$ea_result">;
1581 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1582 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1583 []>, RegConstraint<"$addr.reg = $ea_result">,
1584 NoEncode<"$ea_result">;
1586 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1587 "lfsu $rD, $addr", IIC_LdStLFDU,
1588 []>, RegConstraint<"$addr.reg = $ea_result">,
1589 NoEncode<"$ea_result">;
1591 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1592 "lfdu $rD, $addr", IIC_LdStLFDU,
1593 []>, RegConstraint<"$addr.reg = $ea_result">,
1594 NoEncode<"$ea_result">;
1597 // Indexed (r+r) Loads with Update (preinc).
1598 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1600 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1601 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1602 NoEncode<"$ea_result">;
1604 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1606 "lhaux $rD, $addr", IIC_LdStLHAUX,
1607 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1608 NoEncode<"$ea_result">;
1610 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1612 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1613 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1614 NoEncode<"$ea_result">;
1616 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1618 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1619 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1620 NoEncode<"$ea_result">;
1622 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1624 "lfsux $rD, $addr", IIC_LdStLFDUX,
1625 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1626 NoEncode<"$ea_result">;
1628 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1630 "lfdux $rD, $addr", IIC_LdStLFDUX,
1631 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1632 NoEncode<"$ea_result">;
1636 // Indexed (r+r) Loads.
1638 let PPC970_Unit = 2 in {
1639 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1640 "lbzx $rD, $src", IIC_LdStLoad,
1641 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1642 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1643 "lhax $rD, $src", IIC_LdStLHA,
1644 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1645 PPC970_DGroup_Cracked;
1646 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1647 "lhzx $rD, $src", IIC_LdStLoad,
1648 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1649 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1650 "lwzx $rD, $src", IIC_LdStLoad,
1651 [(set i32:$rD, (load xaddr:$src))]>;
1654 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1655 "lhbrx $rD, $src", IIC_LdStLoad,
1656 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1657 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1658 "lwbrx $rD, $src", IIC_LdStLoad,
1659 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1661 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1662 "lfsx $frD, $src", IIC_LdStLFD,
1663 [(set f32:$frD, (load xaddr:$src))]>;
1664 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1665 "lfdx $frD, $src", IIC_LdStLFD,
1666 [(set f64:$frD, (load xaddr:$src))]>;
1668 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1669 "lfiwax $frD, $src", IIC_LdStLFD,
1670 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1671 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1672 "lfiwzx $frD, $src", IIC_LdStLFD,
1673 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1677 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1678 "lmw $rD, $src", IIC_LdStLMW, []>;
1680 //===----------------------------------------------------------------------===//
1681 // PPC32 Store Instructions.
1684 // Unindexed (r+i) Stores.
1685 let PPC970_Unit = 2 in {
1686 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1687 "stb $rS, $src", IIC_LdStStore,
1688 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1689 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1690 "sth $rS, $src", IIC_LdStStore,
1691 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1692 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1693 "stw $rS, $src", IIC_LdStStore,
1694 [(store i32:$rS, iaddr:$src)]>;
1695 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1696 "stfs $rS, $dst", IIC_LdStSTFD,
1697 [(store f32:$rS, iaddr:$dst)]>;
1698 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1699 "stfd $rS, $dst", IIC_LdStSTFD,
1700 [(store f64:$rS, iaddr:$dst)]>;
1703 // Unindexed (r+i) Stores with Update (preinc).
1704 let PPC970_Unit = 2, mayStore = 1 in {
1705 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1706 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1707 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1708 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1709 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1710 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1711 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1712 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1713 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1714 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1715 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1716 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1717 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1718 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1719 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1722 // Patterns to match the pre-inc stores. We can't put the patterns on
1723 // the instruction definitions directly as ISel wants the address base
1724 // and offset to be separate operands, not a single complex operand.
1725 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1726 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1727 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1728 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1729 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1730 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1731 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1732 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1733 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1734 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1736 // Indexed (r+r) Stores.
1737 let PPC970_Unit = 2 in {
1738 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1739 "stbx $rS, $dst", IIC_LdStStore,
1740 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1741 PPC970_DGroup_Cracked;
1742 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1743 "sthx $rS, $dst", IIC_LdStStore,
1744 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1745 PPC970_DGroup_Cracked;
1746 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1747 "stwx $rS, $dst", IIC_LdStStore,
1748 [(store i32:$rS, xaddr:$dst)]>,
1749 PPC970_DGroup_Cracked;
1751 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1752 "sthbrx $rS, $dst", IIC_LdStStore,
1753 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1754 PPC970_DGroup_Cracked;
1755 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1756 "stwbrx $rS, $dst", IIC_LdStStore,
1757 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1758 PPC970_DGroup_Cracked;
1760 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1761 "stfiwx $frS, $dst", IIC_LdStSTFD,
1762 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1764 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1765 "stfsx $frS, $dst", IIC_LdStSTFD,
1766 [(store f32:$frS, xaddr:$dst)]>;
1767 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1768 "stfdx $frS, $dst", IIC_LdStSTFD,
1769 [(store f64:$frS, xaddr:$dst)]>;
1772 // Indexed (r+r) Stores with Update (preinc).
1773 let PPC970_Unit = 2, mayStore = 1 in {
1774 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1775 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1776 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1777 PPC970_DGroup_Cracked;
1778 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1779 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1780 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1781 PPC970_DGroup_Cracked;
1782 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1783 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1784 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1785 PPC970_DGroup_Cracked;
1786 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1787 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1788 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1789 PPC970_DGroup_Cracked;
1790 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1791 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1792 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1793 PPC970_DGroup_Cracked;
1796 // Patterns to match the pre-inc stores. We can't put the patterns on
1797 // the instruction definitions directly as ISel wants the address base
1798 // and offset to be separate operands, not a single complex operand.
1799 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1800 (STBUX $rS, $ptrreg, $ptroff)>;
1801 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1802 (STHUX $rS, $ptrreg, $ptroff)>;
1803 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1804 (STWUX $rS, $ptrreg, $ptroff)>;
1805 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1806 (STFSUX $rS, $ptrreg, $ptroff)>;
1807 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1808 (STFDUX $rS, $ptrreg, $ptroff)>;
1811 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1812 "stmw $rS, $dst", IIC_LdStLMW, []>;
1814 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1815 "sync $L", IIC_LdStSync, []>;
1817 let isCodeGenOnly = 1 in {
1818 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1819 "msync", IIC_LdStSync, []> {
1824 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>;
1825 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1826 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1827 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1829 //===----------------------------------------------------------------------===//
1830 // PPC32 Arithmetic Instructions.
1833 let PPC970_Unit = 1 in { // FXU Operations.
1834 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1835 "addi $rD, $rA, $imm", IIC_IntSimple,
1836 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1837 let BaseName = "addic" in {
1838 let Defs = [CARRY] in
1839 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1840 "addic $rD, $rA, $imm", IIC_IntGeneral,
1841 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1842 RecFormRel, PPC970_DGroup_Cracked;
1843 let Defs = [CARRY, CR0] in
1844 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1845 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1846 []>, isDOT, RecFormRel;
1848 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1849 "addis $rD, $rA, $imm", IIC_IntSimple,
1850 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1851 let isCodeGenOnly = 1 in
1852 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1853 "la $rD, $sym($rA)", IIC_IntGeneral,
1854 [(set i32:$rD, (add i32:$rA,
1855 (PPClo tglobaladdr:$sym, 0)))]>;
1856 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1857 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1858 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1859 let Defs = [CARRY] in
1860 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1861 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1862 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1864 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1865 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1866 "li $rD, $imm", IIC_IntSimple,
1867 [(set i32:$rD, imm32SExt16:$imm)]>;
1868 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1869 "lis $rD, $imm", IIC_IntSimple,
1870 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1874 let PPC970_Unit = 1 in { // FXU Operations.
1875 let Defs = [CR0] in {
1876 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1877 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1878 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1880 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1881 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1882 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1885 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1886 "ori $dst, $src1, $src2", IIC_IntSimple,
1887 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1888 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1889 "oris $dst, $src1, $src2", IIC_IntSimple,
1890 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1891 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1892 "xori $dst, $src1, $src2", IIC_IntSimple,
1893 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1894 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1895 "xoris $dst, $src1, $src2", IIC_IntSimple,
1896 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1898 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1900 let isCodeGenOnly = 1 in {
1901 // The POWER6 and POWER7 have special group-terminating nops.
1902 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1903 "ori 1, 1, 0", IIC_IntSimple, []>;
1904 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1905 "ori 2, 2, 0", IIC_IntSimple, []>;
1908 let isCompare = 1, hasSideEffects = 0 in {
1909 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1910 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1911 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1912 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1916 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
1917 let isCommutable = 1 in {
1918 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1919 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1920 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1921 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1922 "and", "$rA, $rS, $rB", IIC_IntSimple,
1923 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1925 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1926 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1927 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1928 let isCommutable = 1 in {
1929 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1930 "or", "$rA, $rS, $rB", IIC_IntSimple,
1931 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1932 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1933 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1934 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1936 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1937 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1938 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1939 let isCommutable = 1 in {
1940 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1941 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1942 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1943 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1944 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1945 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1947 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1948 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1949 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1950 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1951 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1952 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1953 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1954 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1955 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1958 let PPC970_Unit = 1 in { // FXU Operations.
1959 let hasSideEffects = 0 in {
1960 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1961 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1962 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1963 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1964 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1965 [(set i32:$rA, (ctlz i32:$rS))]>;
1966 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1967 "extsb", "$rA, $rS", IIC_IntSimple,
1968 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1969 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1970 "extsh", "$rA, $rS", IIC_IntSimple,
1971 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1973 let isCommutable = 1 in
1974 def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1975 "cmpb $rA, $rS, $rB", IIC_IntGeneral,
1976 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
1978 let isCompare = 1, hasSideEffects = 0 in {
1979 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1980 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1981 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1982 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1985 let PPC970_Unit = 3 in { // FPU Operations.
1986 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1987 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1988 let isCompare = 1, hasSideEffects = 0 in {
1989 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1990 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1991 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1992 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1993 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1996 let Uses = [RM] in {
1997 let hasSideEffects = 0 in {
1998 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1999 "fctiw", "$frD, $frB", IIC_FPGeneral,
2001 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
2002 "fctiwz", "$frD, $frB", IIC_FPGeneral,
2003 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
2005 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
2006 "frsp", "$frD, $frB", IIC_FPGeneral,
2007 [(set f32:$frD, (fround f64:$frB))]>;
2009 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2010 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
2011 "frin", "$frD, $frB", IIC_FPGeneral,
2012 [(set f64:$frD, (frnd f64:$frB))]>;
2013 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
2014 "frin", "$frD, $frB", IIC_FPGeneral,
2015 [(set f32:$frD, (frnd f32:$frB))]>;
2018 let hasSideEffects = 0 in {
2019 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2020 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
2021 "frip", "$frD, $frB", IIC_FPGeneral,
2022 [(set f64:$frD, (fceil f64:$frB))]>;
2023 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
2024 "frip", "$frD, $frB", IIC_FPGeneral,
2025 [(set f32:$frD, (fceil f32:$frB))]>;
2026 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2027 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
2028 "friz", "$frD, $frB", IIC_FPGeneral,
2029 [(set f64:$frD, (ftrunc f64:$frB))]>;
2030 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
2031 "friz", "$frD, $frB", IIC_FPGeneral,
2032 [(set f32:$frD, (ftrunc f32:$frB))]>;
2033 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2034 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
2035 "frim", "$frD, $frB", IIC_FPGeneral,
2036 [(set f64:$frD, (ffloor f64:$frB))]>;
2037 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
2038 "frim", "$frD, $frB", IIC_FPGeneral,
2039 [(set f32:$frD, (ffloor f32:$frB))]>;
2041 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
2042 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
2043 [(set f64:$frD, (fsqrt f64:$frB))]>;
2044 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
2045 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
2046 [(set f32:$frD, (fsqrt f32:$frB))]>;
2051 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
2052 /// often coalesced away and we don't want the dispatch group builder to think
2053 /// that they will fill slots (which could cause the load of a LSU reject to
2054 /// sneak into a d-group with a store).
2055 let hasSideEffects = 0 in
2056 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
2057 "fmr", "$frD, $frB", IIC_FPGeneral,
2058 []>, // (set f32:$frD, f32:$frB)
2061 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2062 // These are artificially split into two different forms, for 4/8 byte FP.
2063 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
2064 "fabs", "$frD, $frB", IIC_FPGeneral,
2065 [(set f32:$frD, (fabs f32:$frB))]>;
2066 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2067 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
2068 "fabs", "$frD, $frB", IIC_FPGeneral,
2069 [(set f64:$frD, (fabs f64:$frB))]>;
2070 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
2071 "fnabs", "$frD, $frB", IIC_FPGeneral,
2072 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
2073 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2074 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
2075 "fnabs", "$frD, $frB", IIC_FPGeneral,
2076 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
2077 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
2078 "fneg", "$frD, $frB", IIC_FPGeneral,
2079 [(set f32:$frD, (fneg f32:$frB))]>;
2080 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2081 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
2082 "fneg", "$frD, $frB", IIC_FPGeneral,
2083 [(set f64:$frD, (fneg f64:$frB))]>;
2085 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
2086 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2087 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
2088 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2089 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
2090 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2091 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
2093 // Reciprocal estimates.
2094 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
2095 "fre", "$frD, $frB", IIC_FPGeneral,
2096 [(set f64:$frD, (PPCfre f64:$frB))]>;
2097 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
2098 "fres", "$frD, $frB", IIC_FPGeneral,
2099 [(set f32:$frD, (PPCfre f32:$frB))]>;
2100 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
2101 "frsqrte", "$frD, $frB", IIC_FPGeneral,
2102 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2103 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2104 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2105 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2108 // XL-Form instructions. condition register logical ops.
2110 let hasSideEffects = 0 in
2111 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2112 "mcrf $BF, $BFA", IIC_BrMCR>,
2113 PPC970_DGroup_First, PPC970_Unit_CRU;
2115 // FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2116 // condition-register logical instructions have preferred forms. Specifically,
2117 // it is preferred that the bit specified by the BT field be in the same
2118 // condition register as that specified by the bit BB. We might want to account
2119 // for this via hinting the register allocator and anti-dep breakers, or we
2120 // could constrain the register class to force this constraint and then loosen
2121 // it during register allocation via convertToThreeAddress or some similar
2124 let isCommutable = 1 in {
2125 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
2126 (ins crbitrc:$CRA, crbitrc:$CRB),
2127 "crand $CRD, $CRA, $CRB", IIC_BrCR,
2128 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2130 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2131 (ins crbitrc:$CRA, crbitrc:$CRB),
2132 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2133 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2135 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
2136 (ins crbitrc:$CRA, crbitrc:$CRB),
2137 "cror $CRD, $CRA, $CRB", IIC_BrCR,
2138 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2140 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
2141 (ins crbitrc:$CRA, crbitrc:$CRB),
2142 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2143 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2145 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
2146 (ins crbitrc:$CRA, crbitrc:$CRB),
2147 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2148 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2150 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
2151 (ins crbitrc:$CRA, crbitrc:$CRB),
2152 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2153 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2156 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2157 (ins crbitrc:$CRA, crbitrc:$CRB),
2158 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2159 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2161 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
2162 (ins crbitrc:$CRA, crbitrc:$CRB),
2163 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2164 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2166 let isCodeGenOnly = 1 in {
2167 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2168 "creqv $dst, $dst, $dst", IIC_BrCR,
2169 [(set i1:$dst, 1)]>;
2171 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2172 "crxor $dst, $dst, $dst", IIC_BrCR,
2173 [(set i1:$dst, 0)]>;
2175 let Defs = [CR1EQ], CRD = 6 in {
2176 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2177 "creqv 6, 6, 6", IIC_BrCR,
2180 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2181 "crxor 6, 6, 6", IIC_BrCR,
2186 // XFX-Form instructions. Instructions that deal with SPRs.
2189 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2190 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2191 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2192 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2194 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2195 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2197 // A pseudo-instruction used to implement the read of the 64-bit cycle counter
2198 // on a 32-bit target.
2199 let hasSideEffects = 1, usesCustomInserter = 1 in
2200 def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2203 let Uses = [CTR] in {
2204 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2205 "mfctr $rT", IIC_SprMFSPR>,
2206 PPC970_DGroup_First, PPC970_Unit_FXU;
2208 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2209 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2210 "mtctr $rS", IIC_SprMTSPR>,
2211 PPC970_DGroup_First, PPC970_Unit_FXU;
2213 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2214 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2215 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2216 "mtctr $rS", IIC_SprMTSPR>,
2217 PPC970_DGroup_First, PPC970_Unit_FXU;
2220 let Defs = [LR] in {
2221 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2222 "mtlr $rS", IIC_SprMTSPR>,
2223 PPC970_DGroup_First, PPC970_Unit_FXU;
2225 let Uses = [LR] in {
2226 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2227 "mflr $rT", IIC_SprMFSPR>,
2228 PPC970_DGroup_First, PPC970_Unit_FXU;
2231 let isCodeGenOnly = 1 in {
2232 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2233 // like a GPR on the PPC970. As such, copies in and out have the same
2234 // performance characteristics as an OR instruction.
2235 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2236 "mtspr 256, $rS", IIC_IntGeneral>,
2237 PPC970_DGroup_Single, PPC970_Unit_FXU;
2238 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2239 "mfspr $rT, 256", IIC_IntGeneral>,
2240 PPC970_DGroup_First, PPC970_Unit_FXU;
2242 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2243 (outs VRSAVERC:$reg), (ins gprc:$rS),
2244 "mtspr 256, $rS", IIC_IntGeneral>,
2245 PPC970_DGroup_Single, PPC970_Unit_FXU;
2246 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2247 (ins VRSAVERC:$reg),
2248 "mfspr $rT, 256", IIC_IntGeneral>,
2249 PPC970_DGroup_First, PPC970_Unit_FXU;
2252 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2253 // so we'll need to scavenge a register for it.
2255 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2256 "#SPILL_VRSAVE", []>;
2258 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2259 // spilled), so we'll need to scavenge a register for it.
2261 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2262 "#RESTORE_VRSAVE", []>;
2264 let hasSideEffects = 0 in {
2265 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2266 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2267 PPC970_DGroup_First, PPC970_Unit_CRU;
2269 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2270 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2271 PPC970_MicroCode, PPC970_Unit_CRU;
2273 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2274 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2275 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2276 PPC970_DGroup_First, PPC970_Unit_CRU;
2278 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2279 "mfcr $rT", IIC_SprMFCR>,
2280 PPC970_MicroCode, PPC970_Unit_CRU;
2281 } // hasSideEffects = 0
2283 // Pseudo instruction to perform FADD in round-to-zero mode.
2284 let usesCustomInserter = 1, Uses = [RM] in {
2285 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2286 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2289 // The above pseudo gets expanded to make use of the following instructions
2290 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2291 let Uses = [RM], Defs = [RM] in {
2292 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2293 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2294 PPC970_DGroup_Single, PPC970_Unit_FPU;
2295 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2296 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2297 PPC970_DGroup_Single, PPC970_Unit_FPU;
2298 let isCodeGenOnly = 1 in
2299 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2300 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2301 PPC970_DGroup_Single, PPC970_Unit_FPU;
2303 let Uses = [RM] in {
2304 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2305 "mffs $rT", IIC_IntMFFS,
2306 [(set f64:$rT, (PPCmffs))]>,
2307 PPC970_DGroup_Single, PPC970_Unit_FPU;
2310 def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2311 "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2315 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
2316 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2317 let isCommutable = 1 in
2318 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2319 "add", "$rT, $rA, $rB", IIC_IntSimple,
2320 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2321 let isCodeGenOnly = 1 in
2322 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2323 "add $rT, $rA, $rB", IIC_IntSimple,
2324 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2325 let isCommutable = 1 in
2326 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2327 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2328 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2329 PPC970_DGroup_Cracked;
2331 defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2332 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2333 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>;
2334 defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2335 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2336 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>;
2337 def DIVWE : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2338 "divwe $rT, $rA, $rB", IIC_IntDivW,
2339 [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>,
2340 Requires<[HasExtDiv]>;
2342 def DIVWEo : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2343 "divwe. $rT, $rA, $rB", IIC_IntDivW,
2344 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2345 Requires<[HasExtDiv]>;
2346 def DIVWEU : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2347 "divweu $rT, $rA, $rB", IIC_IntDivW,
2348 [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>,
2349 Requires<[HasExtDiv]>;
2351 def DIVWEUo : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2352 "divweu. $rT, $rA, $rB", IIC_IntDivW,
2353 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2354 Requires<[HasExtDiv]>;
2355 let isCommutable = 1 in {
2356 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2357 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2358 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2359 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2360 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2361 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2362 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2363 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2364 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2366 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2367 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2368 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2369 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2370 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2371 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2372 PPC970_DGroup_Cracked;
2373 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2374 "neg", "$rT, $rA", IIC_IntSimple,
2375 [(set i32:$rT, (ineg i32:$rA))]>;
2376 let Uses = [CARRY] in {
2377 let isCommutable = 1 in
2378 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2379 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2380 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2381 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2382 "addme", "$rT, $rA", IIC_IntGeneral,
2383 [(set i32:$rT, (adde i32:$rA, -1))]>;
2384 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2385 "addze", "$rT, $rA", IIC_IntGeneral,
2386 [(set i32:$rT, (adde i32:$rA, 0))]>;
2387 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2388 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2389 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2390 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2391 "subfme", "$rT, $rA", IIC_IntGeneral,
2392 [(set i32:$rT, (sube -1, i32:$rA))]>;
2393 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2394 "subfze", "$rT, $rA", IIC_IntGeneral,
2395 [(set i32:$rT, (sube 0, i32:$rA))]>;
2399 // A-Form instructions. Most of the instructions executed in the FPU are of
2402 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2403 let Uses = [RM] in {
2404 let isCommutable = 1 in {
2405 defm FMADD : AForm_1r<63, 29,
2406 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2407 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2408 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2409 defm FMADDS : AForm_1r<59, 29,
2410 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2411 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2412 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2413 defm FMSUB : AForm_1r<63, 28,
2414 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2415 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2417 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2418 defm FMSUBS : AForm_1r<59, 28,
2419 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2420 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2422 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2423 defm FNMADD : AForm_1r<63, 31,
2424 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2425 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2427 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2428 defm FNMADDS : AForm_1r<59, 31,
2429 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2430 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2432 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2433 defm FNMSUB : AForm_1r<63, 30,
2434 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2435 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2436 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2437 (fneg f64:$FRB))))]>;
2438 defm FNMSUBS : AForm_1r<59, 30,
2439 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2440 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2441 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2442 (fneg f32:$FRB))))]>;
2445 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2446 // having 4 of these, force the comparison to always be an 8-byte double (code
2447 // should use an FMRSD if the input comparison value really wants to be a float)
2448 // and 4/8 byte forms for the result and operand type..
2449 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2450 defm FSELD : AForm_1r<63, 23,
2451 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2452 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2453 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2454 defm FSELS : AForm_1r<63, 23,
2455 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2456 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2457 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2458 let Uses = [RM] in {
2459 let isCommutable = 1 in {
2460 defm FADD : AForm_2r<63, 21,
2461 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2462 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2463 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2464 defm FADDS : AForm_2r<59, 21,
2465 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2466 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2467 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2469 defm FDIV : AForm_2r<63, 18,
2470 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2471 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2472 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2473 defm FDIVS : AForm_2r<59, 18,
2474 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2475 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2476 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2477 let isCommutable = 1 in {
2478 defm FMUL : AForm_3r<63, 25,
2479 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2480 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2481 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2482 defm FMULS : AForm_3r<59, 25,
2483 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2484 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2485 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2487 defm FSUB : AForm_2r<63, 20,
2488 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2489 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2490 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2491 defm FSUBS : AForm_2r<59, 20,
2492 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2493 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2494 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2498 let hasSideEffects = 0 in {
2499 let PPC970_Unit = 1 in { // FXU Operations.
2501 def ISEL : AForm_4<31, 15,
2502 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2503 "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
2507 let PPC970_Unit = 1 in { // FXU Operations.
2508 // M-Form instructions. rotate and mask instructions.
2510 let isCommutable = 1 in {
2511 // RLWIMI can be commuted if the rotate amount is zero.
2512 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2513 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2514 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2515 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2516 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2518 let BaseName = "rlwinm" in {
2519 def RLWINM : MForm_2<21,
2520 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2521 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2524 def RLWINMo : MForm_2<21,
2525 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2526 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2527 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2529 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2530 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2531 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2534 } // hasSideEffects = 0
2536 //===----------------------------------------------------------------------===//
2537 // PowerPC Instruction Patterns
2540 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2541 def : Pat<(i32 imm:$imm),
2542 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2544 // Implement the 'not' operation with the NOR instruction.
2545 def i32not : OutPatFrag<(ops node:$in),
2547 def : Pat<(not i32:$in),
2550 // ADD an arbitrary immediate.
2551 def : Pat<(add i32:$in, imm:$imm),
2552 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2553 // OR an arbitrary immediate.
2554 def : Pat<(or i32:$in, imm:$imm),
2555 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2556 // XOR an arbitrary immediate.
2557 def : Pat<(xor i32:$in, imm:$imm),
2558 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2560 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2561 (SUBFIC $in, imm:$imm)>;
2564 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2565 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2566 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2567 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2570 def : Pat<(rotl i32:$in, i32:$sh),
2571 (RLWNM $in, $sh, 0, 31)>;
2572 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2573 (RLWINM $in, imm:$imm, 0, 31)>;
2576 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2577 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2580 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2581 (BL tglobaladdr:$dst)>;
2582 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2583 (BL texternalsym:$dst)>;
2585 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2586 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2588 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2589 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2591 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2592 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2596 // Hi and Lo for Darwin Global Addresses.
2597 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2598 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2599 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2600 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2601 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2602 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2603 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2604 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2605 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2606 (ADDIS $in, tglobaltlsaddr:$g)>;
2607 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2608 (ADDI $in, tglobaltlsaddr:$g)>;
2609 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2610 (ADDIS $in, tglobaladdr:$g)>;
2611 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2612 (ADDIS $in, tconstpool:$g)>;
2613 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2614 (ADDIS $in, tjumptable:$g)>;
2615 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2616 (ADDIS $in, tblockaddress:$g)>;
2618 // Support for thread-local storage.
2619 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2620 [(set i32:$rD, (PPCppc32GOT))]>;
2622 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2623 // This uses two output registers, the first as the real output, the second as a
2624 // temporary register, used internally in code generation.
2625 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2626 []>, NoEncode<"$rT">;
2628 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2631 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2632 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2633 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2635 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2638 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2639 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2640 // explicitly defined when this op is created, so not mentioned here.
2641 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2642 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2643 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2646 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2647 // Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR
2648 // are true defines while the rest of the Defs are clobbers.
2649 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2650 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2651 def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2652 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2653 "#ADDItlsgdLADDR32",
2655 (PPCaddiTlsgdLAddr i32:$reg,
2656 tglobaltlsaddr:$disp,
2657 tglobaltlsaddr:$sym))]>;
2658 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2661 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2662 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2663 // explicitly defined when this op is created, so not mentioned here.
2664 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2665 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2666 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2669 (PPCgetTlsldAddr i32:$reg,
2670 tglobaltlsaddr:$sym))]>;
2671 // Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR
2672 // are true defines while the rest of the Defs are clobbers.
2673 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2674 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2675 def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2676 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2677 "#ADDItlsldLADDR32",
2679 (PPCaddiTlsldLAddr i32:$reg,
2680 tglobaltlsaddr:$disp,
2681 tglobaltlsaddr:$sym))]>;
2682 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2685 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2686 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2689 (PPCaddisDtprelHA i32:$reg,
2690 tglobaltlsaddr:$disp))]>;
2692 // Support for Position-independent code
2693 def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2696 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2697 // Get Global (GOT) Base Register offset, from the word immediately preceding
2698 // the function label.
2699 def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2702 // Standard shifts. These are represented separately from the real shifts above
2703 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2705 def : Pat<(sra i32:$rS, i32:$rB),
2707 def : Pat<(srl i32:$rS, i32:$rB),
2709 def : Pat<(shl i32:$rS, i32:$rB),
2712 def : Pat<(zextloadi1 iaddr:$src),
2714 def : Pat<(zextloadi1 xaddr:$src),
2716 def : Pat<(extloadi1 iaddr:$src),
2718 def : Pat<(extloadi1 xaddr:$src),
2720 def : Pat<(extloadi8 iaddr:$src),
2722 def : Pat<(extloadi8 xaddr:$src),
2724 def : Pat<(extloadi16 iaddr:$src),
2726 def : Pat<(extloadi16 xaddr:$src),
2728 def : Pat<(f64 (extloadf32 iaddr:$src)),
2729 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2730 def : Pat<(f64 (extloadf32 xaddr:$src)),
2731 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2733 def : Pat<(f64 (fextend f32:$src)),
2734 (COPY_TO_REGCLASS $src, F8RC)>;
2736 // Only seq_cst fences require the heavyweight sync (SYNC 0).
2737 // All others can use the lightweight sync (SYNC 1).
2738 // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2739 // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2740 // versions of Power.
2741 def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2742 def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2743 def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2744 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2746 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2747 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2748 (FNMSUB $A, $C, $B)>;
2749 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2750 (FNMSUB $A, $C, $B)>;
2751 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2752 (FNMSUBS $A, $C, $B)>;
2753 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2754 (FNMSUBS $A, $C, $B)>;
2756 // FCOPYSIGN's operand types need not agree.
2757 def : Pat<(fcopysign f64:$frB, f32:$frA),
2758 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2759 def : Pat<(fcopysign f32:$frB, f64:$frA),
2760 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2762 include "PPCInstrAltivec.td"
2763 include "PPCInstrSPE.td"
2764 include "PPCInstr64Bit.td"
2765 include "PPCInstrVSX.td"
2766 include "PPCInstrQPX.td"
2767 include "PPCInstrHTM.td"
2769 def crnot : OutPatFrag<(ops node:$in),
2771 def : Pat<(not i1:$in),
2774 // Patterns for arithmetic i1 operations.
2775 def : Pat<(add i1:$a, i1:$b),
2777 def : Pat<(sub i1:$a, i1:$b),
2779 def : Pat<(mul i1:$a, i1:$b),
2782 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2783 // (-1 is used to mean all bits set).
2784 def : Pat<(i1 -1), (CRSET)>;
2786 // i1 extensions, implemented in terms of isel.
2787 def : Pat<(i32 (zext i1:$in)),
2788 (SELECT_I4 $in, (LI 1), (LI 0))>;
2789 def : Pat<(i32 (sext i1:$in)),
2790 (SELECT_I4 $in, (LI -1), (LI 0))>;
2792 def : Pat<(i64 (zext i1:$in)),
2793 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2794 def : Pat<(i64 (sext i1:$in)),
2795 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2797 // FIXME: We should choose either a zext or a sext based on other constants
2799 def : Pat<(i32 (anyext i1:$in)),
2800 (SELECT_I4 $in, (LI 1), (LI 0))>;
2801 def : Pat<(i64 (anyext i1:$in)),
2802 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2804 // match setcc on i1 variables.
2805 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2807 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2809 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2811 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2813 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2815 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2817 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2819 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2821 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2823 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2826 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2827 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2828 // floating-point types.
2830 multiclass CRNotPat<dag pattern, dag result> {
2831 def : Pat<pattern, (crnot result)>;
2832 def : Pat<(not pattern), result>;
2834 // We can also fold the crnot into an extension:
2835 def : Pat<(i32 (zext pattern)),
2836 (SELECT_I4 result, (LI 0), (LI 1))>;
2837 def : Pat<(i32 (sext pattern)),
2838 (SELECT_I4 result, (LI 0), (LI -1))>;
2840 // We can also fold the crnot into an extension:
2841 def : Pat<(i64 (zext pattern)),
2842 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2843 def : Pat<(i64 (sext pattern)),
2844 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2846 // FIXME: We should choose either a zext or a sext based on other constants
2848 def : Pat<(i32 (anyext pattern)),
2849 (SELECT_I4 result, (LI 0), (LI 1))>;
2851 def : Pat<(i64 (anyext pattern)),
2852 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2855 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2856 // we need to write imm:$imm in the output patterns below, not just $imm, or
2857 // else the resulting matcher will not correctly add the immediate operand
2858 // (making it a register operand instead).
2861 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2862 OutPatFrag rfrag, OutPatFrag rfrag8> {
2863 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2865 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2867 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2868 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2869 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2870 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2872 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2874 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2876 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2877 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2878 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2879 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2882 // Note that we do all inversions below with i(32|64)not, instead of using
2883 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2884 // has 2-cycle latency.
2886 defm : ExtSetCCPat<SETEQ,
2887 PatFrag<(ops node:$in, node:$cc),
2888 (setcc $in, 0, $cc)>,
2889 OutPatFrag<(ops node:$in),
2890 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2891 OutPatFrag<(ops node:$in),
2892 (RLDICL (CNTLZD $in), 58, 63)> >;
2894 defm : ExtSetCCPat<SETNE,
2895 PatFrag<(ops node:$in, node:$cc),
2896 (setcc $in, 0, $cc)>,
2897 OutPatFrag<(ops node:$in),
2898 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2899 OutPatFrag<(ops node:$in),
2900 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2902 defm : ExtSetCCPat<SETLT,
2903 PatFrag<(ops node:$in, node:$cc),
2904 (setcc $in, 0, $cc)>,
2905 OutPatFrag<(ops node:$in),
2906 (RLWINM $in, 1, 31, 31)>,
2907 OutPatFrag<(ops node:$in),
2908 (RLDICL $in, 1, 63)> >;
2910 defm : ExtSetCCPat<SETGE,
2911 PatFrag<(ops node:$in, node:$cc),
2912 (setcc $in, 0, $cc)>,
2913 OutPatFrag<(ops node:$in),
2914 (RLWINM (i32not $in), 1, 31, 31)>,
2915 OutPatFrag<(ops node:$in),
2916 (RLDICL (i64not $in), 1, 63)> >;
2918 defm : ExtSetCCPat<SETGT,
2919 PatFrag<(ops node:$in, node:$cc),
2920 (setcc $in, 0, $cc)>,
2921 OutPatFrag<(ops node:$in),
2922 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2923 OutPatFrag<(ops node:$in),
2924 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2926 defm : ExtSetCCPat<SETLE,
2927 PatFrag<(ops node:$in, node:$cc),
2928 (setcc $in, 0, $cc)>,
2929 OutPatFrag<(ops node:$in),
2930 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2931 OutPatFrag<(ops node:$in),
2932 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2934 defm : ExtSetCCPat<SETLT,
2935 PatFrag<(ops node:$in, node:$cc),
2936 (setcc $in, -1, $cc)>,
2937 OutPatFrag<(ops node:$in),
2938 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2939 OutPatFrag<(ops node:$in),
2940 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2942 defm : ExtSetCCPat<SETGE,
2943 PatFrag<(ops node:$in, node:$cc),
2944 (setcc $in, -1, $cc)>,
2945 OutPatFrag<(ops node:$in),
2946 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2947 OutPatFrag<(ops node:$in),
2948 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2950 defm : ExtSetCCPat<SETGT,
2951 PatFrag<(ops node:$in, node:$cc),
2952 (setcc $in, -1, $cc)>,
2953 OutPatFrag<(ops node:$in),
2954 (RLWINM (i32not $in), 1, 31, 31)>,
2955 OutPatFrag<(ops node:$in),
2956 (RLDICL (i64not $in), 1, 63)> >;
2958 defm : ExtSetCCPat<SETLE,
2959 PatFrag<(ops node:$in, node:$cc),
2960 (setcc $in, -1, $cc)>,
2961 OutPatFrag<(ops node:$in),
2962 (RLWINM $in, 1, 31, 31)>,
2963 OutPatFrag<(ops node:$in),
2964 (RLDICL $in, 1, 63)> >;
2967 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2968 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2969 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2970 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2971 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2972 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2973 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2974 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2975 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2976 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2977 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2978 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2980 // For non-equality comparisons, the default code would materialize the
2981 // constant, then compare against it, like this:
2983 // ori r2, r2, 22136
2986 // Since we are just comparing for equality, we can emit this instead:
2987 // xoris r0,r3,0x1234
2988 // cmplwi cr0,r0,0x5678
2991 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2992 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2993 (LO16 imm:$imm)), sub_eq)>;
2995 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2996 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2997 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2998 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2999 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
3000 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3001 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
3002 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3003 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
3004 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3005 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
3006 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3008 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
3009 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3010 (LO16 imm:$imm)), sub_eq)>;
3012 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3013 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3014 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3015 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3016 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3017 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3018 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
3019 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3020 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3021 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3023 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3024 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3025 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
3026 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3027 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
3028 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3029 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
3030 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3031 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
3032 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3035 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3036 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3037 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3038 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3039 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3040 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3041 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
3042 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3043 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3044 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3045 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3046 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3048 // For non-equality comparisons, the default code would materialize the
3049 // constant, then compare against it, like this:
3051 // ori r2, r2, 22136
3054 // Since we are just comparing for equality, we can emit this instead:
3055 // xoris r0,r3,0x1234
3056 // cmpldi cr0,r0,0x5678
3059 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
3060 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3061 (LO16 imm:$imm)), sub_eq)>;
3063 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3064 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3065 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
3066 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3067 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3068 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3069 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
3070 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3071 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
3072 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3073 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3074 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3076 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3077 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3078 (LO16 imm:$imm)), sub_eq)>;
3080 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3081 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3082 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3083 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3084 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3085 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3086 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3087 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3088 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3089 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3091 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3092 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3093 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3094 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3095 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3096 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3097 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
3098 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3099 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3100 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3103 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3104 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3105 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3106 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3107 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3108 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3109 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3110 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3111 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3112 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3113 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3114 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3115 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
3116 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3118 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3119 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3120 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3121 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3122 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3123 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3124 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3125 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3126 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3127 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3128 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3129 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3130 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3131 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3134 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3135 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3136 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3137 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3138 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3139 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3140 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3141 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3142 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3143 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3144 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3145 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3146 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3147 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3149 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3150 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3151 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3152 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3153 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3154 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3155 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3156 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3157 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3158 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3159 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3160 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3161 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3162 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3164 // match select on i1 variables:
3165 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3166 (CROR (CRAND $cond , $tval),
3167 (CRAND (crnot $cond), $fval))>;
3169 // match selectcc on i1 variables:
3170 // select (lhs == rhs), tval, fval is:
3171 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3172 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3173 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3174 (CRAND (CRORC $lhs, $rhs), $fval))>;
3175 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3176 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
3177 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3178 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3179 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3180 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3181 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3182 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
3183 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3184 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3185 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3186 (CRAND (CRORC $rhs, $lhs), $fval))>;
3187 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3188 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3189 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3191 // match selectcc on i1 variables with non-i1 output.
3192 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3193 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3194 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3195 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3196 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3197 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3198 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3199 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3200 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3201 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3202 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3203 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3205 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3206 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3207 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3208 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3209 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3210 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3211 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3212 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3213 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3214 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3215 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3216 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3218 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3219 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3220 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3221 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3222 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3223 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3224 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3225 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3226 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3227 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3228 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3229 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3231 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3232 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3233 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3234 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3235 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3236 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3237 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3238 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3239 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3240 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3241 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3242 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3244 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3245 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3246 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3247 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3248 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3249 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3250 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3251 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3252 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3253 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3254 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3255 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3257 let usesCustomInserter = 1 in {
3258 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3260 [(set i1:$dst, (trunc (not i32:$in)))]>;
3261 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3263 [(set i1:$dst, (trunc i32:$in))]>;
3265 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3267 [(set i1:$dst, (trunc (not i64:$in)))]>;
3268 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3270 [(set i1:$dst, (trunc i64:$in))]>;
3273 def : Pat<(i1 (not (trunc i32:$in))),
3274 (ANDIo_1_EQ_BIT $in)>;
3275 def : Pat<(i1 (not (trunc i64:$in))),
3276 (ANDIo_1_EQ_BIT8 $in)>;
3278 //===----------------------------------------------------------------------===//
3279 // PowerPC Instructions used for assembler/disassembler only
3282 // FIXME: For B=0 or B > 8, the registers following RT are used.
3283 // WARNING: Do not add patterns for this instruction without fixing this.
3284 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3285 "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3287 // FIXME: For B=0 or B > 8, the registers following RT are used.
3288 // WARNING: Do not add patterns for this instruction without fixing this.
3289 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3290 "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3292 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3293 "isync", IIC_SprISYNC, []>;
3295 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3296 "icbi $src", IIC_LdStICBI, []>;
3298 // We used to have EIEIO as value but E[0-9A-Z] is a reserved name
3299 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3300 "eieio", IIC_LdStLoad, []>;
3302 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3303 "wait $L", IIC_LdStLoad, []>;
3305 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3306 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3308 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3309 "mtsr $SR, $RS", IIC_SprMTSR>;
3311 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3312 "mfsr $RS, $SR", IIC_SprMFSR>;
3314 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3315 "mtsrin $RS, $RB", IIC_SprMTSR>;
3317 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3318 "mfsrin $RS, $RB", IIC_SprMFSR>;
3320 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3321 "mtmsr $RS, $L", IIC_SprMTMSR>;
3323 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3324 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3328 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3329 Requires<[IsBookE]> {
3333 let Inst{21-30} = 163;
3336 def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3337 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3338 def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3339 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3341 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3342 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3343 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3344 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3346 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3347 "mfmsr $RT", IIC_SprMFMSR, []>;
3349 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3350 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3352 def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
3353 "mcrfs $BF, $BFA", IIC_BrMCR>;
3355 def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3356 "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
3358 def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3359 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
3361 def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
3362 def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
3364 def MTFSF : XFLForm_1<63, 711, (outs),
3365 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3366 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
3367 def MTFSFo : XFLForm_1<63, 711, (outs),
3368 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3369 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
3371 def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3372 def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3374 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3375 "slbie $RB", IIC_SprSLBIE, []>;
3377 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3378 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3380 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3381 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3383 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3385 def TLBIA : XForm_0<31, 370, (outs), (ins),
3386 "tlbia", IIC_SprTLBIA, []>;
3388 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3389 "tlbsync", IIC_SprTLBSYNC, []>;
3391 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3392 "tlbiel $RB", IIC_SprTLBIEL, []>;
3394 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3395 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3396 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3397 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3399 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3400 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3402 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3403 IIC_LdStLoad>, Requires<[IsBookE]>;
3405 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3406 IIC_LdStLoad>, Requires<[IsBookE]>;
3408 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3409 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3411 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3412 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3414 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3415 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3417 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3418 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3420 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3421 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3422 Requires<[IsPPC4xx]>;
3423 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3424 (ins gprc:$RST, gprc:$A, gprc:$B),
3425 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3426 Requires<[IsPPC4xx]>, isDOT;
3428 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3430 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3431 Requires<[IsBookE]>;
3432 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3433 Requires<[IsBookE]>;
3435 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3437 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3440 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3441 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3442 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3443 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3445 def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3447 def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3448 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3449 def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3450 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3451 def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3452 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3453 def LDCIX : XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3454 "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3456 def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3457 "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3458 def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3459 "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3460 def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3461 "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3462 def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3463 "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3465 //===----------------------------------------------------------------------===//
3466 // PowerPC Assembler Instruction Aliases
3469 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3470 // These are aliases that require C++ handling to convert to the target
3471 // instruction, while InstAliases can be handled directly by tblgen.
3472 class PPCAsmPseudo<string asm, dag iops>
3474 let Namespace = "PPC";
3475 bit PPC64 = 0; // Default value, override with isPPC64
3477 let OutOperandList = (outs);
3478 let InOperandList = iops;
3480 let AsmString = asm;
3481 let isAsmParserOnly = 1;
3485 def : InstAlias<"sc", (SC 0)>;
3487 def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3488 def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>;
3489 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3490 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3492 def : InstAlias<"wait", (WAIT 0)>;
3493 def : InstAlias<"waitrsv", (WAIT 1)>;
3494 def : InstAlias<"waitimpl", (WAIT 2)>;
3496 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3498 def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>;
3499 def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>;
3501 def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3502 def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3503 def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>;
3505 def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3506 def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3507 def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>;
3509 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3510 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3511 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3512 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3514 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3515 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3517 def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3518 def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3520 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3521 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3523 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3524 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3526 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3527 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3529 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3530 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3532 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3533 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3535 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3536 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3538 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3539 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3541 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3542 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3544 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3545 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3547 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3548 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3550 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3551 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3553 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3554 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3556 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3557 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3558 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3560 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3561 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3563 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3564 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3565 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3566 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3568 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3570 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3571 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3573 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3574 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3576 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3578 foreach BATR = 0-3 in {
3579 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3580 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3581 Requires<[IsPPC6xx]>;
3582 def : InstAlias<"mfdbatu $Rx, "#BATR,
3583 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3584 Requires<[IsPPC6xx]>;
3585 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3586 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3587 Requires<[IsPPC6xx]>;
3588 def : InstAlias<"mfdbatl $Rx, "#BATR,
3589 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3590 Requires<[IsPPC6xx]>;
3591 def : InstAlias<"mtibatu "#BATR#", $Rx",
3592 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3593 Requires<[IsPPC6xx]>;
3594 def : InstAlias<"mfibatu $Rx, "#BATR,
3595 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3596 Requires<[IsPPC6xx]>;
3597 def : InstAlias<"mtibatl "#BATR#", $Rx",
3598 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3599 Requires<[IsPPC6xx]>;
3600 def : InstAlias<"mfibatl $Rx, "#BATR,
3601 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3602 Requires<[IsPPC6xx]>;
3605 foreach BR = 0-7 in {
3606 def : InstAlias<"mfbr"#BR#" $Rx",
3607 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3608 Requires<[IsPPC4xx]>;
3609 def : InstAlias<"mtbr"#BR#" $Rx",
3610 (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3611 Requires<[IsPPC4xx]>;
3614 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3615 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3617 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3618 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3620 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3621 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3623 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3624 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3626 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3627 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3629 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3630 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3632 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3634 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3635 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3636 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3637 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3638 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3639 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3640 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3641 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3643 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3644 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3645 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3646 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3648 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3649 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3651 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3652 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3654 foreach SPRG = 0-3 in {
3655 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3656 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3657 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3658 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3660 foreach SPRG = 4-7 in {
3661 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3662 Requires<[IsBookE]>;
3663 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3664 Requires<[IsBookE]>;
3665 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3666 Requires<[IsBookE]>;
3667 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3668 Requires<[IsBookE]>;
3671 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3673 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3674 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3676 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3678 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3679 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3681 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3682 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3683 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3684 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3686 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3688 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3689 Requires<[IsPPC4xx]>;
3690 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3691 Requires<[IsPPC4xx]>;
3692 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3693 Requires<[IsPPC4xx]>;
3694 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3695 Requires<[IsPPC4xx]>;
3697 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3698 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3699 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3700 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3701 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3702 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3703 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3704 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3705 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3706 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3707 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3708 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3709 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3710 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3711 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3712 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3713 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3714 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3715 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3716 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3717 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3718 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3719 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3720 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3721 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3722 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3723 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3724 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3725 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3726 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3727 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3728 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3729 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3730 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3731 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3732 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3734 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3735 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3736 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3737 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3738 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3739 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3741 def : InstAlias<"cntlz $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
3742 def : InstAlias<"cntlz. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
3744 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3745 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3746 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3747 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3748 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3749 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3750 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3751 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3752 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3753 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3754 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3755 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3756 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3757 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3758 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3759 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3760 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3761 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3762 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3763 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3764 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3765 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3766 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3767 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3768 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3769 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3770 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3771 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3772 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3773 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3774 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3775 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3777 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3778 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3779 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3780 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3781 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3782 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3784 def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",
3785 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3786 def RLWINMobm : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b",
3787 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3788 def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b",
3789 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3790 def RLWIMIobm : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",
3791 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3792 def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b",
3793 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3794 def RLWNMobm : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
3795 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3797 // These generic branch instruction forms are used for the assembler parser only.
3798 // Defs and Uses are conservative, since we don't know the BO value.
3799 let PPC970_Unit = 7 in {
3800 let Defs = [CTR], Uses = [CTR, RM] in {
3801 def gBC : BForm_3<16, 0, 0, (outs),
3802 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3803 "bc $bo, $bi, $dst">;
3804 def gBCA : BForm_3<16, 1, 0, (outs),
3805 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3806 "bca $bo, $bi, $dst">;
3808 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3809 def gBCL : BForm_3<16, 0, 1, (outs),
3810 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3811 "bcl $bo, $bi, $dst">;
3812 def gBCLA : BForm_3<16, 1, 1, (outs),
3813 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3814 "bcla $bo, $bi, $dst">;
3816 let Defs = [CTR], Uses = [CTR, LR, RM] in
3817 def gBCLR : XLForm_2<19, 16, 0, (outs),
3818 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3819 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3820 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3821 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3822 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3823 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3824 let Defs = [CTR], Uses = [CTR, LR, RM] in
3825 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3826 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3827 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3828 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3829 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3830 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3831 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3833 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3834 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3835 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3836 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3838 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3839 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3840 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3841 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3842 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3843 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3844 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3846 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3847 : BranchSimpleMnemonic1<name, pm, bo> {
3848 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3849 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3851 defm : BranchSimpleMnemonic2<"t", "", 12>;
3852 defm : BranchSimpleMnemonic2<"f", "", 4>;
3853 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3854 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3855 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3856 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3857 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3858 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3859 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3860 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3862 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3863 def : InstAlias<"b"#name#pm#" $cc, $dst",
3864 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3865 def : InstAlias<"b"#name#pm#" $dst",
3866 (BCC bibo, CR0, condbrtarget:$dst)>;
3868 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3869 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3870 def : InstAlias<"b"#name#"a"#pm#" $dst",
3871 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3873 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3874 (BCCLR bibo, crrc:$cc)>;
3875 def : InstAlias<"b"#name#"lr"#pm,
3878 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3879 (BCCCTR bibo, crrc:$cc)>;
3880 def : InstAlias<"b"#name#"ctr"#pm,
3881 (BCCCTR bibo, CR0)>;
3883 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3884 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3885 def : InstAlias<"b"#name#"l"#pm#" $dst",
3886 (BCCL bibo, CR0, condbrtarget:$dst)>;
3888 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3889 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3890 def : InstAlias<"b"#name#"la"#pm#" $dst",
3891 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3893 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3894 (BCCLRL bibo, crrc:$cc)>;
3895 def : InstAlias<"b"#name#"lrl"#pm,
3896 (BCCLRL bibo, CR0)>;
3898 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3899 (BCCCTRL bibo, crrc:$cc)>;
3900 def : InstAlias<"b"#name#"ctrl"#pm,
3901 (BCCCTRL bibo, CR0)>;
3903 multiclass BranchExtendedMnemonic<string name, int bibo> {
3904 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3905 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3906 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3908 defm : BranchExtendedMnemonic<"lt", 12>;
3909 defm : BranchExtendedMnemonic<"gt", 44>;
3910 defm : BranchExtendedMnemonic<"eq", 76>;
3911 defm : BranchExtendedMnemonic<"un", 108>;
3912 defm : BranchExtendedMnemonic<"so", 108>;
3913 defm : BranchExtendedMnemonic<"ge", 4>;
3914 defm : BranchExtendedMnemonic<"nl", 4>;
3915 defm : BranchExtendedMnemonic<"le", 36>;
3916 defm : BranchExtendedMnemonic<"ng", 36>;
3917 defm : BranchExtendedMnemonic<"ne", 68>;
3918 defm : BranchExtendedMnemonic<"nu", 100>;
3919 defm : BranchExtendedMnemonic<"ns", 100>;
3921 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3922 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3923 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3924 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3925 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3926 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3927 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3928 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3930 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3931 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3932 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3933 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3934 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3935 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3936 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3937 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3939 multiclass TrapExtendedMnemonic<string name, int to> {
3940 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3941 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3942 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3943 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3945 defm : TrapExtendedMnemonic<"lt", 16>;
3946 defm : TrapExtendedMnemonic<"le", 20>;
3947 defm : TrapExtendedMnemonic<"eq", 4>;
3948 defm : TrapExtendedMnemonic<"ge", 12>;
3949 defm : TrapExtendedMnemonic<"gt", 8>;
3950 defm : TrapExtendedMnemonic<"nl", 12>;
3951 defm : TrapExtendedMnemonic<"ne", 24>;
3952 defm : TrapExtendedMnemonic<"ng", 20>;
3953 defm : TrapExtendedMnemonic<"llt", 2>;
3954 defm : TrapExtendedMnemonic<"lle", 6>;
3955 defm : TrapExtendedMnemonic<"lge", 5>;
3956 defm : TrapExtendedMnemonic<"lgt", 1>;
3957 defm : TrapExtendedMnemonic<"lnl", 5>;
3958 defm : TrapExtendedMnemonic<"lng", 6>;
3959 defm : TrapExtendedMnemonic<"u", 31>;
3962 def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>;
3963 def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>;
3964 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>;
3965 def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>;
3966 def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
3967 def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
3970 def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>;
3971 def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>;
3972 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>;
3973 def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
3974 def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
3975 def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;