1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
60 def tocentry32 : Operand<iPTR> {
61 let MIOperandInfo = (ops i32imm:$imm);
64 def SDT_PPCqvfperm : SDTypeProfile<1, 3, [
65 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>
67 def SDT_PPCqvgpci : SDTypeProfile<1, 1, [
68 SDTCisVec<0>, SDTCisInt<1>
70 def SDT_PPCqvaligni : SDTypeProfile<1, 3, [
71 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>
73 def SDT_PPCqvesplati : SDTypeProfile<1, 2, [
74 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
77 def SDT_PPCqbflt : SDTypeProfile<1, 1, [
78 SDTCisVec<0>, SDTCisVec<1>
81 def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
82 SDTCisVec<0>, SDTCisPtrTy<1>
85 //===----------------------------------------------------------------------===//
86 // PowerPC specific DAG Nodes.
89 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
90 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
92 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
93 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
94 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
95 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
96 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
97 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
98 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
99 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
100 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
101 [SDNPHasChain, SDNPMayStore]>;
102 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
103 [SDNPHasChain, SDNPMayLoad]>;
104 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
105 [SDNPHasChain, SDNPMayLoad]>;
107 // Extract FPSCR (not modeled at the DAG level).
108 def PPCmffs : SDNode<"PPCISD::MFFS",
109 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
111 // Perform FADD in round-to-zero mode.
112 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
115 def PPCfsel : SDNode<"PPCISD::FSEL",
116 // Type constraint for fsel.
117 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
118 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
120 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
121 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
122 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp,
123 [SDNPMayLoad, SDNPMemOperand]>;
124 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
125 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
127 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
129 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
130 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
132 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
133 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
134 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
135 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
136 def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
137 SDTypeProfile<1, 3, [
138 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
139 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
140 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
141 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
142 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
143 def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
144 SDTypeProfile<1, 3, [
145 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
146 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
147 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
148 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
150 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
152 def PPCqvfperm : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
153 def PPCqvgpci : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
154 def PPCqvaligni : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
155 def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;
157 def PPCqbflt : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>;
159 def PPCqvlfsb : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb,
160 [SDNPHasChain, SDNPMayLoad]>;
162 def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
164 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
165 // amounts. These nodes are generated by the multi-precision shift code.
166 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
167 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
168 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
170 // These are target-independent nodes, but have target-specific formats.
171 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
172 [SDNPHasChain, SDNPOutGlue]>;
173 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
174 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
176 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
177 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
178 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
180 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
181 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
183 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
186 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
188 def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
189 SDTypeProfile<0, 1, []>,
190 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
193 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
194 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
196 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
197 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
199 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
200 SDTypeProfile<1, 1, [SDTCisInt<0>,
202 [SDNPHasChain, SDNPSideEffect]>;
203 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
204 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
205 [SDNPHasChain, SDNPSideEffect]>;
207 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
208 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
209 [SDNPHasChain, SDNPSideEffect]>;
211 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
212 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
214 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
215 [SDNPHasChain, SDNPOptInGlue]>;
217 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
218 [SDNPHasChain, SDNPMayLoad]>;
219 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
220 [SDNPHasChain, SDNPMayStore]>;
222 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
223 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
224 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
225 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
226 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
228 // Instructions to support atomic operations
229 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
230 [SDNPHasChain, SDNPMayLoad]>;
231 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
232 [SDNPHasChain, SDNPMayStore]>;
234 // Instructions to support dynamic alloca.
235 def SDTDynOp : SDTypeProfile<1, 2, []>;
236 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
238 //===----------------------------------------------------------------------===//
239 // PowerPC specific transformation functions and pattern fragments.
242 def SHL32 : SDNodeXForm<imm, [{
243 // Transformation function: 31 - imm
244 return getI32Imm(31 - N->getZExtValue());
247 def SRL32 : SDNodeXForm<imm, [{
248 // Transformation function: 32 - imm
249 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
252 def LO16 : SDNodeXForm<imm, [{
253 // Transformation function: get the low 16 bits.
254 return getI32Imm((unsigned short)N->getZExtValue());
257 def HI16 : SDNodeXForm<imm, [{
258 // Transformation function: shift the immediate value down into the low bits.
259 return getI32Imm((unsigned)N->getZExtValue() >> 16);
262 def HA16 : SDNodeXForm<imm, [{
263 // Transformation function: shift the immediate value down into the low bits.
264 signed int Val = N->getZExtValue();
265 return getI32Imm((Val - (signed short)Val) >> 16);
267 def MB : SDNodeXForm<imm, [{
268 // Transformation function: get the start bit of a mask
270 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
271 return getI32Imm(mb);
274 def ME : SDNodeXForm<imm, [{
275 // Transformation function: get the end bit of a mask
277 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
278 return getI32Imm(me);
280 def maskimm32 : PatLeaf<(imm), [{
281 // maskImm predicate - True if immediate is a run of ones.
283 if (N->getValueType(0) == MVT::i32)
284 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
289 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
290 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
291 // sign extended field. Used by instructions like 'addi'.
292 return (int32_t)Imm == (short)Imm;
294 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
295 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
296 // sign extended field. Used by instructions like 'addi'.
297 return (int64_t)Imm == (short)Imm;
299 def immZExt16 : PatLeaf<(imm), [{
300 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
301 // field. Used by instructions like 'ori'.
302 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
305 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
306 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
307 // identical in 32-bit mode, but in 64-bit mode, they return true if the
308 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
310 def imm16ShiftedZExt : PatLeaf<(imm), [{
311 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
312 // immediate are set. Used by instructions like 'xoris'.
313 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
316 def imm16ShiftedSExt : PatLeaf<(imm), [{
317 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
318 // immediate are set. Used by instructions like 'addis'. Identical to
319 // imm16ShiftedZExt in 32-bit mode.
320 if (N->getZExtValue() & 0xFFFF) return false;
321 if (N->getValueType(0) == MVT::i32)
323 // For 64-bit, make sure it is sext right.
324 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
327 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
328 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
329 // zero extended field.
330 return isUInt<32>(Imm);
333 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
334 // restricted memrix (4-aligned) constants are alignment sensitive. If these
335 // offsets are hidden behind TOC entries than the values of the lower-order
336 // bits cannot be checked directly. As a result, we need to also incorporate
337 // an alignment check into the relevant patterns.
339 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
340 return cast<LoadSDNode>(N)->getAlignment() >= 4;
342 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
343 (store node:$val, node:$ptr), [{
344 return cast<StoreSDNode>(N)->getAlignment() >= 4;
346 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
347 return cast<LoadSDNode>(N)->getAlignment() >= 4;
349 def aligned4pre_store : PatFrag<
350 (ops node:$val, node:$base, node:$offset),
351 (pre_store node:$val, node:$base, node:$offset), [{
352 return cast<StoreSDNode>(N)->getAlignment() >= 4;
355 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
356 return cast<LoadSDNode>(N)->getAlignment() < 4;
358 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
359 (store node:$val, node:$ptr), [{
360 return cast<StoreSDNode>(N)->getAlignment() < 4;
362 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
363 return cast<LoadSDNode>(N)->getAlignment() < 4;
366 //===----------------------------------------------------------------------===//
367 // PowerPC Flag Definitions.
369 class isPPC64 { bit PPC64 = 1; }
370 class isDOT { bit RC = 1; }
372 class RegConstraint<string C> {
373 string Constraints = C;
375 class NoEncode<string E> {
376 string DisableEncoding = E;
380 //===----------------------------------------------------------------------===//
381 // PowerPC Operand Definitions.
383 // In the default PowerPC assembler syntax, registers are specified simply
384 // by number, so they cannot be distinguished from immediate values (without
385 // looking at the opcode). This means that the default operand matching logic
386 // for the asm parser does not work, and we need to specify custom matchers.
387 // Since those can only be specified with RegisterOperand classes and not
388 // directly on the RegisterClass, all instructions patterns used by the asm
389 // parser need to use a RegisterOperand (instead of a RegisterClass) for
390 // all their register operands.
391 // For this purpose, we define one RegisterOperand for each RegisterClass,
392 // using the same name as the class, just in lower case.
394 def PPCRegGPRCAsmOperand : AsmOperandClass {
395 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
397 def gprc : RegisterOperand<GPRC> {
398 let ParserMatchClass = PPCRegGPRCAsmOperand;
400 def PPCRegG8RCAsmOperand : AsmOperandClass {
401 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
403 def g8rc : RegisterOperand<G8RC> {
404 let ParserMatchClass = PPCRegG8RCAsmOperand;
406 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
407 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
409 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
410 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
412 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
413 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
415 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
416 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
418 def PPCRegF8RCAsmOperand : AsmOperandClass {
419 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
421 def f8rc : RegisterOperand<F8RC> {
422 let ParserMatchClass = PPCRegF8RCAsmOperand;
424 def PPCRegF4RCAsmOperand : AsmOperandClass {
425 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
427 def f4rc : RegisterOperand<F4RC> {
428 let ParserMatchClass = PPCRegF4RCAsmOperand;
430 def PPCRegVRRCAsmOperand : AsmOperandClass {
431 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
433 def vrrc : RegisterOperand<VRRC> {
434 let ParserMatchClass = PPCRegVRRCAsmOperand;
436 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
437 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
439 def crbitrc : RegisterOperand<CRBITRC> {
440 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
442 def PPCRegCRRCAsmOperand : AsmOperandClass {
443 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
445 def crrc : RegisterOperand<CRRC> {
446 let ParserMatchClass = PPCRegCRRCAsmOperand;
449 def PPCU2ImmAsmOperand : AsmOperandClass {
450 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
451 let RenderMethod = "addImmOperands";
453 def u2imm : Operand<i32> {
454 let PrintMethod = "printU2ImmOperand";
455 let ParserMatchClass = PPCU2ImmAsmOperand;
458 def PPCU4ImmAsmOperand : AsmOperandClass {
459 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
460 let RenderMethod = "addImmOperands";
462 def u4imm : Operand<i32> {
463 let PrintMethod = "printU4ImmOperand";
464 let ParserMatchClass = PPCU4ImmAsmOperand;
466 def PPCS5ImmAsmOperand : AsmOperandClass {
467 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
468 let RenderMethod = "addImmOperands";
470 def s5imm : Operand<i32> {
471 let PrintMethod = "printS5ImmOperand";
472 let ParserMatchClass = PPCS5ImmAsmOperand;
473 let DecoderMethod = "decodeSImmOperand<5>";
475 def PPCU5ImmAsmOperand : AsmOperandClass {
476 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
477 let RenderMethod = "addImmOperands";
479 def u5imm : Operand<i32> {
480 let PrintMethod = "printU5ImmOperand";
481 let ParserMatchClass = PPCU5ImmAsmOperand;
482 let DecoderMethod = "decodeUImmOperand<5>";
484 def PPCU6ImmAsmOperand : AsmOperandClass {
485 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
486 let RenderMethod = "addImmOperands";
488 def u6imm : Operand<i32> {
489 let PrintMethod = "printU6ImmOperand";
490 let ParserMatchClass = PPCU6ImmAsmOperand;
491 let DecoderMethod = "decodeUImmOperand<6>";
493 def PPCU12ImmAsmOperand : AsmOperandClass {
494 let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
495 let RenderMethod = "addImmOperands";
497 def u12imm : Operand<i32> {
498 let PrintMethod = "printU12ImmOperand";
499 let ParserMatchClass = PPCU12ImmAsmOperand;
500 let DecoderMethod = "decodeUImmOperand<12>";
502 def PPCS16ImmAsmOperand : AsmOperandClass {
503 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
504 let RenderMethod = "addS16ImmOperands";
506 def s16imm : Operand<i32> {
507 let PrintMethod = "printS16ImmOperand";
508 let EncoderMethod = "getImm16Encoding";
509 let ParserMatchClass = PPCS16ImmAsmOperand;
510 let DecoderMethod = "decodeSImmOperand<16>";
512 def PPCU16ImmAsmOperand : AsmOperandClass {
513 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
514 let RenderMethod = "addU16ImmOperands";
516 def u16imm : Operand<i32> {
517 let PrintMethod = "printU16ImmOperand";
518 let EncoderMethod = "getImm16Encoding";
519 let ParserMatchClass = PPCU16ImmAsmOperand;
520 let DecoderMethod = "decodeUImmOperand<16>";
522 def PPCS17ImmAsmOperand : AsmOperandClass {
523 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
524 let RenderMethod = "addS16ImmOperands";
526 def s17imm : Operand<i32> {
527 // This operand type is used for addis/lis to allow the assembler parser
528 // to accept immediates in the range -65536..65535 for compatibility with
529 // the GNU assembler. The operand is treated as 16-bit otherwise.
530 let PrintMethod = "printS16ImmOperand";
531 let EncoderMethod = "getImm16Encoding";
532 let ParserMatchClass = PPCS17ImmAsmOperand;
533 let DecoderMethod = "decodeSImmOperand<16>";
535 def PPCDirectBrAsmOperand : AsmOperandClass {
536 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
537 let RenderMethod = "addBranchTargetOperands";
539 def directbrtarget : Operand<OtherVT> {
540 let PrintMethod = "printBranchOperand";
541 let EncoderMethod = "getDirectBrEncoding";
542 let ParserMatchClass = PPCDirectBrAsmOperand;
544 def absdirectbrtarget : Operand<OtherVT> {
545 let PrintMethod = "printAbsBranchOperand";
546 let EncoderMethod = "getAbsDirectBrEncoding";
547 let ParserMatchClass = PPCDirectBrAsmOperand;
549 def PPCCondBrAsmOperand : AsmOperandClass {
550 let Name = "CondBr"; let PredicateMethod = "isCondBr";
551 let RenderMethod = "addBranchTargetOperands";
553 def condbrtarget : Operand<OtherVT> {
554 let PrintMethod = "printBranchOperand";
555 let EncoderMethod = "getCondBrEncoding";
556 let ParserMatchClass = PPCCondBrAsmOperand;
558 def abscondbrtarget : Operand<OtherVT> {
559 let PrintMethod = "printAbsBranchOperand";
560 let EncoderMethod = "getAbsCondBrEncoding";
561 let ParserMatchClass = PPCCondBrAsmOperand;
563 def calltarget : Operand<iPTR> {
564 let PrintMethod = "printBranchOperand";
565 let EncoderMethod = "getDirectBrEncoding";
566 let ParserMatchClass = PPCDirectBrAsmOperand;
568 def abscalltarget : Operand<iPTR> {
569 let PrintMethod = "printAbsBranchOperand";
570 let EncoderMethod = "getAbsDirectBrEncoding";
571 let ParserMatchClass = PPCDirectBrAsmOperand;
573 def PPCCRBitMaskOperand : AsmOperandClass {
574 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
576 def crbitm: Operand<i8> {
577 let PrintMethod = "printcrbitm";
578 let EncoderMethod = "get_crbitm_encoding";
579 let DecoderMethod = "decodeCRBitMOperand";
580 let ParserMatchClass = PPCCRBitMaskOperand;
583 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
584 def PPCRegGxRCNoR0Operand : AsmOperandClass {
585 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
587 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
588 let ParserMatchClass = PPCRegGxRCNoR0Operand;
590 // A version of ptr_rc usable with the asm parser.
591 def PPCRegGxRCOperand : AsmOperandClass {
592 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
594 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
595 let ParserMatchClass = PPCRegGxRCOperand;
598 def PPCDispRIOperand : AsmOperandClass {
599 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
600 let RenderMethod = "addS16ImmOperands";
602 def dispRI : Operand<iPTR> {
603 let ParserMatchClass = PPCDispRIOperand;
605 def PPCDispRIXOperand : AsmOperandClass {
606 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
607 let RenderMethod = "addImmOperands";
609 def dispRIX : Operand<iPTR> {
610 let ParserMatchClass = PPCDispRIXOperand;
612 def PPCDispSPE8Operand : AsmOperandClass {
613 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
614 let RenderMethod = "addImmOperands";
616 def dispSPE8 : Operand<iPTR> {
617 let ParserMatchClass = PPCDispSPE8Operand;
619 def PPCDispSPE4Operand : AsmOperandClass {
620 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
621 let RenderMethod = "addImmOperands";
623 def dispSPE4 : Operand<iPTR> {
624 let ParserMatchClass = PPCDispSPE4Operand;
626 def PPCDispSPE2Operand : AsmOperandClass {
627 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
628 let RenderMethod = "addImmOperands";
630 def dispSPE2 : Operand<iPTR> {
631 let ParserMatchClass = PPCDispSPE2Operand;
634 def memri : Operand<iPTR> {
635 let PrintMethod = "printMemRegImm";
636 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
637 let EncoderMethod = "getMemRIEncoding";
638 let DecoderMethod = "decodeMemRIOperands";
640 def memrr : Operand<iPTR> {
641 let PrintMethod = "printMemRegReg";
642 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
644 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
645 let PrintMethod = "printMemRegImm";
646 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
647 let EncoderMethod = "getMemRIXEncoding";
648 let DecoderMethod = "decodeMemRIXOperands";
650 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
651 let PrintMethod = "printMemRegImm";
652 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
653 let EncoderMethod = "getSPE8DisEncoding";
655 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
656 let PrintMethod = "printMemRegImm";
657 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
658 let EncoderMethod = "getSPE4DisEncoding";
660 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
661 let PrintMethod = "printMemRegImm";
662 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
663 let EncoderMethod = "getSPE2DisEncoding";
666 // A single-register address. This is used with the SjLj
667 // pseudo-instructions.
668 def memr : Operand<iPTR> {
669 let MIOperandInfo = (ops ptr_rc:$ptrreg);
671 def PPCTLSRegOperand : AsmOperandClass {
672 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
673 let RenderMethod = "addTLSRegOperands";
675 def tlsreg32 : Operand<i32> {
676 let EncoderMethod = "getTLSRegEncoding";
677 let ParserMatchClass = PPCTLSRegOperand;
679 def tlsgd32 : Operand<i32> {}
680 def tlscall32 : Operand<i32> {
681 let PrintMethod = "printTLSCall";
682 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
683 let EncoderMethod = "getTLSCallEncoding";
686 // PowerPC Predicate operand.
687 def pred : Operand<OtherVT> {
688 let PrintMethod = "printPredicateOperand";
689 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
692 // Define PowerPC specific addressing mode.
693 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
694 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
695 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
696 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
698 // The address in a single register. This is used with the SjLj
699 // pseudo-instructions.
700 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
702 /// This is just the offset part of iaddr, used for preinc.
703 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
705 //===----------------------------------------------------------------------===//
706 // PowerPC Instruction Predicate Definitions.
707 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
708 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
709 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
710 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
711 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
712 def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
713 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
714 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
715 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
716 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
717 def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
719 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
720 def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">;
722 //===----------------------------------------------------------------------===//
723 // PowerPC Multiclass Definitions.
725 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
726 string asmbase, string asmstr, InstrItinClass itin,
728 let BaseName = asmbase in {
729 def NAME : XForm_6<opcode, xo, OOL, IOL,
730 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
731 pattern>, RecFormRel;
733 def o : XForm_6<opcode, xo, OOL, IOL,
734 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
735 []>, isDOT, RecFormRel;
739 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
740 string asmbase, string asmstr, InstrItinClass itin,
742 let BaseName = asmbase in {
743 let Defs = [CARRY] in
744 def NAME : XForm_6<opcode, xo, OOL, IOL,
745 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
746 pattern>, RecFormRel;
747 let Defs = [CARRY, CR0] in
748 def o : XForm_6<opcode, xo, OOL, IOL,
749 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
750 []>, isDOT, RecFormRel;
754 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
755 string asmbase, string asmstr, InstrItinClass itin,
757 let BaseName = asmbase in {
758 let Defs = [CARRY] in
759 def NAME : XForm_10<opcode, xo, OOL, IOL,
760 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
761 pattern>, RecFormRel;
762 let Defs = [CARRY, CR0] in
763 def o : XForm_10<opcode, xo, OOL, IOL,
764 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
765 []>, isDOT, RecFormRel;
769 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
770 string asmbase, string asmstr, InstrItinClass itin,
772 let BaseName = asmbase in {
773 def NAME : XForm_11<opcode, xo, OOL, IOL,
774 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
775 pattern>, RecFormRel;
777 def o : XForm_11<opcode, xo, OOL, IOL,
778 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
779 []>, isDOT, RecFormRel;
783 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
784 string asmbase, string asmstr, InstrItinClass itin,
786 let BaseName = asmbase in {
787 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
788 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
789 pattern>, RecFormRel;
791 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
792 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
793 []>, isDOT, RecFormRel;
797 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
798 string asmbase, string asmstr, InstrItinClass itin,
800 let BaseName = asmbase in {
801 let Defs = [CARRY] in
802 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
803 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
804 pattern>, RecFormRel;
805 let Defs = [CARRY, CR0] in
806 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
807 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
808 []>, isDOT, RecFormRel;
812 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
813 string asmbase, string asmstr, InstrItinClass itin,
815 let BaseName = asmbase in {
816 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
817 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
818 pattern>, RecFormRel;
820 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
821 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
822 []>, isDOT, RecFormRel;
826 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
827 string asmbase, string asmstr, InstrItinClass itin,
829 let BaseName = asmbase in {
830 let Defs = [CARRY] in
831 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
832 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
833 pattern>, RecFormRel;
834 let Defs = [CARRY, CR0] in
835 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
836 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
837 []>, isDOT, RecFormRel;
841 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
842 string asmbase, string asmstr, InstrItinClass itin,
844 let BaseName = asmbase in {
845 def NAME : MForm_2<opcode, OOL, IOL,
846 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
847 pattern>, RecFormRel;
849 def o : MForm_2<opcode, OOL, IOL,
850 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
851 []>, isDOT, RecFormRel;
855 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
856 string asmbase, string asmstr, InstrItinClass itin,
858 let BaseName = asmbase in {
859 def NAME : MDForm_1<opcode, xo, OOL, IOL,
860 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
861 pattern>, RecFormRel;
863 def o : MDForm_1<opcode, xo, OOL, IOL,
864 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
865 []>, isDOT, RecFormRel;
869 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
870 string asmbase, string asmstr, InstrItinClass itin,
872 let BaseName = asmbase in {
873 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
874 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
875 pattern>, RecFormRel;
877 def o : MDSForm_1<opcode, xo, OOL, IOL,
878 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
879 []>, isDOT, RecFormRel;
883 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
884 string asmbase, string asmstr, InstrItinClass itin,
886 let BaseName = asmbase in {
887 let Defs = [CARRY] in
888 def NAME : XSForm_1<opcode, xo, OOL, IOL,
889 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
890 pattern>, RecFormRel;
891 let Defs = [CARRY, CR0] in
892 def o : XSForm_1<opcode, xo, OOL, IOL,
893 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
894 []>, isDOT, RecFormRel;
898 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
899 string asmbase, string asmstr, InstrItinClass itin,
901 let BaseName = asmbase in {
902 def NAME : XForm_26<opcode, xo, OOL, IOL,
903 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
904 pattern>, RecFormRel;
906 def o : XForm_26<opcode, xo, OOL, IOL,
907 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
908 []>, isDOT, RecFormRel;
912 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
913 string asmbase, string asmstr, InstrItinClass itin,
915 let BaseName = asmbase in {
916 def NAME : XForm_28<opcode, xo, OOL, IOL,
917 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
918 pattern>, RecFormRel;
920 def o : XForm_28<opcode, xo, OOL, IOL,
921 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
922 []>, isDOT, RecFormRel;
926 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
927 string asmbase, string asmstr, InstrItinClass itin,
929 let BaseName = asmbase in {
930 def NAME : AForm_1<opcode, xo, OOL, IOL,
931 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
932 pattern>, RecFormRel;
934 def o : AForm_1<opcode, xo, OOL, IOL,
935 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
936 []>, isDOT, RecFormRel;
940 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
941 string asmbase, string asmstr, InstrItinClass itin,
943 let BaseName = asmbase in {
944 def NAME : AForm_2<opcode, xo, OOL, IOL,
945 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
946 pattern>, RecFormRel;
948 def o : AForm_2<opcode, xo, OOL, IOL,
949 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
950 []>, isDOT, RecFormRel;
954 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
955 string asmbase, string asmstr, InstrItinClass itin,
957 let BaseName = asmbase in {
958 def NAME : AForm_3<opcode, xo, OOL, IOL,
959 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
960 pattern>, RecFormRel;
962 def o : AForm_3<opcode, xo, OOL, IOL,
963 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
964 []>, isDOT, RecFormRel;
968 //===----------------------------------------------------------------------===//
969 // PowerPC Instruction Definitions.
971 // Pseudo-instructions:
973 let hasCtrlDep = 1 in {
974 let Defs = [R1], Uses = [R1] in {
975 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
976 [(callseq_start timm:$amt)]>;
977 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
978 [(callseq_end timm:$amt1, timm:$amt2)]>;
981 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
982 "UPDATE_VRSAVE $rD, $rS", []>;
985 let Defs = [R1], Uses = [R1] in
986 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
988 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
990 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
991 // instruction selection into a branch sequence.
992 let usesCustomInserter = 1, // Expanded after instruction selection.
993 PPC970_Single = 1 in {
994 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
995 // because either operand might become the first operand in an isel, and
996 // that operand cannot be r0.
997 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
998 gprc_nor0:$T, gprc_nor0:$F,
999 i32imm:$BROPC), "#SELECT_CC_I4",
1001 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1002 g8rc_nox0:$T, g8rc_nox0:$F,
1003 i32imm:$BROPC), "#SELECT_CC_I8",
1005 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1006 i32imm:$BROPC), "#SELECT_CC_F4",
1008 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1009 i32imm:$BROPC), "#SELECT_CC_F8",
1011 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1012 i32imm:$BROPC), "#SELECT_CC_VRRC",
1015 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
1016 // register bit directly.
1017 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1018 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
1019 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
1020 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1021 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
1022 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
1023 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1024 f4rc:$T, f4rc:$F), "#SELECT_F4",
1025 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
1026 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1027 f8rc:$T, f8rc:$F), "#SELECT_F8",
1028 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1029 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1030 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
1032 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
1035 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
1036 // scavenge a register for it.
1037 let mayStore = 1 in {
1038 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1040 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1041 "#SPILL_CRBIT", []>;
1044 // RESTORE_CR - Indicate that we're restoring the CR register (previously
1045 // spilled), so we'll need to scavenge a register for it.
1046 let mayLoad = 1 in {
1047 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1049 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1050 "#RESTORE_CRBIT", []>;
1053 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1054 let isReturn = 1, Uses = [LR, RM] in
1055 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1056 [(retflag)]>, Requires<[In32BitMode]>;
1057 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1058 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1061 let isCodeGenOnly = 1 in {
1062 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1063 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1066 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1067 "bcctr 12, $bi, 0", IIC_BrB, []>;
1068 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1069 "bcctr 4, $bi, 0", IIC_BrB, []>;
1075 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1078 def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1081 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1082 let isBarrier = 1 in {
1083 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1086 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1087 "ba $dst", IIC_BrB, []>;
1090 // BCC represents an arbitrary conditional branch on a predicate.
1091 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1092 // a two-value operand where a dag node expects two operands. :(
1093 let isCodeGenOnly = 1 in {
1094 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1095 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1096 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1097 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1098 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1100 let isReturn = 1, Uses = [LR, RM] in
1101 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1102 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1105 let isCodeGenOnly = 1 in {
1106 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1107 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1108 "bc 12, $bi, $dst">;
1110 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1111 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1114 let isReturn = 1, Uses = [LR, RM] in
1115 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1116 "bclr 12, $bi, 0", IIC_BrB, []>;
1117 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1118 "bclr 4, $bi, 0", IIC_BrB, []>;
1121 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1122 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1123 "bdzlr", IIC_BrB, []>;
1124 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1125 "bdnzlr", IIC_BrB, []>;
1126 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1127 "bdzlr+", IIC_BrB, []>;
1128 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1129 "bdnzlr+", IIC_BrB, []>;
1130 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1131 "bdzlr-", IIC_BrB, []>;
1132 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1133 "bdnzlr-", IIC_BrB, []>;
1136 let Defs = [CTR], Uses = [CTR] in {
1137 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1139 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1141 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1143 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1145 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1147 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1149 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1151 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1153 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1155 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1157 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1159 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1164 // The unconditional BCL used by the SjLj setjmp code.
1165 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1166 let Defs = [LR], Uses = [RM] in {
1167 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1168 "bcl 20, 31, $dst">;
1172 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1173 // Convenient aliases for call instructions
1174 let Uses = [RM] in {
1175 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1176 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1177 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1178 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1180 let isCodeGenOnly = 1 in {
1181 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1182 "bl $func", IIC_BrB, []>;
1183 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1184 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1185 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1186 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1188 def BCL : BForm_4<16, 12, 0, 1, (outs),
1189 (ins crbitrc:$bi, condbrtarget:$dst),
1190 "bcl 12, $bi, $dst">;
1191 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1192 (ins crbitrc:$bi, condbrtarget:$dst),
1193 "bcl 4, $bi, $dst">;
1196 let Uses = [CTR, RM] in {
1197 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1198 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1199 Requires<[In32BitMode]>;
1201 let isCodeGenOnly = 1 in {
1202 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1203 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1206 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1207 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1208 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1209 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1212 let Uses = [LR, RM] in {
1213 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1214 "blrl", IIC_BrB, []>;
1216 let isCodeGenOnly = 1 in {
1217 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1218 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1221 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1222 "bclrl 12, $bi, 0", IIC_BrB, []>;
1223 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1224 "bclrl 4, $bi, 0", IIC_BrB, []>;
1227 let Defs = [CTR], Uses = [CTR, RM] in {
1228 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1230 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1232 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1234 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1236 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1238 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1240 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1242 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1244 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1246 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1248 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1250 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1253 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1254 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1255 "bdzlrl", IIC_BrB, []>;
1256 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1257 "bdnzlrl", IIC_BrB, []>;
1258 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1259 "bdzlrl+", IIC_BrB, []>;
1260 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1261 "bdnzlrl+", IIC_BrB, []>;
1262 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1263 "bdzlrl-", IIC_BrB, []>;
1264 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1265 "bdnzlrl-", IIC_BrB, []>;
1269 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1270 def TCRETURNdi :Pseudo< (outs),
1271 (ins calltarget:$dst, i32imm:$offset),
1272 "#TC_RETURNd $dst $offset",
1276 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1277 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1278 "#TC_RETURNa $func $offset",
1279 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1281 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1282 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1283 "#TC_RETURNr $dst $offset",
1287 let isCodeGenOnly = 1 in {
1289 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1290 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1291 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1292 []>, Requires<[In32BitMode]>;
1294 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1295 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1296 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1300 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1301 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1302 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1308 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1310 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1311 "#EH_SJLJ_SETJMP32",
1312 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1313 Requires<[In32BitMode]>;
1314 let isTerminator = 1 in
1315 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1316 "#EH_SJLJ_LONGJMP32",
1317 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1318 Requires<[In32BitMode]>;
1321 let isBranch = 1, isTerminator = 1 in {
1322 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1323 "#EH_SjLj_Setup\t$dst", []>;
1327 let PPC970_Unit = 7 in {
1328 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1329 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1332 // DCB* instructions.
1333 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1334 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1335 PPC970_DGroup_Single;
1336 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1337 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1338 PPC970_DGroup_Single;
1339 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1340 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1341 PPC970_DGroup_Single;
1342 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1343 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1344 PPC970_DGroup_Single;
1345 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1346 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1347 PPC970_DGroup_Single;
1348 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1349 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1350 PPC970_DGroup_Single;
1351 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1352 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1353 PPC970_DGroup_Single;
1354 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1355 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1356 PPC970_DGroup_Single;
1358 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1359 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1361 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1362 (DCBT xoaddr:$dst)>; // data prefetch for loads
1363 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1364 (DCBTST xoaddr:$dst)>; // data prefetch for stores
1365 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1366 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1368 // Atomic operations
1369 let usesCustomInserter = 1 in {
1370 let Defs = [CR0] in {
1371 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1372 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1373 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1374 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1375 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1376 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1377 def ATOMIC_LOAD_AND_I8 : Pseudo<
1378 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1379 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1380 def ATOMIC_LOAD_OR_I8 : Pseudo<
1381 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1382 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1383 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1384 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1385 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1386 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1387 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1388 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1389 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1390 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1391 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1392 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1393 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1394 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1395 def ATOMIC_LOAD_AND_I16 : Pseudo<
1396 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1397 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1398 def ATOMIC_LOAD_OR_I16 : Pseudo<
1399 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1400 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1401 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1402 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1403 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1404 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1405 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1406 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1407 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1408 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1409 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1410 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1411 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1412 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1413 def ATOMIC_LOAD_AND_I32 : Pseudo<
1414 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1415 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1416 def ATOMIC_LOAD_OR_I32 : Pseudo<
1417 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1418 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1419 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1420 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1421 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1422 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1423 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1424 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1426 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1427 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1428 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1429 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1430 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1431 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1432 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1433 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1434 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1436 def ATOMIC_SWAP_I8 : Pseudo<
1437 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1438 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1439 def ATOMIC_SWAP_I16 : Pseudo<
1440 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1441 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1442 def ATOMIC_SWAP_I32 : Pseudo<
1443 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1444 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1448 // Instructions to support atomic operations
1449 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1450 "lwarx $rD, $src", IIC_LdStLWARX,
1451 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1454 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1455 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1456 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1459 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1460 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1462 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1463 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1464 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1465 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1466 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1467 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1468 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1469 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1471 //===----------------------------------------------------------------------===//
1472 // PPC32 Load Instructions.
1475 // Unindexed (r+i) Loads.
1476 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1477 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1478 "lbz $rD, $src", IIC_LdStLoad,
1479 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1480 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1481 "lha $rD, $src", IIC_LdStLHA,
1482 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1483 PPC970_DGroup_Cracked;
1484 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1485 "lhz $rD, $src", IIC_LdStLoad,
1486 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1487 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1488 "lwz $rD, $src", IIC_LdStLoad,
1489 [(set i32:$rD, (load iaddr:$src))]>;
1491 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1492 "lfs $rD, $src", IIC_LdStLFD,
1493 [(set f32:$rD, (load iaddr:$src))]>;
1494 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1495 "lfd $rD, $src", IIC_LdStLFD,
1496 [(set f64:$rD, (load iaddr:$src))]>;
1499 // Unindexed (r+i) Loads with Update (preinc).
1500 let mayLoad = 1, hasSideEffects = 0 in {
1501 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1502 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1503 []>, RegConstraint<"$addr.reg = $ea_result">,
1504 NoEncode<"$ea_result">;
1506 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1507 "lhau $rD, $addr", IIC_LdStLHAU,
1508 []>, RegConstraint<"$addr.reg = $ea_result">,
1509 NoEncode<"$ea_result">;
1511 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1512 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1513 []>, RegConstraint<"$addr.reg = $ea_result">,
1514 NoEncode<"$ea_result">;
1516 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1517 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1518 []>, RegConstraint<"$addr.reg = $ea_result">,
1519 NoEncode<"$ea_result">;
1521 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1522 "lfsu $rD, $addr", IIC_LdStLFDU,
1523 []>, RegConstraint<"$addr.reg = $ea_result">,
1524 NoEncode<"$ea_result">;
1526 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1527 "lfdu $rD, $addr", IIC_LdStLFDU,
1528 []>, RegConstraint<"$addr.reg = $ea_result">,
1529 NoEncode<"$ea_result">;
1532 // Indexed (r+r) Loads with Update (preinc).
1533 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1535 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1536 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1537 NoEncode<"$ea_result">;
1539 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1541 "lhaux $rD, $addr", IIC_LdStLHAUX,
1542 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1543 NoEncode<"$ea_result">;
1545 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1547 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1548 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1549 NoEncode<"$ea_result">;
1551 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1553 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1554 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1555 NoEncode<"$ea_result">;
1557 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1559 "lfsux $rD, $addr", IIC_LdStLFDUX,
1560 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1561 NoEncode<"$ea_result">;
1563 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1565 "lfdux $rD, $addr", IIC_LdStLFDUX,
1566 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1567 NoEncode<"$ea_result">;
1571 // Indexed (r+r) Loads.
1573 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1574 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1575 "lbzx $rD, $src", IIC_LdStLoad,
1576 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1577 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1578 "lhax $rD, $src", IIC_LdStLHA,
1579 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1580 PPC970_DGroup_Cracked;
1581 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1582 "lhzx $rD, $src", IIC_LdStLoad,
1583 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1584 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1585 "lwzx $rD, $src", IIC_LdStLoad,
1586 [(set i32:$rD, (load xaddr:$src))]>;
1589 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1590 "lhbrx $rD, $src", IIC_LdStLoad,
1591 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1592 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1593 "lwbrx $rD, $src", IIC_LdStLoad,
1594 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1596 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1597 "lfsx $frD, $src", IIC_LdStLFD,
1598 [(set f32:$frD, (load xaddr:$src))]>;
1599 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1600 "lfdx $frD, $src", IIC_LdStLFD,
1601 [(set f64:$frD, (load xaddr:$src))]>;
1603 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1604 "lfiwax $frD, $src", IIC_LdStLFD,
1605 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1606 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1607 "lfiwzx $frD, $src", IIC_LdStLFD,
1608 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1612 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1613 "lmw $rD, $src", IIC_LdStLMW, []>;
1615 //===----------------------------------------------------------------------===//
1616 // PPC32 Store Instructions.
1619 // Unindexed (r+i) Stores.
1620 let PPC970_Unit = 2 in {
1621 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1622 "stb $rS, $src", IIC_LdStStore,
1623 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1624 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1625 "sth $rS, $src", IIC_LdStStore,
1626 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1627 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1628 "stw $rS, $src", IIC_LdStStore,
1629 [(store i32:$rS, iaddr:$src)]>;
1630 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1631 "stfs $rS, $dst", IIC_LdStSTFD,
1632 [(store f32:$rS, iaddr:$dst)]>;
1633 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1634 "stfd $rS, $dst", IIC_LdStSTFD,
1635 [(store f64:$rS, iaddr:$dst)]>;
1638 // Unindexed (r+i) Stores with Update (preinc).
1639 let PPC970_Unit = 2, mayStore = 1 in {
1640 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1641 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1642 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1643 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1644 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1645 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1646 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1647 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1648 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1649 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1650 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1651 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1652 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1653 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1654 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1657 // Patterns to match the pre-inc stores. We can't put the patterns on
1658 // the instruction definitions directly as ISel wants the address base
1659 // and offset to be separate operands, not a single complex operand.
1660 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1661 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1662 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1663 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1664 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1665 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1666 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1667 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1668 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1669 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1671 // Indexed (r+r) Stores.
1672 let PPC970_Unit = 2 in {
1673 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1674 "stbx $rS, $dst", IIC_LdStStore,
1675 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1676 PPC970_DGroup_Cracked;
1677 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1678 "sthx $rS, $dst", IIC_LdStStore,
1679 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1680 PPC970_DGroup_Cracked;
1681 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1682 "stwx $rS, $dst", IIC_LdStStore,
1683 [(store i32:$rS, xaddr:$dst)]>,
1684 PPC970_DGroup_Cracked;
1686 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1687 "sthbrx $rS, $dst", IIC_LdStStore,
1688 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1689 PPC970_DGroup_Cracked;
1690 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1691 "stwbrx $rS, $dst", IIC_LdStStore,
1692 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1693 PPC970_DGroup_Cracked;
1695 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1696 "stfiwx $frS, $dst", IIC_LdStSTFD,
1697 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1699 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1700 "stfsx $frS, $dst", IIC_LdStSTFD,
1701 [(store f32:$frS, xaddr:$dst)]>;
1702 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1703 "stfdx $frS, $dst", IIC_LdStSTFD,
1704 [(store f64:$frS, xaddr:$dst)]>;
1707 // Indexed (r+r) Stores with Update (preinc).
1708 let PPC970_Unit = 2, mayStore = 1 in {
1709 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1710 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1711 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1712 PPC970_DGroup_Cracked;
1713 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1714 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1715 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1716 PPC970_DGroup_Cracked;
1717 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1718 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1719 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1720 PPC970_DGroup_Cracked;
1721 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1722 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1723 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1724 PPC970_DGroup_Cracked;
1725 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1726 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1727 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1728 PPC970_DGroup_Cracked;
1731 // Patterns to match the pre-inc stores. We can't put the patterns on
1732 // the instruction definitions directly as ISel wants the address base
1733 // and offset to be separate operands, not a single complex operand.
1734 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1735 (STBUX $rS, $ptrreg, $ptroff)>;
1736 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1737 (STHUX $rS, $ptrreg, $ptroff)>;
1738 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1739 (STWUX $rS, $ptrreg, $ptroff)>;
1740 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1741 (STFSUX $rS, $ptrreg, $ptroff)>;
1742 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1743 (STFDUX $rS, $ptrreg, $ptroff)>;
1746 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1747 "stmw $rS, $dst", IIC_LdStLMW, []>;
1749 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1750 "sync $L", IIC_LdStSync, []>;
1752 let isCodeGenOnly = 1 in {
1753 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1754 "msync", IIC_LdStSync, []> {
1759 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>;
1760 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1761 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1762 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1764 //===----------------------------------------------------------------------===//
1765 // PPC32 Arithmetic Instructions.
1768 let PPC970_Unit = 1 in { // FXU Operations.
1769 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1770 "addi $rD, $rA, $imm", IIC_IntSimple,
1771 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1772 let BaseName = "addic" in {
1773 let Defs = [CARRY] in
1774 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1775 "addic $rD, $rA, $imm", IIC_IntGeneral,
1776 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1777 RecFormRel, PPC970_DGroup_Cracked;
1778 let Defs = [CARRY, CR0] in
1779 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1780 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1781 []>, isDOT, RecFormRel;
1783 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1784 "addis $rD, $rA, $imm", IIC_IntSimple,
1785 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1786 let isCodeGenOnly = 1 in
1787 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1788 "la $rD, $sym($rA)", IIC_IntGeneral,
1789 [(set i32:$rD, (add i32:$rA,
1790 (PPClo tglobaladdr:$sym, 0)))]>;
1791 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1792 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1793 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1794 let Defs = [CARRY] in
1795 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1796 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1797 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1799 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1800 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1801 "li $rD, $imm", IIC_IntSimple,
1802 [(set i32:$rD, imm32SExt16:$imm)]>;
1803 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1804 "lis $rD, $imm", IIC_IntSimple,
1805 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1809 let PPC970_Unit = 1 in { // FXU Operations.
1810 let Defs = [CR0] in {
1811 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1812 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1813 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1815 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1816 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1817 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1820 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1821 "ori $dst, $src1, $src2", IIC_IntSimple,
1822 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1823 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1824 "oris $dst, $src1, $src2", IIC_IntSimple,
1825 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1826 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1827 "xori $dst, $src1, $src2", IIC_IntSimple,
1828 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1829 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1830 "xoris $dst, $src1, $src2", IIC_IntSimple,
1831 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1833 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1835 let isCodeGenOnly = 1 in {
1836 // The POWER6 and POWER7 have special group-terminating nops.
1837 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1838 "ori 1, 1, 0", IIC_IntSimple, []>;
1839 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1840 "ori 2, 2, 0", IIC_IntSimple, []>;
1843 let isCompare = 1, hasSideEffects = 0 in {
1844 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1845 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1846 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1847 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1851 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
1852 let isCommutable = 1 in {
1853 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1854 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1855 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1856 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1857 "and", "$rA, $rS, $rB", IIC_IntSimple,
1858 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1860 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1861 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1862 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1863 let isCommutable = 1 in {
1864 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1865 "or", "$rA, $rS, $rB", IIC_IntSimple,
1866 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1867 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1868 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1869 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1871 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1872 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1873 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1874 let isCommutable = 1 in {
1875 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1876 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1877 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1878 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1879 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1880 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1882 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1883 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1884 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1885 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1886 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1887 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1888 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1889 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1890 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1893 let PPC970_Unit = 1 in { // FXU Operations.
1894 let hasSideEffects = 0 in {
1895 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1896 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1897 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1898 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1899 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1900 [(set i32:$rA, (ctlz i32:$rS))]>;
1901 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1902 "extsb", "$rA, $rS", IIC_IntSimple,
1903 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1904 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1905 "extsh", "$rA, $rS", IIC_IntSimple,
1906 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1908 let isCommutable = 1 in
1909 def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1910 "cmpb $rA, $rS, $rB", IIC_IntGeneral,
1911 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
1913 let isCompare = 1, hasSideEffects = 0 in {
1914 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1915 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1916 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1917 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1920 let PPC970_Unit = 3 in { // FPU Operations.
1921 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1922 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1923 let isCompare = 1, hasSideEffects = 0 in {
1924 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1925 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1926 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1927 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1928 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1931 let Uses = [RM] in {
1932 let hasSideEffects = 0 in {
1933 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1934 "fctiw", "$frD, $frB", IIC_FPGeneral,
1936 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1937 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1938 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1940 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1941 "frsp", "$frD, $frB", IIC_FPGeneral,
1942 [(set f32:$frD, (fround f64:$frB))]>;
1944 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1945 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1946 "frin", "$frD, $frB", IIC_FPGeneral,
1947 [(set f64:$frD, (frnd f64:$frB))]>;
1948 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1949 "frin", "$frD, $frB", IIC_FPGeneral,
1950 [(set f32:$frD, (frnd f32:$frB))]>;
1953 let hasSideEffects = 0 in {
1954 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1955 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1956 "frip", "$frD, $frB", IIC_FPGeneral,
1957 [(set f64:$frD, (fceil f64:$frB))]>;
1958 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1959 "frip", "$frD, $frB", IIC_FPGeneral,
1960 [(set f32:$frD, (fceil f32:$frB))]>;
1961 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1962 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1963 "friz", "$frD, $frB", IIC_FPGeneral,
1964 [(set f64:$frD, (ftrunc f64:$frB))]>;
1965 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1966 "friz", "$frD, $frB", IIC_FPGeneral,
1967 [(set f32:$frD, (ftrunc f32:$frB))]>;
1968 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1969 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1970 "frim", "$frD, $frB", IIC_FPGeneral,
1971 [(set f64:$frD, (ffloor f64:$frB))]>;
1972 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1973 "frim", "$frD, $frB", IIC_FPGeneral,
1974 [(set f32:$frD, (ffloor f32:$frB))]>;
1976 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1977 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1978 [(set f64:$frD, (fsqrt f64:$frB))]>;
1979 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1980 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1981 [(set f32:$frD, (fsqrt f32:$frB))]>;
1986 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1987 /// often coalesced away and we don't want the dispatch group builder to think
1988 /// that they will fill slots (which could cause the load of a LSU reject to
1989 /// sneak into a d-group with a store).
1990 let hasSideEffects = 0 in
1991 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1992 "fmr", "$frD, $frB", IIC_FPGeneral,
1993 []>, // (set f32:$frD, f32:$frB)
1996 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
1997 // These are artificially split into two different forms, for 4/8 byte FP.
1998 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1999 "fabs", "$frD, $frB", IIC_FPGeneral,
2000 [(set f32:$frD, (fabs f32:$frB))]>;
2001 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2002 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
2003 "fabs", "$frD, $frB", IIC_FPGeneral,
2004 [(set f64:$frD, (fabs f64:$frB))]>;
2005 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
2006 "fnabs", "$frD, $frB", IIC_FPGeneral,
2007 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
2008 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2009 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
2010 "fnabs", "$frD, $frB", IIC_FPGeneral,
2011 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
2012 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
2013 "fneg", "$frD, $frB", IIC_FPGeneral,
2014 [(set f32:$frD, (fneg f32:$frB))]>;
2015 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2016 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
2017 "fneg", "$frD, $frB", IIC_FPGeneral,
2018 [(set f64:$frD, (fneg f64:$frB))]>;
2020 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
2021 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2022 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
2023 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2024 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
2025 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2026 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
2028 // Reciprocal estimates.
2029 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
2030 "fre", "$frD, $frB", IIC_FPGeneral,
2031 [(set f64:$frD, (PPCfre f64:$frB))]>;
2032 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
2033 "fres", "$frD, $frB", IIC_FPGeneral,
2034 [(set f32:$frD, (PPCfre f32:$frB))]>;
2035 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
2036 "frsqrte", "$frD, $frB", IIC_FPGeneral,
2037 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2038 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2039 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2040 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2043 // XL-Form instructions. condition register logical ops.
2045 let hasSideEffects = 0 in
2046 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2047 "mcrf $BF, $BFA", IIC_BrMCR>,
2048 PPC970_DGroup_First, PPC970_Unit_CRU;
2050 // FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2051 // condition-register logical instructions have preferred forms. Specifically,
2052 // it is preferred that the bit specified by the BT field be in the same
2053 // condition register as that specified by the bit BB. We might want to account
2054 // for this via hinting the register allocator and anti-dep breakers, or we
2055 // could constrain the register class to force this constraint and then loosen
2056 // it during register allocation via convertToThreeAddress or some similar
2059 let isCommutable = 1 in {
2060 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
2061 (ins crbitrc:$CRA, crbitrc:$CRB),
2062 "crand $CRD, $CRA, $CRB", IIC_BrCR,
2063 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2065 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2066 (ins crbitrc:$CRA, crbitrc:$CRB),
2067 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2068 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2070 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
2071 (ins crbitrc:$CRA, crbitrc:$CRB),
2072 "cror $CRD, $CRA, $CRB", IIC_BrCR,
2073 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2075 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
2076 (ins crbitrc:$CRA, crbitrc:$CRB),
2077 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2078 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2080 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
2081 (ins crbitrc:$CRA, crbitrc:$CRB),
2082 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2083 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2085 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
2086 (ins crbitrc:$CRA, crbitrc:$CRB),
2087 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2088 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2091 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2092 (ins crbitrc:$CRA, crbitrc:$CRB),
2093 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2094 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2096 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
2097 (ins crbitrc:$CRA, crbitrc:$CRB),
2098 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2099 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2101 let isCodeGenOnly = 1 in {
2102 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2103 "creqv $dst, $dst, $dst", IIC_BrCR,
2104 [(set i1:$dst, 1)]>;
2106 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2107 "crxor $dst, $dst, $dst", IIC_BrCR,
2108 [(set i1:$dst, 0)]>;
2110 let Defs = [CR1EQ], CRD = 6 in {
2111 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2112 "creqv 6, 6, 6", IIC_BrCR,
2115 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2116 "crxor 6, 6, 6", IIC_BrCR,
2121 // XFX-Form instructions. Instructions that deal with SPRs.
2124 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2125 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2126 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2127 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2129 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2130 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2132 // A pseudo-instruction used to implement the read of the 64-bit cycle counter
2133 // on a 32-bit target.
2134 let hasSideEffects = 1, usesCustomInserter = 1 in
2135 def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2138 let Uses = [CTR] in {
2139 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2140 "mfctr $rT", IIC_SprMFSPR>,
2141 PPC970_DGroup_First, PPC970_Unit_FXU;
2143 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2144 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2145 "mtctr $rS", IIC_SprMTSPR>,
2146 PPC970_DGroup_First, PPC970_Unit_FXU;
2148 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2149 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2150 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2151 "mtctr $rS", IIC_SprMTSPR>,
2152 PPC970_DGroup_First, PPC970_Unit_FXU;
2155 let Defs = [LR] in {
2156 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2157 "mtlr $rS", IIC_SprMTSPR>,
2158 PPC970_DGroup_First, PPC970_Unit_FXU;
2160 let Uses = [LR] in {
2161 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2162 "mflr $rT", IIC_SprMFSPR>,
2163 PPC970_DGroup_First, PPC970_Unit_FXU;
2166 let isCodeGenOnly = 1 in {
2167 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2168 // like a GPR on the PPC970. As such, copies in and out have the same
2169 // performance characteristics as an OR instruction.
2170 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2171 "mtspr 256, $rS", IIC_IntGeneral>,
2172 PPC970_DGroup_Single, PPC970_Unit_FXU;
2173 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2174 "mfspr $rT, 256", IIC_IntGeneral>,
2175 PPC970_DGroup_First, PPC970_Unit_FXU;
2177 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2178 (outs VRSAVERC:$reg), (ins gprc:$rS),
2179 "mtspr 256, $rS", IIC_IntGeneral>,
2180 PPC970_DGroup_Single, PPC970_Unit_FXU;
2181 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2182 (ins VRSAVERC:$reg),
2183 "mfspr $rT, 256", IIC_IntGeneral>,
2184 PPC970_DGroup_First, PPC970_Unit_FXU;
2187 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2188 // so we'll need to scavenge a register for it.
2190 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2191 "#SPILL_VRSAVE", []>;
2193 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2194 // spilled), so we'll need to scavenge a register for it.
2196 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2197 "#RESTORE_VRSAVE", []>;
2199 let hasSideEffects = 0 in {
2200 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2201 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2202 PPC970_DGroup_First, PPC970_Unit_CRU;
2204 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2205 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2206 PPC970_MicroCode, PPC970_Unit_CRU;
2208 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2209 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2210 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2211 PPC970_DGroup_First, PPC970_Unit_CRU;
2213 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2214 "mfcr $rT", IIC_SprMFCR>,
2215 PPC970_MicroCode, PPC970_Unit_CRU;
2216 } // hasSideEffects = 0
2218 // Pseudo instruction to perform FADD in round-to-zero mode.
2219 let usesCustomInserter = 1, Uses = [RM] in {
2220 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2221 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2224 // The above pseudo gets expanded to make use of the following instructions
2225 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2226 let Uses = [RM], Defs = [RM] in {
2227 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2228 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2229 PPC970_DGroup_Single, PPC970_Unit_FPU;
2230 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2231 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2232 PPC970_DGroup_Single, PPC970_Unit_FPU;
2233 let isCodeGenOnly = 1 in
2234 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2235 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2236 PPC970_DGroup_Single, PPC970_Unit_FPU;
2238 let Uses = [RM] in {
2239 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2240 "mffs $rT", IIC_IntMFFS,
2241 [(set f64:$rT, (PPCmffs))]>,
2242 PPC970_DGroup_Single, PPC970_Unit_FPU;
2245 def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2246 "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2250 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
2251 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2252 let isCommutable = 1 in
2253 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2254 "add", "$rT, $rA, $rB", IIC_IntSimple,
2255 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2256 let isCodeGenOnly = 1 in
2257 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2258 "add $rT, $rA, $rB", IIC_IntSimple,
2259 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2260 let isCommutable = 1 in
2261 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2262 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2263 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2264 PPC970_DGroup_Cracked;
2266 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2267 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2268 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2269 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2270 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2271 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2272 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2273 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2274 let isCommutable = 1 in {
2275 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2276 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2277 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2278 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2279 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2280 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2281 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2282 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2283 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2285 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2286 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2287 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2288 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2289 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2290 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2291 PPC970_DGroup_Cracked;
2292 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2293 "neg", "$rT, $rA", IIC_IntSimple,
2294 [(set i32:$rT, (ineg i32:$rA))]>;
2295 let Uses = [CARRY] in {
2296 let isCommutable = 1 in
2297 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2298 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2299 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2300 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2301 "addme", "$rT, $rA", IIC_IntGeneral,
2302 [(set i32:$rT, (adde i32:$rA, -1))]>;
2303 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2304 "addze", "$rT, $rA", IIC_IntGeneral,
2305 [(set i32:$rT, (adde i32:$rA, 0))]>;
2306 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2307 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2308 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2309 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2310 "subfme", "$rT, $rA", IIC_IntGeneral,
2311 [(set i32:$rT, (sube -1, i32:$rA))]>;
2312 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2313 "subfze", "$rT, $rA", IIC_IntGeneral,
2314 [(set i32:$rT, (sube 0, i32:$rA))]>;
2318 // A-Form instructions. Most of the instructions executed in the FPU are of
2321 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2322 let Uses = [RM] in {
2323 let isCommutable = 1 in {
2324 defm FMADD : AForm_1r<63, 29,
2325 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2326 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2327 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2328 defm FMADDS : AForm_1r<59, 29,
2329 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2330 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2331 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2332 defm FMSUB : AForm_1r<63, 28,
2333 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2334 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2336 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2337 defm FMSUBS : AForm_1r<59, 28,
2338 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2339 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2341 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2342 defm FNMADD : AForm_1r<63, 31,
2343 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2344 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2346 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2347 defm FNMADDS : AForm_1r<59, 31,
2348 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2349 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2351 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2352 defm FNMSUB : AForm_1r<63, 30,
2353 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2354 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2355 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2356 (fneg f64:$FRB))))]>;
2357 defm FNMSUBS : AForm_1r<59, 30,
2358 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2359 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2360 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2361 (fneg f32:$FRB))))]>;
2364 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2365 // having 4 of these, force the comparison to always be an 8-byte double (code
2366 // should use an FMRSD if the input comparison value really wants to be a float)
2367 // and 4/8 byte forms for the result and operand type..
2368 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2369 defm FSELD : AForm_1r<63, 23,
2370 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2371 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2372 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2373 defm FSELS : AForm_1r<63, 23,
2374 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2375 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2376 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2377 let Uses = [RM] in {
2378 let isCommutable = 1 in {
2379 defm FADD : AForm_2r<63, 21,
2380 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2381 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2382 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2383 defm FADDS : AForm_2r<59, 21,
2384 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2385 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2386 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2388 defm FDIV : AForm_2r<63, 18,
2389 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2390 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2391 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2392 defm FDIVS : AForm_2r<59, 18,
2393 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2394 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2395 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2396 let isCommutable = 1 in {
2397 defm FMUL : AForm_3r<63, 25,
2398 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2399 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2400 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2401 defm FMULS : AForm_3r<59, 25,
2402 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2403 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2404 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2406 defm FSUB : AForm_2r<63, 20,
2407 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2408 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2409 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2410 defm FSUBS : AForm_2r<59, 20,
2411 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2412 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2413 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2417 let hasSideEffects = 0 in {
2418 let PPC970_Unit = 1 in { // FXU Operations.
2420 def ISEL : AForm_4<31, 15,
2421 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2422 "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
2426 let PPC970_Unit = 1 in { // FXU Operations.
2427 // M-Form instructions. rotate and mask instructions.
2429 let isCommutable = 1 in {
2430 // RLWIMI can be commuted if the rotate amount is zero.
2431 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2432 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2433 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2434 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2435 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2437 let BaseName = "rlwinm" in {
2438 def RLWINM : MForm_2<21,
2439 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2440 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2443 def RLWINMo : MForm_2<21,
2444 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2445 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2446 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2448 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2449 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2450 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2453 } // hasSideEffects = 0
2455 //===----------------------------------------------------------------------===//
2456 // PowerPC Instruction Patterns
2459 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2460 def : Pat<(i32 imm:$imm),
2461 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2463 // Implement the 'not' operation with the NOR instruction.
2464 def i32not : OutPatFrag<(ops node:$in),
2466 def : Pat<(not i32:$in),
2469 // ADD an arbitrary immediate.
2470 def : Pat<(add i32:$in, imm:$imm),
2471 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2472 // OR an arbitrary immediate.
2473 def : Pat<(or i32:$in, imm:$imm),
2474 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2475 // XOR an arbitrary immediate.
2476 def : Pat<(xor i32:$in, imm:$imm),
2477 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2479 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2480 (SUBFIC $in, imm:$imm)>;
2483 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2484 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2485 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2486 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2489 def : Pat<(rotl i32:$in, i32:$sh),
2490 (RLWNM $in, $sh, 0, 31)>;
2491 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2492 (RLWINM $in, imm:$imm, 0, 31)>;
2495 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2496 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2499 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2500 (BL tglobaladdr:$dst)>;
2501 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2502 (BL texternalsym:$dst)>;
2504 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2505 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2507 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2508 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2510 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2511 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2515 // Hi and Lo for Darwin Global Addresses.
2516 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2517 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2518 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2519 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2520 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2521 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2522 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2523 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2524 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2525 (ADDIS $in, tglobaltlsaddr:$g)>;
2526 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2527 (ADDI $in, tglobaltlsaddr:$g)>;
2528 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2529 (ADDIS $in, tglobaladdr:$g)>;
2530 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2531 (ADDIS $in, tconstpool:$g)>;
2532 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2533 (ADDIS $in, tjumptable:$g)>;
2534 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2535 (ADDIS $in, tblockaddress:$g)>;
2537 // Support for thread-local storage.
2538 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2539 [(set i32:$rD, (PPCppc32GOT))]>;
2541 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2542 // This uses two output registers, the first as the real output, the second as a
2543 // temporary register, used internally in code generation.
2544 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2545 []>, NoEncode<"$rT">;
2547 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2550 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2551 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2552 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2554 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2557 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2558 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2559 // explicitly defined when this op is created, so not mentioned here.
2560 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2561 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2562 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2565 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2566 // Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR
2567 // are true defines while the rest of the Defs are clobbers.
2568 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2569 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2570 def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2571 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2572 "#ADDItlsgdLADDR32",
2574 (PPCaddiTlsgdLAddr i32:$reg,
2575 tglobaltlsaddr:$disp,
2576 tglobaltlsaddr:$sym))]>;
2577 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2580 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2581 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2582 // explicitly defined when this op is created, so not mentioned here.
2583 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2584 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2585 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2588 (PPCgetTlsldAddr i32:$reg,
2589 tglobaltlsaddr:$sym))]>;
2590 // Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR
2591 // are true defines while the rest of the Defs are clobbers.
2592 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2593 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2594 def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2595 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2596 "#ADDItlsldLADDR32",
2598 (PPCaddiTlsldLAddr i32:$reg,
2599 tglobaltlsaddr:$disp,
2600 tglobaltlsaddr:$sym))]>;
2601 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2604 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2605 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2608 (PPCaddisDtprelHA i32:$reg,
2609 tglobaltlsaddr:$disp))]>;
2611 // Support for Position-independent code
2612 def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2615 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2616 // Get Global (GOT) Base Register offset, from the word immediately preceding
2617 // the function label.
2618 def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2621 // Standard shifts. These are represented separately from the real shifts above
2622 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2624 def : Pat<(sra i32:$rS, i32:$rB),
2626 def : Pat<(srl i32:$rS, i32:$rB),
2628 def : Pat<(shl i32:$rS, i32:$rB),
2631 def : Pat<(zextloadi1 iaddr:$src),
2633 def : Pat<(zextloadi1 xaddr:$src),
2635 def : Pat<(extloadi1 iaddr:$src),
2637 def : Pat<(extloadi1 xaddr:$src),
2639 def : Pat<(extloadi8 iaddr:$src),
2641 def : Pat<(extloadi8 xaddr:$src),
2643 def : Pat<(extloadi16 iaddr:$src),
2645 def : Pat<(extloadi16 xaddr:$src),
2647 def : Pat<(f64 (extloadf32 iaddr:$src)),
2648 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2649 def : Pat<(f64 (extloadf32 xaddr:$src)),
2650 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2652 def : Pat<(f64 (fextend f32:$src)),
2653 (COPY_TO_REGCLASS $src, F8RC)>;
2655 // Only seq_cst fences require the heavyweight sync (SYNC 0).
2656 // All others can use the lightweight sync (SYNC 1).
2657 // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2658 // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2659 // versions of Power.
2660 def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2661 def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2662 def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2663 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2665 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2666 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2667 (FNMSUB $A, $C, $B)>;
2668 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2669 (FNMSUB $A, $C, $B)>;
2670 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2671 (FNMSUBS $A, $C, $B)>;
2672 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2673 (FNMSUBS $A, $C, $B)>;
2675 // FCOPYSIGN's operand types need not agree.
2676 def : Pat<(fcopysign f64:$frB, f32:$frA),
2677 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2678 def : Pat<(fcopysign f32:$frB, f64:$frA),
2679 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2681 include "PPCInstrAltivec.td"
2682 include "PPCInstrSPE.td"
2683 include "PPCInstr64Bit.td"
2684 include "PPCInstrVSX.td"
2685 include "PPCInstrQPX.td"
2687 def crnot : OutPatFrag<(ops node:$in),
2689 def : Pat<(not i1:$in),
2692 // Patterns for arithmetic i1 operations.
2693 def : Pat<(add i1:$a, i1:$b),
2695 def : Pat<(sub i1:$a, i1:$b),
2697 def : Pat<(mul i1:$a, i1:$b),
2700 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2701 // (-1 is used to mean all bits set).
2702 def : Pat<(i1 -1), (CRSET)>;
2704 // i1 extensions, implemented in terms of isel.
2705 def : Pat<(i32 (zext i1:$in)),
2706 (SELECT_I4 $in, (LI 1), (LI 0))>;
2707 def : Pat<(i32 (sext i1:$in)),
2708 (SELECT_I4 $in, (LI -1), (LI 0))>;
2710 def : Pat<(i64 (zext i1:$in)),
2711 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2712 def : Pat<(i64 (sext i1:$in)),
2713 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2715 // FIXME: We should choose either a zext or a sext based on other constants
2717 def : Pat<(i32 (anyext i1:$in)),
2718 (SELECT_I4 $in, (LI 1), (LI 0))>;
2719 def : Pat<(i64 (anyext i1:$in)),
2720 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2722 // match setcc on i1 variables.
2723 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2725 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2727 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2729 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2731 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2733 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2735 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2737 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2739 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2741 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2744 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2745 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2746 // floating-point types.
2748 multiclass CRNotPat<dag pattern, dag result> {
2749 def : Pat<pattern, (crnot result)>;
2750 def : Pat<(not pattern), result>;
2752 // We can also fold the crnot into an extension:
2753 def : Pat<(i32 (zext pattern)),
2754 (SELECT_I4 result, (LI 0), (LI 1))>;
2755 def : Pat<(i32 (sext pattern)),
2756 (SELECT_I4 result, (LI 0), (LI -1))>;
2758 // We can also fold the crnot into an extension:
2759 def : Pat<(i64 (zext pattern)),
2760 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2761 def : Pat<(i64 (sext pattern)),
2762 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2764 // FIXME: We should choose either a zext or a sext based on other constants
2766 def : Pat<(i32 (anyext pattern)),
2767 (SELECT_I4 result, (LI 0), (LI 1))>;
2769 def : Pat<(i64 (anyext pattern)),
2770 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2773 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2774 // we need to write imm:$imm in the output patterns below, not just $imm, or
2775 // else the resulting matcher will not correctly add the immediate operand
2776 // (making it a register operand instead).
2779 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2780 OutPatFrag rfrag, OutPatFrag rfrag8> {
2781 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2783 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2785 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2786 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2787 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2788 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2790 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2792 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2794 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2795 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2796 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2797 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2800 // Note that we do all inversions below with i(32|64)not, instead of using
2801 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2802 // has 2-cycle latency.
2804 defm : ExtSetCCPat<SETEQ,
2805 PatFrag<(ops node:$in, node:$cc),
2806 (setcc $in, 0, $cc)>,
2807 OutPatFrag<(ops node:$in),
2808 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2809 OutPatFrag<(ops node:$in),
2810 (RLDICL (CNTLZD $in), 58, 63)> >;
2812 defm : ExtSetCCPat<SETNE,
2813 PatFrag<(ops node:$in, node:$cc),
2814 (setcc $in, 0, $cc)>,
2815 OutPatFrag<(ops node:$in),
2816 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2817 OutPatFrag<(ops node:$in),
2818 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2820 defm : ExtSetCCPat<SETLT,
2821 PatFrag<(ops node:$in, node:$cc),
2822 (setcc $in, 0, $cc)>,
2823 OutPatFrag<(ops node:$in),
2824 (RLWINM $in, 1, 31, 31)>,
2825 OutPatFrag<(ops node:$in),
2826 (RLDICL $in, 1, 63)> >;
2828 defm : ExtSetCCPat<SETGE,
2829 PatFrag<(ops node:$in, node:$cc),
2830 (setcc $in, 0, $cc)>,
2831 OutPatFrag<(ops node:$in),
2832 (RLWINM (i32not $in), 1, 31, 31)>,
2833 OutPatFrag<(ops node:$in),
2834 (RLDICL (i64not $in), 1, 63)> >;
2836 defm : ExtSetCCPat<SETGT,
2837 PatFrag<(ops node:$in, node:$cc),
2838 (setcc $in, 0, $cc)>,
2839 OutPatFrag<(ops node:$in),
2840 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2841 OutPatFrag<(ops node:$in),
2842 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2844 defm : ExtSetCCPat<SETLE,
2845 PatFrag<(ops node:$in, node:$cc),
2846 (setcc $in, 0, $cc)>,
2847 OutPatFrag<(ops node:$in),
2848 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2849 OutPatFrag<(ops node:$in),
2850 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2852 defm : ExtSetCCPat<SETLT,
2853 PatFrag<(ops node:$in, node:$cc),
2854 (setcc $in, -1, $cc)>,
2855 OutPatFrag<(ops node:$in),
2856 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2857 OutPatFrag<(ops node:$in),
2858 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2860 defm : ExtSetCCPat<SETGE,
2861 PatFrag<(ops node:$in, node:$cc),
2862 (setcc $in, -1, $cc)>,
2863 OutPatFrag<(ops node:$in),
2864 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2865 OutPatFrag<(ops node:$in),
2866 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2868 defm : ExtSetCCPat<SETGT,
2869 PatFrag<(ops node:$in, node:$cc),
2870 (setcc $in, -1, $cc)>,
2871 OutPatFrag<(ops node:$in),
2872 (RLWINM (i32not $in), 1, 31, 31)>,
2873 OutPatFrag<(ops node:$in),
2874 (RLDICL (i64not $in), 1, 63)> >;
2876 defm : ExtSetCCPat<SETLE,
2877 PatFrag<(ops node:$in, node:$cc),
2878 (setcc $in, -1, $cc)>,
2879 OutPatFrag<(ops node:$in),
2880 (RLWINM $in, 1, 31, 31)>,
2881 OutPatFrag<(ops node:$in),
2882 (RLDICL $in, 1, 63)> >;
2885 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2886 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2887 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2888 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2889 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2890 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2891 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2892 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2893 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2894 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2895 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2896 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2898 // For non-equality comparisons, the default code would materialize the
2899 // constant, then compare against it, like this:
2901 // ori r2, r2, 22136
2904 // Since we are just comparing for equality, we can emit this instead:
2905 // xoris r0,r3,0x1234
2906 // cmplwi cr0,r0,0x5678
2909 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2910 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2911 (LO16 imm:$imm)), sub_eq)>;
2913 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2914 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2915 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2916 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2917 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2918 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2919 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2920 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2921 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2922 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2923 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2924 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2926 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2927 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2928 (LO16 imm:$imm)), sub_eq)>;
2930 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
2931 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2932 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2933 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2934 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2935 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2936 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
2937 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2938 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2939 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2941 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2942 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2943 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
2944 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2945 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2946 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2947 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
2948 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2949 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2950 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2953 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
2954 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2955 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2956 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2957 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2958 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2959 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
2960 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2961 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
2962 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2963 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
2964 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2966 // For non-equality comparisons, the default code would materialize the
2967 // constant, then compare against it, like this:
2969 // ori r2, r2, 22136
2972 // Since we are just comparing for equality, we can emit this instead:
2973 // xoris r0,r3,0x1234
2974 // cmpldi cr0,r0,0x5678
2977 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
2978 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2979 (LO16 imm:$imm)), sub_eq)>;
2981 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
2982 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2983 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
2984 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2985 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
2986 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2987 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
2988 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2989 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
2990 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2991 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
2992 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2994 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
2995 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2996 (LO16 imm:$imm)), sub_eq)>;
2998 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
2999 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3000 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3001 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3002 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3003 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3004 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3005 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3006 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3007 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3009 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3010 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3011 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3012 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3013 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3014 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3015 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
3016 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3017 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3018 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3021 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3022 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3023 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3024 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3025 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3026 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3027 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3028 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3029 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3030 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3031 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3032 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3033 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
3034 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3036 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3037 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3038 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3039 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3040 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3041 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3042 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3043 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3044 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3045 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3046 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3047 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3048 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3049 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3052 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3053 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3054 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3055 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3056 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3057 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3058 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3059 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3060 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3061 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3062 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3063 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3064 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3065 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3067 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3068 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3069 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3070 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3071 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3072 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3073 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3074 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3075 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3076 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3077 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3078 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3079 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3080 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3082 // match select on i1 variables:
3083 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3084 (CROR (CRAND $cond , $tval),
3085 (CRAND (crnot $cond), $fval))>;
3087 // match selectcc on i1 variables:
3088 // select (lhs == rhs), tval, fval is:
3089 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3090 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3091 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3092 (CRAND (CRORC $lhs, $rhs), $fval))>;
3093 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3094 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
3095 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3096 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3097 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3098 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3099 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3100 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
3101 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3102 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3103 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3104 (CRAND (CRORC $rhs, $lhs), $fval))>;
3105 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3106 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3107 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3109 // match selectcc on i1 variables with non-i1 output.
3110 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3111 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3112 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3113 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3114 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3115 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3116 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3117 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3118 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3119 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3120 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3121 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3123 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3124 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3125 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3126 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3127 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3128 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3129 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3130 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3131 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3132 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3133 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3134 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3136 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3137 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3138 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3139 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3140 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3141 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3142 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3143 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3144 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3145 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3146 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3147 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3149 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3150 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3151 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3152 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3153 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3154 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3155 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3156 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3157 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3158 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3159 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3160 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3162 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3163 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3164 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3165 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3166 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3167 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3168 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3169 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3170 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3171 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3172 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3173 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3175 let usesCustomInserter = 1 in {
3176 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3178 [(set i1:$dst, (trunc (not i32:$in)))]>;
3179 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3181 [(set i1:$dst, (trunc i32:$in))]>;
3183 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3185 [(set i1:$dst, (trunc (not i64:$in)))]>;
3186 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3188 [(set i1:$dst, (trunc i64:$in))]>;
3191 def : Pat<(i1 (not (trunc i32:$in))),
3192 (ANDIo_1_EQ_BIT $in)>;
3193 def : Pat<(i1 (not (trunc i64:$in))),
3194 (ANDIo_1_EQ_BIT8 $in)>;
3196 //===----------------------------------------------------------------------===//
3197 // PowerPC Instructions used for assembler/disassembler only
3200 // FIXME: For B=0 or B > 8, the registers following RT are used.
3201 // WARNING: Do not add patterns for this instruction without fixing this.
3202 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3203 "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3205 // FIXME: For B=0 or B > 8, the registers following RT are used.
3206 // WARNING: Do not add patterns for this instruction without fixing this.
3207 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3208 "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3210 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3211 "isync", IIC_SprISYNC, []>;
3213 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3214 "icbi $src", IIC_LdStICBI, []>;
3216 // We used to have EIEIO as value but E[0-9A-Z] is a reserved name
3217 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3218 "eieio", IIC_LdStLoad, []>;
3220 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3221 "wait $L", IIC_LdStLoad, []>;
3223 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3224 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3226 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3227 "mtsr $SR, $RS", IIC_SprMTSR>;
3229 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3230 "mfsr $RS, $SR", IIC_SprMFSR>;
3232 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3233 "mtsrin $RS, $RB", IIC_SprMTSR>;
3235 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3236 "mfsrin $RS, $RB", IIC_SprMFSR>;
3238 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3239 "mtmsr $RS, $L", IIC_SprMTMSR>;
3241 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3242 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3246 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3247 Requires<[IsBookE]> {
3251 let Inst{21-30} = 163;
3254 def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3255 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3256 def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3257 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3259 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3260 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3261 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3262 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3264 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3265 "mfmsr $RT", IIC_SprMFMSR, []>;
3267 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3268 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3270 def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
3271 "mcrfs $BF, $BFA", IIC_BrMCR>;
3273 def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3274 "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
3276 def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3277 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
3279 def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
3280 def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
3282 def MTFSF : XFLForm_1<63, 711, (outs),
3283 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3284 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
3285 def MTFSFo : XFLForm_1<63, 711, (outs),
3286 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3287 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
3289 def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3290 def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3292 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3293 "slbie $RB", IIC_SprSLBIE, []>;
3295 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3296 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3298 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3299 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3301 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3303 def TLBIA : XForm_0<31, 370, (outs), (ins),
3304 "tlbia", IIC_SprTLBIA, []>;
3306 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3307 "tlbsync", IIC_SprTLBSYNC, []>;
3309 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3310 "tlbiel $RB", IIC_SprTLBIEL, []>;
3312 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3313 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3314 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3315 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3317 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3318 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3320 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3321 IIC_LdStLoad>, Requires<[IsBookE]>;
3323 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3324 IIC_LdStLoad>, Requires<[IsBookE]>;
3326 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3327 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3329 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3330 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3332 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3333 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3335 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3336 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3338 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3339 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3340 Requires<[IsPPC4xx]>;
3341 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3342 (ins gprc:$RST, gprc:$A, gprc:$B),
3343 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3344 Requires<[IsPPC4xx]>, isDOT;
3346 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3348 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3349 Requires<[IsBookE]>;
3350 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3351 Requires<[IsBookE]>;
3353 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3355 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3358 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3359 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3360 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3361 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3363 def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3365 def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3366 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3367 def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3368 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3369 def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3370 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3371 def LDCIX : XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3372 "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3374 def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3375 "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3376 def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3377 "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3378 def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3379 "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3380 def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3381 "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3383 //===----------------------------------------------------------------------===//
3384 // PowerPC Assembler Instruction Aliases
3387 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3388 // These are aliases that require C++ handling to convert to the target
3389 // instruction, while InstAliases can be handled directly by tblgen.
3390 class PPCAsmPseudo<string asm, dag iops>
3392 let Namespace = "PPC";
3393 bit PPC64 = 0; // Default value, override with isPPC64
3395 let OutOperandList = (outs);
3396 let InOperandList = iops;
3398 let AsmString = asm;
3399 let isAsmParserOnly = 1;
3403 def : InstAlias<"sc", (SC 0)>;
3405 def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3406 def : InstAlias<"msync", (SYNC 0)>, Requires<[HasSYNC]>;
3407 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3408 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3410 def : InstAlias<"wait", (WAIT 0)>;
3411 def : InstAlias<"waitrsv", (WAIT 1)>;
3412 def : InstAlias<"waitimpl", (WAIT 2)>;
3414 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3416 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3417 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3418 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3419 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3421 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3422 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3424 def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3425 def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3427 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3428 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3430 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3431 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3433 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3434 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3436 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3437 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3439 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3440 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3442 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3443 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3445 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3446 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3448 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3449 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3451 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3452 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3454 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3455 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3457 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3458 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3460 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3461 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3463 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3464 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3465 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3467 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3468 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3470 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3471 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3472 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3473 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3475 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3477 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3478 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3480 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3481 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3483 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3485 foreach BATR = 0-3 in {
3486 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3487 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3488 Requires<[IsPPC6xx]>;
3489 def : InstAlias<"mfdbatu $Rx, "#BATR,
3490 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3491 Requires<[IsPPC6xx]>;
3492 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3493 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3494 Requires<[IsPPC6xx]>;
3495 def : InstAlias<"mfdbatl $Rx, "#BATR,
3496 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3497 Requires<[IsPPC6xx]>;
3498 def : InstAlias<"mtibatu "#BATR#", $Rx",
3499 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3500 Requires<[IsPPC6xx]>;
3501 def : InstAlias<"mfibatu $Rx, "#BATR,
3502 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3503 Requires<[IsPPC6xx]>;
3504 def : InstAlias<"mtibatl "#BATR#", $Rx",
3505 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3506 Requires<[IsPPC6xx]>;
3507 def : InstAlias<"mfibatl $Rx, "#BATR,
3508 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3509 Requires<[IsPPC6xx]>;
3512 foreach BR = 0-7 in {
3513 def : InstAlias<"mfbr"#BR#" $Rx",
3514 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3515 Requires<[IsPPC4xx]>;
3516 def : InstAlias<"mtbr"#BR#" $Rx",
3517 (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3518 Requires<[IsPPC4xx]>;
3521 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3522 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3524 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3525 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3527 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3528 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3530 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3531 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3533 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3534 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3536 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3537 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3539 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3541 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3542 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3543 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3544 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3545 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3546 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3547 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3548 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3550 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3551 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3552 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3553 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3555 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3556 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3558 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3559 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3561 foreach SPRG = 0-3 in {
3562 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3563 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3564 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3565 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3567 foreach SPRG = 4-7 in {
3568 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3569 Requires<[IsBookE]>;
3570 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3571 Requires<[IsBookE]>;
3572 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3573 Requires<[IsBookE]>;
3574 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3575 Requires<[IsBookE]>;
3578 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3580 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3581 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3583 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3585 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3586 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3588 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3589 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3590 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3591 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3593 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3595 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3596 Requires<[IsPPC4xx]>;
3597 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3598 Requires<[IsPPC4xx]>;
3599 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3600 Requires<[IsPPC4xx]>;
3601 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3602 Requires<[IsPPC4xx]>;
3604 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3605 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3606 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3607 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3608 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3609 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3610 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3611 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3612 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3613 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3614 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3615 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3616 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3617 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3618 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3619 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3620 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3621 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3622 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3623 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3624 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3625 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3626 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3627 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3628 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3629 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3630 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3631 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3632 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3633 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3634 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3635 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3636 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3637 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3638 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3639 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3641 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3642 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3643 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3644 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3645 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3646 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3648 def : InstAlias<"cntlz $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
3649 def : InstAlias<"cntlz. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
3651 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3652 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3653 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3654 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3655 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3656 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3657 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3658 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3659 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3660 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3661 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3662 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3663 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3664 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3665 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3666 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3667 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3668 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3669 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3670 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3671 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3672 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3673 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3674 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3675 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3676 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3677 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3678 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3679 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3680 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3681 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3682 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3684 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3685 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3686 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3687 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3688 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3689 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3691 // These generic branch instruction forms are used for the assembler parser only.
3692 // Defs and Uses are conservative, since we don't know the BO value.
3693 let PPC970_Unit = 7 in {
3694 let Defs = [CTR], Uses = [CTR, RM] in {
3695 def gBC : BForm_3<16, 0, 0, (outs),
3696 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3697 "bc $bo, $bi, $dst">;
3698 def gBCA : BForm_3<16, 1, 0, (outs),
3699 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3700 "bca $bo, $bi, $dst">;
3702 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3703 def gBCL : BForm_3<16, 0, 1, (outs),
3704 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3705 "bcl $bo, $bi, $dst">;
3706 def gBCLA : BForm_3<16, 1, 1, (outs),
3707 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3708 "bcla $bo, $bi, $dst">;
3710 let Defs = [CTR], Uses = [CTR, LR, RM] in
3711 def gBCLR : XLForm_2<19, 16, 0, (outs),
3712 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3713 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3714 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3715 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3716 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3717 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3718 let Defs = [CTR], Uses = [CTR, LR, RM] in
3719 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3720 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3721 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3722 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3723 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3724 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3725 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3727 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3728 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3729 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3730 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3732 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3733 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3734 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3735 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3736 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3737 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3738 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3740 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3741 : BranchSimpleMnemonic1<name, pm, bo> {
3742 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3743 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3745 defm : BranchSimpleMnemonic2<"t", "", 12>;
3746 defm : BranchSimpleMnemonic2<"f", "", 4>;
3747 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3748 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3749 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3750 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3751 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3752 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3753 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3754 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3756 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3757 def : InstAlias<"b"#name#pm#" $cc, $dst",
3758 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3759 def : InstAlias<"b"#name#pm#" $dst",
3760 (BCC bibo, CR0, condbrtarget:$dst)>;
3762 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3763 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3764 def : InstAlias<"b"#name#"a"#pm#" $dst",
3765 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3767 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3768 (BCCLR bibo, crrc:$cc)>;
3769 def : InstAlias<"b"#name#"lr"#pm,
3772 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3773 (BCCCTR bibo, crrc:$cc)>;
3774 def : InstAlias<"b"#name#"ctr"#pm,
3775 (BCCCTR bibo, CR0)>;
3777 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3778 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3779 def : InstAlias<"b"#name#"l"#pm#" $dst",
3780 (BCCL bibo, CR0, condbrtarget:$dst)>;
3782 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3783 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3784 def : InstAlias<"b"#name#"la"#pm#" $dst",
3785 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3787 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3788 (BCCLRL bibo, crrc:$cc)>;
3789 def : InstAlias<"b"#name#"lrl"#pm,
3790 (BCCLRL bibo, CR0)>;
3792 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3793 (BCCCTRL bibo, crrc:$cc)>;
3794 def : InstAlias<"b"#name#"ctrl"#pm,
3795 (BCCCTRL bibo, CR0)>;
3797 multiclass BranchExtendedMnemonic<string name, int bibo> {
3798 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3799 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3800 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3802 defm : BranchExtendedMnemonic<"lt", 12>;
3803 defm : BranchExtendedMnemonic<"gt", 44>;
3804 defm : BranchExtendedMnemonic<"eq", 76>;
3805 defm : BranchExtendedMnemonic<"un", 108>;
3806 defm : BranchExtendedMnemonic<"so", 108>;
3807 defm : BranchExtendedMnemonic<"ge", 4>;
3808 defm : BranchExtendedMnemonic<"nl", 4>;
3809 defm : BranchExtendedMnemonic<"le", 36>;
3810 defm : BranchExtendedMnemonic<"ng", 36>;
3811 defm : BranchExtendedMnemonic<"ne", 68>;
3812 defm : BranchExtendedMnemonic<"nu", 100>;
3813 defm : BranchExtendedMnemonic<"ns", 100>;
3815 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3816 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3817 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3818 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3819 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3820 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3821 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3822 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3824 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3825 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3826 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3827 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3828 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3829 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3830 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3831 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3833 multiclass TrapExtendedMnemonic<string name, int to> {
3834 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3835 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3836 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3837 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3839 defm : TrapExtendedMnemonic<"lt", 16>;
3840 defm : TrapExtendedMnemonic<"le", 20>;
3841 defm : TrapExtendedMnemonic<"eq", 4>;
3842 defm : TrapExtendedMnemonic<"ge", 12>;
3843 defm : TrapExtendedMnemonic<"gt", 8>;
3844 defm : TrapExtendedMnemonic<"nl", 12>;
3845 defm : TrapExtendedMnemonic<"ne", 24>;
3846 defm : TrapExtendedMnemonic<"ng", 20>;
3847 defm : TrapExtendedMnemonic<"llt", 2>;
3848 defm : TrapExtendedMnemonic<"lle", 6>;
3849 defm : TrapExtendedMnemonic<"lge", 5>;
3850 defm : TrapExtendedMnemonic<"lgt", 1>;
3851 defm : TrapExtendedMnemonic<"lnl", 5>;
3852 defm : TrapExtendedMnemonic<"lng", 6>;
3853 defm : TrapExtendedMnemonic<"u", 31>;
3856 def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>;
3857 def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>;
3858 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>;
3859 def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>;
3860 def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
3861 def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
3864 def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>;
3865 def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>;
3866 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>;
3867 def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
3868 def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
3869 def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;