1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 2, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
56 def SDT_PPCnop : SDTypeProfile<0, 0, []>;
58 //===----------------------------------------------------------------------===//
59 // PowerPC specific DAG Nodes.
62 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
63 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
64 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
65 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
66 [SDNPHasChain, SDNPMayStore]>;
68 // This sequence is used for long double->int conversions. It changes the
69 // bits in the FPSCR which is not modelled.
70 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
72 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
73 [SDNPInGlue, SDNPOutGlue]>;
74 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
75 [SDNPInGlue, SDNPOutGlue]>;
76 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
77 [SDNPInGlue, SDNPOutGlue]>;
78 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
83 def PPCfsel : SDNode<"PPCISD::FSEL",
84 // Type constraint for fsel.
85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
88 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
89 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
90 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
91 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
92 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
94 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
96 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
97 // amounts. These nodes are generated by the multi-precision shift code.
98 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
99 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
100 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
102 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
103 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
104 [SDNPHasChain, SDNPMayStore]>;
106 // These are target-independent nodes, but have target-specific formats.
107 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
108 [SDNPHasChain, SDNPOutGlue]>;
109 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
112 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
113 def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall,
114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
116 def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall,
117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def PPCcall_nop_SVR4 : SDNode<"PPCISD::CALL_NOP_SVR4", SDT_PPCCall,
120 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
122 def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInGlue, SDNPOutGlue]>;
123 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
125 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
126 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
127 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
128 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
129 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
131 def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone,
132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
135 def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone,
136 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
139 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
140 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
143 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
145 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
146 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
148 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
149 [SDNPHasChain, SDNPOptInGlue]>;
151 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
152 [SDNPHasChain, SDNPMayLoad]>;
153 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
154 [SDNPHasChain, SDNPMayStore]>;
156 // Instructions to support atomic operations
157 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
158 [SDNPHasChain, SDNPMayLoad]>;
159 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
160 [SDNPHasChain, SDNPMayStore]>;
162 // Instructions to support dynamic alloca.
163 def SDTDynOp : SDTypeProfile<1, 2, []>;
164 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
166 //===----------------------------------------------------------------------===//
167 // PowerPC specific transformation functions and pattern fragments.
170 def SHL32 : SDNodeXForm<imm, [{
171 // Transformation function: 31 - imm
172 return getI32Imm(31 - N->getZExtValue());
175 def SRL32 : SDNodeXForm<imm, [{
176 // Transformation function: 32 - imm
177 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
180 def LO16 : SDNodeXForm<imm, [{
181 // Transformation function: get the low 16 bits.
182 return getI32Imm((unsigned short)N->getZExtValue());
185 def HI16 : SDNodeXForm<imm, [{
186 // Transformation function: shift the immediate value down into the low bits.
187 return getI32Imm((unsigned)N->getZExtValue() >> 16);
190 def HA16 : SDNodeXForm<imm, [{
191 // Transformation function: shift the immediate value down into the low bits.
192 signed int Val = N->getZExtValue();
193 return getI32Imm((Val - (signed short)Val) >> 16);
195 def MB : SDNodeXForm<imm, [{
196 // Transformation function: get the start bit of a mask
198 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
199 return getI32Imm(mb);
202 def ME : SDNodeXForm<imm, [{
203 // Transformation function: get the end bit of a mask
205 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
206 return getI32Imm(me);
208 def maskimm32 : PatLeaf<(imm), [{
209 // maskImm predicate - True if immediate is a run of ones.
211 if (N->getValueType(0) == MVT::i32)
212 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
217 def immSExt16 : PatLeaf<(imm), [{
218 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
219 // field. Used by instructions like 'addi'.
220 if (N->getValueType(0) == MVT::i32)
221 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
223 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
225 def immZExt16 : PatLeaf<(imm), [{
226 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
227 // field. Used by instructions like 'ori'.
228 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
231 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
232 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
233 // identical in 32-bit mode, but in 64-bit mode, they return true if the
234 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
236 def imm16ShiftedZExt : PatLeaf<(imm), [{
237 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
238 // immediate are set. Used by instructions like 'xoris'.
239 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
242 def imm16ShiftedSExt : PatLeaf<(imm), [{
243 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
244 // immediate are set. Used by instructions like 'addis'. Identical to
245 // imm16ShiftedZExt in 32-bit mode.
246 if (N->getZExtValue() & 0xFFFF) return false;
247 if (N->getValueType(0) == MVT::i32)
249 // For 64-bit, make sure it is sext right.
250 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
254 //===----------------------------------------------------------------------===//
255 // PowerPC Flag Definitions.
257 class isPPC64 { bit PPC64 = 1; }
259 list<Register> Defs = [CR0];
263 class RegConstraint<string C> {
264 string Constraints = C;
266 class NoEncode<string E> {
267 string DisableEncoding = E;
271 //===----------------------------------------------------------------------===//
272 // PowerPC Operand Definitions.
274 def s5imm : Operand<i32> {
275 let PrintMethod = "printS5ImmOperand";
277 def u5imm : Operand<i32> {
278 let PrintMethod = "printU5ImmOperand";
280 def u6imm : Operand<i32> {
281 let PrintMethod = "printU6ImmOperand";
283 def s16imm : Operand<i32> {
284 let PrintMethod = "printS16ImmOperand";
286 def u16imm : Operand<i32> {
287 let PrintMethod = "printU16ImmOperand";
289 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
290 let PrintMethod = "printS16X4ImmOperand";
292 def directbrtarget : Operand<OtherVT> {
293 let PrintMethod = "printBranchOperand";
294 let EncoderMethod = "getDirectBrEncoding";
296 def condbrtarget : Operand<OtherVT> {
297 let PrintMethod = "printBranchOperand";
298 let EncoderMethod = "getCondBrEncoding";
300 def calltarget : Operand<iPTR> {
301 let EncoderMethod = "getDirectBrEncoding";
303 def aaddr : Operand<iPTR> {
304 let PrintMethod = "printAbsAddrOperand";
306 def symbolHi: Operand<i32> {
307 let PrintMethod = "printSymbolHi";
308 let EncoderMethod = "getHA16Encoding";
310 def symbolLo: Operand<i32> {
311 let PrintMethod = "printSymbolLo";
312 let EncoderMethod = "getLO16Encoding";
314 def crbitm: Operand<i8> {
315 let PrintMethod = "printcrbitm";
316 let EncoderMethod = "get_crbitm_encoding";
319 def memri : Operand<iPTR> {
320 let PrintMethod = "printMemRegImm";
321 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
322 let EncoderMethod = "getMemRIEncoding";
324 def memrr : Operand<iPTR> {
325 let PrintMethod = "printMemRegReg";
326 let MIOperandInfo = (ops ptr_rc, ptr_rc);
328 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
329 let PrintMethod = "printMemRegImmShifted";
330 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
331 let EncoderMethod = "getMemRIXEncoding";
333 def tocentry : Operand<iPTR> {
334 let MIOperandInfo = (ops i32imm:$imm);
337 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
338 // that doesn't matter.
339 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
340 (ops (i32 20), (i32 zero_reg))> {
341 let PrintMethod = "printPredicateOperand";
344 // Define PowerPC specific addressing mode.
345 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
346 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
347 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
348 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
350 /// This is just the offset part of iaddr, used for preinc.
351 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
353 //===----------------------------------------------------------------------===//
354 // PowerPC Instruction Predicate Definitions.
355 def FPContractions : Predicate<"!TM.Options.NoExcessFPPrecision">;
356 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
357 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
358 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
360 //===----------------------------------------------------------------------===//
361 // PowerPC Instruction Definitions.
363 // Pseudo-instructions:
365 let hasCtrlDep = 1 in {
366 let Defs = [R1], Uses = [R1] in {
367 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "",
368 [(callseq_start timm:$amt)]>;
369 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "",
370 [(callseq_end timm:$amt1, timm:$amt2)]>;
373 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
374 "UPDATE_VRSAVE $rD, $rS", []>;
377 let Defs = [R1], Uses = [R1] in
378 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "",
380 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
382 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
383 // instruction selection into a branch sequence.
384 let usesCustomInserter = 1, // Expanded after instruction selection.
385 PPC970_Single = 1 in {
386 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
389 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
392 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
395 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
398 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
403 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
404 // scavenge a register for it.
406 def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
409 // RESTORE_CR - Indicate that we're restoring the CR register (previously
410 // spilled), so we'll need to scavenge a register for it.
412 def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
415 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
416 let isReturn = 1, Uses = [LR, RM] in
417 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
418 "b${p:cc}lr ${p:reg}", BrB,
420 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
421 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
425 def MovePCtoLR : Pseudo<(outs), (ins), "", []>,
428 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
429 let isBarrier = 1 in {
430 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
435 // BCC represents an arbitrary conditional branch on a predicate.
436 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
437 // a two-value operand where a dag node expects two operands. :(
438 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
439 "b${cond:cc} ${cond:reg}, $dst"
440 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
444 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
445 // Convenient aliases for call instructions
447 def BL_Darwin : IForm<18, 0, 1,
448 (outs), (ins calltarget:$func, variable_ops),
449 "bl $func", BrB, []>; // See Pat patterns below.
450 def BLA_Darwin : IForm<18, 1, 1,
451 (outs), (ins aaddr:$func, variable_ops),
452 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>;
454 let Uses = [CTR, RM] in {
455 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
456 (outs), (ins variable_ops),
458 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>;
463 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
464 // Convenient aliases for call instructions
466 def BL_SVR4 : IForm<18, 0, 1,
467 (outs), (ins calltarget:$func, variable_ops),
468 "bl $func", BrB, []>; // See Pat patterns below.
469 def BLA_SVR4 : IForm<18, 1, 1,
470 (outs), (ins aaddr:$func, variable_ops),
472 [(PPCcall_SVR4 (i32 imm:$func))]>;
474 let Uses = [CTR, RM] in {
475 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1,
476 (outs), (ins variable_ops),
478 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>;
483 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
484 def TCRETURNdi :Pseudo< (outs),
485 (ins calltarget:$dst, i32imm:$offset, variable_ops),
486 "#TC_RETURNd $dst $offset",
490 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
491 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
492 "#TC_RETURNa $func $offset",
493 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
495 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
496 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops),
497 "#TC_RETURNr $dst $offset",
501 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
502 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
503 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
504 Requires<[In32BitMode]>;
508 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
509 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
510 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
515 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
516 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
517 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
522 // DCB* instructions.
523 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
524 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
525 PPC970_DGroup_Single;
526 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
527 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
528 PPC970_DGroup_Single;
529 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
530 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
531 PPC970_DGroup_Single;
532 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
533 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
534 PPC970_DGroup_Single;
535 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
536 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
537 PPC970_DGroup_Single;
538 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
539 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
540 PPC970_DGroup_Single;
541 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
542 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
543 PPC970_DGroup_Single;
544 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
545 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
546 PPC970_DGroup_Single;
549 let usesCustomInserter = 1 in {
550 let Defs = [CR0] in {
551 def ATOMIC_LOAD_ADD_I8 : Pseudo<
552 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
553 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
554 def ATOMIC_LOAD_SUB_I8 : Pseudo<
555 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
556 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
557 def ATOMIC_LOAD_AND_I8 : Pseudo<
558 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
559 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
560 def ATOMIC_LOAD_OR_I8 : Pseudo<
561 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
562 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
563 def ATOMIC_LOAD_XOR_I8 : Pseudo<
564 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
565 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
566 def ATOMIC_LOAD_NAND_I8 : Pseudo<
567 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
568 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
569 def ATOMIC_LOAD_ADD_I16 : Pseudo<
570 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
571 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
572 def ATOMIC_LOAD_SUB_I16 : Pseudo<
573 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
574 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
575 def ATOMIC_LOAD_AND_I16 : Pseudo<
576 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
577 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
578 def ATOMIC_LOAD_OR_I16 : Pseudo<
579 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
580 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
581 def ATOMIC_LOAD_XOR_I16 : Pseudo<
582 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
583 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
584 def ATOMIC_LOAD_NAND_I16 : Pseudo<
585 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
586 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
587 def ATOMIC_LOAD_ADD_I32 : Pseudo<
588 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
589 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
590 def ATOMIC_LOAD_SUB_I32 : Pseudo<
591 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
592 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
593 def ATOMIC_LOAD_AND_I32 : Pseudo<
594 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
595 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
596 def ATOMIC_LOAD_OR_I32 : Pseudo<
597 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
598 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
599 def ATOMIC_LOAD_XOR_I32 : Pseudo<
600 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
601 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
602 def ATOMIC_LOAD_NAND_I32 : Pseudo<
603 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
604 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
606 def ATOMIC_CMP_SWAP_I8 : Pseudo<
607 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
609 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
610 def ATOMIC_CMP_SWAP_I16 : Pseudo<
611 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
613 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
614 def ATOMIC_CMP_SWAP_I32 : Pseudo<
615 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
617 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
619 def ATOMIC_SWAP_I8 : Pseudo<
620 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
621 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
622 def ATOMIC_SWAP_I16 : Pseudo<
623 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
624 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
625 def ATOMIC_SWAP_I32 : Pseudo<
626 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
627 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
631 // Instructions to support atomic operations
632 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
633 "lwarx $rD, $src", LdStLWARX,
634 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
637 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
638 "stwcx. $rS, $dst", LdStSTWCX,
639 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
642 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
643 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>;
645 //===----------------------------------------------------------------------===//
646 // PPC32 Load Instructions.
649 // Unindexed (r+i) Loads.
650 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
651 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
652 "lbz $rD, $src", LdStGeneral,
653 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
654 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
655 "lha $rD, $src", LdStLHA,
656 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
657 PPC970_DGroup_Cracked;
658 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
659 "lhz $rD, $src", LdStGeneral,
660 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
661 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
662 "lwz $rD, $src", LdStGeneral,
663 [(set GPRC:$rD, (load iaddr:$src))]>;
665 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
666 "lfs $rD, $src", LdStLFDU,
667 [(set F4RC:$rD, (load iaddr:$src))]>;
668 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
669 "lfd $rD, $src", LdStLFD,
670 [(set F8RC:$rD, (load iaddr:$src))]>;
673 // Unindexed (r+i) Loads with Update (preinc).
675 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
676 "lbzu $rD, $addr", LdStGeneral,
677 []>, RegConstraint<"$addr.reg = $ea_result">,
678 NoEncode<"$ea_result">;
680 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
681 "lhau $rD, $addr", LdStGeneral,
682 []>, RegConstraint<"$addr.reg = $ea_result">,
683 NoEncode<"$ea_result">;
685 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
686 "lhzu $rD, $addr", LdStGeneral,
687 []>, RegConstraint<"$addr.reg = $ea_result">,
688 NoEncode<"$ea_result">;
690 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
691 "lwzu $rD, $addr", LdStGeneral,
692 []>, RegConstraint<"$addr.reg = $ea_result">,
693 NoEncode<"$ea_result">;
695 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
696 "lfs $rD, $addr", LdStLFDU,
697 []>, RegConstraint<"$addr.reg = $ea_result">,
698 NoEncode<"$ea_result">;
700 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
701 "lfd $rD, $addr", LdStLFD,
702 []>, RegConstraint<"$addr.reg = $ea_result">,
703 NoEncode<"$ea_result">;
707 // Indexed (r+r) Loads.
709 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
710 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
711 "lbzx $rD, $src", LdStGeneral,
712 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
713 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
714 "lhax $rD, $src", LdStLHA,
715 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
716 PPC970_DGroup_Cracked;
717 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
718 "lhzx $rD, $src", LdStGeneral,
719 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
720 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
721 "lwzx $rD, $src", LdStGeneral,
722 [(set GPRC:$rD, (load xaddr:$src))]>;
725 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
726 "lhbrx $rD, $src", LdStGeneral,
727 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>;
728 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
729 "lwbrx $rD, $src", LdStGeneral,
730 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>;
732 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
733 "lfsx $frD, $src", LdStLFDU,
734 [(set F4RC:$frD, (load xaddr:$src))]>;
735 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
736 "lfdx $frD, $src", LdStLFDU,
737 [(set F8RC:$frD, (load xaddr:$src))]>;
740 //===----------------------------------------------------------------------===//
741 // PPC32 Store Instructions.
744 // Unindexed (r+i) Stores.
745 let PPC970_Unit = 2 in {
746 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
747 "stb $rS, $src", LdStGeneral,
748 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
749 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
750 "sth $rS, $src", LdStGeneral,
751 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
752 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
753 "stw $rS, $src", LdStGeneral,
754 [(store GPRC:$rS, iaddr:$src)]>;
755 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
756 "stfs $rS, $dst", LdStUX,
757 [(store F4RC:$rS, iaddr:$dst)]>;
758 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
759 "stfd $rS, $dst", LdStUX,
760 [(store F8RC:$rS, iaddr:$dst)]>;
763 // Unindexed (r+i) Stores with Update (preinc).
764 let PPC970_Unit = 2 in {
765 def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
766 symbolLo:$ptroff, ptr_rc:$ptrreg),
767 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
768 [(set ptr_rc:$ea_res,
769 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
770 iaddroff:$ptroff))]>,
771 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
772 def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
773 symbolLo:$ptroff, ptr_rc:$ptrreg),
774 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
775 [(set ptr_rc:$ea_res,
776 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
777 iaddroff:$ptroff))]>,
778 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
779 def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
780 symbolLo:$ptroff, ptr_rc:$ptrreg),
781 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
782 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
783 iaddroff:$ptroff))]>,
784 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
785 def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
786 symbolLo:$ptroff, ptr_rc:$ptrreg),
787 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
788 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
789 iaddroff:$ptroff))]>,
790 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
791 def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
792 symbolLo:$ptroff, ptr_rc:$ptrreg),
793 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
794 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
795 iaddroff:$ptroff))]>,
796 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
800 // Indexed (r+r) Stores.
802 let PPC970_Unit = 2 in {
803 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
804 "stbx $rS, $dst", LdStGeneral,
805 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
806 PPC970_DGroup_Cracked;
807 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
808 "sthx $rS, $dst", LdStGeneral,
809 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
810 PPC970_DGroup_Cracked;
811 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
812 "stwx $rS, $dst", LdStGeneral,
813 [(store GPRC:$rS, xaddr:$dst)]>,
814 PPC970_DGroup_Cracked;
816 let mayStore = 1 in {
817 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
818 "stwux $rS, $rA, $rB", LdStGeneral,
821 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
822 "sthbrx $rS, $dst", LdStGeneral,
823 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>,
824 PPC970_DGroup_Cracked;
825 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
826 "stwbrx $rS, $dst", LdStGeneral,
827 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>,
828 PPC970_DGroup_Cracked;
830 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
831 "stfiwx $frS, $dst", LdStUX,
832 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
834 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
835 "stfsx $frS, $dst", LdStUX,
836 [(store F4RC:$frS, xaddr:$dst)]>;
837 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
838 "stfdx $frS, $dst", LdStUX,
839 [(store F8RC:$frS, xaddr:$dst)]>;
842 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
846 //===----------------------------------------------------------------------===//
847 // PPC32 Arithmetic Instructions.
850 let PPC970_Unit = 1 in { // FXU Operations.
851 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
852 "addi $rD, $rA, $imm", IntGeneral,
853 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
854 let Defs = [CARRY] in {
855 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
856 "addic $rD, $rA, $imm", IntGeneral,
857 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
858 PPC970_DGroup_Cracked;
859 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
860 "addic. $rD, $rA, $imm", IntGeneral,
863 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
864 "addis $rD, $rA, $imm", IntGeneral,
865 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
866 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
867 "la $rD, $sym($rA)", IntGeneral,
868 [(set GPRC:$rD, (add GPRC:$rA,
869 (PPClo tglobaladdr:$sym, 0)))]>;
870 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
871 "mulli $rD, $rA, $imm", IntMulLI,
872 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
873 let Defs = [CARRY] in {
874 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
875 "subfic $rD, $rA, $imm", IntGeneral,
876 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
879 let isReMaterializable = 1 in {
880 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
881 "li $rD, $imm", IntGeneral,
882 [(set GPRC:$rD, immSExt16:$imm)]>;
883 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
884 "lis $rD, $imm", IntGeneral,
885 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
889 let PPC970_Unit = 1 in { // FXU Operations.
890 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
891 "andi. $dst, $src1, $src2", IntGeneral,
892 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
894 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
895 "andis. $dst, $src1, $src2", IntGeneral,
896 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
898 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
899 "ori $dst, $src1, $src2", IntGeneral,
900 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
901 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
902 "oris $dst, $src1, $src2", IntGeneral,
903 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
904 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
905 "xori $dst, $src1, $src2", IntGeneral,
906 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
907 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
908 "xoris $dst, $src1, $src2", IntGeneral,
909 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
910 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
912 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
913 "cmpwi $crD, $rA, $imm", IntCompare>;
914 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
915 "cmplwi $dst, $src1, $src2", IntCompare>;
919 let PPC970_Unit = 1 in { // FXU Operations.
920 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
921 "nand $rA, $rS, $rB", IntGeneral,
922 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
923 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
924 "and $rA, $rS, $rB", IntGeneral,
925 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
926 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
927 "andc $rA, $rS, $rB", IntGeneral,
928 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
929 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
930 "or $rA, $rS, $rB", IntGeneral,
931 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
932 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
933 "nor $rA, $rS, $rB", IntGeneral,
934 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
935 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
936 "orc $rA, $rS, $rB", IntGeneral,
937 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
938 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
939 "eqv $rA, $rS, $rB", IntGeneral,
940 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
941 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
942 "xor $rA, $rS, $rB", IntGeneral,
943 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
944 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
945 "slw $rA, $rS, $rB", IntGeneral,
946 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
947 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
948 "srw $rA, $rS, $rB", IntGeneral,
949 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
950 let Defs = [CARRY] in {
951 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
952 "sraw $rA, $rS, $rB", IntShift,
953 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
957 let PPC970_Unit = 1 in { // FXU Operations.
958 let Defs = [CARRY] in {
959 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
960 "srawi $rA, $rS, $SH", IntShift,
961 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
963 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
964 "cntlzw $rA, $rS", IntGeneral,
965 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
966 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
967 "extsb $rA, $rS", IntGeneral,
968 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
969 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
970 "extsh $rA, $rS", IntGeneral,
971 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
973 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
974 "cmpw $crD, $rA, $rB", IntCompare>;
975 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
976 "cmplw $crD, $rA, $rB", IntCompare>;
978 let PPC970_Unit = 3 in { // FPU Operations.
979 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
980 // "fcmpo $crD, $fA, $fB", FPCompare>;
981 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
982 "fcmpu $crD, $fA, $fB", FPCompare>;
983 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
984 "fcmpu $crD, $fA, $fB", FPCompare>;
987 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
988 "fctiwz $frD, $frB", FPGeneral,
989 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
990 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
991 "frsp $frD, $frB", FPGeneral,
992 [(set F4RC:$frD, (fround F8RC:$frB))]>;
993 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
994 "fsqrt $frD, $frB", FPSqrt,
995 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
996 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
997 "fsqrts $frD, $frB", FPSqrt,
998 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
1002 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1003 /// often coalesced away and we don't want the dispatch group builder to think
1004 /// that they will fill slots (which could cause the load of a LSU reject to
1005 /// sneak into a d-group with a store).
1006 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1007 "fmr $frD, $frB", FPGeneral,
1008 []>, // (set F4RC:$frD, F4RC:$frB)
1011 let PPC970_Unit = 3 in { // FPU Operations.
1012 // These are artificially split into two different forms, for 4/8 byte FP.
1013 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1014 "fabs $frD, $frB", FPGeneral,
1015 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
1016 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1017 "fabs $frD, $frB", FPGeneral,
1018 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
1019 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1020 "fnabs $frD, $frB", FPGeneral,
1021 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
1022 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1023 "fnabs $frD, $frB", FPGeneral,
1024 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
1025 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1026 "fneg $frD, $frB", FPGeneral,
1027 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
1028 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1029 "fneg $frD, $frB", FPGeneral,
1030 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
1034 // XL-Form instructions. condition register logical ops.
1036 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1037 "mcrf $BF, $BFA", BrMCR>,
1038 PPC970_DGroup_First, PPC970_Unit_CRU;
1040 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1041 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1042 "creqv $CRD, $CRA, $CRB", BrCR,
1045 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1046 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1047 "cror $CRD, $CRA, $CRB", BrCR,
1050 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1051 "creqv $dst, $dst, $dst", BrCR,
1054 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins),
1055 "crxor $dst, $dst, $dst", BrCR,
1058 // XFX-Form instructions. Instructions that deal with SPRs.
1060 let Uses = [CTR] in {
1061 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1062 "mfctr $rT", SprMFSPR>,
1063 PPC970_DGroup_First, PPC970_Unit_FXU;
1065 let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in {
1066 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1067 "mtctr $rS", SprMTSPR>,
1068 PPC970_DGroup_First, PPC970_Unit_FXU;
1071 let Defs = [LR] in {
1072 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1073 "mtlr $rS", SprMTSPR>,
1074 PPC970_DGroup_First, PPC970_Unit_FXU;
1076 let Uses = [LR] in {
1077 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1078 "mflr $rT", SprMFSPR>,
1079 PPC970_DGroup_First, PPC970_Unit_FXU;
1082 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1083 // a GPR on the PPC970. As such, copies in and out have the same performance
1084 // characteristics as an OR instruction.
1085 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1086 "mtspr 256, $rS", IntGeneral>,
1087 PPC970_DGroup_Single, PPC970_Unit_FXU;
1088 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1089 "mfspr $rT, 256", IntGeneral>,
1090 PPC970_DGroup_First, PPC970_Unit_FXU;
1092 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
1093 "mtcrf $FXM, $rS", BrMCRX>,
1094 PPC970_MicroCode, PPC970_Unit_CRU;
1096 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1097 // declaring that here gives the local register allocator problems with this:
1099 // MFCR <kill of whatever preg got assigned to vreg>
1100 // while not declaring it breaks DeadMachineInstructionElimination.
1101 // As it turns out, in all cases where we currently use this,
1102 // we're only interested in one subregister of it. Represent this in the
1103 // instruction to keep the register allocator from becoming confused.
1105 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1106 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1108 PPC970_MicroCode, PPC970_Unit_CRU;
1110 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1111 "mfcr $rT", SprMFCR>,
1112 PPC970_MicroCode, PPC970_Unit_CRU;
1114 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1115 "mfcr $rT, $FXM", SprMFCR>,
1116 PPC970_DGroup_First, PPC970_Unit_CRU;
1118 // Instructions to manipulate FPSCR. Only long double handling uses these.
1119 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1121 let Uses = [RM], Defs = [RM] in {
1122 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1123 "mtfsb0 $FM", IntMTFSB0,
1124 [(PPCmtfsb0 (i32 imm:$FM))]>,
1125 PPC970_DGroup_Single, PPC970_Unit_FPU;
1126 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1127 "mtfsb1 $FM", IntMTFSB0,
1128 [(PPCmtfsb1 (i32 imm:$FM))]>,
1129 PPC970_DGroup_Single, PPC970_Unit_FPU;
1130 // MTFSF does not actually produce an FP result. We pretend it copies
1131 // input reg B to the output. If we didn't do this it would look like the
1132 // instruction had no outputs (because we aren't modelling the FPSCR) and
1133 // it would be deleted.
1134 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1135 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1136 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1137 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1138 F8RC:$rT, F8RC:$FRB))]>,
1139 PPC970_DGroup_Single, PPC970_Unit_FPU;
1141 let Uses = [RM] in {
1142 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1143 "mffs $rT", IntMFFS,
1144 [(set F8RC:$rT, (PPCmffs))]>,
1145 PPC970_DGroup_Single, PPC970_Unit_FPU;
1146 def FADDrtz: AForm_2<63, 21,
1147 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1148 "fadd $FRT, $FRA, $FRB", FPGeneral,
1149 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1150 PPC970_DGroup_Single, PPC970_Unit_FPU;
1154 let PPC970_Unit = 1 in { // FXU Operations.
1156 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1158 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1159 "add $rT, $rA, $rB", IntGeneral,
1160 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1161 let Defs = [CARRY] in {
1162 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1163 "addc $rT, $rA, $rB", IntGeneral,
1164 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1165 PPC970_DGroup_Cracked;
1167 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1168 "divw $rT, $rA, $rB", IntDivW,
1169 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1170 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1171 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1172 "divwu $rT, $rA, $rB", IntDivW,
1173 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1174 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1175 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1176 "mulhw $rT, $rA, $rB", IntMulHW,
1177 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1178 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1179 "mulhwu $rT, $rA, $rB", IntMulHWU,
1180 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1181 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1182 "mullw $rT, $rA, $rB", IntMulHW,
1183 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1184 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1185 "subf $rT, $rA, $rB", IntGeneral,
1186 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1187 let Defs = [CARRY] in {
1188 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1189 "subfc $rT, $rA, $rB", IntGeneral,
1190 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1191 PPC970_DGroup_Cracked;
1193 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1194 "neg $rT, $rA", IntGeneral,
1195 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1196 let Uses = [CARRY], Defs = [CARRY] in {
1197 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1198 "adde $rT, $rA, $rB", IntGeneral,
1199 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1200 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1201 "addme $rT, $rA", IntGeneral,
1202 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>;
1203 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1204 "addze $rT, $rA", IntGeneral,
1205 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1206 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1207 "subfe $rT, $rA, $rB", IntGeneral,
1208 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1209 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1210 "subfme $rT, $rA", IntGeneral,
1211 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>;
1212 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1213 "subfze $rT, $rA", IntGeneral,
1214 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1218 // A-Form instructions. Most of the instructions executed in the FPU are of
1221 let PPC970_Unit = 3 in { // FPU Operations.
1222 let Uses = [RM] in {
1223 def FMADD : AForm_1<63, 29,
1224 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1225 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1226 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1228 Requires<[FPContractions]>;
1229 def FMADDS : AForm_1<59, 29,
1230 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1231 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1232 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1234 Requires<[FPContractions]>;
1235 def FMSUB : AForm_1<63, 28,
1236 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1237 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1238 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1240 Requires<[FPContractions]>;
1241 def FMSUBS : AForm_1<59, 28,
1242 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1243 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1244 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1246 Requires<[FPContractions]>;
1247 def FNMADD : AForm_1<63, 31,
1248 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1249 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1250 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1252 Requires<[FPContractions]>;
1253 def FNMADDS : AForm_1<59, 31,
1254 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1255 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1256 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1258 Requires<[FPContractions]>;
1259 def FNMSUB : AForm_1<63, 30,
1260 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1261 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1262 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1264 Requires<[FPContractions]>;
1265 def FNMSUBS : AForm_1<59, 30,
1266 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1267 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1268 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1270 Requires<[FPContractions]>;
1272 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1273 // having 4 of these, force the comparison to always be an 8-byte double (code
1274 // should use an FMRSD if the input comparison value really wants to be a float)
1275 // and 4/8 byte forms for the result and operand type..
1276 def FSELD : AForm_1<63, 23,
1277 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1278 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1279 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1280 def FSELS : AForm_1<63, 23,
1281 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1282 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1283 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1284 let Uses = [RM] in {
1285 def FADD : AForm_2<63, 21,
1286 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1287 "fadd $FRT, $FRA, $FRB", FPGeneral,
1288 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1289 def FADDS : AForm_2<59, 21,
1290 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1291 "fadds $FRT, $FRA, $FRB", FPGeneral,
1292 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1293 def FDIV : AForm_2<63, 18,
1294 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1295 "fdiv $FRT, $FRA, $FRB", FPDivD,
1296 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1297 def FDIVS : AForm_2<59, 18,
1298 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1299 "fdivs $FRT, $FRA, $FRB", FPDivS,
1300 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1301 def FMUL : AForm_3<63, 25,
1302 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1303 "fmul $FRT, $FRA, $FRB", FPFused,
1304 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1305 def FMULS : AForm_3<59, 25,
1306 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1307 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1308 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1309 def FSUB : AForm_2<63, 20,
1310 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1311 "fsub $FRT, $FRA, $FRB", FPGeneral,
1312 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1313 def FSUBS : AForm_2<59, 20,
1314 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1315 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1316 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1320 let PPC970_Unit = 1 in { // FXU Operations.
1321 // M-Form instructions. rotate and mask instructions.
1323 let isCommutable = 1 in {
1324 // RLWIMI can be commuted if the rotate amount is zero.
1325 def RLWIMI : MForm_2<20,
1326 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1327 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1328 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1331 def RLWINM : MForm_2<21,
1332 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1333 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1335 def RLWINMo : MForm_2<21,
1336 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1337 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1338 []>, isDOT, PPC970_DGroup_Cracked;
1339 def RLWNM : MForm_2<23,
1340 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1341 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1346 //===----------------------------------------------------------------------===//
1347 // PowerPC Instruction Patterns
1350 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1351 def : Pat<(i32 imm:$imm),
1352 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1354 // Implement the 'not' operation with the NOR instruction.
1355 def NOT : Pat<(not GPRC:$in),
1356 (NOR GPRC:$in, GPRC:$in)>;
1358 // ADD an arbitrary immediate.
1359 def : Pat<(add GPRC:$in, imm:$imm),
1360 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1361 // OR an arbitrary immediate.
1362 def : Pat<(or GPRC:$in, imm:$imm),
1363 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1364 // XOR an arbitrary immediate.
1365 def : Pat<(xor GPRC:$in, imm:$imm),
1366 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1368 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1369 (SUBFIC GPRC:$in, imm:$imm)>;
1372 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1373 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1374 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1375 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1378 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1379 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1380 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1381 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1384 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1385 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1388 def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)),
1389 (BL_Darwin tglobaladdr:$dst)>;
1390 def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)),
1391 (BL_Darwin texternalsym:$dst)>;
1392 def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)),
1393 (BL_SVR4 tglobaladdr:$dst)>;
1394 def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)),
1395 (BL_SVR4 texternalsym:$dst)>;
1398 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1399 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1401 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1402 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1404 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1405 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1409 // Hi and Lo for Darwin Global Addresses.
1410 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1411 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1412 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1413 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1414 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1415 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1416 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1417 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1418 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1419 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1420 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1421 (ADDIS GPRC:$in, tconstpool:$g)>;
1422 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1423 (ADDIS GPRC:$in, tjumptable:$g)>;
1424 def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)),
1425 (ADDIS GPRC:$in, tblockaddress:$g)>;
1427 // Fused negative multiply subtract, alternate pattern
1428 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1429 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1430 Requires<[FPContractions]>;
1431 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1432 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1433 Requires<[FPContractions]>;
1435 // Standard shifts. These are represented separately from the real shifts above
1436 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1438 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1439 (SRAW GPRC:$rS, GPRC:$rB)>;
1440 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1441 (SRW GPRC:$rS, GPRC:$rB)>;
1442 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1443 (SLW GPRC:$rS, GPRC:$rB)>;
1445 def : Pat<(zextloadi1 iaddr:$src),
1447 def : Pat<(zextloadi1 xaddr:$src),
1449 def : Pat<(extloadi1 iaddr:$src),
1451 def : Pat<(extloadi1 xaddr:$src),
1453 def : Pat<(extloadi8 iaddr:$src),
1455 def : Pat<(extloadi8 xaddr:$src),
1457 def : Pat<(extloadi16 iaddr:$src),
1459 def : Pat<(extloadi16 xaddr:$src),
1461 def : Pat<(f64 (extloadf32 iaddr:$src)),
1462 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1463 def : Pat<(f64 (extloadf32 xaddr:$src)),
1464 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1466 def : Pat<(f64 (fextend F4RC:$src)),
1467 (COPY_TO_REGCLASS F4RC:$src, F8RC)>;
1470 def : Pat<(membarrier (i32 imm /*ll*/),
1474 (i32 imm /*device*/)),
1477 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
1479 include "PPCInstrAltivec.td"
1480 include "PPCInstr64Bit.td"