1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
50 SDTCisPtrTy<0>, SDTCisVT<1, i32>
53 def tocentry32 : Operand<iPTR> {
54 let MIOperandInfo = (ops i32imm:$imm);
57 def SDT_PPCqvfperm : SDTypeProfile<1, 3, [
58 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>
60 def SDT_PPCqvgpci : SDTypeProfile<1, 1, [
61 SDTCisVec<0>, SDTCisInt<1>
63 def SDT_PPCqvaligni : SDTypeProfile<1, 3, [
64 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>
66 def SDT_PPCqvesplati : SDTypeProfile<1, 2, [
67 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
70 def SDT_PPCqbflt : SDTypeProfile<1, 1, [
71 SDTCisVec<0>, SDTCisVec<1>
74 def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
75 SDTCisVec<0>, SDTCisPtrTy<1>
78 //===----------------------------------------------------------------------===//
79 // PowerPC specific DAG Nodes.
82 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
83 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
85 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
86 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
87 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
88 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
89 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
90 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
91 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
92 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
93 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
94 [SDNPHasChain, SDNPMayStore]>;
95 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
96 [SDNPHasChain, SDNPMayLoad]>;
97 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
98 [SDNPHasChain, SDNPMayLoad]>;
100 // Extract FPSCR (not modeled at the DAG level).
101 def PPCmffs : SDNode<"PPCISD::MFFS",
102 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
104 // Perform FADD in round-to-zero mode.
105 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
108 def PPCfsel : SDNode<"PPCISD::FSEL",
109 // Type constraint for fsel.
110 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
111 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
113 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
114 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
115 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp,
116 [SDNPMayLoad, SDNPMemOperand]>;
117 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
118 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
120 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
122 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
123 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
125 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
126 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
127 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
128 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
129 def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
130 SDTypeProfile<1, 3, [
131 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
132 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
133 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
134 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
135 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
136 def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
137 SDTypeProfile<1, 3, [
138 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
139 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
140 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
141 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
143 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
145 def PPCqvfperm : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
146 def PPCqvgpci : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
147 def PPCqvaligni : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
148 def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;
150 def PPCqbflt : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>;
152 def PPCqvlfsb : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb,
153 [SDNPHasChain, SDNPMayLoad]>;
155 def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
157 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
158 // amounts. These nodes are generated by the multi-precision shift code.
159 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
160 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
161 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
163 // These are target-independent nodes, but have target-specific formats.
164 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
165 [SDNPHasChain, SDNPOutGlue]>;
166 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
167 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
169 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
170 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
171 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
173 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
174 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
176 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
177 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
178 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
179 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
181 def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
182 SDTypeProfile<0, 1, []>,
183 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
186 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
187 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
189 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
190 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
192 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
193 SDTypeProfile<1, 1, [SDTCisInt<0>,
195 [SDNPHasChain, SDNPSideEffect]>;
196 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
197 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
198 [SDNPHasChain, SDNPSideEffect]>;
200 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
201 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
202 [SDNPHasChain, SDNPSideEffect]>;
204 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
205 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
207 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
208 [SDNPHasChain, SDNPOptInGlue]>;
210 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
211 [SDNPHasChain, SDNPMayLoad]>;
212 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
213 [SDNPHasChain, SDNPMayStore]>;
215 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
216 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
217 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
218 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
219 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
221 // Instructions to support dynamic alloca.
222 def SDTDynOp : SDTypeProfile<1, 2, []>;
223 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
225 //===----------------------------------------------------------------------===//
226 // PowerPC specific transformation functions and pattern fragments.
229 def SHL32 : SDNodeXForm<imm, [{
230 // Transformation function: 31 - imm
231 return getI32Imm(31 - N->getZExtValue());
234 def SRL32 : SDNodeXForm<imm, [{
235 // Transformation function: 32 - imm
236 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
239 def LO16 : SDNodeXForm<imm, [{
240 // Transformation function: get the low 16 bits.
241 return getI32Imm((unsigned short)N->getZExtValue());
244 def HI16 : SDNodeXForm<imm, [{
245 // Transformation function: shift the immediate value down into the low bits.
246 return getI32Imm((unsigned)N->getZExtValue() >> 16);
249 def HA16 : SDNodeXForm<imm, [{
250 // Transformation function: shift the immediate value down into the low bits.
251 signed int Val = N->getZExtValue();
252 return getI32Imm((Val - (signed short)Val) >> 16);
254 def MB : SDNodeXForm<imm, [{
255 // Transformation function: get the start bit of a mask
257 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
258 return getI32Imm(mb);
261 def ME : SDNodeXForm<imm, [{
262 // Transformation function: get the end bit of a mask
264 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
265 return getI32Imm(me);
267 def maskimm32 : PatLeaf<(imm), [{
268 // maskImm predicate - True if immediate is a run of ones.
270 if (N->getValueType(0) == MVT::i32)
271 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
276 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
277 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
278 // sign extended field. Used by instructions like 'addi'.
279 return (int32_t)Imm == (short)Imm;
281 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
282 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
283 // sign extended field. Used by instructions like 'addi'.
284 return (int64_t)Imm == (short)Imm;
286 def immZExt16 : PatLeaf<(imm), [{
287 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
288 // field. Used by instructions like 'ori'.
289 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
292 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
293 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
294 // identical in 32-bit mode, but in 64-bit mode, they return true if the
295 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
297 def imm16ShiftedZExt : PatLeaf<(imm), [{
298 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
299 // immediate are set. Used by instructions like 'xoris'.
300 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
303 def imm16ShiftedSExt : PatLeaf<(imm), [{
304 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
305 // immediate are set. Used by instructions like 'addis'. Identical to
306 // imm16ShiftedZExt in 32-bit mode.
307 if (N->getZExtValue() & 0xFFFF) return false;
308 if (N->getValueType(0) == MVT::i32)
310 // For 64-bit, make sure it is sext right.
311 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
314 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
315 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
316 // zero extended field.
317 return isUInt<32>(Imm);
320 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
321 // restricted memrix (4-aligned) constants are alignment sensitive. If these
322 // offsets are hidden behind TOC entries than the values of the lower-order
323 // bits cannot be checked directly. As a result, we need to also incorporate
324 // an alignment check into the relevant patterns.
326 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
327 return cast<LoadSDNode>(N)->getAlignment() >= 4;
329 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
330 (store node:$val, node:$ptr), [{
331 return cast<StoreSDNode>(N)->getAlignment() >= 4;
333 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
334 return cast<LoadSDNode>(N)->getAlignment() >= 4;
336 def aligned4pre_store : PatFrag<
337 (ops node:$val, node:$base, node:$offset),
338 (pre_store node:$val, node:$base, node:$offset), [{
339 return cast<StoreSDNode>(N)->getAlignment() >= 4;
342 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
343 return cast<LoadSDNode>(N)->getAlignment() < 4;
345 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
346 (store node:$val, node:$ptr), [{
347 return cast<StoreSDNode>(N)->getAlignment() < 4;
349 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
350 return cast<LoadSDNode>(N)->getAlignment() < 4;
353 //===----------------------------------------------------------------------===//
354 // PowerPC Flag Definitions.
356 class isPPC64 { bit PPC64 = 1; }
357 class isDOT { bit RC = 1; }
359 class RegConstraint<string C> {
360 string Constraints = C;
362 class NoEncode<string E> {
363 string DisableEncoding = E;
367 //===----------------------------------------------------------------------===//
368 // PowerPC Operand Definitions.
370 // In the default PowerPC assembler syntax, registers are specified simply
371 // by number, so they cannot be distinguished from immediate values (without
372 // looking at the opcode). This means that the default operand matching logic
373 // for the asm parser does not work, and we need to specify custom matchers.
374 // Since those can only be specified with RegisterOperand classes and not
375 // directly on the RegisterClass, all instructions patterns used by the asm
376 // parser need to use a RegisterOperand (instead of a RegisterClass) for
377 // all their register operands.
378 // For this purpose, we define one RegisterOperand for each RegisterClass,
379 // using the same name as the class, just in lower case.
381 def PPCRegGPRCAsmOperand : AsmOperandClass {
382 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
384 def gprc : RegisterOperand<GPRC> {
385 let ParserMatchClass = PPCRegGPRCAsmOperand;
387 def PPCRegG8RCAsmOperand : AsmOperandClass {
388 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
390 def g8rc : RegisterOperand<G8RC> {
391 let ParserMatchClass = PPCRegG8RCAsmOperand;
393 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
394 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
396 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
397 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
399 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
400 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
402 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
403 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
405 def PPCRegF8RCAsmOperand : AsmOperandClass {
406 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
408 def f8rc : RegisterOperand<F8RC> {
409 let ParserMatchClass = PPCRegF8RCAsmOperand;
411 def PPCRegF4RCAsmOperand : AsmOperandClass {
412 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
414 def f4rc : RegisterOperand<F4RC> {
415 let ParserMatchClass = PPCRegF4RCAsmOperand;
417 def PPCRegVRRCAsmOperand : AsmOperandClass {
418 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
420 def vrrc : RegisterOperand<VRRC> {
421 let ParserMatchClass = PPCRegVRRCAsmOperand;
423 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
424 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
426 def crbitrc : RegisterOperand<CRBITRC> {
427 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
429 def PPCRegCRRCAsmOperand : AsmOperandClass {
430 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
432 def crrc : RegisterOperand<CRRC> {
433 let ParserMatchClass = PPCRegCRRCAsmOperand;
435 def crrc0 : RegisterOperand<CRRC0> {
436 let ParserMatchClass = PPCRegCRRCAsmOperand;
439 def PPCU1ImmAsmOperand : AsmOperandClass {
440 let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
441 let RenderMethod = "addImmOperands";
443 def u1imm : Operand<i32> {
444 let PrintMethod = "printU1ImmOperand";
445 let ParserMatchClass = PPCU1ImmAsmOperand;
448 def PPCU2ImmAsmOperand : AsmOperandClass {
449 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
450 let RenderMethod = "addImmOperands";
452 def u2imm : Operand<i32> {
453 let PrintMethod = "printU2ImmOperand";
454 let ParserMatchClass = PPCU2ImmAsmOperand;
457 def PPCU3ImmAsmOperand : AsmOperandClass {
458 let Name = "U3Imm"; let PredicateMethod = "isU3Imm";
459 let RenderMethod = "addImmOperands";
461 def u3imm : Operand<i32> {
462 let PrintMethod = "printU3ImmOperand";
463 let ParserMatchClass = PPCU3ImmAsmOperand;
466 def PPCU4ImmAsmOperand : AsmOperandClass {
467 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
468 let RenderMethod = "addImmOperands";
470 def u4imm : Operand<i32> {
471 let PrintMethod = "printU4ImmOperand";
472 let ParserMatchClass = PPCU4ImmAsmOperand;
474 def PPCS5ImmAsmOperand : AsmOperandClass {
475 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
476 let RenderMethod = "addImmOperands";
478 def s5imm : Operand<i32> {
479 let PrintMethod = "printS5ImmOperand";
480 let ParserMatchClass = PPCS5ImmAsmOperand;
481 let DecoderMethod = "decodeSImmOperand<5>";
483 def PPCU5ImmAsmOperand : AsmOperandClass {
484 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
485 let RenderMethod = "addImmOperands";
487 def u5imm : Operand<i32> {
488 let PrintMethod = "printU5ImmOperand";
489 let ParserMatchClass = PPCU5ImmAsmOperand;
490 let DecoderMethod = "decodeUImmOperand<5>";
492 def PPCU6ImmAsmOperand : AsmOperandClass {
493 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
494 let RenderMethod = "addImmOperands";
496 def u6imm : Operand<i32> {
497 let PrintMethod = "printU6ImmOperand";
498 let ParserMatchClass = PPCU6ImmAsmOperand;
499 let DecoderMethod = "decodeUImmOperand<6>";
501 def PPCU12ImmAsmOperand : AsmOperandClass {
502 let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
503 let RenderMethod = "addImmOperands";
505 def u12imm : Operand<i32> {
506 let PrintMethod = "printU12ImmOperand";
507 let ParserMatchClass = PPCU12ImmAsmOperand;
508 let DecoderMethod = "decodeUImmOperand<12>";
510 def PPCS16ImmAsmOperand : AsmOperandClass {
511 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
512 let RenderMethod = "addS16ImmOperands";
514 def s16imm : Operand<i32> {
515 let PrintMethod = "printS16ImmOperand";
516 let EncoderMethod = "getImm16Encoding";
517 let ParserMatchClass = PPCS16ImmAsmOperand;
518 let DecoderMethod = "decodeSImmOperand<16>";
520 def PPCU16ImmAsmOperand : AsmOperandClass {
521 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
522 let RenderMethod = "addU16ImmOperands";
524 def u16imm : Operand<i32> {
525 let PrintMethod = "printU16ImmOperand";
526 let EncoderMethod = "getImm16Encoding";
527 let ParserMatchClass = PPCU16ImmAsmOperand;
528 let DecoderMethod = "decodeUImmOperand<16>";
530 def PPCS17ImmAsmOperand : AsmOperandClass {
531 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
532 let RenderMethod = "addS16ImmOperands";
534 def s17imm : Operand<i32> {
535 // This operand type is used for addis/lis to allow the assembler parser
536 // to accept immediates in the range -65536..65535 for compatibility with
537 // the GNU assembler. The operand is treated as 16-bit otherwise.
538 let PrintMethod = "printS16ImmOperand";
539 let EncoderMethod = "getImm16Encoding";
540 let ParserMatchClass = PPCS17ImmAsmOperand;
541 let DecoderMethod = "decodeSImmOperand<16>";
543 def PPCDirectBrAsmOperand : AsmOperandClass {
544 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
545 let RenderMethod = "addBranchTargetOperands";
547 def directbrtarget : Operand<OtherVT> {
548 let PrintMethod = "printBranchOperand";
549 let EncoderMethod = "getDirectBrEncoding";
550 let ParserMatchClass = PPCDirectBrAsmOperand;
552 def absdirectbrtarget : Operand<OtherVT> {
553 let PrintMethod = "printAbsBranchOperand";
554 let EncoderMethod = "getAbsDirectBrEncoding";
555 let ParserMatchClass = PPCDirectBrAsmOperand;
557 def PPCCondBrAsmOperand : AsmOperandClass {
558 let Name = "CondBr"; let PredicateMethod = "isCondBr";
559 let RenderMethod = "addBranchTargetOperands";
561 def condbrtarget : Operand<OtherVT> {
562 let PrintMethod = "printBranchOperand";
563 let EncoderMethod = "getCondBrEncoding";
564 let ParserMatchClass = PPCCondBrAsmOperand;
566 def abscondbrtarget : Operand<OtherVT> {
567 let PrintMethod = "printAbsBranchOperand";
568 let EncoderMethod = "getAbsCondBrEncoding";
569 let ParserMatchClass = PPCCondBrAsmOperand;
571 def calltarget : Operand<iPTR> {
572 let PrintMethod = "printBranchOperand";
573 let EncoderMethod = "getDirectBrEncoding";
574 let ParserMatchClass = PPCDirectBrAsmOperand;
576 def abscalltarget : Operand<iPTR> {
577 let PrintMethod = "printAbsBranchOperand";
578 let EncoderMethod = "getAbsDirectBrEncoding";
579 let ParserMatchClass = PPCDirectBrAsmOperand;
581 def PPCCRBitMaskOperand : AsmOperandClass {
582 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
584 def crbitm: Operand<i8> {
585 let PrintMethod = "printcrbitm";
586 let EncoderMethod = "get_crbitm_encoding";
587 let DecoderMethod = "decodeCRBitMOperand";
588 let ParserMatchClass = PPCCRBitMaskOperand;
591 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
592 def PPCRegGxRCNoR0Operand : AsmOperandClass {
593 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
595 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
596 let ParserMatchClass = PPCRegGxRCNoR0Operand;
598 // A version of ptr_rc usable with the asm parser.
599 def PPCRegGxRCOperand : AsmOperandClass {
600 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
602 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
603 let ParserMatchClass = PPCRegGxRCOperand;
606 def PPCDispRIOperand : AsmOperandClass {
607 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
608 let RenderMethod = "addS16ImmOperands";
610 def dispRI : Operand<iPTR> {
611 let ParserMatchClass = PPCDispRIOperand;
613 def PPCDispRIXOperand : AsmOperandClass {
614 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
615 let RenderMethod = "addImmOperands";
617 def dispRIX : Operand<iPTR> {
618 let ParserMatchClass = PPCDispRIXOperand;
620 def PPCDispSPE8Operand : AsmOperandClass {
621 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
622 let RenderMethod = "addImmOperands";
624 def dispSPE8 : Operand<iPTR> {
625 let ParserMatchClass = PPCDispSPE8Operand;
627 def PPCDispSPE4Operand : AsmOperandClass {
628 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
629 let RenderMethod = "addImmOperands";
631 def dispSPE4 : Operand<iPTR> {
632 let ParserMatchClass = PPCDispSPE4Operand;
634 def PPCDispSPE2Operand : AsmOperandClass {
635 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
636 let RenderMethod = "addImmOperands";
638 def dispSPE2 : Operand<iPTR> {
639 let ParserMatchClass = PPCDispSPE2Operand;
642 def memri : Operand<iPTR> {
643 let PrintMethod = "printMemRegImm";
644 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
645 let EncoderMethod = "getMemRIEncoding";
646 let DecoderMethod = "decodeMemRIOperands";
648 def memrr : Operand<iPTR> {
649 let PrintMethod = "printMemRegReg";
650 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
652 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
653 let PrintMethod = "printMemRegImm";
654 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
655 let EncoderMethod = "getMemRIXEncoding";
656 let DecoderMethod = "decodeMemRIXOperands";
658 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
659 let PrintMethod = "printMemRegImm";
660 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
661 let EncoderMethod = "getSPE8DisEncoding";
663 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
664 let PrintMethod = "printMemRegImm";
665 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
666 let EncoderMethod = "getSPE4DisEncoding";
668 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
669 let PrintMethod = "printMemRegImm";
670 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
671 let EncoderMethod = "getSPE2DisEncoding";
674 // A single-register address. This is used with the SjLj
675 // pseudo-instructions.
676 def memr : Operand<iPTR> {
677 let MIOperandInfo = (ops ptr_rc:$ptrreg);
679 def PPCTLSRegOperand : AsmOperandClass {
680 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
681 let RenderMethod = "addTLSRegOperands";
683 def tlsreg32 : Operand<i32> {
684 let EncoderMethod = "getTLSRegEncoding";
685 let ParserMatchClass = PPCTLSRegOperand;
687 def tlsgd32 : Operand<i32> {}
688 def tlscall32 : Operand<i32> {
689 let PrintMethod = "printTLSCall";
690 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
691 let EncoderMethod = "getTLSCallEncoding";
694 // PowerPC Predicate operand.
695 def pred : Operand<OtherVT> {
696 let PrintMethod = "printPredicateOperand";
697 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
700 // Define PowerPC specific addressing mode.
701 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
702 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
703 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
704 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
706 // The address in a single register. This is used with the SjLj
707 // pseudo-instructions.
708 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
710 /// This is just the offset part of iaddr, used for preinc.
711 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
713 //===----------------------------------------------------------------------===//
714 // PowerPC Instruction Predicate Definitions.
715 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
716 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
717 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
718 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
719 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
720 def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
721 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
722 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
723 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
724 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
725 def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
726 def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
727 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
728 def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">;
730 //===----------------------------------------------------------------------===//
731 // PowerPC Multiclass Definitions.
733 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
734 string asmbase, string asmstr, InstrItinClass itin,
736 let BaseName = asmbase in {
737 def NAME : XForm_6<opcode, xo, OOL, IOL,
738 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
739 pattern>, RecFormRel;
741 def o : XForm_6<opcode, xo, OOL, IOL,
742 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
743 []>, isDOT, RecFormRel;
747 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
748 string asmbase, string asmstr, InstrItinClass itin,
750 let BaseName = asmbase in {
751 let Defs = [CARRY] in
752 def NAME : XForm_6<opcode, xo, OOL, IOL,
753 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
754 pattern>, RecFormRel;
755 let Defs = [CARRY, CR0] in
756 def o : XForm_6<opcode, xo, OOL, IOL,
757 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
758 []>, isDOT, RecFormRel;
762 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
763 string asmbase, string asmstr, InstrItinClass itin,
765 let BaseName = asmbase in {
766 let Defs = [CARRY] in
767 def NAME : XForm_10<opcode, xo, OOL, IOL,
768 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
769 pattern>, RecFormRel;
770 let Defs = [CARRY, CR0] in
771 def o : XForm_10<opcode, xo, OOL, IOL,
772 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
773 []>, isDOT, RecFormRel;
777 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
778 string asmbase, string asmstr, InstrItinClass itin,
780 let BaseName = asmbase in {
781 def NAME : XForm_11<opcode, xo, OOL, IOL,
782 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
783 pattern>, RecFormRel;
785 def o : XForm_11<opcode, xo, OOL, IOL,
786 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
787 []>, isDOT, RecFormRel;
791 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
792 string asmbase, string asmstr, InstrItinClass itin,
794 let BaseName = asmbase in {
795 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
796 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
797 pattern>, RecFormRel;
799 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
800 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
801 []>, isDOT, RecFormRel;
805 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
806 string asmbase, string asmstr, InstrItinClass itin,
808 let BaseName = asmbase in {
809 let Defs = [CARRY] in
810 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
811 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
812 pattern>, RecFormRel;
813 let Defs = [CARRY, CR0] in
814 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
815 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
816 []>, isDOT, RecFormRel;
820 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
821 string asmbase, string asmstr, InstrItinClass itin,
823 let BaseName = asmbase in {
824 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
825 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
826 pattern>, RecFormRel;
828 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
829 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
830 []>, isDOT, RecFormRel;
834 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
835 string asmbase, string asmstr, InstrItinClass itin,
837 let BaseName = asmbase in {
838 let Defs = [CARRY] in
839 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
840 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
841 pattern>, RecFormRel;
842 let Defs = [CARRY, CR0] in
843 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
844 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
845 []>, isDOT, RecFormRel;
849 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
850 string asmbase, string asmstr, InstrItinClass itin,
852 let BaseName = asmbase in {
853 def NAME : MForm_2<opcode, OOL, IOL,
854 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
855 pattern>, RecFormRel;
857 def o : MForm_2<opcode, OOL, IOL,
858 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
859 []>, isDOT, RecFormRel;
863 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
864 string asmbase, string asmstr, InstrItinClass itin,
866 let BaseName = asmbase in {
867 def NAME : MDForm_1<opcode, xo, OOL, IOL,
868 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
869 pattern>, RecFormRel;
871 def o : MDForm_1<opcode, xo, OOL, IOL,
872 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
873 []>, isDOT, RecFormRel;
877 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
878 string asmbase, string asmstr, InstrItinClass itin,
880 let BaseName = asmbase in {
881 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
882 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
883 pattern>, RecFormRel;
885 def o : MDSForm_1<opcode, xo, OOL, IOL,
886 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
887 []>, isDOT, RecFormRel;
891 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
892 string asmbase, string asmstr, InstrItinClass itin,
894 let BaseName = asmbase in {
895 let Defs = [CARRY] in
896 def NAME : XSForm_1<opcode, xo, OOL, IOL,
897 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
898 pattern>, RecFormRel;
899 let Defs = [CARRY, CR0] in
900 def o : XSForm_1<opcode, xo, OOL, IOL,
901 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
902 []>, isDOT, RecFormRel;
906 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
907 string asmbase, string asmstr, InstrItinClass itin,
909 let BaseName = asmbase in {
910 def NAME : XForm_26<opcode, xo, OOL, IOL,
911 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
912 pattern>, RecFormRel;
914 def o : XForm_26<opcode, xo, OOL, IOL,
915 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
916 []>, isDOT, RecFormRel;
920 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
921 string asmbase, string asmstr, InstrItinClass itin,
923 let BaseName = asmbase in {
924 def NAME : XForm_28<opcode, xo, OOL, IOL,
925 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
926 pattern>, RecFormRel;
928 def o : XForm_28<opcode, xo, OOL, IOL,
929 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
930 []>, isDOT, RecFormRel;
934 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
935 string asmbase, string asmstr, InstrItinClass itin,
937 let BaseName = asmbase in {
938 def NAME : AForm_1<opcode, xo, OOL, IOL,
939 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
940 pattern>, RecFormRel;
942 def o : AForm_1<opcode, xo, OOL, IOL,
943 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
944 []>, isDOT, RecFormRel;
948 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
949 string asmbase, string asmstr, InstrItinClass itin,
951 let BaseName = asmbase in {
952 def NAME : AForm_2<opcode, xo, OOL, IOL,
953 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
954 pattern>, RecFormRel;
956 def o : AForm_2<opcode, xo, OOL, IOL,
957 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
958 []>, isDOT, RecFormRel;
962 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
963 string asmbase, string asmstr, InstrItinClass itin,
965 let BaseName = asmbase in {
966 def NAME : AForm_3<opcode, xo, OOL, IOL,
967 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
968 pattern>, RecFormRel;
970 def o : AForm_3<opcode, xo, OOL, IOL,
971 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
972 []>, isDOT, RecFormRel;
976 //===----------------------------------------------------------------------===//
977 // PowerPC Instruction Definitions.
979 // Pseudo-instructions:
981 let hasCtrlDep = 1 in {
982 let Defs = [R1], Uses = [R1] in {
983 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
984 [(callseq_start timm:$amt)]>;
985 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
986 [(callseq_end timm:$amt1, timm:$amt2)]>;
989 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
990 "UPDATE_VRSAVE $rD, $rS", []>;
993 let Defs = [R1], Uses = [R1] in
994 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
996 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
998 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
999 // instruction selection into a branch sequence.
1000 let usesCustomInserter = 1, // Expanded after instruction selection.
1001 PPC970_Single = 1 in {
1002 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
1003 // because either operand might become the first operand in an isel, and
1004 // that operand cannot be r0.
1005 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1006 gprc_nor0:$T, gprc_nor0:$F,
1007 i32imm:$BROPC), "#SELECT_CC_I4",
1009 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1010 g8rc_nox0:$T, g8rc_nox0:$F,
1011 i32imm:$BROPC), "#SELECT_CC_I8",
1013 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1014 i32imm:$BROPC), "#SELECT_CC_F4",
1016 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1017 i32imm:$BROPC), "#SELECT_CC_F8",
1019 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1020 i32imm:$BROPC), "#SELECT_CC_VRRC",
1023 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
1024 // register bit directly.
1025 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1026 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
1027 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
1028 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1029 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
1030 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
1031 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1032 f4rc:$T, f4rc:$F), "#SELECT_F4",
1033 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
1034 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1035 f8rc:$T, f8rc:$F), "#SELECT_F8",
1036 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1037 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1038 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
1040 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
1043 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
1044 // scavenge a register for it.
1045 let mayStore = 1 in {
1046 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1048 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1049 "#SPILL_CRBIT", []>;
1052 // RESTORE_CR - Indicate that we're restoring the CR register (previously
1053 // spilled), so we'll need to scavenge a register for it.
1054 let mayLoad = 1 in {
1055 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1057 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1058 "#RESTORE_CRBIT", []>;
1061 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1062 let isReturn = 1, Uses = [LR, RM] in
1063 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1064 [(retflag)]>, Requires<[In32BitMode]>;
1065 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1066 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1069 let isCodeGenOnly = 1 in {
1070 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1071 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1074 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1075 "bcctr 12, $bi, 0", IIC_BrB, []>;
1076 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1077 "bcctr 4, $bi, 0", IIC_BrB, []>;
1083 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1086 def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1089 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1090 let isBarrier = 1 in {
1091 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1094 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1095 "ba $dst", IIC_BrB, []>;
1098 // BCC represents an arbitrary conditional branch on a predicate.
1099 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1100 // a two-value operand where a dag node expects two operands. :(
1101 let isCodeGenOnly = 1 in {
1102 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1103 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1104 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1105 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1106 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1108 let isReturn = 1, Uses = [LR, RM] in
1109 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1110 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1113 let isCodeGenOnly = 1 in {
1114 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1115 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1116 "bc 12, $bi, $dst">;
1118 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1119 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1122 let isReturn = 1, Uses = [LR, RM] in
1123 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1124 "bclr 12, $bi, 0", IIC_BrB, []>;
1125 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1126 "bclr 4, $bi, 0", IIC_BrB, []>;
1129 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1130 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1131 "bdzlr", IIC_BrB, []>;
1132 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1133 "bdnzlr", IIC_BrB, []>;
1134 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1135 "bdzlr+", IIC_BrB, []>;
1136 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1137 "bdnzlr+", IIC_BrB, []>;
1138 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1139 "bdzlr-", IIC_BrB, []>;
1140 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1141 "bdnzlr-", IIC_BrB, []>;
1144 let Defs = [CTR], Uses = [CTR] in {
1145 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1147 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1149 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1151 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1153 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1155 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1157 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1159 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1161 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1163 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1165 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1167 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1172 // The unconditional BCL used by the SjLj setjmp code.
1173 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1174 let Defs = [LR], Uses = [RM] in {
1175 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1176 "bcl 20, 31, $dst">;
1180 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1181 // Convenient aliases for call instructions
1182 let Uses = [RM] in {
1183 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1184 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1185 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1186 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1188 let isCodeGenOnly = 1 in {
1189 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1190 "bl $func", IIC_BrB, []>;
1191 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1192 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1193 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1194 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1196 def BCL : BForm_4<16, 12, 0, 1, (outs),
1197 (ins crbitrc:$bi, condbrtarget:$dst),
1198 "bcl 12, $bi, $dst">;
1199 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1200 (ins crbitrc:$bi, condbrtarget:$dst),
1201 "bcl 4, $bi, $dst">;
1204 let Uses = [CTR, RM] in {
1205 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1206 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1207 Requires<[In32BitMode]>;
1209 let isCodeGenOnly = 1 in {
1210 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1211 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1214 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1215 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1216 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1217 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1220 let Uses = [LR, RM] in {
1221 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1222 "blrl", IIC_BrB, []>;
1224 let isCodeGenOnly = 1 in {
1225 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1226 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1229 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1230 "bclrl 12, $bi, 0", IIC_BrB, []>;
1231 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1232 "bclrl 4, $bi, 0", IIC_BrB, []>;
1235 let Defs = [CTR], Uses = [CTR, RM] in {
1236 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1238 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1240 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1242 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1244 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1246 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1248 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1250 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1252 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1254 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1256 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1258 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1261 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1262 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1263 "bdzlrl", IIC_BrB, []>;
1264 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1265 "bdnzlrl", IIC_BrB, []>;
1266 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1267 "bdzlrl+", IIC_BrB, []>;
1268 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1269 "bdnzlrl+", IIC_BrB, []>;
1270 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1271 "bdzlrl-", IIC_BrB, []>;
1272 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1273 "bdnzlrl-", IIC_BrB, []>;
1277 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1278 def TCRETURNdi :Pseudo< (outs),
1279 (ins calltarget:$dst, i32imm:$offset),
1280 "#TC_RETURNd $dst $offset",
1284 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1285 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1286 "#TC_RETURNa $func $offset",
1287 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1289 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1290 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1291 "#TC_RETURNr $dst $offset",
1295 let isCodeGenOnly = 1 in {
1297 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1298 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1299 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1300 []>, Requires<[In32BitMode]>;
1302 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1303 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1304 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1308 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1309 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1310 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1316 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1318 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1319 "#EH_SJLJ_SETJMP32",
1320 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1321 Requires<[In32BitMode]>;
1322 let isTerminator = 1 in
1323 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1324 "#EH_SJLJ_LONGJMP32",
1325 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1326 Requires<[In32BitMode]>;
1329 let isBranch = 1, isTerminator = 1 in {
1330 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1331 "#EH_SjLj_Setup\t$dst", []>;
1335 let PPC970_Unit = 7 in {
1336 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1337 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1340 // DCB* instructions.
1341 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1342 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1343 PPC970_DGroup_Single;
1344 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1345 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1346 PPC970_DGroup_Single;
1347 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1348 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1349 PPC970_DGroup_Single;
1350 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1351 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1352 PPC970_DGroup_Single;
1353 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1354 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1355 PPC970_DGroup_Single;
1356 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1357 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1358 PPC970_DGroup_Single;
1359 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1360 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1361 PPC970_DGroup_Single;
1362 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1363 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1364 PPC970_DGroup_Single;
1366 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1367 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1369 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1370 (DCBT xoaddr:$dst)>; // data prefetch for loads
1371 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1372 (DCBTST xoaddr:$dst)>; // data prefetch for stores
1373 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1374 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1376 // Atomic operations
1377 let usesCustomInserter = 1 in {
1378 let Defs = [CR0] in {
1379 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1380 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1381 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1382 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1383 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1384 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1385 def ATOMIC_LOAD_AND_I8 : Pseudo<
1386 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1387 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1388 def ATOMIC_LOAD_OR_I8 : Pseudo<
1389 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1390 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1391 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1392 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1393 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1394 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1395 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1396 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1397 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1398 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1399 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1400 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1401 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1402 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1403 def ATOMIC_LOAD_AND_I16 : Pseudo<
1404 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1405 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1406 def ATOMIC_LOAD_OR_I16 : Pseudo<
1407 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1408 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1409 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1410 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1411 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1412 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1413 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1414 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1415 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1416 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1417 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1418 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1419 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1420 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1421 def ATOMIC_LOAD_AND_I32 : Pseudo<
1422 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1423 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1424 def ATOMIC_LOAD_OR_I32 : Pseudo<
1425 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1426 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1427 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1428 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1429 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1430 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1431 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1432 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1434 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1435 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1436 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1437 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1438 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1439 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1440 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1441 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1442 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1444 def ATOMIC_SWAP_I8 : Pseudo<
1445 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1446 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1447 def ATOMIC_SWAP_I16 : Pseudo<
1448 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1449 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1450 def ATOMIC_SWAP_I32 : Pseudo<
1451 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1452 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1456 // Instructions to support atomic operations
1457 let mayLoad = 1, hasSideEffects = 0 in {
1458 def LBARX : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
1459 "lbarx $rD, $src", IIC_LdStLWARX, []>,
1460 Requires<[HasPartwordAtomics]>;
1462 def LHARX : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src),
1463 "lharx $rD, $src", IIC_LdStLWARX, []>,
1464 Requires<[HasPartwordAtomics]>;
1466 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1467 "lwarx $rD, $src", IIC_LdStLWARX, []>;
1469 // Instructions to support lock versions of atomics
1470 // (EH=1 - see Power ISA 2.07 Book II 4.4.2)
1471 def LBARXL : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
1472 "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1473 Requires<[HasPartwordAtomics]>;
1475 def LHARXL : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src),
1476 "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1477 Requires<[HasPartwordAtomics]>;
1479 def LWARXL : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1480 "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
1483 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {
1484 def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
1485 "stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
1486 isDOT, Requires<[HasPartwordAtomics]>;
1488 def STHCX : XForm_1<31, 726, (outs), (ins gprc:$rS, memrr:$dst),
1489 "sthcx. $rS, $dst", IIC_LdStSTWCX, []>,
1490 isDOT, Requires<[HasPartwordAtomics]>;
1492 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1493 "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
1496 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1497 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1499 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1500 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1501 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1502 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1503 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1504 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1505 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1506 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1508 //===----------------------------------------------------------------------===//
1509 // PPC32 Load Instructions.
1512 // Unindexed (r+i) Loads.
1513 let PPC970_Unit = 2 in {
1514 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1515 "lbz $rD, $src", IIC_LdStLoad,
1516 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1517 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1518 "lha $rD, $src", IIC_LdStLHA,
1519 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1520 PPC970_DGroup_Cracked;
1521 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1522 "lhz $rD, $src", IIC_LdStLoad,
1523 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1524 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1525 "lwz $rD, $src", IIC_LdStLoad,
1526 [(set i32:$rD, (load iaddr:$src))]>;
1528 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1529 "lfs $rD, $src", IIC_LdStLFD,
1530 [(set f32:$rD, (load iaddr:$src))]>;
1531 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1532 "lfd $rD, $src", IIC_LdStLFD,
1533 [(set f64:$rD, (load iaddr:$src))]>;
1536 // Unindexed (r+i) Loads with Update (preinc).
1537 let mayLoad = 1, hasSideEffects = 0 in {
1538 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1539 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1540 []>, RegConstraint<"$addr.reg = $ea_result">,
1541 NoEncode<"$ea_result">;
1543 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1544 "lhau $rD, $addr", IIC_LdStLHAU,
1545 []>, RegConstraint<"$addr.reg = $ea_result">,
1546 NoEncode<"$ea_result">;
1548 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1549 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1550 []>, RegConstraint<"$addr.reg = $ea_result">,
1551 NoEncode<"$ea_result">;
1553 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1554 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1555 []>, RegConstraint<"$addr.reg = $ea_result">,
1556 NoEncode<"$ea_result">;
1558 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1559 "lfsu $rD, $addr", IIC_LdStLFDU,
1560 []>, RegConstraint<"$addr.reg = $ea_result">,
1561 NoEncode<"$ea_result">;
1563 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1564 "lfdu $rD, $addr", IIC_LdStLFDU,
1565 []>, RegConstraint<"$addr.reg = $ea_result">,
1566 NoEncode<"$ea_result">;
1569 // Indexed (r+r) Loads with Update (preinc).
1570 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1572 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1573 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1574 NoEncode<"$ea_result">;
1576 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1578 "lhaux $rD, $addr", IIC_LdStLHAUX,
1579 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1580 NoEncode<"$ea_result">;
1582 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1584 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1585 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1586 NoEncode<"$ea_result">;
1588 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1590 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1591 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1592 NoEncode<"$ea_result">;
1594 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1596 "lfsux $rD, $addr", IIC_LdStLFDUX,
1597 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1598 NoEncode<"$ea_result">;
1600 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1602 "lfdux $rD, $addr", IIC_LdStLFDUX,
1603 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1604 NoEncode<"$ea_result">;
1608 // Indexed (r+r) Loads.
1610 let PPC970_Unit = 2 in {
1611 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1612 "lbzx $rD, $src", IIC_LdStLoad,
1613 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1614 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1615 "lhax $rD, $src", IIC_LdStLHA,
1616 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1617 PPC970_DGroup_Cracked;
1618 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1619 "lhzx $rD, $src", IIC_LdStLoad,
1620 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1621 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1622 "lwzx $rD, $src", IIC_LdStLoad,
1623 [(set i32:$rD, (load xaddr:$src))]>;
1626 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1627 "lhbrx $rD, $src", IIC_LdStLoad,
1628 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1629 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1630 "lwbrx $rD, $src", IIC_LdStLoad,
1631 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1633 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1634 "lfsx $frD, $src", IIC_LdStLFD,
1635 [(set f32:$frD, (load xaddr:$src))]>;
1636 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1637 "lfdx $frD, $src", IIC_LdStLFD,
1638 [(set f64:$frD, (load xaddr:$src))]>;
1640 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1641 "lfiwax $frD, $src", IIC_LdStLFD,
1642 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1643 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1644 "lfiwzx $frD, $src", IIC_LdStLFD,
1645 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1649 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1650 "lmw $rD, $src", IIC_LdStLMW, []>;
1652 //===----------------------------------------------------------------------===//
1653 // PPC32 Store Instructions.
1656 // Unindexed (r+i) Stores.
1657 let PPC970_Unit = 2 in {
1658 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1659 "stb $rS, $src", IIC_LdStStore,
1660 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1661 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1662 "sth $rS, $src", IIC_LdStStore,
1663 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1664 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1665 "stw $rS, $src", IIC_LdStStore,
1666 [(store i32:$rS, iaddr:$src)]>;
1667 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1668 "stfs $rS, $dst", IIC_LdStSTFD,
1669 [(store f32:$rS, iaddr:$dst)]>;
1670 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1671 "stfd $rS, $dst", IIC_LdStSTFD,
1672 [(store f64:$rS, iaddr:$dst)]>;
1675 // Unindexed (r+i) Stores with Update (preinc).
1676 let PPC970_Unit = 2, mayStore = 1 in {
1677 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1678 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1679 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1680 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1681 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1682 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1683 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1684 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1685 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1686 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1687 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1688 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1689 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1690 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1691 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1694 // Patterns to match the pre-inc stores. We can't put the patterns on
1695 // the instruction definitions directly as ISel wants the address base
1696 // and offset to be separate operands, not a single complex operand.
1697 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1698 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1699 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1700 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1701 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1702 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1703 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1704 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1705 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1706 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1708 // Indexed (r+r) Stores.
1709 let PPC970_Unit = 2 in {
1710 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1711 "stbx $rS, $dst", IIC_LdStStore,
1712 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1713 PPC970_DGroup_Cracked;
1714 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1715 "sthx $rS, $dst", IIC_LdStStore,
1716 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1717 PPC970_DGroup_Cracked;
1718 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1719 "stwx $rS, $dst", IIC_LdStStore,
1720 [(store i32:$rS, xaddr:$dst)]>,
1721 PPC970_DGroup_Cracked;
1723 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1724 "sthbrx $rS, $dst", IIC_LdStStore,
1725 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1726 PPC970_DGroup_Cracked;
1727 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1728 "stwbrx $rS, $dst", IIC_LdStStore,
1729 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1730 PPC970_DGroup_Cracked;
1732 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1733 "stfiwx $frS, $dst", IIC_LdStSTFD,
1734 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1736 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1737 "stfsx $frS, $dst", IIC_LdStSTFD,
1738 [(store f32:$frS, xaddr:$dst)]>;
1739 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1740 "stfdx $frS, $dst", IIC_LdStSTFD,
1741 [(store f64:$frS, xaddr:$dst)]>;
1744 // Indexed (r+r) Stores with Update (preinc).
1745 let PPC970_Unit = 2, mayStore = 1 in {
1746 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1747 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1748 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1749 PPC970_DGroup_Cracked;
1750 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1751 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1752 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1753 PPC970_DGroup_Cracked;
1754 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1755 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1756 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1757 PPC970_DGroup_Cracked;
1758 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1759 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1760 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1761 PPC970_DGroup_Cracked;
1762 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1763 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1764 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1765 PPC970_DGroup_Cracked;
1768 // Patterns to match the pre-inc stores. We can't put the patterns on
1769 // the instruction definitions directly as ISel wants the address base
1770 // and offset to be separate operands, not a single complex operand.
1771 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1772 (STBUX $rS, $ptrreg, $ptroff)>;
1773 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1774 (STHUX $rS, $ptrreg, $ptroff)>;
1775 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1776 (STWUX $rS, $ptrreg, $ptroff)>;
1777 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1778 (STFSUX $rS, $ptrreg, $ptroff)>;
1779 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1780 (STFDUX $rS, $ptrreg, $ptroff)>;
1783 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1784 "stmw $rS, $dst", IIC_LdStLMW, []>;
1786 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1787 "sync $L", IIC_LdStSync, []>;
1789 let isCodeGenOnly = 1 in {
1790 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1791 "msync", IIC_LdStSync, []> {
1796 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>;
1797 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1798 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1799 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1801 //===----------------------------------------------------------------------===//
1802 // PPC32 Arithmetic Instructions.
1805 let PPC970_Unit = 1 in { // FXU Operations.
1806 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1807 "addi $rD, $rA, $imm", IIC_IntSimple,
1808 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1809 let BaseName = "addic" in {
1810 let Defs = [CARRY] in
1811 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1812 "addic $rD, $rA, $imm", IIC_IntGeneral,
1813 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1814 RecFormRel, PPC970_DGroup_Cracked;
1815 let Defs = [CARRY, CR0] in
1816 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1817 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1818 []>, isDOT, RecFormRel;
1820 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1821 "addis $rD, $rA, $imm", IIC_IntSimple,
1822 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1823 let isCodeGenOnly = 1 in
1824 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1825 "la $rD, $sym($rA)", IIC_IntGeneral,
1826 [(set i32:$rD, (add i32:$rA,
1827 (PPClo tglobaladdr:$sym, 0)))]>;
1828 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1829 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1830 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1831 let Defs = [CARRY] in
1832 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1833 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1834 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1836 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1837 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1838 "li $rD, $imm", IIC_IntSimple,
1839 [(set i32:$rD, imm32SExt16:$imm)]>;
1840 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1841 "lis $rD, $imm", IIC_IntSimple,
1842 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1846 let PPC970_Unit = 1 in { // FXU Operations.
1847 let Defs = [CR0] in {
1848 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1849 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1850 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1852 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1853 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1854 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1857 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1858 "ori $dst, $src1, $src2", IIC_IntSimple,
1859 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1860 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1861 "oris $dst, $src1, $src2", IIC_IntSimple,
1862 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1863 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1864 "xori $dst, $src1, $src2", IIC_IntSimple,
1865 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1866 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1867 "xoris $dst, $src1, $src2", IIC_IntSimple,
1868 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1870 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1872 let isCodeGenOnly = 1 in {
1873 // The POWER6 and POWER7 have special group-terminating nops.
1874 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1875 "ori 1, 1, 0", IIC_IntSimple, []>;
1876 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1877 "ori 2, 2, 0", IIC_IntSimple, []>;
1880 let isCompare = 1, hasSideEffects = 0 in {
1881 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1882 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1883 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1884 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1888 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
1889 let isCommutable = 1 in {
1890 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1891 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1892 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1893 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1894 "and", "$rA, $rS, $rB", IIC_IntSimple,
1895 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1897 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1898 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1899 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1900 let isCommutable = 1 in {
1901 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1902 "or", "$rA, $rS, $rB", IIC_IntSimple,
1903 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1904 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1905 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1906 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1908 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1909 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1910 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1911 let isCommutable = 1 in {
1912 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1913 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1914 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1915 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1916 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1917 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1919 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1920 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1921 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1922 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1923 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1924 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1925 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1926 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1927 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1930 let PPC970_Unit = 1 in { // FXU Operations.
1931 let hasSideEffects = 0 in {
1932 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1933 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1934 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1935 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1936 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1937 [(set i32:$rA, (ctlz i32:$rS))]>;
1938 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1939 "extsb", "$rA, $rS", IIC_IntSimple,
1940 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1941 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1942 "extsh", "$rA, $rS", IIC_IntSimple,
1943 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1945 let isCommutable = 1 in
1946 def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1947 "cmpb $rA, $rS, $rB", IIC_IntGeneral,
1948 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
1950 let isCompare = 1, hasSideEffects = 0 in {
1951 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1952 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1953 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1954 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1957 let PPC970_Unit = 3 in { // FPU Operations.
1958 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1959 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1960 let isCompare = 1, hasSideEffects = 0 in {
1961 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1962 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1963 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1964 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1965 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1968 let Uses = [RM] in {
1969 let hasSideEffects = 0 in {
1970 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1971 "fctiw", "$frD, $frB", IIC_FPGeneral,
1973 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1974 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1975 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1977 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1978 "frsp", "$frD, $frB", IIC_FPGeneral,
1979 [(set f32:$frD, (fround f64:$frB))]>;
1981 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1982 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1983 "frin", "$frD, $frB", IIC_FPGeneral,
1984 [(set f64:$frD, (frnd f64:$frB))]>;
1985 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1986 "frin", "$frD, $frB", IIC_FPGeneral,
1987 [(set f32:$frD, (frnd f32:$frB))]>;
1990 let hasSideEffects = 0 in {
1991 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1992 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1993 "frip", "$frD, $frB", IIC_FPGeneral,
1994 [(set f64:$frD, (fceil f64:$frB))]>;
1995 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1996 "frip", "$frD, $frB", IIC_FPGeneral,
1997 [(set f32:$frD, (fceil f32:$frB))]>;
1998 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1999 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
2000 "friz", "$frD, $frB", IIC_FPGeneral,
2001 [(set f64:$frD, (ftrunc f64:$frB))]>;
2002 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
2003 "friz", "$frD, $frB", IIC_FPGeneral,
2004 [(set f32:$frD, (ftrunc f32:$frB))]>;
2005 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2006 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
2007 "frim", "$frD, $frB", IIC_FPGeneral,
2008 [(set f64:$frD, (ffloor f64:$frB))]>;
2009 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
2010 "frim", "$frD, $frB", IIC_FPGeneral,
2011 [(set f32:$frD, (ffloor f32:$frB))]>;
2013 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
2014 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
2015 [(set f64:$frD, (fsqrt f64:$frB))]>;
2016 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
2017 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
2018 [(set f32:$frD, (fsqrt f32:$frB))]>;
2023 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
2024 /// often coalesced away and we don't want the dispatch group builder to think
2025 /// that they will fill slots (which could cause the load of a LSU reject to
2026 /// sneak into a d-group with a store).
2027 let hasSideEffects = 0 in
2028 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
2029 "fmr", "$frD, $frB", IIC_FPGeneral,
2030 []>, // (set f32:$frD, f32:$frB)
2033 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2034 // These are artificially split into two different forms, for 4/8 byte FP.
2035 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
2036 "fabs", "$frD, $frB", IIC_FPGeneral,
2037 [(set f32:$frD, (fabs f32:$frB))]>;
2038 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2039 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
2040 "fabs", "$frD, $frB", IIC_FPGeneral,
2041 [(set f64:$frD, (fabs f64:$frB))]>;
2042 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
2043 "fnabs", "$frD, $frB", IIC_FPGeneral,
2044 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
2045 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2046 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
2047 "fnabs", "$frD, $frB", IIC_FPGeneral,
2048 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
2049 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
2050 "fneg", "$frD, $frB", IIC_FPGeneral,
2051 [(set f32:$frD, (fneg f32:$frB))]>;
2052 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2053 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
2054 "fneg", "$frD, $frB", IIC_FPGeneral,
2055 [(set f64:$frD, (fneg f64:$frB))]>;
2057 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
2058 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2059 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
2060 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2061 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
2062 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2063 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
2065 // Reciprocal estimates.
2066 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
2067 "fre", "$frD, $frB", IIC_FPGeneral,
2068 [(set f64:$frD, (PPCfre f64:$frB))]>;
2069 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
2070 "fres", "$frD, $frB", IIC_FPGeneral,
2071 [(set f32:$frD, (PPCfre f32:$frB))]>;
2072 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
2073 "frsqrte", "$frD, $frB", IIC_FPGeneral,
2074 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2075 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2076 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2077 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2080 // XL-Form instructions. condition register logical ops.
2082 let hasSideEffects = 0 in
2083 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2084 "mcrf $BF, $BFA", IIC_BrMCR>,
2085 PPC970_DGroup_First, PPC970_Unit_CRU;
2087 // FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2088 // condition-register logical instructions have preferred forms. Specifically,
2089 // it is preferred that the bit specified by the BT field be in the same
2090 // condition register as that specified by the bit BB. We might want to account
2091 // for this via hinting the register allocator and anti-dep breakers, or we
2092 // could constrain the register class to force this constraint and then loosen
2093 // it during register allocation via convertToThreeAddress or some similar
2096 let isCommutable = 1 in {
2097 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
2098 (ins crbitrc:$CRA, crbitrc:$CRB),
2099 "crand $CRD, $CRA, $CRB", IIC_BrCR,
2100 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2102 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2103 (ins crbitrc:$CRA, crbitrc:$CRB),
2104 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2105 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2107 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
2108 (ins crbitrc:$CRA, crbitrc:$CRB),
2109 "cror $CRD, $CRA, $CRB", IIC_BrCR,
2110 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2112 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
2113 (ins crbitrc:$CRA, crbitrc:$CRB),
2114 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2115 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2117 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
2118 (ins crbitrc:$CRA, crbitrc:$CRB),
2119 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2120 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2122 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
2123 (ins crbitrc:$CRA, crbitrc:$CRB),
2124 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2125 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2128 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2129 (ins crbitrc:$CRA, crbitrc:$CRB),
2130 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2131 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2133 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
2134 (ins crbitrc:$CRA, crbitrc:$CRB),
2135 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2136 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2138 let isCodeGenOnly = 1 in {
2139 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2140 "creqv $dst, $dst, $dst", IIC_BrCR,
2141 [(set i1:$dst, 1)]>;
2143 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2144 "crxor $dst, $dst, $dst", IIC_BrCR,
2145 [(set i1:$dst, 0)]>;
2147 let Defs = [CR1EQ], CRD = 6 in {
2148 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2149 "creqv 6, 6, 6", IIC_BrCR,
2152 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2153 "crxor 6, 6, 6", IIC_BrCR,
2158 // XFX-Form instructions. Instructions that deal with SPRs.
2161 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2162 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2163 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2164 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2166 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2167 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2169 // A pseudo-instruction used to implement the read of the 64-bit cycle counter
2170 // on a 32-bit target.
2171 let hasSideEffects = 1, usesCustomInserter = 1 in
2172 def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2175 let Uses = [CTR] in {
2176 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2177 "mfctr $rT", IIC_SprMFSPR>,
2178 PPC970_DGroup_First, PPC970_Unit_FXU;
2180 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2181 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2182 "mtctr $rS", IIC_SprMTSPR>,
2183 PPC970_DGroup_First, PPC970_Unit_FXU;
2185 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2186 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2187 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2188 "mtctr $rS", IIC_SprMTSPR>,
2189 PPC970_DGroup_First, PPC970_Unit_FXU;
2192 let Defs = [LR] in {
2193 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2194 "mtlr $rS", IIC_SprMTSPR>,
2195 PPC970_DGroup_First, PPC970_Unit_FXU;
2197 let Uses = [LR] in {
2198 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2199 "mflr $rT", IIC_SprMFSPR>,
2200 PPC970_DGroup_First, PPC970_Unit_FXU;
2203 let isCodeGenOnly = 1 in {
2204 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2205 // like a GPR on the PPC970. As such, copies in and out have the same
2206 // performance characteristics as an OR instruction.
2207 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2208 "mtspr 256, $rS", IIC_IntGeneral>,
2209 PPC970_DGroup_Single, PPC970_Unit_FXU;
2210 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2211 "mfspr $rT, 256", IIC_IntGeneral>,
2212 PPC970_DGroup_First, PPC970_Unit_FXU;
2214 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2215 (outs VRSAVERC:$reg), (ins gprc:$rS),
2216 "mtspr 256, $rS", IIC_IntGeneral>,
2217 PPC970_DGroup_Single, PPC970_Unit_FXU;
2218 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2219 (ins VRSAVERC:$reg),
2220 "mfspr $rT, 256", IIC_IntGeneral>,
2221 PPC970_DGroup_First, PPC970_Unit_FXU;
2224 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2225 // so we'll need to scavenge a register for it.
2227 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2228 "#SPILL_VRSAVE", []>;
2230 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2231 // spilled), so we'll need to scavenge a register for it.
2233 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2234 "#RESTORE_VRSAVE", []>;
2236 let hasSideEffects = 0 in {
2237 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2238 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2239 PPC970_DGroup_First, PPC970_Unit_CRU;
2241 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2242 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2243 PPC970_MicroCode, PPC970_Unit_CRU;
2245 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2246 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2247 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2248 PPC970_DGroup_First, PPC970_Unit_CRU;
2250 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2251 "mfcr $rT", IIC_SprMFCR>,
2252 PPC970_MicroCode, PPC970_Unit_CRU;
2253 } // hasSideEffects = 0
2255 // Pseudo instruction to perform FADD in round-to-zero mode.
2256 let usesCustomInserter = 1, Uses = [RM] in {
2257 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2258 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2261 // The above pseudo gets expanded to make use of the following instructions
2262 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2263 let Uses = [RM], Defs = [RM] in {
2264 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2265 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2266 PPC970_DGroup_Single, PPC970_Unit_FPU;
2267 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2268 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2269 PPC970_DGroup_Single, PPC970_Unit_FPU;
2270 let isCodeGenOnly = 1 in
2271 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2272 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2273 PPC970_DGroup_Single, PPC970_Unit_FPU;
2275 let Uses = [RM] in {
2276 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2277 "mffs $rT", IIC_IntMFFS,
2278 [(set f64:$rT, (PPCmffs))]>,
2279 PPC970_DGroup_Single, PPC970_Unit_FPU;
2282 def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2283 "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2287 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
2288 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2289 let isCommutable = 1 in
2290 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2291 "add", "$rT, $rA, $rB", IIC_IntSimple,
2292 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2293 let isCodeGenOnly = 1 in
2294 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2295 "add $rT, $rA, $rB", IIC_IntSimple,
2296 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2297 let isCommutable = 1 in
2298 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2299 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2300 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2301 PPC970_DGroup_Cracked;
2303 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2304 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2305 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2306 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2307 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2308 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2309 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2310 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2311 let isCommutable = 1 in {
2312 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2313 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2314 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2315 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2316 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2317 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2318 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2319 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2320 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2322 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2323 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2324 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2325 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2326 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2327 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2328 PPC970_DGroup_Cracked;
2329 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2330 "neg", "$rT, $rA", IIC_IntSimple,
2331 [(set i32:$rT, (ineg i32:$rA))]>;
2332 let Uses = [CARRY] in {
2333 let isCommutable = 1 in
2334 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2335 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2336 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2337 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2338 "addme", "$rT, $rA", IIC_IntGeneral,
2339 [(set i32:$rT, (adde i32:$rA, -1))]>;
2340 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2341 "addze", "$rT, $rA", IIC_IntGeneral,
2342 [(set i32:$rT, (adde i32:$rA, 0))]>;
2343 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2344 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2345 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2346 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2347 "subfme", "$rT, $rA", IIC_IntGeneral,
2348 [(set i32:$rT, (sube -1, i32:$rA))]>;
2349 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2350 "subfze", "$rT, $rA", IIC_IntGeneral,
2351 [(set i32:$rT, (sube 0, i32:$rA))]>;
2355 // A-Form instructions. Most of the instructions executed in the FPU are of
2358 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2359 let Uses = [RM] in {
2360 let isCommutable = 1 in {
2361 defm FMADD : AForm_1r<63, 29,
2362 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2363 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2364 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2365 defm FMADDS : AForm_1r<59, 29,
2366 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2367 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2368 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2369 defm FMSUB : AForm_1r<63, 28,
2370 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2371 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2373 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2374 defm FMSUBS : AForm_1r<59, 28,
2375 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2376 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2378 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2379 defm FNMADD : AForm_1r<63, 31,
2380 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2381 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2383 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2384 defm FNMADDS : AForm_1r<59, 31,
2385 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2386 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2388 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2389 defm FNMSUB : AForm_1r<63, 30,
2390 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2391 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2392 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2393 (fneg f64:$FRB))))]>;
2394 defm FNMSUBS : AForm_1r<59, 30,
2395 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2396 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2397 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2398 (fneg f32:$FRB))))]>;
2401 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2402 // having 4 of these, force the comparison to always be an 8-byte double (code
2403 // should use an FMRSD if the input comparison value really wants to be a float)
2404 // and 4/8 byte forms for the result and operand type..
2405 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2406 defm FSELD : AForm_1r<63, 23,
2407 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2408 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2409 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2410 defm FSELS : AForm_1r<63, 23,
2411 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2412 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2413 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2414 let Uses = [RM] in {
2415 let isCommutable = 1 in {
2416 defm FADD : AForm_2r<63, 21,
2417 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2418 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2419 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2420 defm FADDS : AForm_2r<59, 21,
2421 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2422 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2423 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2425 defm FDIV : AForm_2r<63, 18,
2426 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2427 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2428 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2429 defm FDIVS : AForm_2r<59, 18,
2430 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2431 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2432 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2433 let isCommutable = 1 in {
2434 defm FMUL : AForm_3r<63, 25,
2435 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2436 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2437 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2438 defm FMULS : AForm_3r<59, 25,
2439 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2440 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2441 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2443 defm FSUB : AForm_2r<63, 20,
2444 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2445 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2446 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2447 defm FSUBS : AForm_2r<59, 20,
2448 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2449 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2450 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2454 let hasSideEffects = 0 in {
2455 let PPC970_Unit = 1 in { // FXU Operations.
2457 def ISEL : AForm_4<31, 15,
2458 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2459 "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
2463 let PPC970_Unit = 1 in { // FXU Operations.
2464 // M-Form instructions. rotate and mask instructions.
2466 let isCommutable = 1 in {
2467 // RLWIMI can be commuted if the rotate amount is zero.
2468 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2469 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2470 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2471 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2472 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2474 let BaseName = "rlwinm" in {
2475 def RLWINM : MForm_2<21,
2476 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2477 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2480 def RLWINMo : MForm_2<21,
2481 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2482 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2483 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2485 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2486 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2487 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2490 } // hasSideEffects = 0
2492 //===----------------------------------------------------------------------===//
2493 // PowerPC Instruction Patterns
2496 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2497 def : Pat<(i32 imm:$imm),
2498 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2500 // Implement the 'not' operation with the NOR instruction.
2501 def i32not : OutPatFrag<(ops node:$in),
2503 def : Pat<(not i32:$in),
2506 // ADD an arbitrary immediate.
2507 def : Pat<(add i32:$in, imm:$imm),
2508 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2509 // OR an arbitrary immediate.
2510 def : Pat<(or i32:$in, imm:$imm),
2511 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2512 // XOR an arbitrary immediate.
2513 def : Pat<(xor i32:$in, imm:$imm),
2514 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2516 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2517 (SUBFIC $in, imm:$imm)>;
2520 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2521 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2522 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2523 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2526 def : Pat<(rotl i32:$in, i32:$sh),
2527 (RLWNM $in, $sh, 0, 31)>;
2528 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2529 (RLWINM $in, imm:$imm, 0, 31)>;
2532 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2533 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2536 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2537 (BL tglobaladdr:$dst)>;
2538 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2539 (BL texternalsym:$dst)>;
2541 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2542 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2544 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2545 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2547 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2548 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2552 // Hi and Lo for Darwin Global Addresses.
2553 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2554 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2555 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2556 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2557 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2558 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2559 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2560 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2561 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2562 (ADDIS $in, tglobaltlsaddr:$g)>;
2563 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2564 (ADDI $in, tglobaltlsaddr:$g)>;
2565 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2566 (ADDIS $in, tglobaladdr:$g)>;
2567 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2568 (ADDIS $in, tconstpool:$g)>;
2569 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2570 (ADDIS $in, tjumptable:$g)>;
2571 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2572 (ADDIS $in, tblockaddress:$g)>;
2574 // Support for thread-local storage.
2575 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2576 [(set i32:$rD, (PPCppc32GOT))]>;
2578 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2579 // This uses two output registers, the first as the real output, the second as a
2580 // temporary register, used internally in code generation.
2581 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2582 []>, NoEncode<"$rT">;
2584 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2587 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2588 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2589 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2591 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2594 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2595 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2596 // explicitly defined when this op is created, so not mentioned here.
2597 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2598 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2599 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2602 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2603 // Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR
2604 // are true defines while the rest of the Defs are clobbers.
2605 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2606 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2607 def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2608 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2609 "#ADDItlsgdLADDR32",
2611 (PPCaddiTlsgdLAddr i32:$reg,
2612 tglobaltlsaddr:$disp,
2613 tglobaltlsaddr:$sym))]>;
2614 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2617 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2618 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2619 // explicitly defined when this op is created, so not mentioned here.
2620 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2621 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2622 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2625 (PPCgetTlsldAddr i32:$reg,
2626 tglobaltlsaddr:$sym))]>;
2627 // Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR
2628 // are true defines while the rest of the Defs are clobbers.
2629 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2630 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2631 def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2632 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2633 "#ADDItlsldLADDR32",
2635 (PPCaddiTlsldLAddr i32:$reg,
2636 tglobaltlsaddr:$disp,
2637 tglobaltlsaddr:$sym))]>;
2638 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2641 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2642 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2645 (PPCaddisDtprelHA i32:$reg,
2646 tglobaltlsaddr:$disp))]>;
2648 // Support for Position-independent code
2649 def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2652 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2653 // Get Global (GOT) Base Register offset, from the word immediately preceding
2654 // the function label.
2655 def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2658 // Standard shifts. These are represented separately from the real shifts above
2659 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2661 def : Pat<(sra i32:$rS, i32:$rB),
2663 def : Pat<(srl i32:$rS, i32:$rB),
2665 def : Pat<(shl i32:$rS, i32:$rB),
2668 def : Pat<(zextloadi1 iaddr:$src),
2670 def : Pat<(zextloadi1 xaddr:$src),
2672 def : Pat<(extloadi1 iaddr:$src),
2674 def : Pat<(extloadi1 xaddr:$src),
2676 def : Pat<(extloadi8 iaddr:$src),
2678 def : Pat<(extloadi8 xaddr:$src),
2680 def : Pat<(extloadi16 iaddr:$src),
2682 def : Pat<(extloadi16 xaddr:$src),
2684 def : Pat<(f64 (extloadf32 iaddr:$src)),
2685 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2686 def : Pat<(f64 (extloadf32 xaddr:$src)),
2687 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2689 def : Pat<(f64 (fextend f32:$src)),
2690 (COPY_TO_REGCLASS $src, F8RC)>;
2692 // Only seq_cst fences require the heavyweight sync (SYNC 0).
2693 // All others can use the lightweight sync (SYNC 1).
2694 // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2695 // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2696 // versions of Power.
2697 def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2698 def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2699 def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2700 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2702 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2703 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2704 (FNMSUB $A, $C, $B)>;
2705 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2706 (FNMSUB $A, $C, $B)>;
2707 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2708 (FNMSUBS $A, $C, $B)>;
2709 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2710 (FNMSUBS $A, $C, $B)>;
2712 // FCOPYSIGN's operand types need not agree.
2713 def : Pat<(fcopysign f64:$frB, f32:$frA),
2714 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2715 def : Pat<(fcopysign f32:$frB, f64:$frA),
2716 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2718 include "PPCInstrAltivec.td"
2719 include "PPCInstrSPE.td"
2720 include "PPCInstr64Bit.td"
2721 include "PPCInstrVSX.td"
2722 include "PPCInstrQPX.td"
2723 include "PPCInstrHTM.td"
2725 def crnot : OutPatFrag<(ops node:$in),
2727 def : Pat<(not i1:$in),
2730 // Patterns for arithmetic i1 operations.
2731 def : Pat<(add i1:$a, i1:$b),
2733 def : Pat<(sub i1:$a, i1:$b),
2735 def : Pat<(mul i1:$a, i1:$b),
2738 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2739 // (-1 is used to mean all bits set).
2740 def : Pat<(i1 -1), (CRSET)>;
2742 // i1 extensions, implemented in terms of isel.
2743 def : Pat<(i32 (zext i1:$in)),
2744 (SELECT_I4 $in, (LI 1), (LI 0))>;
2745 def : Pat<(i32 (sext i1:$in)),
2746 (SELECT_I4 $in, (LI -1), (LI 0))>;
2748 def : Pat<(i64 (zext i1:$in)),
2749 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2750 def : Pat<(i64 (sext i1:$in)),
2751 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2753 // FIXME: We should choose either a zext or a sext based on other constants
2755 def : Pat<(i32 (anyext i1:$in)),
2756 (SELECT_I4 $in, (LI 1), (LI 0))>;
2757 def : Pat<(i64 (anyext i1:$in)),
2758 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2760 // match setcc on i1 variables.
2761 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2763 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2765 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2767 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2769 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2771 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2773 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2775 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2777 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2779 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2782 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2783 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2784 // floating-point types.
2786 multiclass CRNotPat<dag pattern, dag result> {
2787 def : Pat<pattern, (crnot result)>;
2788 def : Pat<(not pattern), result>;
2790 // We can also fold the crnot into an extension:
2791 def : Pat<(i32 (zext pattern)),
2792 (SELECT_I4 result, (LI 0), (LI 1))>;
2793 def : Pat<(i32 (sext pattern)),
2794 (SELECT_I4 result, (LI 0), (LI -1))>;
2796 // We can also fold the crnot into an extension:
2797 def : Pat<(i64 (zext pattern)),
2798 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2799 def : Pat<(i64 (sext pattern)),
2800 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2802 // FIXME: We should choose either a zext or a sext based on other constants
2804 def : Pat<(i32 (anyext pattern)),
2805 (SELECT_I4 result, (LI 0), (LI 1))>;
2807 def : Pat<(i64 (anyext pattern)),
2808 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2811 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2812 // we need to write imm:$imm in the output patterns below, not just $imm, or
2813 // else the resulting matcher will not correctly add the immediate operand
2814 // (making it a register operand instead).
2817 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2818 OutPatFrag rfrag, OutPatFrag rfrag8> {
2819 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2821 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2823 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2824 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2825 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2826 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2828 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2830 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2832 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2833 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2834 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2835 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2838 // Note that we do all inversions below with i(32|64)not, instead of using
2839 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2840 // has 2-cycle latency.
2842 defm : ExtSetCCPat<SETEQ,
2843 PatFrag<(ops node:$in, node:$cc),
2844 (setcc $in, 0, $cc)>,
2845 OutPatFrag<(ops node:$in),
2846 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2847 OutPatFrag<(ops node:$in),
2848 (RLDICL (CNTLZD $in), 58, 63)> >;
2850 defm : ExtSetCCPat<SETNE,
2851 PatFrag<(ops node:$in, node:$cc),
2852 (setcc $in, 0, $cc)>,
2853 OutPatFrag<(ops node:$in),
2854 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2855 OutPatFrag<(ops node:$in),
2856 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2858 defm : ExtSetCCPat<SETLT,
2859 PatFrag<(ops node:$in, node:$cc),
2860 (setcc $in, 0, $cc)>,
2861 OutPatFrag<(ops node:$in),
2862 (RLWINM $in, 1, 31, 31)>,
2863 OutPatFrag<(ops node:$in),
2864 (RLDICL $in, 1, 63)> >;
2866 defm : ExtSetCCPat<SETGE,
2867 PatFrag<(ops node:$in, node:$cc),
2868 (setcc $in, 0, $cc)>,
2869 OutPatFrag<(ops node:$in),
2870 (RLWINM (i32not $in), 1, 31, 31)>,
2871 OutPatFrag<(ops node:$in),
2872 (RLDICL (i64not $in), 1, 63)> >;
2874 defm : ExtSetCCPat<SETGT,
2875 PatFrag<(ops node:$in, node:$cc),
2876 (setcc $in, 0, $cc)>,
2877 OutPatFrag<(ops node:$in),
2878 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2879 OutPatFrag<(ops node:$in),
2880 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2882 defm : ExtSetCCPat<SETLE,
2883 PatFrag<(ops node:$in, node:$cc),
2884 (setcc $in, 0, $cc)>,
2885 OutPatFrag<(ops node:$in),
2886 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2887 OutPatFrag<(ops node:$in),
2888 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2890 defm : ExtSetCCPat<SETLT,
2891 PatFrag<(ops node:$in, node:$cc),
2892 (setcc $in, -1, $cc)>,
2893 OutPatFrag<(ops node:$in),
2894 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2895 OutPatFrag<(ops node:$in),
2896 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2898 defm : ExtSetCCPat<SETGE,
2899 PatFrag<(ops node:$in, node:$cc),
2900 (setcc $in, -1, $cc)>,
2901 OutPatFrag<(ops node:$in),
2902 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2903 OutPatFrag<(ops node:$in),
2904 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2906 defm : ExtSetCCPat<SETGT,
2907 PatFrag<(ops node:$in, node:$cc),
2908 (setcc $in, -1, $cc)>,
2909 OutPatFrag<(ops node:$in),
2910 (RLWINM (i32not $in), 1, 31, 31)>,
2911 OutPatFrag<(ops node:$in),
2912 (RLDICL (i64not $in), 1, 63)> >;
2914 defm : ExtSetCCPat<SETLE,
2915 PatFrag<(ops node:$in, node:$cc),
2916 (setcc $in, -1, $cc)>,
2917 OutPatFrag<(ops node:$in),
2918 (RLWINM $in, 1, 31, 31)>,
2919 OutPatFrag<(ops node:$in),
2920 (RLDICL $in, 1, 63)> >;
2923 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2924 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2925 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2926 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2927 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2928 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2929 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2930 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2931 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2932 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2933 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2934 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2936 // For non-equality comparisons, the default code would materialize the
2937 // constant, then compare against it, like this:
2939 // ori r2, r2, 22136
2942 // Since we are just comparing for equality, we can emit this instead:
2943 // xoris r0,r3,0x1234
2944 // cmplwi cr0,r0,0x5678
2947 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2948 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2949 (LO16 imm:$imm)), sub_eq)>;
2951 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2952 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2953 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2954 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2955 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2956 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2957 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2958 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2959 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2960 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2961 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2962 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2964 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2965 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2966 (LO16 imm:$imm)), sub_eq)>;
2968 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
2969 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2970 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2971 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2972 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2973 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2974 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
2975 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2976 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2977 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2979 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2980 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2981 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
2982 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2983 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2984 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2985 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
2986 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2987 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2988 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2991 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
2992 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2993 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2994 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2995 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2996 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2997 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
2998 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2999 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3000 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3001 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3002 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3004 // For non-equality comparisons, the default code would materialize the
3005 // constant, then compare against it, like this:
3007 // ori r2, r2, 22136
3010 // Since we are just comparing for equality, we can emit this instead:
3011 // xoris r0,r3,0x1234
3012 // cmpldi cr0,r0,0x5678
3015 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
3016 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3017 (LO16 imm:$imm)), sub_eq)>;
3019 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3020 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3021 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
3022 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3023 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3024 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3025 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
3026 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3027 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
3028 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3029 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3030 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3032 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3033 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3034 (LO16 imm:$imm)), sub_eq)>;
3036 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3037 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3038 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3039 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3040 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3041 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3042 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3043 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3044 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3045 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3047 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3048 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3049 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3050 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3051 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3052 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3053 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
3054 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3055 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3056 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3059 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3060 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3061 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3062 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3063 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3064 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3065 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3066 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3067 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3068 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3069 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3070 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3071 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
3072 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3074 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3075 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3076 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3077 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3078 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3079 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3080 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3081 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3082 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3083 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3084 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3085 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3086 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3087 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3090 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3091 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3092 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3093 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3094 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3095 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3096 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3097 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3098 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3099 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3100 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3101 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3102 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3103 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3105 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3106 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3107 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3108 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3109 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3110 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3111 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3112 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3113 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3114 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3115 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3116 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3117 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3118 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3120 // match select on i1 variables:
3121 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3122 (CROR (CRAND $cond , $tval),
3123 (CRAND (crnot $cond), $fval))>;
3125 // match selectcc on i1 variables:
3126 // select (lhs == rhs), tval, fval is:
3127 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3128 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3129 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3130 (CRAND (CRORC $lhs, $rhs), $fval))>;
3131 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3132 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
3133 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3134 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3135 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3136 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3137 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3138 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
3139 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3140 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3141 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3142 (CRAND (CRORC $rhs, $lhs), $fval))>;
3143 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3144 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3145 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3147 // match selectcc on i1 variables with non-i1 output.
3148 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3149 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3150 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3151 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3152 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3153 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3154 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3155 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3156 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3157 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3158 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3159 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3161 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3162 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3163 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3164 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3165 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3166 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3167 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3168 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3169 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3170 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3171 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3172 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3174 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3175 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3176 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3177 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3178 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3179 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3180 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3181 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3182 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3183 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3184 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3185 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3187 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3188 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3189 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3190 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3191 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3192 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3193 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3194 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3195 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3196 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3197 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3198 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3200 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3201 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3202 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3203 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3204 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3205 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3206 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3207 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3208 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3209 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3210 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3211 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3213 let usesCustomInserter = 1 in {
3214 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3216 [(set i1:$dst, (trunc (not i32:$in)))]>;
3217 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3219 [(set i1:$dst, (trunc i32:$in))]>;
3221 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3223 [(set i1:$dst, (trunc (not i64:$in)))]>;
3224 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3226 [(set i1:$dst, (trunc i64:$in))]>;
3229 def : Pat<(i1 (not (trunc i32:$in))),
3230 (ANDIo_1_EQ_BIT $in)>;
3231 def : Pat<(i1 (not (trunc i64:$in))),
3232 (ANDIo_1_EQ_BIT8 $in)>;
3234 //===----------------------------------------------------------------------===//
3235 // PowerPC Instructions used for assembler/disassembler only
3238 // FIXME: For B=0 or B > 8, the registers following RT are used.
3239 // WARNING: Do not add patterns for this instruction without fixing this.
3240 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3241 "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3243 // FIXME: For B=0 or B > 8, the registers following RT are used.
3244 // WARNING: Do not add patterns for this instruction without fixing this.
3245 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3246 "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3248 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3249 "isync", IIC_SprISYNC, []>;
3251 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3252 "icbi $src", IIC_LdStICBI, []>;
3254 // We used to have EIEIO as value but E[0-9A-Z] is a reserved name
3255 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3256 "eieio", IIC_LdStLoad, []>;
3258 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3259 "wait $L", IIC_LdStLoad, []>;
3261 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3262 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3264 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3265 "mtsr $SR, $RS", IIC_SprMTSR>;
3267 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3268 "mfsr $RS, $SR", IIC_SprMFSR>;
3270 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3271 "mtsrin $RS, $RB", IIC_SprMTSR>;
3273 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3274 "mfsrin $RS, $RB", IIC_SprMFSR>;
3276 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3277 "mtmsr $RS, $L", IIC_SprMTMSR>;
3279 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3280 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3284 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3285 Requires<[IsBookE]> {
3289 let Inst{21-30} = 163;
3292 def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3293 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3294 def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3295 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3297 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3298 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3299 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3300 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3302 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3303 "mfmsr $RT", IIC_SprMFMSR, []>;
3305 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3306 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3308 def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
3309 "mcrfs $BF, $BFA", IIC_BrMCR>;
3311 def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3312 "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
3314 def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3315 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
3317 def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
3318 def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
3320 def MTFSF : XFLForm_1<63, 711, (outs),
3321 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3322 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
3323 def MTFSFo : XFLForm_1<63, 711, (outs),
3324 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3325 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
3327 def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3328 def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3330 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3331 "slbie $RB", IIC_SprSLBIE, []>;
3333 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3334 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3336 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3337 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3339 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3341 def TLBIA : XForm_0<31, 370, (outs), (ins),
3342 "tlbia", IIC_SprTLBIA, []>;
3344 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3345 "tlbsync", IIC_SprTLBSYNC, []>;
3347 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3348 "tlbiel $RB", IIC_SprTLBIEL, []>;
3350 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3351 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3352 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3353 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3355 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3356 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3358 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3359 IIC_LdStLoad>, Requires<[IsBookE]>;
3361 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3362 IIC_LdStLoad>, Requires<[IsBookE]>;
3364 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3365 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3367 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3368 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3370 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3371 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3373 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3374 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3376 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3377 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3378 Requires<[IsPPC4xx]>;
3379 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3380 (ins gprc:$RST, gprc:$A, gprc:$B),
3381 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3382 Requires<[IsPPC4xx]>, isDOT;
3384 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3386 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3387 Requires<[IsBookE]>;
3388 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3389 Requires<[IsBookE]>;
3391 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3393 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3396 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3397 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3398 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3399 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3401 def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3403 def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3404 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3405 def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3406 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3407 def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3408 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3409 def LDCIX : XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3410 "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3412 def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3413 "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3414 def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3415 "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3416 def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3417 "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3418 def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3419 "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3421 //===----------------------------------------------------------------------===//
3422 // PowerPC Assembler Instruction Aliases
3425 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3426 // These are aliases that require C++ handling to convert to the target
3427 // instruction, while InstAliases can be handled directly by tblgen.
3428 class PPCAsmPseudo<string asm, dag iops>
3430 let Namespace = "PPC";
3431 bit PPC64 = 0; // Default value, override with isPPC64
3433 let OutOperandList = (outs);
3434 let InOperandList = iops;
3436 let AsmString = asm;
3437 let isAsmParserOnly = 1;
3441 def : InstAlias<"sc", (SC 0)>;
3443 def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3444 def : InstAlias<"msync", (SYNC 0)>, Requires<[HasSYNC]>;
3445 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3446 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3448 def : InstAlias<"wait", (WAIT 0)>;
3449 def : InstAlias<"waitrsv", (WAIT 1)>;
3450 def : InstAlias<"waitimpl", (WAIT 2)>;
3452 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3454 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3455 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3456 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3457 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3459 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3460 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3462 def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3463 def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3465 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3466 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3468 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3469 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3471 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3472 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3474 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3475 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3477 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3478 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3480 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3481 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3483 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3484 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3486 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3487 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3489 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3490 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3492 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3493 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3495 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3496 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3498 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3499 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3501 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3502 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3503 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3505 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3506 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3508 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3509 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3510 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3511 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3513 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3515 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3516 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3518 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3519 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3521 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3523 foreach BATR = 0-3 in {
3524 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3525 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3526 Requires<[IsPPC6xx]>;
3527 def : InstAlias<"mfdbatu $Rx, "#BATR,
3528 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3529 Requires<[IsPPC6xx]>;
3530 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3531 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3532 Requires<[IsPPC6xx]>;
3533 def : InstAlias<"mfdbatl $Rx, "#BATR,
3534 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3535 Requires<[IsPPC6xx]>;
3536 def : InstAlias<"mtibatu "#BATR#", $Rx",
3537 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3538 Requires<[IsPPC6xx]>;
3539 def : InstAlias<"mfibatu $Rx, "#BATR,
3540 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3541 Requires<[IsPPC6xx]>;
3542 def : InstAlias<"mtibatl "#BATR#", $Rx",
3543 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3544 Requires<[IsPPC6xx]>;
3545 def : InstAlias<"mfibatl $Rx, "#BATR,
3546 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3547 Requires<[IsPPC6xx]>;
3550 foreach BR = 0-7 in {
3551 def : InstAlias<"mfbr"#BR#" $Rx",
3552 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3553 Requires<[IsPPC4xx]>;
3554 def : InstAlias<"mtbr"#BR#" $Rx",
3555 (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3556 Requires<[IsPPC4xx]>;
3559 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3560 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3562 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3563 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3565 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3566 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3568 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3569 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3571 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3572 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3574 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3575 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3577 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3579 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3580 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3581 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3582 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3583 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3584 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3585 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3586 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3588 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3589 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3590 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3591 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3593 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3594 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3596 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3597 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3599 foreach SPRG = 0-3 in {
3600 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3601 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3602 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3603 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3605 foreach SPRG = 4-7 in {
3606 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3607 Requires<[IsBookE]>;
3608 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3609 Requires<[IsBookE]>;
3610 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3611 Requires<[IsBookE]>;
3612 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3613 Requires<[IsBookE]>;
3616 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3618 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3619 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3621 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3623 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3624 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3626 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3627 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3628 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3629 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3631 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3633 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3634 Requires<[IsPPC4xx]>;
3635 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3636 Requires<[IsPPC4xx]>;
3637 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3638 Requires<[IsPPC4xx]>;
3639 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3640 Requires<[IsPPC4xx]>;
3642 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3643 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3644 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3645 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3646 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3647 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3648 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3649 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3650 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3651 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3652 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3653 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3654 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3655 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3656 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3657 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3658 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3659 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3660 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3661 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3662 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3663 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3664 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3665 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3666 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3667 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3668 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3669 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3670 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3671 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3672 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3673 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3674 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3675 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3676 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3677 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3679 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3680 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3681 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3682 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3683 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3684 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3686 def : InstAlias<"cntlz $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
3687 def : InstAlias<"cntlz. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
3689 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3690 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3691 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3692 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3693 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3694 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3695 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3696 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3697 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3698 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3699 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3700 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3701 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3702 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3703 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3704 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3705 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3706 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3707 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3708 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3709 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3710 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3711 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3712 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3713 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3714 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3715 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3716 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3717 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3718 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3719 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3720 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3722 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3723 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3724 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3725 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3726 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3727 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3729 def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",
3730 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3731 def RLWINMobm : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b",
3732 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3733 def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b",
3734 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3735 def RLWIMIobm : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",
3736 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3737 def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b",
3738 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3739 def RLWNMobm : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
3740 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3742 // These generic branch instruction forms are used for the assembler parser only.
3743 // Defs and Uses are conservative, since we don't know the BO value.
3744 let PPC970_Unit = 7 in {
3745 let Defs = [CTR], Uses = [CTR, RM] in {
3746 def gBC : BForm_3<16, 0, 0, (outs),
3747 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3748 "bc $bo, $bi, $dst">;
3749 def gBCA : BForm_3<16, 1, 0, (outs),
3750 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3751 "bca $bo, $bi, $dst">;
3753 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3754 def gBCL : BForm_3<16, 0, 1, (outs),
3755 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3756 "bcl $bo, $bi, $dst">;
3757 def gBCLA : BForm_3<16, 1, 1, (outs),
3758 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3759 "bcla $bo, $bi, $dst">;
3761 let Defs = [CTR], Uses = [CTR, LR, RM] in
3762 def gBCLR : XLForm_2<19, 16, 0, (outs),
3763 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3764 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3765 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3766 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3767 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3768 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3769 let Defs = [CTR], Uses = [CTR, LR, RM] in
3770 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3771 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3772 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3773 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3774 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3775 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3776 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3778 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3779 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3780 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3781 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3783 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3784 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3785 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3786 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3787 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3788 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3789 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3791 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3792 : BranchSimpleMnemonic1<name, pm, bo> {
3793 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3794 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3796 defm : BranchSimpleMnemonic2<"t", "", 12>;
3797 defm : BranchSimpleMnemonic2<"f", "", 4>;
3798 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3799 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3800 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3801 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3802 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3803 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3804 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3805 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3807 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3808 def : InstAlias<"b"#name#pm#" $cc, $dst",
3809 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3810 def : InstAlias<"b"#name#pm#" $dst",
3811 (BCC bibo, CR0, condbrtarget:$dst)>;
3813 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3814 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3815 def : InstAlias<"b"#name#"a"#pm#" $dst",
3816 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3818 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3819 (BCCLR bibo, crrc:$cc)>;
3820 def : InstAlias<"b"#name#"lr"#pm,
3823 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3824 (BCCCTR bibo, crrc:$cc)>;
3825 def : InstAlias<"b"#name#"ctr"#pm,
3826 (BCCCTR bibo, CR0)>;
3828 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3829 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3830 def : InstAlias<"b"#name#"l"#pm#" $dst",
3831 (BCCL bibo, CR0, condbrtarget:$dst)>;
3833 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3834 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3835 def : InstAlias<"b"#name#"la"#pm#" $dst",
3836 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3838 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3839 (BCCLRL bibo, crrc:$cc)>;
3840 def : InstAlias<"b"#name#"lrl"#pm,
3841 (BCCLRL bibo, CR0)>;
3843 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3844 (BCCCTRL bibo, crrc:$cc)>;
3845 def : InstAlias<"b"#name#"ctrl"#pm,
3846 (BCCCTRL bibo, CR0)>;
3848 multiclass BranchExtendedMnemonic<string name, int bibo> {
3849 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3850 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3851 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3853 defm : BranchExtendedMnemonic<"lt", 12>;
3854 defm : BranchExtendedMnemonic<"gt", 44>;
3855 defm : BranchExtendedMnemonic<"eq", 76>;
3856 defm : BranchExtendedMnemonic<"un", 108>;
3857 defm : BranchExtendedMnemonic<"so", 108>;
3858 defm : BranchExtendedMnemonic<"ge", 4>;
3859 defm : BranchExtendedMnemonic<"nl", 4>;
3860 defm : BranchExtendedMnemonic<"le", 36>;
3861 defm : BranchExtendedMnemonic<"ng", 36>;
3862 defm : BranchExtendedMnemonic<"ne", 68>;
3863 defm : BranchExtendedMnemonic<"nu", 100>;
3864 defm : BranchExtendedMnemonic<"ns", 100>;
3866 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3867 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3868 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3869 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3870 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3871 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3872 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3873 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3875 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3876 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3877 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3878 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3879 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3880 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3881 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3882 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3884 multiclass TrapExtendedMnemonic<string name, int to> {
3885 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3886 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3887 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3888 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3890 defm : TrapExtendedMnemonic<"lt", 16>;
3891 defm : TrapExtendedMnemonic<"le", 20>;
3892 defm : TrapExtendedMnemonic<"eq", 4>;
3893 defm : TrapExtendedMnemonic<"ge", 12>;
3894 defm : TrapExtendedMnemonic<"gt", 8>;
3895 defm : TrapExtendedMnemonic<"nl", 12>;
3896 defm : TrapExtendedMnemonic<"ne", 24>;
3897 defm : TrapExtendedMnemonic<"ng", 20>;
3898 defm : TrapExtendedMnemonic<"llt", 2>;
3899 defm : TrapExtendedMnemonic<"lle", 6>;
3900 defm : TrapExtendedMnemonic<"lge", 5>;
3901 defm : TrapExtendedMnemonic<"lgt", 1>;
3902 defm : TrapExtendedMnemonic<"lnl", 5>;
3903 defm : TrapExtendedMnemonic<"lng", 6>;
3904 defm : TrapExtendedMnemonic<"u", 31>;
3907 def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>;
3908 def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>;
3909 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>;
3910 def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>;
3911 def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
3912 def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
3915 def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>;
3916 def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>;
3917 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>;
3918 def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
3919 def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
3920 def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;