1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
61 //===----------------------------------------------------------------------===//
62 // PowerPC specific DAG Nodes.
65 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
66 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
68 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
69 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
70 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
71 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
72 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
73 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
74 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
75 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
76 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
77 [SDNPHasChain, SDNPMayStore]>;
78 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
79 [SDNPHasChain, SDNPMayLoad]>;
80 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
81 [SDNPHasChain, SDNPMayLoad]>;
83 // Extract FPSCR (not modeled at the DAG level).
84 def PPCmffs : SDNode<"PPCISD::MFFS",
85 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
87 // Perform FADD in round-to-zero mode.
88 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
91 def PPCfsel : SDNode<"PPCISD::FSEL",
92 // Type constraint for fsel.
93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
96 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
97 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
98 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
99 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
100 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
102 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
104 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
105 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
107 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
108 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
109 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
110 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
111 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
112 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
113 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
114 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
116 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
118 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
120 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
121 // amounts. These nodes are generated by the multi-precision shift code.
122 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
123 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
124 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
126 // These are target-independent nodes, but have target-specific formats.
127 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
128 [SDNPHasChain, SDNPOutGlue]>;
129 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
132 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
133 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
134 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
136 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
139 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
141 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
142 [SDNPHasChain, SDNPSideEffect,
143 SDNPInGlue, SDNPOutGlue]>;
144 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
145 [SDNPHasChain, SDNPSideEffect,
146 SDNPInGlue, SDNPOutGlue]>;
147 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
149 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
150 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
153 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
154 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
156 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
157 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
159 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
160 SDTypeProfile<1, 1, [SDTCisInt<0>,
162 [SDNPHasChain, SDNPSideEffect]>;
163 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
164 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
165 [SDNPHasChain, SDNPSideEffect]>;
167 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
168 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
169 [SDNPHasChain, SDNPSideEffect]>;
171 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
172 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
174 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
175 [SDNPHasChain, SDNPOptInGlue]>;
177 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
178 [SDNPHasChain, SDNPMayLoad]>;
179 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
180 [SDNPHasChain, SDNPMayStore]>;
182 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
183 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
186 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
188 // Instructions to support atomic operations
189 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
190 [SDNPHasChain, SDNPMayLoad]>;
191 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
192 [SDNPHasChain, SDNPMayStore]>;
194 // Instructions to support medium and large code model
195 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
196 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
197 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
200 // Instructions to support dynamic alloca.
201 def SDTDynOp : SDTypeProfile<1, 2, []>;
202 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
204 //===----------------------------------------------------------------------===//
205 // PowerPC specific transformation functions and pattern fragments.
208 def SHL32 : SDNodeXForm<imm, [{
209 // Transformation function: 31 - imm
210 return getI32Imm(31 - N->getZExtValue());
213 def SRL32 : SDNodeXForm<imm, [{
214 // Transformation function: 32 - imm
215 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
218 def LO16 : SDNodeXForm<imm, [{
219 // Transformation function: get the low 16 bits.
220 return getI32Imm((unsigned short)N->getZExtValue());
223 def HI16 : SDNodeXForm<imm, [{
224 // Transformation function: shift the immediate value down into the low bits.
225 return getI32Imm((unsigned)N->getZExtValue() >> 16);
228 def HA16 : SDNodeXForm<imm, [{
229 // Transformation function: shift the immediate value down into the low bits.
230 signed int Val = N->getZExtValue();
231 return getI32Imm((Val - (signed short)Val) >> 16);
233 def MB : SDNodeXForm<imm, [{
234 // Transformation function: get the start bit of a mask
236 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
237 return getI32Imm(mb);
240 def ME : SDNodeXForm<imm, [{
241 // Transformation function: get the end bit of a mask
243 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
244 return getI32Imm(me);
246 def maskimm32 : PatLeaf<(imm), [{
247 // maskImm predicate - True if immediate is a run of ones.
249 if (N->getValueType(0) == MVT::i32)
250 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
255 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
256 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
257 // sign extended field. Used by instructions like 'addi'.
258 return (int32_t)Imm == (short)Imm;
260 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
261 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
262 // sign extended field. Used by instructions like 'addi'.
263 return (int64_t)Imm == (short)Imm;
265 def immZExt16 : PatLeaf<(imm), [{
266 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
267 // field. Used by instructions like 'ori'.
268 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
271 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
272 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
273 // identical in 32-bit mode, but in 64-bit mode, they return true if the
274 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
276 def imm16ShiftedZExt : PatLeaf<(imm), [{
277 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
278 // immediate are set. Used by instructions like 'xoris'.
279 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
282 def imm16ShiftedSExt : PatLeaf<(imm), [{
283 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
284 // immediate are set. Used by instructions like 'addis'. Identical to
285 // imm16ShiftedZExt in 32-bit mode.
286 if (N->getZExtValue() & 0xFFFF) return false;
287 if (N->getValueType(0) == MVT::i32)
289 // For 64-bit, make sure it is sext right.
290 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
293 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
294 // restricted memrix (4-aligned) constants are alignment sensitive. If these
295 // offsets are hidden behind TOC entries than the values of the lower-order
296 // bits cannot be checked directly. As a result, we need to also incorporate
297 // an alignment check into the relevant patterns.
299 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
300 return cast<LoadSDNode>(N)->getAlignment() >= 4;
302 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
303 (store node:$val, node:$ptr), [{
304 return cast<StoreSDNode>(N)->getAlignment() >= 4;
306 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
307 return cast<LoadSDNode>(N)->getAlignment() >= 4;
309 def aligned4pre_store : PatFrag<
310 (ops node:$val, node:$base, node:$offset),
311 (pre_store node:$val, node:$base, node:$offset), [{
312 return cast<StoreSDNode>(N)->getAlignment() >= 4;
315 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
316 return cast<LoadSDNode>(N)->getAlignment() < 4;
318 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
319 (store node:$val, node:$ptr), [{
320 return cast<StoreSDNode>(N)->getAlignment() < 4;
322 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
323 return cast<LoadSDNode>(N)->getAlignment() < 4;
326 //===----------------------------------------------------------------------===//
327 // PowerPC Flag Definitions.
329 class isPPC64 { bit PPC64 = 1; }
330 class isDOT { bit RC = 1; }
332 class RegConstraint<string C> {
333 string Constraints = C;
335 class NoEncode<string E> {
336 string DisableEncoding = E;
340 //===----------------------------------------------------------------------===//
341 // PowerPC Operand Definitions.
343 // In the default PowerPC assembler syntax, registers are specified simply
344 // by number, so they cannot be distinguished from immediate values (without
345 // looking at the opcode). This means that the default operand matching logic
346 // for the asm parser does not work, and we need to specify custom matchers.
347 // Since those can only be specified with RegisterOperand classes and not
348 // directly on the RegisterClass, all instructions patterns used by the asm
349 // parser need to use a RegisterOperand (instead of a RegisterClass) for
350 // all their register operands.
351 // For this purpose, we define one RegisterOperand for each RegisterClass,
352 // using the same name as the class, just in lower case.
354 def PPCRegGPRCAsmOperand : AsmOperandClass {
355 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
357 def gprc : RegisterOperand<GPRC> {
358 let ParserMatchClass = PPCRegGPRCAsmOperand;
360 def PPCRegG8RCAsmOperand : AsmOperandClass {
361 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
363 def g8rc : RegisterOperand<G8RC> {
364 let ParserMatchClass = PPCRegG8RCAsmOperand;
366 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
367 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
369 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
370 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
372 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
373 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
375 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
376 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
378 def PPCRegF8RCAsmOperand : AsmOperandClass {
379 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
381 def f8rc : RegisterOperand<F8RC> {
382 let ParserMatchClass = PPCRegF8RCAsmOperand;
384 def PPCRegF4RCAsmOperand : AsmOperandClass {
385 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
387 def f4rc : RegisterOperand<F4RC> {
388 let ParserMatchClass = PPCRegF4RCAsmOperand;
390 def PPCRegVRRCAsmOperand : AsmOperandClass {
391 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
393 def vrrc : RegisterOperand<VRRC> {
394 let ParserMatchClass = PPCRegVRRCAsmOperand;
396 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
397 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
399 def crbitrc : RegisterOperand<CRBITRC> {
400 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
402 def PPCRegCRRCAsmOperand : AsmOperandClass {
403 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
405 def crrc : RegisterOperand<CRRC> {
406 let ParserMatchClass = PPCRegCRRCAsmOperand;
409 def PPCS5ImmAsmOperand : AsmOperandClass {
410 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
411 let RenderMethod = "addImmOperands";
413 def s5imm : Operand<i32> {
414 let PrintMethod = "printS5ImmOperand";
415 let ParserMatchClass = PPCS5ImmAsmOperand;
416 let DecoderMethod = "decodeSImmOperand<5>";
418 def PPCU5ImmAsmOperand : AsmOperandClass {
419 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
420 let RenderMethod = "addImmOperands";
422 def u5imm : Operand<i32> {
423 let PrintMethod = "printU5ImmOperand";
424 let ParserMatchClass = PPCU5ImmAsmOperand;
425 let DecoderMethod = "decodeUImmOperand<5>";
427 def PPCU6ImmAsmOperand : AsmOperandClass {
428 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
429 let RenderMethod = "addImmOperands";
431 def u6imm : Operand<i32> {
432 let PrintMethod = "printU6ImmOperand";
433 let ParserMatchClass = PPCU6ImmAsmOperand;
434 let DecoderMethod = "decodeUImmOperand<6>";
436 def PPCS16ImmAsmOperand : AsmOperandClass {
437 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
438 let RenderMethod = "addImmOperands";
440 def s16imm : Operand<i32> {
441 let PrintMethod = "printS16ImmOperand";
442 let EncoderMethod = "getImm16Encoding";
443 let ParserMatchClass = PPCS16ImmAsmOperand;
444 let DecoderMethod = "decodeSImmOperand<16>";
446 def PPCU16ImmAsmOperand : AsmOperandClass {
447 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
448 let RenderMethod = "addImmOperands";
450 def u16imm : Operand<i32> {
451 let PrintMethod = "printU16ImmOperand";
452 let EncoderMethod = "getImm16Encoding";
453 let ParserMatchClass = PPCU16ImmAsmOperand;
454 let DecoderMethod = "decodeUImmOperand<16>";
456 def PPCS17ImmAsmOperand : AsmOperandClass {
457 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
458 let RenderMethod = "addImmOperands";
460 def s17imm : Operand<i32> {
461 // This operand type is used for addis/lis to allow the assembler parser
462 // to accept immediates in the range -65536..65535 for compatibility with
463 // the GNU assembler. The operand is treated as 16-bit otherwise.
464 let PrintMethod = "printS16ImmOperand";
465 let EncoderMethod = "getImm16Encoding";
466 let ParserMatchClass = PPCS17ImmAsmOperand;
467 let DecoderMethod = "decodeSImmOperand<16>";
469 def PPCDirectBrAsmOperand : AsmOperandClass {
470 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
471 let RenderMethod = "addBranchTargetOperands";
473 def directbrtarget : Operand<OtherVT> {
474 let PrintMethod = "printBranchOperand";
475 let EncoderMethod = "getDirectBrEncoding";
476 let ParserMatchClass = PPCDirectBrAsmOperand;
478 def absdirectbrtarget : Operand<OtherVT> {
479 let PrintMethod = "printAbsBranchOperand";
480 let EncoderMethod = "getAbsDirectBrEncoding";
481 let ParserMatchClass = PPCDirectBrAsmOperand;
483 def PPCCondBrAsmOperand : AsmOperandClass {
484 let Name = "CondBr"; let PredicateMethod = "isCondBr";
485 let RenderMethod = "addBranchTargetOperands";
487 def condbrtarget : Operand<OtherVT> {
488 let PrintMethod = "printBranchOperand";
489 let EncoderMethod = "getCondBrEncoding";
490 let ParserMatchClass = PPCCondBrAsmOperand;
492 def abscondbrtarget : Operand<OtherVT> {
493 let PrintMethod = "printAbsBranchOperand";
494 let EncoderMethod = "getAbsCondBrEncoding";
495 let ParserMatchClass = PPCCondBrAsmOperand;
497 def calltarget : Operand<iPTR> {
498 let PrintMethod = "printBranchOperand";
499 let EncoderMethod = "getDirectBrEncoding";
500 let ParserMatchClass = PPCDirectBrAsmOperand;
502 def abscalltarget : Operand<iPTR> {
503 let PrintMethod = "printAbsBranchOperand";
504 let EncoderMethod = "getAbsDirectBrEncoding";
505 let ParserMatchClass = PPCDirectBrAsmOperand;
507 def PPCCRBitMaskOperand : AsmOperandClass {
508 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
510 def crbitm: Operand<i8> {
511 let PrintMethod = "printcrbitm";
512 let EncoderMethod = "get_crbitm_encoding";
513 let DecoderMethod = "decodeCRBitMOperand";
514 let ParserMatchClass = PPCCRBitMaskOperand;
517 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
518 def PPCRegGxRCNoR0Operand : AsmOperandClass {
519 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
521 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
522 let ParserMatchClass = PPCRegGxRCNoR0Operand;
524 // A version of ptr_rc usable with the asm parser.
525 def PPCRegGxRCOperand : AsmOperandClass {
526 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
528 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
529 let ParserMatchClass = PPCRegGxRCOperand;
532 def PPCDispRIOperand : AsmOperandClass {
533 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
534 let RenderMethod = "addImmOperands";
536 def dispRI : Operand<iPTR> {
537 let ParserMatchClass = PPCDispRIOperand;
539 def PPCDispRIXOperand : AsmOperandClass {
540 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
541 let RenderMethod = "addImmOperands";
543 def dispRIX : Operand<iPTR> {
544 let ParserMatchClass = PPCDispRIXOperand;
547 def memri : Operand<iPTR> {
548 let PrintMethod = "printMemRegImm";
549 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
550 let EncoderMethod = "getMemRIEncoding";
551 let DecoderMethod = "decodeMemRIOperands";
553 def memrr : Operand<iPTR> {
554 let PrintMethod = "printMemRegReg";
555 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
557 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
558 let PrintMethod = "printMemRegImm";
559 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
560 let EncoderMethod = "getMemRIXEncoding";
561 let DecoderMethod = "decodeMemRIXOperands";
564 // A single-register address. This is used with the SjLj
565 // pseudo-instructions.
566 def memr : Operand<iPTR> {
567 let MIOperandInfo = (ops ptr_rc:$ptrreg);
569 def PPCTLSRegOperand : AsmOperandClass {
570 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
571 let RenderMethod = "addTLSRegOperands";
573 def tlsreg32 : Operand<i32> {
574 let EncoderMethod = "getTLSRegEncoding";
575 let ParserMatchClass = PPCTLSRegOperand;
578 // PowerPC Predicate operand.
579 def pred : Operand<OtherVT> {
580 let PrintMethod = "printPredicateOperand";
581 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
584 // Define PowerPC specific addressing mode.
585 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
586 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
587 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
588 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
590 // The address in a single register. This is used with the SjLj
591 // pseudo-instructions.
592 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
594 /// This is just the offset part of iaddr, used for preinc.
595 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
597 //===----------------------------------------------------------------------===//
598 // PowerPC Instruction Predicate Definitions.
599 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
600 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
601 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
603 //===----------------------------------------------------------------------===//
604 // PowerPC Multiclass Definitions.
606 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
607 string asmbase, string asmstr, InstrItinClass itin,
609 let BaseName = asmbase in {
610 def NAME : XForm_6<opcode, xo, OOL, IOL,
611 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
612 pattern>, RecFormRel;
614 def o : XForm_6<opcode, xo, OOL, IOL,
615 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
616 []>, isDOT, RecFormRel;
620 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
621 string asmbase, string asmstr, InstrItinClass itin,
623 let BaseName = asmbase in {
624 let Defs = [CARRY] in
625 def NAME : XForm_6<opcode, xo, OOL, IOL,
626 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
627 pattern>, RecFormRel;
628 let Defs = [CARRY, CR0] in
629 def o : XForm_6<opcode, xo, OOL, IOL,
630 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
631 []>, isDOT, RecFormRel;
635 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
636 string asmbase, string asmstr, InstrItinClass itin,
638 let BaseName = asmbase in {
639 let Defs = [CARRY] in
640 def NAME : XForm_10<opcode, xo, OOL, IOL,
641 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
642 pattern>, RecFormRel;
643 let Defs = [CARRY, CR0] in
644 def o : XForm_10<opcode, xo, OOL, IOL,
645 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
646 []>, isDOT, RecFormRel;
650 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
651 string asmbase, string asmstr, InstrItinClass itin,
653 let BaseName = asmbase in {
654 def NAME : XForm_11<opcode, xo, OOL, IOL,
655 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
656 pattern>, RecFormRel;
658 def o : XForm_11<opcode, xo, OOL, IOL,
659 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
660 []>, isDOT, RecFormRel;
664 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
665 string asmbase, string asmstr, InstrItinClass itin,
667 let BaseName = asmbase in {
668 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
669 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
670 pattern>, RecFormRel;
672 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
673 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
674 []>, isDOT, RecFormRel;
678 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
679 string asmbase, string asmstr, InstrItinClass itin,
681 let BaseName = asmbase in {
682 let Defs = [CARRY] in
683 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
684 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
685 pattern>, RecFormRel;
686 let Defs = [CARRY, CR0] in
687 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
688 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
689 []>, isDOT, RecFormRel;
693 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
694 string asmbase, string asmstr, InstrItinClass itin,
696 let BaseName = asmbase in {
697 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
698 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
699 pattern>, RecFormRel;
701 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
702 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
703 []>, isDOT, RecFormRel;
707 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
708 string asmbase, string asmstr, InstrItinClass itin,
710 let BaseName = asmbase in {
711 let Defs = [CARRY] in
712 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
713 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
714 pattern>, RecFormRel;
715 let Defs = [CARRY, CR0] in
716 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
717 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
718 []>, isDOT, RecFormRel;
722 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
723 string asmbase, string asmstr, InstrItinClass itin,
725 let BaseName = asmbase in {
726 def NAME : MForm_2<opcode, OOL, IOL,
727 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
728 pattern>, RecFormRel;
730 def o : MForm_2<opcode, OOL, IOL,
731 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
732 []>, isDOT, RecFormRel;
736 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
737 string asmbase, string asmstr, InstrItinClass itin,
739 let BaseName = asmbase in {
740 def NAME : MDForm_1<opcode, xo, OOL, IOL,
741 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
742 pattern>, RecFormRel;
744 def o : MDForm_1<opcode, xo, OOL, IOL,
745 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
746 []>, isDOT, RecFormRel;
750 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
751 string asmbase, string asmstr, InstrItinClass itin,
753 let BaseName = asmbase in {
754 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
755 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
756 pattern>, RecFormRel;
758 def o : MDSForm_1<opcode, xo, OOL, IOL,
759 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
760 []>, isDOT, RecFormRel;
764 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
765 string asmbase, string asmstr, InstrItinClass itin,
767 let BaseName = asmbase in {
768 let Defs = [CARRY] in
769 def NAME : XSForm_1<opcode, xo, OOL, IOL,
770 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
771 pattern>, RecFormRel;
772 let Defs = [CARRY, CR0] in
773 def o : XSForm_1<opcode, xo, OOL, IOL,
774 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
775 []>, isDOT, RecFormRel;
779 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
780 string asmbase, string asmstr, InstrItinClass itin,
782 let BaseName = asmbase in {
783 def NAME : XForm_26<opcode, xo, OOL, IOL,
784 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
785 pattern>, RecFormRel;
787 def o : XForm_26<opcode, xo, OOL, IOL,
788 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
789 []>, isDOT, RecFormRel;
793 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
794 string asmbase, string asmstr, InstrItinClass itin,
796 let BaseName = asmbase in {
797 def NAME : XForm_28<opcode, xo, OOL, IOL,
798 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
799 pattern>, RecFormRel;
801 def o : XForm_28<opcode, xo, OOL, IOL,
802 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
803 []>, isDOT, RecFormRel;
807 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
808 string asmbase, string asmstr, InstrItinClass itin,
810 let BaseName = asmbase in {
811 def NAME : AForm_1<opcode, xo, OOL, IOL,
812 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
813 pattern>, RecFormRel;
815 def o : AForm_1<opcode, xo, OOL, IOL,
816 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
817 []>, isDOT, RecFormRel;
821 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
822 string asmbase, string asmstr, InstrItinClass itin,
824 let BaseName = asmbase in {
825 def NAME : AForm_2<opcode, xo, OOL, IOL,
826 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
827 pattern>, RecFormRel;
829 def o : AForm_2<opcode, xo, OOL, IOL,
830 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
831 []>, isDOT, RecFormRel;
835 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
836 string asmbase, string asmstr, InstrItinClass itin,
838 let BaseName = asmbase in {
839 def NAME : AForm_3<opcode, xo, OOL, IOL,
840 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
841 pattern>, RecFormRel;
843 def o : AForm_3<opcode, xo, OOL, IOL,
844 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
845 []>, isDOT, RecFormRel;
849 //===----------------------------------------------------------------------===//
850 // PowerPC Instruction Definitions.
852 // Pseudo-instructions:
854 let hasCtrlDep = 1 in {
855 let Defs = [R1], Uses = [R1] in {
856 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
857 [(callseq_start timm:$amt)]>;
858 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
859 [(callseq_end timm:$amt1, timm:$amt2)]>;
862 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
863 "UPDATE_VRSAVE $rD, $rS", []>;
866 let Defs = [R1], Uses = [R1] in
867 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
869 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
871 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
872 // instruction selection into a branch sequence.
873 let usesCustomInserter = 1, // Expanded after instruction selection.
874 PPC970_Single = 1 in {
875 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
876 // because either operand might become the first operand in an isel, and
877 // that operand cannot be r0.
878 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
879 gprc_nor0:$T, gprc_nor0:$F,
880 i32imm:$BROPC), "#SELECT_CC_I4",
882 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
883 g8rc_nox0:$T, g8rc_nox0:$F,
884 i32imm:$BROPC), "#SELECT_CC_I8",
886 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
887 i32imm:$BROPC), "#SELECT_CC_F4",
889 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
890 i32imm:$BROPC), "#SELECT_CC_F8",
892 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
893 i32imm:$BROPC), "#SELECT_CC_VRRC",
897 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
898 // scavenge a register for it.
900 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
903 // RESTORE_CR - Indicate that we're restoring the CR register (previously
904 // spilled), so we'll need to scavenge a register for it.
906 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
909 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
910 let isReturn = 1, Uses = [LR, RM] in
911 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
913 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
914 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
917 let isCodeGenOnly = 1 in
918 def BCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
919 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
925 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
928 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
929 let isBarrier = 1 in {
930 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
933 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
934 "ba $dst", IIC_BrB, []>;
937 // BCC represents an arbitrary conditional branch on a predicate.
938 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
939 // a two-value operand where a dag node expects two operands. :(
940 let isCodeGenOnly = 1 in {
941 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
942 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
943 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
944 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
945 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
947 let isReturn = 1, Uses = [LR, RM] in
948 def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
949 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
952 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
953 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
954 "bdzlr", IIC_BrB, []>;
955 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
956 "bdnzlr", IIC_BrB, []>;
957 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
958 "bdzlr+", IIC_BrB, []>;
959 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
960 "bdnzlr+", IIC_BrB, []>;
961 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
962 "bdzlr-", IIC_BrB, []>;
963 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
964 "bdnzlr-", IIC_BrB, []>;
967 let Defs = [CTR], Uses = [CTR] in {
968 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
970 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
972 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
974 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
976 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
978 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
980 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
982 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
984 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
986 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
988 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
990 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
995 // The unconditional BCL used by the SjLj setjmp code.
996 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
997 let Defs = [LR], Uses = [RM] in {
998 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1003 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1004 // Convenient aliases for call instructions
1005 let Uses = [RM] in {
1006 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1007 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1008 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1009 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1011 let isCodeGenOnly = 1 in {
1012 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1013 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1014 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1015 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1018 let Uses = [CTR, RM] in {
1019 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1020 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1021 Requires<[In32BitMode]>;
1023 let isCodeGenOnly = 1 in
1024 def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1025 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1028 let Uses = [LR, RM] in {
1029 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1030 "blrl", IIC_BrB, []>;
1032 let isCodeGenOnly = 1 in
1033 def BCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1034 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1037 let Defs = [CTR], Uses = [CTR, RM] in {
1038 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1040 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1042 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1044 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1046 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1048 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1050 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1052 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1054 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1056 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1058 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1060 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1063 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1064 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1065 "bdzlrl", IIC_BrB, []>;
1066 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1067 "bdnzlrl", IIC_BrB, []>;
1068 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1069 "bdzlrl+", IIC_BrB, []>;
1070 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1071 "bdnzlrl+", IIC_BrB, []>;
1072 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1073 "bdzlrl-", IIC_BrB, []>;
1074 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1075 "bdnzlrl-", IIC_BrB, []>;
1079 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1080 def TCRETURNdi :Pseudo< (outs),
1081 (ins calltarget:$dst, i32imm:$offset),
1082 "#TC_RETURNd $dst $offset",
1086 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1087 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1088 "#TC_RETURNa $func $offset",
1089 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1091 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1092 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1093 "#TC_RETURNr $dst $offset",
1097 let isCodeGenOnly = 1 in {
1099 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1100 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1101 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1102 []>, Requires<[In32BitMode]>;
1104 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1105 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1106 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1110 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1111 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1112 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1118 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1120 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1121 "#EH_SJLJ_SETJMP32",
1122 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1123 Requires<[In32BitMode]>;
1124 let isTerminator = 1 in
1125 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1126 "#EH_SJLJ_LONGJMP32",
1127 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1128 Requires<[In32BitMode]>;
1131 let isBranch = 1, isTerminator = 1 in {
1132 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1133 "#EH_SjLj_Setup\t$dst", []>;
1137 let PPC970_Unit = 7 in {
1138 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1139 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1142 // DCB* instructions.
1143 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1144 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1145 PPC970_DGroup_Single;
1146 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1147 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1148 PPC970_DGroup_Single;
1149 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1150 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1151 PPC970_DGroup_Single;
1152 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1153 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1154 PPC970_DGroup_Single;
1155 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1156 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1157 PPC970_DGroup_Single;
1158 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1159 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1160 PPC970_DGroup_Single;
1161 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1162 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1163 PPC970_DGroup_Single;
1164 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1165 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1166 PPC970_DGroup_Single;
1168 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1169 (DCBT xoaddr:$dst)>;
1171 // Atomic operations
1172 let usesCustomInserter = 1 in {
1173 let Defs = [CR0] in {
1174 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1175 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1176 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1177 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1178 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1179 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1180 def ATOMIC_LOAD_AND_I8 : Pseudo<
1181 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1182 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1183 def ATOMIC_LOAD_OR_I8 : Pseudo<
1184 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1185 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1186 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1187 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1188 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1189 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1190 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1191 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1192 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1193 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1194 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1195 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1196 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1197 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1198 def ATOMIC_LOAD_AND_I16 : Pseudo<
1199 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1200 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1201 def ATOMIC_LOAD_OR_I16 : Pseudo<
1202 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1203 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1204 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1205 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1206 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1207 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1208 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1209 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1210 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1211 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1212 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1213 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1214 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1215 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1216 def ATOMIC_LOAD_AND_I32 : Pseudo<
1217 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1218 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1219 def ATOMIC_LOAD_OR_I32 : Pseudo<
1220 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1221 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1222 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1223 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1224 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1225 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1226 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1227 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1229 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1230 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1231 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1232 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1233 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1234 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1235 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1236 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1237 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1239 def ATOMIC_SWAP_I8 : Pseudo<
1240 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1241 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1242 def ATOMIC_SWAP_I16 : Pseudo<
1243 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1244 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1245 def ATOMIC_SWAP_I32 : Pseudo<
1246 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1247 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1251 // Instructions to support atomic operations
1252 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1253 "lwarx $rD, $src", IIC_LdStLWARX,
1254 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1257 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1258 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1259 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1262 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1263 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1265 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1266 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1267 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1268 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1269 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1270 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1271 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1272 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1274 //===----------------------------------------------------------------------===//
1275 // PPC32 Load Instructions.
1278 // Unindexed (r+i) Loads.
1279 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1280 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1281 "lbz $rD, $src", IIC_LdStLoad,
1282 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1283 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1284 "lha $rD, $src", IIC_LdStLHA,
1285 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1286 PPC970_DGroup_Cracked;
1287 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1288 "lhz $rD, $src", IIC_LdStLoad,
1289 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1290 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1291 "lwz $rD, $src", IIC_LdStLoad,
1292 [(set i32:$rD, (load iaddr:$src))]>;
1294 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1295 "lfs $rD, $src", IIC_LdStLFD,
1296 [(set f32:$rD, (load iaddr:$src))]>;
1297 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1298 "lfd $rD, $src", IIC_LdStLFD,
1299 [(set f64:$rD, (load iaddr:$src))]>;
1302 // Unindexed (r+i) Loads with Update (preinc).
1303 let mayLoad = 1, neverHasSideEffects = 1 in {
1304 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1305 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1306 []>, RegConstraint<"$addr.reg = $ea_result">,
1307 NoEncode<"$ea_result">;
1309 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1310 "lhau $rD, $addr", IIC_LdStLHAU,
1311 []>, RegConstraint<"$addr.reg = $ea_result">,
1312 NoEncode<"$ea_result">;
1314 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1315 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1316 []>, RegConstraint<"$addr.reg = $ea_result">,
1317 NoEncode<"$ea_result">;
1319 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1320 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1321 []>, RegConstraint<"$addr.reg = $ea_result">,
1322 NoEncode<"$ea_result">;
1324 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1325 "lfsu $rD, $addr", IIC_LdStLFDU,
1326 []>, RegConstraint<"$addr.reg = $ea_result">,
1327 NoEncode<"$ea_result">;
1329 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1330 "lfdu $rD, $addr", IIC_LdStLFDU,
1331 []>, RegConstraint<"$addr.reg = $ea_result">,
1332 NoEncode<"$ea_result">;
1335 // Indexed (r+r) Loads with Update (preinc).
1336 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1338 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1339 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1340 NoEncode<"$ea_result">;
1342 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1344 "lhaux $rD, $addr", IIC_LdStLHAUX,
1345 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1346 NoEncode<"$ea_result">;
1348 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1350 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1351 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1352 NoEncode<"$ea_result">;
1354 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1356 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1357 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1358 NoEncode<"$ea_result">;
1360 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1362 "lfsux $rD, $addr", IIC_LdStLFDUX,
1363 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1364 NoEncode<"$ea_result">;
1366 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1368 "lfdux $rD, $addr", IIC_LdStLFDUX,
1369 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1370 NoEncode<"$ea_result">;
1374 // Indexed (r+r) Loads.
1376 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1377 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1378 "lbzx $rD, $src", IIC_LdStLoad,
1379 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1380 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1381 "lhax $rD, $src", IIC_LdStLHA,
1382 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1383 PPC970_DGroup_Cracked;
1384 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1385 "lhzx $rD, $src", IIC_LdStLoad,
1386 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1387 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1388 "lwzx $rD, $src", IIC_LdStLoad,
1389 [(set i32:$rD, (load xaddr:$src))]>;
1392 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1393 "lhbrx $rD, $src", IIC_LdStLoad,
1394 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1395 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1396 "lwbrx $rD, $src", IIC_LdStLoad,
1397 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1399 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1400 "lfsx $frD, $src", IIC_LdStLFD,
1401 [(set f32:$frD, (load xaddr:$src))]>;
1402 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1403 "lfdx $frD, $src", IIC_LdStLFD,
1404 [(set f64:$frD, (load xaddr:$src))]>;
1406 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1407 "lfiwax $frD, $src", IIC_LdStLFD,
1408 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1409 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1410 "lfiwzx $frD, $src", IIC_LdStLFD,
1411 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1415 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1416 "lmw $rD, $src", IIC_LdStLMW, []>;
1418 //===----------------------------------------------------------------------===//
1419 // PPC32 Store Instructions.
1422 // Unindexed (r+i) Stores.
1423 let PPC970_Unit = 2 in {
1424 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1425 "stb $rS, $src", IIC_LdStStore,
1426 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1427 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1428 "sth $rS, $src", IIC_LdStStore,
1429 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1430 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1431 "stw $rS, $src", IIC_LdStStore,
1432 [(store i32:$rS, iaddr:$src)]>;
1433 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1434 "stfs $rS, $dst", IIC_LdStSTFD,
1435 [(store f32:$rS, iaddr:$dst)]>;
1436 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1437 "stfd $rS, $dst", IIC_LdStSTFD,
1438 [(store f64:$rS, iaddr:$dst)]>;
1441 // Unindexed (r+i) Stores with Update (preinc).
1442 let PPC970_Unit = 2, mayStore = 1 in {
1443 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1444 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1445 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1446 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1447 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1448 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1449 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1450 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1451 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1452 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1453 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1454 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1455 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1456 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1457 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1460 // Patterns to match the pre-inc stores. We can't put the patterns on
1461 // the instruction definitions directly as ISel wants the address base
1462 // and offset to be separate operands, not a single complex operand.
1463 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1464 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1465 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1466 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1467 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1468 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1469 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1470 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1471 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1472 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1474 // Indexed (r+r) Stores.
1475 let PPC970_Unit = 2 in {
1476 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1477 "stbx $rS, $dst", IIC_LdStStore,
1478 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1479 PPC970_DGroup_Cracked;
1480 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1481 "sthx $rS, $dst", IIC_LdStStore,
1482 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1483 PPC970_DGroup_Cracked;
1484 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1485 "stwx $rS, $dst", IIC_LdStStore,
1486 [(store i32:$rS, xaddr:$dst)]>,
1487 PPC970_DGroup_Cracked;
1489 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1490 "sthbrx $rS, $dst", IIC_LdStStore,
1491 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1492 PPC970_DGroup_Cracked;
1493 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1494 "stwbrx $rS, $dst", IIC_LdStStore,
1495 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1496 PPC970_DGroup_Cracked;
1498 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1499 "stfiwx $frS, $dst", IIC_LdStSTFD,
1500 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1502 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1503 "stfsx $frS, $dst", IIC_LdStSTFD,
1504 [(store f32:$frS, xaddr:$dst)]>;
1505 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1506 "stfdx $frS, $dst", IIC_LdStSTFD,
1507 [(store f64:$frS, xaddr:$dst)]>;
1510 // Indexed (r+r) Stores with Update (preinc).
1511 let PPC970_Unit = 2, mayStore = 1 in {
1512 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1513 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1514 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1515 PPC970_DGroup_Cracked;
1516 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1517 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1518 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1519 PPC970_DGroup_Cracked;
1520 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1521 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1522 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1523 PPC970_DGroup_Cracked;
1524 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1525 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1526 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1527 PPC970_DGroup_Cracked;
1528 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1529 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1530 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1531 PPC970_DGroup_Cracked;
1534 // Patterns to match the pre-inc stores. We can't put the patterns on
1535 // the instruction definitions directly as ISel wants the address base
1536 // and offset to be separate operands, not a single complex operand.
1537 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1538 (STBUX $rS, $ptrreg, $ptroff)>;
1539 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1540 (STHUX $rS, $ptrreg, $ptroff)>;
1541 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1542 (STWUX $rS, $ptrreg, $ptroff)>;
1543 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1544 (STFSUX $rS, $ptrreg, $ptroff)>;
1545 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1546 (STFDUX $rS, $ptrreg, $ptroff)>;
1549 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1550 "stmw $rS, $dst", IIC_LdStLMW, []>;
1552 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1553 "sync $L", IIC_LdStSync, []>;
1554 def : Pat<(int_ppc_sync), (SYNC 0)>;
1556 //===----------------------------------------------------------------------===//
1557 // PPC32 Arithmetic Instructions.
1560 let PPC970_Unit = 1 in { // FXU Operations.
1561 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1562 "addi $rD, $rA, $imm", IIC_IntSimple,
1563 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1564 let BaseName = "addic" in {
1565 let Defs = [CARRY] in
1566 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1567 "addic $rD, $rA, $imm", IIC_IntGeneral,
1568 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1569 RecFormRel, PPC970_DGroup_Cracked;
1570 let Defs = [CARRY, CR0] in
1571 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1572 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1573 []>, isDOT, RecFormRel;
1575 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1576 "addis $rD, $rA, $imm", IIC_IntSimple,
1577 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1578 let isCodeGenOnly = 1 in
1579 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1580 "la $rD, $sym($rA)", IIC_IntGeneral,
1581 [(set i32:$rD, (add i32:$rA,
1582 (PPClo tglobaladdr:$sym, 0)))]>;
1583 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1584 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1585 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1586 let Defs = [CARRY] in
1587 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1588 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1589 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1591 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1592 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1593 "li $rD, $imm", IIC_IntSimple,
1594 [(set i32:$rD, imm32SExt16:$imm)]>;
1595 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1596 "lis $rD, $imm", IIC_IntSimple,
1597 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1601 let PPC970_Unit = 1 in { // FXU Operations.
1602 let Defs = [CR0] in {
1603 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1604 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1605 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1607 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1608 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1609 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1612 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1613 "ori $dst, $src1, $src2", IIC_IntSimple,
1614 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1615 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1616 "oris $dst, $src1, $src2", IIC_IntSimple,
1617 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1618 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1619 "xori $dst, $src1, $src2", IIC_IntSimple,
1620 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1621 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1622 "xoris $dst, $src1, $src2", IIC_IntSimple,
1623 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1625 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1627 let isCodeGenOnly = 1 in {
1628 // The POWER6 and POWER7 have special group-terminating nops.
1629 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1630 "ori 1, 1, 0", IIC_IntSimple, []>;
1631 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1632 "ori 2, 2, 0", IIC_IntSimple, []>;
1635 let isCompare = 1, neverHasSideEffects = 1 in {
1636 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1637 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1638 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1639 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1643 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1644 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1645 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1646 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1647 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1648 "and", "$rA, $rS, $rB", IIC_IntSimple,
1649 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1650 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1651 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1652 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1653 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1654 "or", "$rA, $rS, $rB", IIC_IntSimple,
1655 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1656 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1657 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1658 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1659 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1660 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1661 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1662 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1663 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1664 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1665 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1666 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1667 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1668 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1669 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1670 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1671 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1672 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1673 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1674 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1675 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1676 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1679 let PPC970_Unit = 1 in { // FXU Operations.
1680 let neverHasSideEffects = 1 in {
1681 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1682 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1683 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1684 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1685 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1686 [(set i32:$rA, (ctlz i32:$rS))]>;
1687 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1688 "extsb", "$rA, $rS", IIC_IntSimple,
1689 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1690 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1691 "extsh", "$rA, $rS", IIC_IntSimple,
1692 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1694 let isCompare = 1, neverHasSideEffects = 1 in {
1695 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1696 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1697 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1698 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1701 let PPC970_Unit = 3 in { // FPU Operations.
1702 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1703 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1704 let isCompare = 1, neverHasSideEffects = 1 in {
1705 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1706 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1707 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1708 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1709 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1712 let Uses = [RM] in {
1713 let neverHasSideEffects = 1 in {
1714 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1715 "fctiw", "$frD, $frB", IIC_FPGeneral,
1717 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1718 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1719 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1721 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1722 "frsp", "$frD, $frB", IIC_FPGeneral,
1723 [(set f32:$frD, (fround f64:$frB))]>;
1725 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1726 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1727 "frin", "$frD, $frB", IIC_FPGeneral,
1728 [(set f64:$frD, (frnd f64:$frB))]>;
1729 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1730 "frin", "$frD, $frB", IIC_FPGeneral,
1731 [(set f32:$frD, (frnd f32:$frB))]>;
1734 let neverHasSideEffects = 1 in {
1735 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1736 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1737 "frip", "$frD, $frB", IIC_FPGeneral,
1738 [(set f64:$frD, (fceil f64:$frB))]>;
1739 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1740 "frip", "$frD, $frB", IIC_FPGeneral,
1741 [(set f32:$frD, (fceil f32:$frB))]>;
1742 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1743 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1744 "friz", "$frD, $frB", IIC_FPGeneral,
1745 [(set f64:$frD, (ftrunc f64:$frB))]>;
1746 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1747 "friz", "$frD, $frB", IIC_FPGeneral,
1748 [(set f32:$frD, (ftrunc f32:$frB))]>;
1749 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1750 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1751 "frim", "$frD, $frB", IIC_FPGeneral,
1752 [(set f64:$frD, (ffloor f64:$frB))]>;
1753 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1754 "frim", "$frD, $frB", IIC_FPGeneral,
1755 [(set f32:$frD, (ffloor f32:$frB))]>;
1757 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1758 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1759 [(set f64:$frD, (fsqrt f64:$frB))]>;
1760 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1761 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1762 [(set f32:$frD, (fsqrt f32:$frB))]>;
1767 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1768 /// often coalesced away and we don't want the dispatch group builder to think
1769 /// that they will fill slots (which could cause the load of a LSU reject to
1770 /// sneak into a d-group with a store).
1771 let neverHasSideEffects = 1 in
1772 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1773 "fmr", "$frD, $frB", IIC_FPGeneral,
1774 []>, // (set f32:$frD, f32:$frB)
1777 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1778 // These are artificially split into two different forms, for 4/8 byte FP.
1779 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1780 "fabs", "$frD, $frB", IIC_FPGeneral,
1781 [(set f32:$frD, (fabs f32:$frB))]>;
1782 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1783 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1784 "fabs", "$frD, $frB", IIC_FPGeneral,
1785 [(set f64:$frD, (fabs f64:$frB))]>;
1786 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1787 "fnabs", "$frD, $frB", IIC_FPGeneral,
1788 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1789 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1790 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1791 "fnabs", "$frD, $frB", IIC_FPGeneral,
1792 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1793 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1794 "fneg", "$frD, $frB", IIC_FPGeneral,
1795 [(set f32:$frD, (fneg f32:$frB))]>;
1796 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1797 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1798 "fneg", "$frD, $frB", IIC_FPGeneral,
1799 [(set f64:$frD, (fneg f64:$frB))]>;
1801 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1802 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1803 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1804 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1805 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1806 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1807 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1809 // Reciprocal estimates.
1810 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1811 "fre", "$frD, $frB", IIC_FPGeneral,
1812 [(set f64:$frD, (PPCfre f64:$frB))]>;
1813 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1814 "fres", "$frD, $frB", IIC_FPGeneral,
1815 [(set f32:$frD, (PPCfre f32:$frB))]>;
1816 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1817 "frsqrte", "$frD, $frB", IIC_FPGeneral,
1818 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1819 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1820 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
1821 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1824 // XL-Form instructions. condition register logical ops.
1826 let neverHasSideEffects = 1 in
1827 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1828 "mcrf $BF, $BFA", IIC_BrMCR>,
1829 PPC970_DGroup_First, PPC970_Unit_CRU;
1831 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
1832 (ins crbitrc:$CRA, crbitrc:$CRB),
1833 "crand $CRD, $CRA, $CRB", IIC_BrCR, []>;
1835 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
1836 (ins crbitrc:$CRA, crbitrc:$CRB),
1837 "crnand $CRD, $CRA, $CRB", IIC_BrCR, []>;
1839 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
1840 (ins crbitrc:$CRA, crbitrc:$CRB),
1841 "cror $CRD, $CRA, $CRB", IIC_BrCR, []>;
1843 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
1844 (ins crbitrc:$CRA, crbitrc:$CRB),
1845 "crxor $CRD, $CRA, $CRB", IIC_BrCR, []>;
1847 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
1848 (ins crbitrc:$CRA, crbitrc:$CRB),
1849 "crnor $CRD, $CRA, $CRB", IIC_BrCR, []>;
1851 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
1852 (ins crbitrc:$CRA, crbitrc:$CRB),
1853 "creqv $CRD, $CRA, $CRB", IIC_BrCR, []>;
1855 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
1856 (ins crbitrc:$CRA, crbitrc:$CRB),
1857 "crandc $CRD, $CRA, $CRB", IIC_BrCR, []>;
1859 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
1860 (ins crbitrc:$CRA, crbitrc:$CRB),
1861 "crorc $CRD, $CRA, $CRB", IIC_BrCR, []>;
1863 let isCodeGenOnly = 1 in {
1864 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
1865 "creqv $dst, $dst, $dst", IIC_BrCR,
1868 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
1869 "crxor $dst, $dst, $dst", IIC_BrCR,
1872 let Defs = [CR1EQ], CRD = 6 in {
1873 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1874 "creqv 6, 6, 6", IIC_BrCR,
1877 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1878 "crxor 6, 6, 6", IIC_BrCR,
1883 // XFX-Form instructions. Instructions that deal with SPRs.
1886 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
1887 "mfspr $RT, $SPR", IIC_SprMFSPR>;
1888 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
1889 "mtspr $SPR, $RT", IIC_SprMTSPR>;
1891 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
1892 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
1894 let Uses = [CTR] in {
1895 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
1896 "mfctr $rT", IIC_SprMFSPR>,
1897 PPC970_DGroup_First, PPC970_Unit_FXU;
1899 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1900 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1901 "mtctr $rS", IIC_SprMTSPR>,
1902 PPC970_DGroup_First, PPC970_Unit_FXU;
1904 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
1905 let Pattern = [(int_ppc_mtctr i32:$rS)] in
1906 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1907 "mtctr $rS", IIC_SprMTSPR>,
1908 PPC970_DGroup_First, PPC970_Unit_FXU;
1911 let Defs = [LR] in {
1912 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
1913 "mtlr $rS", IIC_SprMTSPR>,
1914 PPC970_DGroup_First, PPC970_Unit_FXU;
1916 let Uses = [LR] in {
1917 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
1918 "mflr $rT", IIC_SprMFSPR>,
1919 PPC970_DGroup_First, PPC970_Unit_FXU;
1922 let isCodeGenOnly = 1 in {
1923 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
1924 // like a GPR on the PPC970. As such, copies in and out have the same
1925 // performance characteristics as an OR instruction.
1926 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
1927 "mtspr 256, $rS", IIC_IntGeneral>,
1928 PPC970_DGroup_Single, PPC970_Unit_FXU;
1929 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
1930 "mfspr $rT, 256", IIC_IntGeneral>,
1931 PPC970_DGroup_First, PPC970_Unit_FXU;
1933 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1934 (outs VRSAVERC:$reg), (ins gprc:$rS),
1935 "mtspr 256, $rS", IIC_IntGeneral>,
1936 PPC970_DGroup_Single, PPC970_Unit_FXU;
1937 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
1938 (ins VRSAVERC:$reg),
1939 "mfspr $rT, 256", IIC_IntGeneral>,
1940 PPC970_DGroup_First, PPC970_Unit_FXU;
1943 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1944 // so we'll need to scavenge a register for it.
1946 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1947 "#SPILL_VRSAVE", []>;
1949 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1950 // spilled), so we'll need to scavenge a register for it.
1952 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1953 "#RESTORE_VRSAVE", []>;
1955 let neverHasSideEffects = 1 in {
1956 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
1957 "mtocrf $FXM, $ST", IIC_BrMCRX>,
1958 PPC970_DGroup_First, PPC970_Unit_CRU;
1960 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
1961 "mtcrf $FXM, $rS", IIC_BrMCRX>,
1962 PPC970_MicroCode, PPC970_Unit_CRU;
1964 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
1965 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
1966 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
1967 PPC970_DGroup_First, PPC970_Unit_CRU;
1969 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
1970 "mfcr $rT", IIC_SprMFCR>,
1971 PPC970_MicroCode, PPC970_Unit_CRU;
1972 } // neverHasSideEffects = 1
1974 // Pseudo instruction to perform FADD in round-to-zero mode.
1975 let usesCustomInserter = 1, Uses = [RM] in {
1976 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
1977 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
1980 // The above pseudo gets expanded to make use of the following instructions
1981 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
1982 let Uses = [RM], Defs = [RM] in {
1983 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1984 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
1985 PPC970_DGroup_Single, PPC970_Unit_FPU;
1986 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1987 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
1988 PPC970_DGroup_Single, PPC970_Unit_FPU;
1989 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
1990 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
1991 PPC970_DGroup_Single, PPC970_Unit_FPU;
1993 let Uses = [RM] in {
1994 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
1995 "mffs $rT", IIC_IntMFFS,
1996 [(set f64:$rT, (PPCmffs))]>,
1997 PPC970_DGroup_Single, PPC970_Unit_FPU;
2001 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
2002 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2004 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2005 "add", "$rT, $rA, $rB", IIC_IntSimple,
2006 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2007 let isCodeGenOnly = 1 in
2008 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2009 "add $rT, $rA, $rB", IIC_IntSimple,
2010 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2011 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2012 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2013 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2014 PPC970_DGroup_Cracked;
2015 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2016 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2017 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2018 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2019 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2020 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2021 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2022 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2023 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2024 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2025 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2026 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2027 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2028 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2029 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2030 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2031 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2032 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2033 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2034 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2035 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2036 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2037 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2038 PPC970_DGroup_Cracked;
2039 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2040 "neg", "$rT, $rA", IIC_IntSimple,
2041 [(set i32:$rT, (ineg i32:$rA))]>;
2042 let Uses = [CARRY] in {
2043 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2044 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2045 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2046 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2047 "addme", "$rT, $rA", IIC_IntGeneral,
2048 [(set i32:$rT, (adde i32:$rA, -1))]>;
2049 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2050 "addze", "$rT, $rA", IIC_IntGeneral,
2051 [(set i32:$rT, (adde i32:$rA, 0))]>;
2052 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2053 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2054 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2055 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2056 "subfme", "$rT, $rA", IIC_IntGeneral,
2057 [(set i32:$rT, (sube -1, i32:$rA))]>;
2058 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2059 "subfze", "$rT, $rA", IIC_IntGeneral,
2060 [(set i32:$rT, (sube 0, i32:$rA))]>;
2064 // A-Form instructions. Most of the instructions executed in the FPU are of
2067 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
2068 let Uses = [RM] in {
2069 defm FMADD : AForm_1r<63, 29,
2070 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2071 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2072 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2073 defm FMADDS : AForm_1r<59, 29,
2074 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2075 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2076 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2077 defm FMSUB : AForm_1r<63, 28,
2078 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2079 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2081 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2082 defm FMSUBS : AForm_1r<59, 28,
2083 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2084 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2086 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2087 defm FNMADD : AForm_1r<63, 31,
2088 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2089 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2091 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2092 defm FNMADDS : AForm_1r<59, 31,
2093 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2094 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2096 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2097 defm FNMSUB : AForm_1r<63, 30,
2098 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2099 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2100 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2101 (fneg f64:$FRB))))]>;
2102 defm FNMSUBS : AForm_1r<59, 30,
2103 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2104 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2105 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2106 (fneg f32:$FRB))))]>;
2108 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2109 // having 4 of these, force the comparison to always be an 8-byte double (code
2110 // should use an FMRSD if the input comparison value really wants to be a float)
2111 // and 4/8 byte forms for the result and operand type..
2112 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2113 defm FSELD : AForm_1r<63, 23,
2114 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2115 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2116 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2117 defm FSELS : AForm_1r<63, 23,
2118 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2119 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2120 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2121 let Uses = [RM] in {
2122 defm FADD : AForm_2r<63, 21,
2123 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2124 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2125 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2126 defm FADDS : AForm_2r<59, 21,
2127 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2128 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2129 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2130 defm FDIV : AForm_2r<63, 18,
2131 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2132 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2133 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2134 defm FDIVS : AForm_2r<59, 18,
2135 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2136 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2137 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2138 defm FMUL : AForm_3r<63, 25,
2139 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2140 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2141 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2142 defm FMULS : AForm_3r<59, 25,
2143 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2144 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2145 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2146 defm FSUB : AForm_2r<63, 20,
2147 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2148 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2149 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2150 defm FSUBS : AForm_2r<59, 20,
2151 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2152 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2153 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2157 let neverHasSideEffects = 1 in {
2158 let PPC970_Unit = 1 in { // FXU Operations.
2160 def ISEL : AForm_4<31, 15,
2161 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2162 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
2166 let PPC970_Unit = 1 in { // FXU Operations.
2167 // M-Form instructions. rotate and mask instructions.
2169 let isCommutable = 1 in {
2170 // RLWIMI can be commuted if the rotate amount is zero.
2171 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2172 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2173 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2174 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2175 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2177 let BaseName = "rlwinm" in {
2178 def RLWINM : MForm_2<21,
2179 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2180 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2183 def RLWINMo : MForm_2<21,
2184 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2185 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2186 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2188 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2189 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2190 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2193 } // neverHasSideEffects = 1
2195 //===----------------------------------------------------------------------===//
2196 // PowerPC Instruction Patterns
2199 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2200 def : Pat<(i32 imm:$imm),
2201 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2203 // Implement the 'not' operation with the NOR instruction.
2204 def NOT : Pat<(not i32:$in),
2207 // ADD an arbitrary immediate.
2208 def : Pat<(add i32:$in, imm:$imm),
2209 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2210 // OR an arbitrary immediate.
2211 def : Pat<(or i32:$in, imm:$imm),
2212 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2213 // XOR an arbitrary immediate.
2214 def : Pat<(xor i32:$in, imm:$imm),
2215 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2217 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2218 (SUBFIC $in, imm:$imm)>;
2221 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2222 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2223 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2224 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2227 def : Pat<(rotl i32:$in, i32:$sh),
2228 (RLWNM $in, $sh, 0, 31)>;
2229 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2230 (RLWINM $in, imm:$imm, 0, 31)>;
2233 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2234 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2237 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2238 (BL tglobaladdr:$dst)>;
2239 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2240 (BL texternalsym:$dst)>;
2243 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2244 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2246 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2247 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2249 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2250 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2254 // Hi and Lo for Darwin Global Addresses.
2255 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2256 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2257 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2258 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2259 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2260 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2261 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2262 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2263 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2264 (ADDIS $in, tglobaltlsaddr:$g)>;
2265 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2266 (ADDI $in, tglobaltlsaddr:$g)>;
2267 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2268 (ADDIS $in, tglobaladdr:$g)>;
2269 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2270 (ADDIS $in, tconstpool:$g)>;
2271 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2272 (ADDIS $in, tjumptable:$g)>;
2273 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2274 (ADDIS $in, tblockaddress:$g)>;
2276 // Support for thread-local storage.
2277 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2278 [(set i32:$rD, (PPCppc32GOT))]>;
2280 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2283 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2284 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2285 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2287 // Standard shifts. These are represented separately from the real shifts above
2288 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2290 def : Pat<(sra i32:$rS, i32:$rB),
2292 def : Pat<(srl i32:$rS, i32:$rB),
2294 def : Pat<(shl i32:$rS, i32:$rB),
2297 def : Pat<(zextloadi1 iaddr:$src),
2299 def : Pat<(zextloadi1 xaddr:$src),
2301 def : Pat<(extloadi1 iaddr:$src),
2303 def : Pat<(extloadi1 xaddr:$src),
2305 def : Pat<(extloadi8 iaddr:$src),
2307 def : Pat<(extloadi8 xaddr:$src),
2309 def : Pat<(extloadi16 iaddr:$src),
2311 def : Pat<(extloadi16 xaddr:$src),
2313 def : Pat<(f64 (extloadf32 iaddr:$src)),
2314 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2315 def : Pat<(f64 (extloadf32 xaddr:$src)),
2316 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2318 def : Pat<(f64 (fextend f32:$src)),
2319 (COPY_TO_REGCLASS $src, F8RC)>;
2321 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>;
2323 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2324 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2325 (FNMSUB $A, $C, $B)>;
2326 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2327 (FNMSUB $A, $C, $B)>;
2328 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2329 (FNMSUBS $A, $C, $B)>;
2330 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2331 (FNMSUBS $A, $C, $B)>;
2333 // FCOPYSIGN's operand types need not agree.
2334 def : Pat<(fcopysign f64:$frB, f32:$frA),
2335 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2336 def : Pat<(fcopysign f32:$frB, f64:$frA),
2337 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2339 include "PPCInstrAltivec.td"
2340 include "PPCInstr64Bit.td"
2343 //===----------------------------------------------------------------------===//
2344 // PowerPC Instructions used for assembler/disassembler only
2347 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
2348 "isync", IIC_SprISYNC, []>;
2350 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
2351 "icbi $src", IIC_LdStICBI, []>;
2353 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
2354 "eieio", IIC_LdStLoad, []>;
2356 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
2357 "wait $L", IIC_LdStLoad, []>;
2359 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
2360 "mtmsr $RS, $L", IIC_SprMTMSR>;
2362 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
2363 "mfmsr $RT", IIC_SprMFMSR, []>;
2365 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
2366 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
2368 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
2369 "slbie $RB", IIC_SprSLBIE, []>;
2371 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
2372 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
2374 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
2375 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
2377 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
2379 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
2380 "tlbsync", IIC_SprTLBSYNC, []>;
2382 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
2383 "tlbiel $RB", IIC_SprTLBIEL, []>;
2385 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
2386 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
2388 //===----------------------------------------------------------------------===//
2389 // PowerPC Assembler Instruction Aliases
2392 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
2393 // These are aliases that require C++ handling to convert to the target
2394 // instruction, while InstAliases can be handled directly by tblgen.
2395 class PPCAsmPseudo<string asm, dag iops>
2397 let Namespace = "PPC";
2398 bit PPC64 = 0; // Default value, override with isPPC64
2400 let OutOperandList = (outs);
2401 let InOperandList = iops;
2403 let AsmString = asm;
2404 let isAsmParserOnly = 1;
2408 def : InstAlias<"sc", (SC 0)>;
2410 def : InstAlias<"sync", (SYNC 0)>;
2411 def : InstAlias<"msync", (SYNC 0)>;
2412 def : InstAlias<"lwsync", (SYNC 1)>;
2413 def : InstAlias<"ptesync", (SYNC 2)>;
2415 def : InstAlias<"wait", (WAIT 0)>;
2416 def : InstAlias<"waitrsv", (WAIT 1)>;
2417 def : InstAlias<"waitimpl", (WAIT 2)>;
2419 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
2420 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
2421 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
2422 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
2424 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
2425 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
2427 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
2428 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
2430 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
2432 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2433 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2435 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2436 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2438 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
2440 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
2442 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
2443 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2444 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
2445 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2446 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
2447 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2448 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
2449 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2451 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2452 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2453 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2454 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2456 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
2457 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
2459 def : InstAlias<"mfsprg $RT, 0", (MFSPR gprc:$RT, 272)>;
2460 def : InstAlias<"mfsprg $RT, 1", (MFSPR gprc:$RT, 273)>;
2461 def : InstAlias<"mfsprg $RT, 2", (MFSPR gprc:$RT, 274)>;
2462 def : InstAlias<"mfsprg $RT, 3", (MFSPR gprc:$RT, 275)>;
2464 def : InstAlias<"mfsprg0 $RT", (MFSPR gprc:$RT, 272)>;
2465 def : InstAlias<"mfsprg1 $RT", (MFSPR gprc:$RT, 273)>;
2466 def : InstAlias<"mfsprg2 $RT", (MFSPR gprc:$RT, 274)>;
2467 def : InstAlias<"mfsprg3 $RT", (MFSPR gprc:$RT, 275)>;
2469 def : InstAlias<"mtsprg 0, $RT", (MTSPR 272, gprc:$RT)>;
2470 def : InstAlias<"mtsprg 1, $RT", (MTSPR 273, gprc:$RT)>;
2471 def : InstAlias<"mtsprg 2, $RT", (MTSPR 274, gprc:$RT)>;
2472 def : InstAlias<"mtsprg 3, $RT", (MTSPR 275, gprc:$RT)>;
2474 def : InstAlias<"mtsprg0 $RT", (MTSPR 272, gprc:$RT)>;
2475 def : InstAlias<"mtsprg1 $RT", (MTSPR 273, gprc:$RT)>;
2476 def : InstAlias<"mtsprg2 $RT", (MTSPR 274, gprc:$RT)>;
2477 def : InstAlias<"mtsprg3 $RT", (MTSPR 275, gprc:$RT)>;
2479 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
2481 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
2482 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
2484 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
2486 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
2487 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
2489 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
2490 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
2491 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
2492 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
2494 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
2496 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
2497 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2498 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
2499 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2500 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
2501 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2502 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
2503 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2504 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
2505 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2506 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
2507 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2508 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
2509 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2510 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
2511 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2512 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
2513 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2514 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
2515 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2516 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
2517 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2518 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
2519 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2520 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
2521 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2522 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
2523 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2524 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
2525 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2526 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
2527 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2528 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
2529 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
2530 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
2531 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
2533 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
2534 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
2535 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
2536 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
2537 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
2538 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
2540 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
2541 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2542 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
2543 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2544 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
2545 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2546 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
2547 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2548 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
2549 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2550 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
2551 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2552 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
2553 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2554 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
2555 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2556 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
2557 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2558 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
2559 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2560 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
2561 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2562 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
2563 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2564 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
2565 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2566 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
2567 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2568 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
2569 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
2570 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
2571 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
2573 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
2574 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
2575 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
2576 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
2577 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
2578 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
2580 // These generic branch instruction forms are used for the assembler parser only.
2581 // Defs and Uses are conservative, since we don't know the BO value.
2582 let PPC970_Unit = 7 in {
2583 let Defs = [CTR], Uses = [CTR, RM] in {
2584 def gBC : BForm_3<16, 0, 0, (outs),
2585 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
2586 "bc $bo, $bi, $dst">;
2587 def gBCA : BForm_3<16, 1, 0, (outs),
2588 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
2589 "bca $bo, $bi, $dst">;
2591 let Defs = [LR, CTR], Uses = [CTR, RM] in {
2592 def gBCL : BForm_3<16, 0, 1, (outs),
2593 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
2594 "bcl $bo, $bi, $dst">;
2595 def gBCLA : BForm_3<16, 1, 1, (outs),
2596 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
2597 "bcla $bo, $bi, $dst">;
2599 let Defs = [CTR], Uses = [CTR, LR, RM] in
2600 def gBCLR : XLForm_2<19, 16, 0, (outs),
2601 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2602 "bclr $bo, $bi, $bh", IIC_BrB, []>;
2603 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
2604 def gBCLRL : XLForm_2<19, 16, 1, (outs),
2605 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2606 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
2607 let Defs = [CTR], Uses = [CTR, LR, RM] in
2608 def gBCCTR : XLForm_2<19, 528, 0, (outs),
2609 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2610 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
2611 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
2612 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
2613 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2614 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
2616 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
2617 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
2618 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
2619 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
2621 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
2622 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
2623 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
2624 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
2625 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
2626 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
2627 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
2629 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
2630 : BranchSimpleMnemonic1<name, pm, bo> {
2631 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
2632 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
2634 defm : BranchSimpleMnemonic2<"t", "", 12>;
2635 defm : BranchSimpleMnemonic2<"f", "", 4>;
2636 defm : BranchSimpleMnemonic2<"t", "-", 14>;
2637 defm : BranchSimpleMnemonic2<"f", "-", 6>;
2638 defm : BranchSimpleMnemonic2<"t", "+", 15>;
2639 defm : BranchSimpleMnemonic2<"f", "+", 7>;
2640 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
2641 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
2642 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
2643 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
2645 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
2646 def : InstAlias<"b"#name#pm#" $cc, $dst",
2647 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
2648 def : InstAlias<"b"#name#pm#" $dst",
2649 (BCC bibo, CR0, condbrtarget:$dst)>;
2651 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
2652 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
2653 def : InstAlias<"b"#name#"a"#pm#" $dst",
2654 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
2656 def : InstAlias<"b"#name#"lr"#pm#" $cc",
2657 (BCLR bibo, crrc:$cc)>;
2658 def : InstAlias<"b"#name#"lr"#pm,
2661 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
2662 (BCCTR bibo, crrc:$cc)>;
2663 def : InstAlias<"b"#name#"ctr"#pm,
2666 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
2667 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
2668 def : InstAlias<"b"#name#"l"#pm#" $dst",
2669 (BCCL bibo, CR0, condbrtarget:$dst)>;
2671 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
2672 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
2673 def : InstAlias<"b"#name#"la"#pm#" $dst",
2674 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
2676 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
2677 (BCLRL bibo, crrc:$cc)>;
2678 def : InstAlias<"b"#name#"lrl"#pm,
2681 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
2682 (BCCTRL bibo, crrc:$cc)>;
2683 def : InstAlias<"b"#name#"ctrl"#pm,
2684 (BCCTRL bibo, CR0)>;
2686 multiclass BranchExtendedMnemonic<string name, int bibo> {
2687 defm : BranchExtendedMnemonicPM<name, "", bibo>;
2688 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
2689 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
2691 defm : BranchExtendedMnemonic<"lt", 12>;
2692 defm : BranchExtendedMnemonic<"gt", 44>;
2693 defm : BranchExtendedMnemonic<"eq", 76>;
2694 defm : BranchExtendedMnemonic<"un", 108>;
2695 defm : BranchExtendedMnemonic<"so", 108>;
2696 defm : BranchExtendedMnemonic<"ge", 4>;
2697 defm : BranchExtendedMnemonic<"nl", 4>;
2698 defm : BranchExtendedMnemonic<"le", 36>;
2699 defm : BranchExtendedMnemonic<"ng", 36>;
2700 defm : BranchExtendedMnemonic<"ne", 68>;
2701 defm : BranchExtendedMnemonic<"nu", 100>;
2702 defm : BranchExtendedMnemonic<"ns", 100>;
2704 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
2705 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
2706 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
2707 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
2708 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
2709 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
2710 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
2711 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
2713 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
2714 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
2715 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
2716 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
2717 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
2718 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
2719 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
2720 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
2722 multiclass TrapExtendedMnemonic<string name, int to> {
2723 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
2724 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
2725 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
2726 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
2728 defm : TrapExtendedMnemonic<"lt", 16>;
2729 defm : TrapExtendedMnemonic<"le", 20>;
2730 defm : TrapExtendedMnemonic<"eq", 4>;
2731 defm : TrapExtendedMnemonic<"ge", 12>;
2732 defm : TrapExtendedMnemonic<"gt", 8>;
2733 defm : TrapExtendedMnemonic<"nl", 12>;
2734 defm : TrapExtendedMnemonic<"ne", 24>;
2735 defm : TrapExtendedMnemonic<"ng", 20>;
2736 defm : TrapExtendedMnemonic<"llt", 2>;
2737 defm : TrapExtendedMnemonic<"lle", 6>;
2738 defm : TrapExtendedMnemonic<"lge", 5>;
2739 defm : TrapExtendedMnemonic<"lgt", 1>;
2740 defm : TrapExtendedMnemonic<"lnl", 5>;
2741 defm : TrapExtendedMnemonic<"lng", 6>;
2742 defm : TrapExtendedMnemonic<"u", 31>;