1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
60 def tocentry32 : Operand<iPTR> {
61 let MIOperandInfo = (ops i32imm:$imm);
64 //===----------------------------------------------------------------------===//
65 // PowerPC specific DAG Nodes.
68 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
69 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
71 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
72 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
73 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
74 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
75 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
76 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
77 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
78 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
79 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
80 [SDNPHasChain, SDNPMayStore]>;
81 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
82 [SDNPHasChain, SDNPMayLoad]>;
83 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
84 [SDNPHasChain, SDNPMayLoad]>;
86 // Extract FPSCR (not modeled at the DAG level).
87 def PPCmffs : SDNode<"PPCISD::MFFS",
88 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
90 // Perform FADD in round-to-zero mode.
91 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
94 def PPCfsel : SDNode<"PPCISD::FSEL",
95 // Type constraint for fsel.
96 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
97 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
99 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
100 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
101 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
102 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
103 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
105 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
107 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
108 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
110 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
111 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
112 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
113 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
114 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
115 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
116 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
117 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
119 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
121 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
123 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
124 // amounts. These nodes are generated by the multi-precision shift code.
125 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
126 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
127 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
129 // These are target-independent nodes, but have target-specific formats.
130 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
131 [SDNPHasChain, SDNPOutGlue]>;
132 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
135 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
136 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
139 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
142 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
143 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
144 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
145 [SDNPHasChain, SDNPSideEffect,
146 SDNPInGlue, SDNPOutGlue]>;
147 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
149 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
150 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
153 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
154 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
156 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
157 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
159 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
160 SDTypeProfile<1, 1, [SDTCisInt<0>,
162 [SDNPHasChain, SDNPSideEffect]>;
163 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
164 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
165 [SDNPHasChain, SDNPSideEffect]>;
167 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
168 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
169 [SDNPHasChain, SDNPSideEffect]>;
171 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
172 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
174 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
175 [SDNPHasChain, SDNPOptInGlue]>;
177 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
178 [SDNPHasChain, SDNPMayLoad]>;
179 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
180 [SDNPHasChain, SDNPMayStore]>;
182 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
183 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
186 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
188 // Instructions to support atomic operations
189 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
190 [SDNPHasChain, SDNPMayLoad]>;
191 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
192 [SDNPHasChain, SDNPMayStore]>;
194 // Instructions to support medium and large code model
195 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
196 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
197 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
200 // Instructions to support dynamic alloca.
201 def SDTDynOp : SDTypeProfile<1, 2, []>;
202 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
204 //===----------------------------------------------------------------------===//
205 // PowerPC specific transformation functions and pattern fragments.
208 def SHL32 : SDNodeXForm<imm, [{
209 // Transformation function: 31 - imm
210 return getI32Imm(31 - N->getZExtValue());
213 def SRL32 : SDNodeXForm<imm, [{
214 // Transformation function: 32 - imm
215 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
218 def LO16 : SDNodeXForm<imm, [{
219 // Transformation function: get the low 16 bits.
220 return getI32Imm((unsigned short)N->getZExtValue());
223 def HI16 : SDNodeXForm<imm, [{
224 // Transformation function: shift the immediate value down into the low bits.
225 return getI32Imm((unsigned)N->getZExtValue() >> 16);
228 def HA16 : SDNodeXForm<imm, [{
229 // Transformation function: shift the immediate value down into the low bits.
230 signed int Val = N->getZExtValue();
231 return getI32Imm((Val - (signed short)Val) >> 16);
233 def MB : SDNodeXForm<imm, [{
234 // Transformation function: get the start bit of a mask
236 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
237 return getI32Imm(mb);
240 def ME : SDNodeXForm<imm, [{
241 // Transformation function: get the end bit of a mask
243 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
244 return getI32Imm(me);
246 def maskimm32 : PatLeaf<(imm), [{
247 // maskImm predicate - True if immediate is a run of ones.
249 if (N->getValueType(0) == MVT::i32)
250 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
255 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
256 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
257 // sign extended field. Used by instructions like 'addi'.
258 return (int32_t)Imm == (short)Imm;
260 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
261 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
262 // sign extended field. Used by instructions like 'addi'.
263 return (int64_t)Imm == (short)Imm;
265 def immZExt16 : PatLeaf<(imm), [{
266 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
267 // field. Used by instructions like 'ori'.
268 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
271 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
272 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
273 // identical in 32-bit mode, but in 64-bit mode, they return true if the
274 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
276 def imm16ShiftedZExt : PatLeaf<(imm), [{
277 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
278 // immediate are set. Used by instructions like 'xoris'.
279 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
282 def imm16ShiftedSExt : PatLeaf<(imm), [{
283 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
284 // immediate are set. Used by instructions like 'addis'. Identical to
285 // imm16ShiftedZExt in 32-bit mode.
286 if (N->getZExtValue() & 0xFFFF) return false;
287 if (N->getValueType(0) == MVT::i32)
289 // For 64-bit, make sure it is sext right.
290 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
293 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
294 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
295 // zero extended field.
296 return isUInt<32>(Imm);
299 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
300 // restricted memrix (4-aligned) constants are alignment sensitive. If these
301 // offsets are hidden behind TOC entries than the values of the lower-order
302 // bits cannot be checked directly. As a result, we need to also incorporate
303 // an alignment check into the relevant patterns.
305 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
306 return cast<LoadSDNode>(N)->getAlignment() >= 4;
308 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
309 (store node:$val, node:$ptr), [{
310 return cast<StoreSDNode>(N)->getAlignment() >= 4;
312 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
313 return cast<LoadSDNode>(N)->getAlignment() >= 4;
315 def aligned4pre_store : PatFrag<
316 (ops node:$val, node:$base, node:$offset),
317 (pre_store node:$val, node:$base, node:$offset), [{
318 return cast<StoreSDNode>(N)->getAlignment() >= 4;
321 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
322 return cast<LoadSDNode>(N)->getAlignment() < 4;
324 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
325 (store node:$val, node:$ptr), [{
326 return cast<StoreSDNode>(N)->getAlignment() < 4;
328 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
329 return cast<LoadSDNode>(N)->getAlignment() < 4;
332 //===----------------------------------------------------------------------===//
333 // PowerPC Flag Definitions.
335 class isPPC64 { bit PPC64 = 1; }
336 class isDOT { bit RC = 1; }
338 class RegConstraint<string C> {
339 string Constraints = C;
341 class NoEncode<string E> {
342 string DisableEncoding = E;
346 //===----------------------------------------------------------------------===//
347 // PowerPC Operand Definitions.
349 // In the default PowerPC assembler syntax, registers are specified simply
350 // by number, so they cannot be distinguished from immediate values (without
351 // looking at the opcode). This means that the default operand matching logic
352 // for the asm parser does not work, and we need to specify custom matchers.
353 // Since those can only be specified with RegisterOperand classes and not
354 // directly on the RegisterClass, all instructions patterns used by the asm
355 // parser need to use a RegisterOperand (instead of a RegisterClass) for
356 // all their register operands.
357 // For this purpose, we define one RegisterOperand for each RegisterClass,
358 // using the same name as the class, just in lower case.
360 def PPCRegGPRCAsmOperand : AsmOperandClass {
361 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
363 def gprc : RegisterOperand<GPRC> {
364 let ParserMatchClass = PPCRegGPRCAsmOperand;
366 def PPCRegG8RCAsmOperand : AsmOperandClass {
367 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
369 def g8rc : RegisterOperand<G8RC> {
370 let ParserMatchClass = PPCRegG8RCAsmOperand;
372 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
373 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
375 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
376 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
378 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
379 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
381 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
382 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
384 def PPCRegF8RCAsmOperand : AsmOperandClass {
385 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
387 def f8rc : RegisterOperand<F8RC> {
388 let ParserMatchClass = PPCRegF8RCAsmOperand;
390 def PPCRegF4RCAsmOperand : AsmOperandClass {
391 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
393 def f4rc : RegisterOperand<F4RC> {
394 let ParserMatchClass = PPCRegF4RCAsmOperand;
396 def PPCRegVRRCAsmOperand : AsmOperandClass {
397 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
399 def vrrc : RegisterOperand<VRRC> {
400 let ParserMatchClass = PPCRegVRRCAsmOperand;
402 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
403 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
405 def crbitrc : RegisterOperand<CRBITRC> {
406 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
408 def PPCRegCRRCAsmOperand : AsmOperandClass {
409 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
411 def crrc : RegisterOperand<CRRC> {
412 let ParserMatchClass = PPCRegCRRCAsmOperand;
415 def PPCU2ImmAsmOperand : AsmOperandClass {
416 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
417 let RenderMethod = "addImmOperands";
419 def u2imm : Operand<i32> {
420 let PrintMethod = "printU2ImmOperand";
421 let ParserMatchClass = PPCU2ImmAsmOperand;
424 def PPCU4ImmAsmOperand : AsmOperandClass {
425 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
426 let RenderMethod = "addImmOperands";
428 def u4imm : Operand<i32> {
429 let PrintMethod = "printU4ImmOperand";
430 let ParserMatchClass = PPCU4ImmAsmOperand;
432 def PPCS5ImmAsmOperand : AsmOperandClass {
433 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
434 let RenderMethod = "addImmOperands";
436 def s5imm : Operand<i32> {
437 let PrintMethod = "printS5ImmOperand";
438 let ParserMatchClass = PPCS5ImmAsmOperand;
439 let DecoderMethod = "decodeSImmOperand<5>";
441 def PPCU5ImmAsmOperand : AsmOperandClass {
442 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
443 let RenderMethod = "addImmOperands";
445 def u5imm : Operand<i32> {
446 let PrintMethod = "printU5ImmOperand";
447 let ParserMatchClass = PPCU5ImmAsmOperand;
448 let DecoderMethod = "decodeUImmOperand<5>";
450 def PPCU6ImmAsmOperand : AsmOperandClass {
451 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
452 let RenderMethod = "addImmOperands";
454 def u6imm : Operand<i32> {
455 let PrintMethod = "printU6ImmOperand";
456 let ParserMatchClass = PPCU6ImmAsmOperand;
457 let DecoderMethod = "decodeUImmOperand<6>";
459 def PPCS16ImmAsmOperand : AsmOperandClass {
460 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
461 let RenderMethod = "addS16ImmOperands";
463 def s16imm : Operand<i32> {
464 let PrintMethod = "printS16ImmOperand";
465 let EncoderMethod = "getImm16Encoding";
466 let ParserMatchClass = PPCS16ImmAsmOperand;
467 let DecoderMethod = "decodeSImmOperand<16>";
469 def PPCU16ImmAsmOperand : AsmOperandClass {
470 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
471 let RenderMethod = "addU16ImmOperands";
473 def u16imm : Operand<i32> {
474 let PrintMethod = "printU16ImmOperand";
475 let EncoderMethod = "getImm16Encoding";
476 let ParserMatchClass = PPCU16ImmAsmOperand;
477 let DecoderMethod = "decodeUImmOperand<16>";
479 def PPCS17ImmAsmOperand : AsmOperandClass {
480 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
481 let RenderMethod = "addS16ImmOperands";
483 def s17imm : Operand<i32> {
484 // This operand type is used for addis/lis to allow the assembler parser
485 // to accept immediates in the range -65536..65535 for compatibility with
486 // the GNU assembler. The operand is treated as 16-bit otherwise.
487 let PrintMethod = "printS16ImmOperand";
488 let EncoderMethod = "getImm16Encoding";
489 let ParserMatchClass = PPCS17ImmAsmOperand;
490 let DecoderMethod = "decodeSImmOperand<16>";
492 def PPCDirectBrAsmOperand : AsmOperandClass {
493 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
494 let RenderMethod = "addBranchTargetOperands";
496 def directbrtarget : Operand<OtherVT> {
497 let PrintMethod = "printBranchOperand";
498 let EncoderMethod = "getDirectBrEncoding";
499 let ParserMatchClass = PPCDirectBrAsmOperand;
501 def absdirectbrtarget : Operand<OtherVT> {
502 let PrintMethod = "printAbsBranchOperand";
503 let EncoderMethod = "getAbsDirectBrEncoding";
504 let ParserMatchClass = PPCDirectBrAsmOperand;
506 def PPCCondBrAsmOperand : AsmOperandClass {
507 let Name = "CondBr"; let PredicateMethod = "isCondBr";
508 let RenderMethod = "addBranchTargetOperands";
510 def condbrtarget : Operand<OtherVT> {
511 let PrintMethod = "printBranchOperand";
512 let EncoderMethod = "getCondBrEncoding";
513 let ParserMatchClass = PPCCondBrAsmOperand;
515 def abscondbrtarget : Operand<OtherVT> {
516 let PrintMethod = "printAbsBranchOperand";
517 let EncoderMethod = "getAbsCondBrEncoding";
518 let ParserMatchClass = PPCCondBrAsmOperand;
520 def calltarget : Operand<iPTR> {
521 let PrintMethod = "printBranchOperand";
522 let EncoderMethod = "getDirectBrEncoding";
523 let ParserMatchClass = PPCDirectBrAsmOperand;
525 def abscalltarget : Operand<iPTR> {
526 let PrintMethod = "printAbsBranchOperand";
527 let EncoderMethod = "getAbsDirectBrEncoding";
528 let ParserMatchClass = PPCDirectBrAsmOperand;
530 def PPCCRBitMaskOperand : AsmOperandClass {
531 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
533 def crbitm: Operand<i8> {
534 let PrintMethod = "printcrbitm";
535 let EncoderMethod = "get_crbitm_encoding";
536 let DecoderMethod = "decodeCRBitMOperand";
537 let ParserMatchClass = PPCCRBitMaskOperand;
540 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
541 def PPCRegGxRCNoR0Operand : AsmOperandClass {
542 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
544 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
545 let ParserMatchClass = PPCRegGxRCNoR0Operand;
547 // A version of ptr_rc usable with the asm parser.
548 def PPCRegGxRCOperand : AsmOperandClass {
549 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
551 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
552 let ParserMatchClass = PPCRegGxRCOperand;
555 def PPCDispRIOperand : AsmOperandClass {
556 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
557 let RenderMethod = "addS16ImmOperands";
559 def dispRI : Operand<iPTR> {
560 let ParserMatchClass = PPCDispRIOperand;
562 def PPCDispRIXOperand : AsmOperandClass {
563 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
564 let RenderMethod = "addImmOperands";
566 def dispRIX : Operand<iPTR> {
567 let ParserMatchClass = PPCDispRIXOperand;
569 def PPCDispSPE8Operand : AsmOperandClass {
570 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
571 let RenderMethod = "addImmOperands";
573 def dispSPE8 : Operand<iPTR> {
574 let ParserMatchClass = PPCDispSPE8Operand;
576 def PPCDispSPE4Operand : AsmOperandClass {
577 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
578 let RenderMethod = "addImmOperands";
580 def dispSPE4 : Operand<iPTR> {
581 let ParserMatchClass = PPCDispSPE4Operand;
583 def PPCDispSPE2Operand : AsmOperandClass {
584 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
585 let RenderMethod = "addImmOperands";
587 def dispSPE2 : Operand<iPTR> {
588 let ParserMatchClass = PPCDispSPE2Operand;
591 def memri : Operand<iPTR> {
592 let PrintMethod = "printMemRegImm";
593 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
594 let EncoderMethod = "getMemRIEncoding";
595 let DecoderMethod = "decodeMemRIOperands";
597 def memrr : Operand<iPTR> {
598 let PrintMethod = "printMemRegReg";
599 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
601 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
602 let PrintMethod = "printMemRegImm";
603 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
604 let EncoderMethod = "getMemRIXEncoding";
605 let DecoderMethod = "decodeMemRIXOperands";
607 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
608 let PrintMethod = "printMemRegImm";
609 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
610 let EncoderMethod = "getSPE8DisEncoding";
612 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
613 let PrintMethod = "printMemRegImm";
614 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
615 let EncoderMethod = "getSPE4DisEncoding";
617 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
618 let PrintMethod = "printMemRegImm";
619 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
620 let EncoderMethod = "getSPE2DisEncoding";
623 // A single-register address. This is used with the SjLj
624 // pseudo-instructions.
625 def memr : Operand<iPTR> {
626 let MIOperandInfo = (ops ptr_rc:$ptrreg);
628 def PPCTLSRegOperand : AsmOperandClass {
629 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
630 let RenderMethod = "addTLSRegOperands";
632 def tlsreg32 : Operand<i32> {
633 let EncoderMethod = "getTLSRegEncoding";
634 let ParserMatchClass = PPCTLSRegOperand;
636 def tlsgd32 : Operand<i32> {}
637 def tlscall32 : Operand<i32> {
638 let PrintMethod = "printTLSCall";
639 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
640 let EncoderMethod = "getTLSCallEncoding";
643 // PowerPC Predicate operand.
644 def pred : Operand<OtherVT> {
645 let PrintMethod = "printPredicateOperand";
646 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
649 // Define PowerPC specific addressing mode.
650 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
651 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
652 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
653 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
655 // The address in a single register. This is used with the SjLj
656 // pseudo-instructions.
657 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
659 /// This is just the offset part of iaddr, used for preinc.
660 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
662 //===----------------------------------------------------------------------===//
663 // PowerPC Instruction Predicate Definitions.
664 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
665 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
666 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
667 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
668 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
669 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
670 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
671 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
673 //===----------------------------------------------------------------------===//
674 // PowerPC Multiclass Definitions.
676 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
677 string asmbase, string asmstr, InstrItinClass itin,
679 let BaseName = asmbase in {
680 def NAME : XForm_6<opcode, xo, OOL, IOL,
681 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
682 pattern>, RecFormRel;
684 def o : XForm_6<opcode, xo, OOL, IOL,
685 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
686 []>, isDOT, RecFormRel;
690 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
691 string asmbase, string asmstr, InstrItinClass itin,
693 let BaseName = asmbase in {
694 let Defs = [CARRY] in
695 def NAME : XForm_6<opcode, xo, OOL, IOL,
696 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
697 pattern>, RecFormRel;
698 let Defs = [CARRY, CR0] in
699 def o : XForm_6<opcode, xo, OOL, IOL,
700 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
701 []>, isDOT, RecFormRel;
705 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
706 string asmbase, string asmstr, InstrItinClass itin,
708 let BaseName = asmbase in {
709 let Defs = [CARRY] in
710 def NAME : XForm_10<opcode, xo, OOL, IOL,
711 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
712 pattern>, RecFormRel;
713 let Defs = [CARRY, CR0] in
714 def o : XForm_10<opcode, xo, OOL, IOL,
715 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
716 []>, isDOT, RecFormRel;
720 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
721 string asmbase, string asmstr, InstrItinClass itin,
723 let BaseName = asmbase in {
724 def NAME : XForm_11<opcode, xo, OOL, IOL,
725 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
726 pattern>, RecFormRel;
728 def o : XForm_11<opcode, xo, OOL, IOL,
729 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
730 []>, isDOT, RecFormRel;
734 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
735 string asmbase, string asmstr, InstrItinClass itin,
737 let BaseName = asmbase in {
738 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
739 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
740 pattern>, RecFormRel;
742 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
743 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
744 []>, isDOT, RecFormRel;
748 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
749 string asmbase, string asmstr, InstrItinClass itin,
751 let BaseName = asmbase in {
752 let Defs = [CARRY] in
753 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
754 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
755 pattern>, RecFormRel;
756 let Defs = [CARRY, CR0] in
757 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
758 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
759 []>, isDOT, RecFormRel;
763 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
764 string asmbase, string asmstr, InstrItinClass itin,
766 let BaseName = asmbase in {
767 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
768 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
769 pattern>, RecFormRel;
771 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
772 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
773 []>, isDOT, RecFormRel;
777 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
778 string asmbase, string asmstr, InstrItinClass itin,
780 let BaseName = asmbase in {
781 let Defs = [CARRY] in
782 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
783 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
784 pattern>, RecFormRel;
785 let Defs = [CARRY, CR0] in
786 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
787 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
788 []>, isDOT, RecFormRel;
792 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
793 string asmbase, string asmstr, InstrItinClass itin,
795 let BaseName = asmbase in {
796 def NAME : MForm_2<opcode, OOL, IOL,
797 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
798 pattern>, RecFormRel;
800 def o : MForm_2<opcode, OOL, IOL,
801 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
802 []>, isDOT, RecFormRel;
806 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
807 string asmbase, string asmstr, InstrItinClass itin,
809 let BaseName = asmbase in {
810 def NAME : MDForm_1<opcode, xo, OOL, IOL,
811 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
812 pattern>, RecFormRel;
814 def o : MDForm_1<opcode, xo, OOL, IOL,
815 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
816 []>, isDOT, RecFormRel;
820 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
821 string asmbase, string asmstr, InstrItinClass itin,
823 let BaseName = asmbase in {
824 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
825 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
826 pattern>, RecFormRel;
828 def o : MDSForm_1<opcode, xo, OOL, IOL,
829 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
830 []>, isDOT, RecFormRel;
834 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
835 string asmbase, string asmstr, InstrItinClass itin,
837 let BaseName = asmbase in {
838 let Defs = [CARRY] in
839 def NAME : XSForm_1<opcode, xo, OOL, IOL,
840 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
841 pattern>, RecFormRel;
842 let Defs = [CARRY, CR0] in
843 def o : XSForm_1<opcode, xo, OOL, IOL,
844 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
845 []>, isDOT, RecFormRel;
849 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
850 string asmbase, string asmstr, InstrItinClass itin,
852 let BaseName = asmbase in {
853 def NAME : XForm_26<opcode, xo, OOL, IOL,
854 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
855 pattern>, RecFormRel;
857 def o : XForm_26<opcode, xo, OOL, IOL,
858 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
859 []>, isDOT, RecFormRel;
863 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
864 string asmbase, string asmstr, InstrItinClass itin,
866 let BaseName = asmbase in {
867 def NAME : XForm_28<opcode, xo, OOL, IOL,
868 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
869 pattern>, RecFormRel;
871 def o : XForm_28<opcode, xo, OOL, IOL,
872 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
873 []>, isDOT, RecFormRel;
877 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
878 string asmbase, string asmstr, InstrItinClass itin,
880 let BaseName = asmbase in {
881 def NAME : AForm_1<opcode, xo, OOL, IOL,
882 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
883 pattern>, RecFormRel;
885 def o : AForm_1<opcode, xo, OOL, IOL,
886 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
887 []>, isDOT, RecFormRel;
891 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
892 string asmbase, string asmstr, InstrItinClass itin,
894 let BaseName = asmbase in {
895 def NAME : AForm_2<opcode, xo, OOL, IOL,
896 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
897 pattern>, RecFormRel;
899 def o : AForm_2<opcode, xo, OOL, IOL,
900 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
901 []>, isDOT, RecFormRel;
905 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
906 string asmbase, string asmstr, InstrItinClass itin,
908 let BaseName = asmbase in {
909 def NAME : AForm_3<opcode, xo, OOL, IOL,
910 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
911 pattern>, RecFormRel;
913 def o : AForm_3<opcode, xo, OOL, IOL,
914 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
915 []>, isDOT, RecFormRel;
919 //===----------------------------------------------------------------------===//
920 // PowerPC Instruction Definitions.
922 // Pseudo-instructions:
924 let hasCtrlDep = 1 in {
925 let Defs = [R1], Uses = [R1] in {
926 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
927 [(callseq_start timm:$amt)]>;
928 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
929 [(callseq_end timm:$amt1, timm:$amt2)]>;
932 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
933 "UPDATE_VRSAVE $rD, $rS", []>;
936 let Defs = [R1], Uses = [R1] in
937 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
939 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
941 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
942 // instruction selection into a branch sequence.
943 let usesCustomInserter = 1, // Expanded after instruction selection.
944 PPC970_Single = 1 in {
945 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
946 // because either operand might become the first operand in an isel, and
947 // that operand cannot be r0.
948 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
949 gprc_nor0:$T, gprc_nor0:$F,
950 i32imm:$BROPC), "#SELECT_CC_I4",
952 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
953 g8rc_nox0:$T, g8rc_nox0:$F,
954 i32imm:$BROPC), "#SELECT_CC_I8",
956 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
957 i32imm:$BROPC), "#SELECT_CC_F4",
959 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
960 i32imm:$BROPC), "#SELECT_CC_F8",
962 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
963 i32imm:$BROPC), "#SELECT_CC_VRRC",
966 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
967 // register bit directly.
968 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
969 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
970 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
971 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
972 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
973 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
974 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
975 f4rc:$T, f4rc:$F), "#SELECT_F4",
976 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
977 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
978 f8rc:$T, f8rc:$F), "#SELECT_F8",
979 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
980 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
981 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
983 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
986 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
987 // scavenge a register for it.
988 let mayStore = 1 in {
989 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
991 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
995 // RESTORE_CR - Indicate that we're restoring the CR register (previously
996 // spilled), so we'll need to scavenge a register for it.
998 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1000 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1001 "#RESTORE_CRBIT", []>;
1004 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1005 let isReturn = 1, Uses = [LR, RM] in
1006 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1008 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1009 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1012 let isCodeGenOnly = 1 in {
1013 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1014 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1017 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1018 "bcctr 12, $bi, 0", IIC_BrB, []>;
1019 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1020 "bcctr 4, $bi, 0", IIC_BrB, []>;
1026 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1029 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1030 let isBarrier = 1 in {
1031 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1034 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1035 "ba $dst", IIC_BrB, []>;
1038 // BCC represents an arbitrary conditional branch on a predicate.
1039 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1040 // a two-value operand where a dag node expects two operands. :(
1041 let isCodeGenOnly = 1 in {
1042 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1043 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1044 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1045 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1046 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1048 let isReturn = 1, Uses = [LR, RM] in
1049 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1050 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1053 let isCodeGenOnly = 1 in {
1054 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1055 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1056 "bc 12, $bi, $dst">;
1058 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1059 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1062 let isReturn = 1, Uses = [LR, RM] in
1063 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1064 "bclr 12, $bi, 0", IIC_BrB, []>;
1065 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1066 "bclr 4, $bi, 0", IIC_BrB, []>;
1069 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1070 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1071 "bdzlr", IIC_BrB, []>;
1072 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1073 "bdnzlr", IIC_BrB, []>;
1074 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1075 "bdzlr+", IIC_BrB, []>;
1076 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1077 "bdnzlr+", IIC_BrB, []>;
1078 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1079 "bdzlr-", IIC_BrB, []>;
1080 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1081 "bdnzlr-", IIC_BrB, []>;
1084 let Defs = [CTR], Uses = [CTR] in {
1085 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1087 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1089 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1091 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1093 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1095 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1097 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1099 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1101 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1103 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1105 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1107 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1112 // The unconditional BCL used by the SjLj setjmp code.
1113 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1114 let Defs = [LR], Uses = [RM] in {
1115 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1116 "bcl 20, 31, $dst">;
1120 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1121 // Convenient aliases for call instructions
1122 let Uses = [RM] in {
1123 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1124 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1125 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1126 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1128 let isCodeGenOnly = 1 in {
1129 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1130 "bl $func", IIC_BrB, []>;
1131 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1132 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1133 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1134 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1136 def BCL : BForm_4<16, 12, 0, 1, (outs),
1137 (ins crbitrc:$bi, condbrtarget:$dst),
1138 "bcl 12, $bi, $dst">;
1139 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1140 (ins crbitrc:$bi, condbrtarget:$dst),
1141 "bcl 4, $bi, $dst">;
1144 let Uses = [CTR, RM] in {
1145 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1146 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1147 Requires<[In32BitMode]>;
1149 let isCodeGenOnly = 1 in {
1150 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1151 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1154 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1155 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1156 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1157 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1160 let Uses = [LR, RM] in {
1161 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1162 "blrl", IIC_BrB, []>;
1164 let isCodeGenOnly = 1 in {
1165 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1166 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1169 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1170 "bclrl 12, $bi, 0", IIC_BrB, []>;
1171 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1172 "bclrl 4, $bi, 0", IIC_BrB, []>;
1175 let Defs = [CTR], Uses = [CTR, RM] in {
1176 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1178 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1180 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1182 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1184 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1186 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1188 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1190 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1192 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1194 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1196 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1198 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1201 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1202 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1203 "bdzlrl", IIC_BrB, []>;
1204 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1205 "bdnzlrl", IIC_BrB, []>;
1206 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1207 "bdzlrl+", IIC_BrB, []>;
1208 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1209 "bdnzlrl+", IIC_BrB, []>;
1210 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1211 "bdzlrl-", IIC_BrB, []>;
1212 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1213 "bdnzlrl-", IIC_BrB, []>;
1217 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1218 def TCRETURNdi :Pseudo< (outs),
1219 (ins calltarget:$dst, i32imm:$offset),
1220 "#TC_RETURNd $dst $offset",
1224 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1225 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1226 "#TC_RETURNa $func $offset",
1227 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1229 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1230 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1231 "#TC_RETURNr $dst $offset",
1235 let isCodeGenOnly = 1 in {
1237 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1238 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1239 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1240 []>, Requires<[In32BitMode]>;
1242 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1243 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1244 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1248 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1249 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1250 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1256 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1258 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1259 "#EH_SJLJ_SETJMP32",
1260 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1261 Requires<[In32BitMode]>;
1262 let isTerminator = 1 in
1263 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1264 "#EH_SJLJ_LONGJMP32",
1265 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1266 Requires<[In32BitMode]>;
1269 let isBranch = 1, isTerminator = 1 in {
1270 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1271 "#EH_SjLj_Setup\t$dst", []>;
1275 let PPC970_Unit = 7 in {
1276 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1277 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1280 // DCB* instructions.
1281 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1282 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1283 PPC970_DGroup_Single;
1284 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1285 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1286 PPC970_DGroup_Single;
1287 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1288 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1289 PPC970_DGroup_Single;
1290 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1291 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1292 PPC970_DGroup_Single;
1293 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1294 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1295 PPC970_DGroup_Single;
1296 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1297 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1298 PPC970_DGroup_Single;
1299 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1300 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1301 PPC970_DGroup_Single;
1302 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1303 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1304 PPC970_DGroup_Single;
1306 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1307 "icbt $CT, $src", IIC_LdStLoad>, Requires<[IsBookE]>;
1309 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1310 (DCBT xoaddr:$dst)>; // data prefetch for loads
1311 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1312 (DCBTST xoaddr:$dst)>; // data prefetch for stores
1313 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1314 (ICBT 0, xoaddr:$dst)>; // inst prefetch (for read)
1316 // Atomic operations
1317 let usesCustomInserter = 1 in {
1318 let Defs = [CR0] in {
1319 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1320 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1321 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1322 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1323 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1324 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1325 def ATOMIC_LOAD_AND_I8 : Pseudo<
1326 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1327 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1328 def ATOMIC_LOAD_OR_I8 : Pseudo<
1329 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1330 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1331 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1332 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1333 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1334 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1335 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1336 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1337 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1338 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1339 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1340 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1341 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1342 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1343 def ATOMIC_LOAD_AND_I16 : Pseudo<
1344 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1345 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1346 def ATOMIC_LOAD_OR_I16 : Pseudo<
1347 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1348 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1349 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1350 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1351 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1352 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1353 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1354 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1355 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1356 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1357 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1358 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1359 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1360 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1361 def ATOMIC_LOAD_AND_I32 : Pseudo<
1362 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1363 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1364 def ATOMIC_LOAD_OR_I32 : Pseudo<
1365 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1366 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1367 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1368 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1369 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1370 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1371 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1372 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1374 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1375 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1376 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1377 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1378 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1379 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1380 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1381 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1382 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1384 def ATOMIC_SWAP_I8 : Pseudo<
1385 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1386 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1387 def ATOMIC_SWAP_I16 : Pseudo<
1388 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1389 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1390 def ATOMIC_SWAP_I32 : Pseudo<
1391 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1392 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1396 // Instructions to support atomic operations
1397 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1398 "lwarx $rD, $src", IIC_LdStLWARX,
1399 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1402 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1403 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1404 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1407 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1408 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1410 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1411 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1412 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1413 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1414 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1415 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1416 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1417 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1419 //===----------------------------------------------------------------------===//
1420 // PPC32 Load Instructions.
1423 // Unindexed (r+i) Loads.
1424 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1425 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1426 "lbz $rD, $src", IIC_LdStLoad,
1427 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1428 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1429 "lha $rD, $src", IIC_LdStLHA,
1430 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1431 PPC970_DGroup_Cracked;
1432 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1433 "lhz $rD, $src", IIC_LdStLoad,
1434 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1435 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1436 "lwz $rD, $src", IIC_LdStLoad,
1437 [(set i32:$rD, (load iaddr:$src))]>;
1439 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1440 "lfs $rD, $src", IIC_LdStLFD,
1441 [(set f32:$rD, (load iaddr:$src))]>;
1442 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1443 "lfd $rD, $src", IIC_LdStLFD,
1444 [(set f64:$rD, (load iaddr:$src))]>;
1447 // Unindexed (r+i) Loads with Update (preinc).
1448 let mayLoad = 1, neverHasSideEffects = 1 in {
1449 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1450 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1451 []>, RegConstraint<"$addr.reg = $ea_result">,
1452 NoEncode<"$ea_result">;
1454 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1455 "lhau $rD, $addr", IIC_LdStLHAU,
1456 []>, RegConstraint<"$addr.reg = $ea_result">,
1457 NoEncode<"$ea_result">;
1459 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1460 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1461 []>, RegConstraint<"$addr.reg = $ea_result">,
1462 NoEncode<"$ea_result">;
1464 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1465 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1466 []>, RegConstraint<"$addr.reg = $ea_result">,
1467 NoEncode<"$ea_result">;
1469 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1470 "lfsu $rD, $addr", IIC_LdStLFDU,
1471 []>, RegConstraint<"$addr.reg = $ea_result">,
1472 NoEncode<"$ea_result">;
1474 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1475 "lfdu $rD, $addr", IIC_LdStLFDU,
1476 []>, RegConstraint<"$addr.reg = $ea_result">,
1477 NoEncode<"$ea_result">;
1480 // Indexed (r+r) Loads with Update (preinc).
1481 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1483 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1484 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1485 NoEncode<"$ea_result">;
1487 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1489 "lhaux $rD, $addr", IIC_LdStLHAUX,
1490 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1491 NoEncode<"$ea_result">;
1493 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1495 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1496 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1497 NoEncode<"$ea_result">;
1499 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1501 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1502 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1503 NoEncode<"$ea_result">;
1505 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1507 "lfsux $rD, $addr", IIC_LdStLFDUX,
1508 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1509 NoEncode<"$ea_result">;
1511 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1513 "lfdux $rD, $addr", IIC_LdStLFDUX,
1514 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1515 NoEncode<"$ea_result">;
1519 // Indexed (r+r) Loads.
1521 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1522 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1523 "lbzx $rD, $src", IIC_LdStLoad,
1524 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1525 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1526 "lhax $rD, $src", IIC_LdStLHA,
1527 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1528 PPC970_DGroup_Cracked;
1529 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1530 "lhzx $rD, $src", IIC_LdStLoad,
1531 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1532 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1533 "lwzx $rD, $src", IIC_LdStLoad,
1534 [(set i32:$rD, (load xaddr:$src))]>;
1537 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1538 "lhbrx $rD, $src", IIC_LdStLoad,
1539 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1540 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1541 "lwbrx $rD, $src", IIC_LdStLoad,
1542 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1544 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1545 "lfsx $frD, $src", IIC_LdStLFD,
1546 [(set f32:$frD, (load xaddr:$src))]>;
1547 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1548 "lfdx $frD, $src", IIC_LdStLFD,
1549 [(set f64:$frD, (load xaddr:$src))]>;
1551 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1552 "lfiwax $frD, $src", IIC_LdStLFD,
1553 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1554 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1555 "lfiwzx $frD, $src", IIC_LdStLFD,
1556 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1560 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1561 "lmw $rD, $src", IIC_LdStLMW, []>;
1563 //===----------------------------------------------------------------------===//
1564 // PPC32 Store Instructions.
1567 // Unindexed (r+i) Stores.
1568 let PPC970_Unit = 2 in {
1569 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1570 "stb $rS, $src", IIC_LdStStore,
1571 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1572 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1573 "sth $rS, $src", IIC_LdStStore,
1574 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1575 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1576 "stw $rS, $src", IIC_LdStStore,
1577 [(store i32:$rS, iaddr:$src)]>;
1578 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1579 "stfs $rS, $dst", IIC_LdStSTFD,
1580 [(store f32:$rS, iaddr:$dst)]>;
1581 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1582 "stfd $rS, $dst", IIC_LdStSTFD,
1583 [(store f64:$rS, iaddr:$dst)]>;
1586 // Unindexed (r+i) Stores with Update (preinc).
1587 let PPC970_Unit = 2, mayStore = 1 in {
1588 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1589 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1590 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1591 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1592 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1593 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1594 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1595 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1596 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1597 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1598 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1599 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1600 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1601 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1602 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1605 // Patterns to match the pre-inc stores. We can't put the patterns on
1606 // the instruction definitions directly as ISel wants the address base
1607 // and offset to be separate operands, not a single complex operand.
1608 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1609 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1610 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1611 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1612 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1613 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1614 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1615 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1616 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1617 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1619 // Indexed (r+r) Stores.
1620 let PPC970_Unit = 2 in {
1621 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1622 "stbx $rS, $dst", IIC_LdStStore,
1623 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1624 PPC970_DGroup_Cracked;
1625 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1626 "sthx $rS, $dst", IIC_LdStStore,
1627 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1628 PPC970_DGroup_Cracked;
1629 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1630 "stwx $rS, $dst", IIC_LdStStore,
1631 [(store i32:$rS, xaddr:$dst)]>,
1632 PPC970_DGroup_Cracked;
1634 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1635 "sthbrx $rS, $dst", IIC_LdStStore,
1636 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1637 PPC970_DGroup_Cracked;
1638 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1639 "stwbrx $rS, $dst", IIC_LdStStore,
1640 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1641 PPC970_DGroup_Cracked;
1643 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1644 "stfiwx $frS, $dst", IIC_LdStSTFD,
1645 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1647 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1648 "stfsx $frS, $dst", IIC_LdStSTFD,
1649 [(store f32:$frS, xaddr:$dst)]>;
1650 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1651 "stfdx $frS, $dst", IIC_LdStSTFD,
1652 [(store f64:$frS, xaddr:$dst)]>;
1655 // Indexed (r+r) Stores with Update (preinc).
1656 let PPC970_Unit = 2, mayStore = 1 in {
1657 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1658 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1659 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1660 PPC970_DGroup_Cracked;
1661 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1662 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1663 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1664 PPC970_DGroup_Cracked;
1665 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1666 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1667 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1668 PPC970_DGroup_Cracked;
1669 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1670 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1671 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1672 PPC970_DGroup_Cracked;
1673 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1674 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1675 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1676 PPC970_DGroup_Cracked;
1679 // Patterns to match the pre-inc stores. We can't put the patterns on
1680 // the instruction definitions directly as ISel wants the address base
1681 // and offset to be separate operands, not a single complex operand.
1682 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1683 (STBUX $rS, $ptrreg, $ptroff)>;
1684 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1685 (STHUX $rS, $ptrreg, $ptroff)>;
1686 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1687 (STWUX $rS, $ptrreg, $ptroff)>;
1688 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1689 (STFSUX $rS, $ptrreg, $ptroff)>;
1690 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1691 (STFDUX $rS, $ptrreg, $ptroff)>;
1694 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1695 "stmw $rS, $dst", IIC_LdStLMW, []>;
1697 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1698 "sync $L", IIC_LdStSync, []>, Requires<[IsNotBookE]>;
1700 let isCodeGenOnly = 1 in {
1701 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1702 "msync", IIC_LdStSync, []>, Requires<[IsBookE]> {
1707 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[IsNotBookE]>;
1708 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[IsBookE]>;
1710 //===----------------------------------------------------------------------===//
1711 // PPC32 Arithmetic Instructions.
1714 let PPC970_Unit = 1 in { // FXU Operations.
1715 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1716 "addi $rD, $rA, $imm", IIC_IntSimple,
1717 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1718 let BaseName = "addic" in {
1719 let Defs = [CARRY] in
1720 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1721 "addic $rD, $rA, $imm", IIC_IntGeneral,
1722 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1723 RecFormRel, PPC970_DGroup_Cracked;
1724 let Defs = [CARRY, CR0] in
1725 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1726 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1727 []>, isDOT, RecFormRel;
1729 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1730 "addis $rD, $rA, $imm", IIC_IntSimple,
1731 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1732 let isCodeGenOnly = 1 in
1733 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1734 "la $rD, $sym($rA)", IIC_IntGeneral,
1735 [(set i32:$rD, (add i32:$rA,
1736 (PPClo tglobaladdr:$sym, 0)))]>;
1737 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1738 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1739 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1740 let Defs = [CARRY] in
1741 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1742 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1743 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1745 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1746 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1747 "li $rD, $imm", IIC_IntSimple,
1748 [(set i32:$rD, imm32SExt16:$imm)]>;
1749 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1750 "lis $rD, $imm", IIC_IntSimple,
1751 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1755 let PPC970_Unit = 1 in { // FXU Operations.
1756 let Defs = [CR0] in {
1757 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1758 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1759 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1761 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1762 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1763 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1766 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1767 "ori $dst, $src1, $src2", IIC_IntSimple,
1768 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1769 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1770 "oris $dst, $src1, $src2", IIC_IntSimple,
1771 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1772 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1773 "xori $dst, $src1, $src2", IIC_IntSimple,
1774 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1775 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1776 "xoris $dst, $src1, $src2", IIC_IntSimple,
1777 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1779 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1781 let isCodeGenOnly = 1 in {
1782 // The POWER6 and POWER7 have special group-terminating nops.
1783 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1784 "ori 1, 1, 0", IIC_IntSimple, []>;
1785 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1786 "ori 2, 2, 0", IIC_IntSimple, []>;
1789 let isCompare = 1, neverHasSideEffects = 1 in {
1790 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1791 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1792 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1793 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1797 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1798 let isCommutable = 1 in {
1799 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1800 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1801 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1802 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1803 "and", "$rA, $rS, $rB", IIC_IntSimple,
1804 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1806 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1807 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1808 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1809 let isCommutable = 1 in {
1810 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1811 "or", "$rA, $rS, $rB", IIC_IntSimple,
1812 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1813 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1814 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1815 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1817 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1818 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1819 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1820 let isCommutable = 1 in {
1821 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1822 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1823 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1824 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1825 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1826 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1828 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1829 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1830 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1831 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1832 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1833 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1834 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1835 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1836 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1839 let PPC970_Unit = 1 in { // FXU Operations.
1840 let neverHasSideEffects = 1 in {
1841 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1842 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1843 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1844 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1845 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1846 [(set i32:$rA, (ctlz i32:$rS))]>;
1847 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1848 "extsb", "$rA, $rS", IIC_IntSimple,
1849 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1850 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1851 "extsh", "$rA, $rS", IIC_IntSimple,
1852 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1854 let isCompare = 1, neverHasSideEffects = 1 in {
1855 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1856 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1857 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1858 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1861 let PPC970_Unit = 3 in { // FPU Operations.
1862 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1863 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1864 let isCompare = 1, neverHasSideEffects = 1 in {
1865 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1866 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1867 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1868 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1869 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1872 let Uses = [RM] in {
1873 let neverHasSideEffects = 1 in {
1874 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1875 "fctiw", "$frD, $frB", IIC_FPGeneral,
1877 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1878 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1879 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1881 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1882 "frsp", "$frD, $frB", IIC_FPGeneral,
1883 [(set f32:$frD, (fround f64:$frB))]>;
1885 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1886 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1887 "frin", "$frD, $frB", IIC_FPGeneral,
1888 [(set f64:$frD, (frnd f64:$frB))]>;
1889 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1890 "frin", "$frD, $frB", IIC_FPGeneral,
1891 [(set f32:$frD, (frnd f32:$frB))]>;
1894 let neverHasSideEffects = 1 in {
1895 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1896 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1897 "frip", "$frD, $frB", IIC_FPGeneral,
1898 [(set f64:$frD, (fceil f64:$frB))]>;
1899 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1900 "frip", "$frD, $frB", IIC_FPGeneral,
1901 [(set f32:$frD, (fceil f32:$frB))]>;
1902 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1903 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1904 "friz", "$frD, $frB", IIC_FPGeneral,
1905 [(set f64:$frD, (ftrunc f64:$frB))]>;
1906 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1907 "friz", "$frD, $frB", IIC_FPGeneral,
1908 [(set f32:$frD, (ftrunc f32:$frB))]>;
1909 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1910 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1911 "frim", "$frD, $frB", IIC_FPGeneral,
1912 [(set f64:$frD, (ffloor f64:$frB))]>;
1913 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1914 "frim", "$frD, $frB", IIC_FPGeneral,
1915 [(set f32:$frD, (ffloor f32:$frB))]>;
1917 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1918 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1919 [(set f64:$frD, (fsqrt f64:$frB))]>;
1920 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1921 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1922 [(set f32:$frD, (fsqrt f32:$frB))]>;
1927 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1928 /// often coalesced away and we don't want the dispatch group builder to think
1929 /// that they will fill slots (which could cause the load of a LSU reject to
1930 /// sneak into a d-group with a store).
1931 let neverHasSideEffects = 1 in
1932 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1933 "fmr", "$frD, $frB", IIC_FPGeneral,
1934 []>, // (set f32:$frD, f32:$frB)
1937 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1938 // These are artificially split into two different forms, for 4/8 byte FP.
1939 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1940 "fabs", "$frD, $frB", IIC_FPGeneral,
1941 [(set f32:$frD, (fabs f32:$frB))]>;
1942 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1943 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1944 "fabs", "$frD, $frB", IIC_FPGeneral,
1945 [(set f64:$frD, (fabs f64:$frB))]>;
1946 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1947 "fnabs", "$frD, $frB", IIC_FPGeneral,
1948 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1949 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1950 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1951 "fnabs", "$frD, $frB", IIC_FPGeneral,
1952 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1953 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1954 "fneg", "$frD, $frB", IIC_FPGeneral,
1955 [(set f32:$frD, (fneg f32:$frB))]>;
1956 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1957 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1958 "fneg", "$frD, $frB", IIC_FPGeneral,
1959 [(set f64:$frD, (fneg f64:$frB))]>;
1961 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1962 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1963 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1964 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1965 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1966 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1967 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1969 // Reciprocal estimates.
1970 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1971 "fre", "$frD, $frB", IIC_FPGeneral,
1972 [(set f64:$frD, (PPCfre f64:$frB))]>;
1973 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1974 "fres", "$frD, $frB", IIC_FPGeneral,
1975 [(set f32:$frD, (PPCfre f32:$frB))]>;
1976 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1977 "frsqrte", "$frD, $frB", IIC_FPGeneral,
1978 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1979 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1980 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
1981 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1984 // XL-Form instructions. condition register logical ops.
1986 let neverHasSideEffects = 1 in
1987 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1988 "mcrf $BF, $BFA", IIC_BrMCR>,
1989 PPC970_DGroup_First, PPC970_Unit_CRU;
1991 let isCommutable = 1 in {
1992 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
1993 (ins crbitrc:$CRA, crbitrc:$CRB),
1994 "crand $CRD, $CRA, $CRB", IIC_BrCR,
1995 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
1997 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
1998 (ins crbitrc:$CRA, crbitrc:$CRB),
1999 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2000 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2002 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
2003 (ins crbitrc:$CRA, crbitrc:$CRB),
2004 "cror $CRD, $CRA, $CRB", IIC_BrCR,
2005 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2007 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
2008 (ins crbitrc:$CRA, crbitrc:$CRB),
2009 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2010 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2012 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
2013 (ins crbitrc:$CRA, crbitrc:$CRB),
2014 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2015 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2017 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
2018 (ins crbitrc:$CRA, crbitrc:$CRB),
2019 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2020 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2023 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2024 (ins crbitrc:$CRA, crbitrc:$CRB),
2025 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2026 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2028 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
2029 (ins crbitrc:$CRA, crbitrc:$CRB),
2030 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2031 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2033 let isCodeGenOnly = 1 in {
2034 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2035 "creqv $dst, $dst, $dst", IIC_BrCR,
2036 [(set i1:$dst, 1)]>;
2038 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2039 "crxor $dst, $dst, $dst", IIC_BrCR,
2040 [(set i1:$dst, 0)]>;
2042 let Defs = [CR1EQ], CRD = 6 in {
2043 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2044 "creqv 6, 6, 6", IIC_BrCR,
2047 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2048 "crxor 6, 6, 6", IIC_BrCR,
2053 // XFX-Form instructions. Instructions that deal with SPRs.
2056 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2057 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2058 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2059 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2061 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2062 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2064 let Uses = [CTR] in {
2065 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2066 "mfctr $rT", IIC_SprMFSPR>,
2067 PPC970_DGroup_First, PPC970_Unit_FXU;
2069 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2070 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2071 "mtctr $rS", IIC_SprMTSPR>,
2072 PPC970_DGroup_First, PPC970_Unit_FXU;
2074 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2075 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2076 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2077 "mtctr $rS", IIC_SprMTSPR>,
2078 PPC970_DGroup_First, PPC970_Unit_FXU;
2081 let Defs = [LR] in {
2082 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2083 "mtlr $rS", IIC_SprMTSPR>,
2084 PPC970_DGroup_First, PPC970_Unit_FXU;
2086 let Uses = [LR] in {
2087 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2088 "mflr $rT", IIC_SprMFSPR>,
2089 PPC970_DGroup_First, PPC970_Unit_FXU;
2092 let isCodeGenOnly = 1 in {
2093 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2094 // like a GPR on the PPC970. As such, copies in and out have the same
2095 // performance characteristics as an OR instruction.
2096 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2097 "mtspr 256, $rS", IIC_IntGeneral>,
2098 PPC970_DGroup_Single, PPC970_Unit_FXU;
2099 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2100 "mfspr $rT, 256", IIC_IntGeneral>,
2101 PPC970_DGroup_First, PPC970_Unit_FXU;
2103 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2104 (outs VRSAVERC:$reg), (ins gprc:$rS),
2105 "mtspr 256, $rS", IIC_IntGeneral>,
2106 PPC970_DGroup_Single, PPC970_Unit_FXU;
2107 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2108 (ins VRSAVERC:$reg),
2109 "mfspr $rT, 256", IIC_IntGeneral>,
2110 PPC970_DGroup_First, PPC970_Unit_FXU;
2113 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2114 // so we'll need to scavenge a register for it.
2116 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2117 "#SPILL_VRSAVE", []>;
2119 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2120 // spilled), so we'll need to scavenge a register for it.
2122 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2123 "#RESTORE_VRSAVE", []>;
2125 let neverHasSideEffects = 1 in {
2126 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2127 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2128 PPC970_DGroup_First, PPC970_Unit_CRU;
2130 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2131 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2132 PPC970_MicroCode, PPC970_Unit_CRU;
2134 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2135 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2136 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2137 PPC970_DGroup_First, PPC970_Unit_CRU;
2139 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2140 "mfcr $rT", IIC_SprMFCR>,
2141 PPC970_MicroCode, PPC970_Unit_CRU;
2142 } // neverHasSideEffects = 1
2144 // Pseudo instruction to perform FADD in round-to-zero mode.
2145 let usesCustomInserter = 1, Uses = [RM] in {
2146 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2147 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2150 // The above pseudo gets expanded to make use of the following instructions
2151 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2152 let Uses = [RM], Defs = [RM] in {
2153 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2154 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2155 PPC970_DGroup_Single, PPC970_Unit_FPU;
2156 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2157 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2158 PPC970_DGroup_Single, PPC970_Unit_FPU;
2159 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2160 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2161 PPC970_DGroup_Single, PPC970_Unit_FPU;
2163 let Uses = [RM] in {
2164 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2165 "mffs $rT", IIC_IntMFFS,
2166 [(set f64:$rT, (PPCmffs))]>,
2167 PPC970_DGroup_Single, PPC970_Unit_FPU;
2171 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
2172 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2173 let isCommutable = 1 in
2174 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2175 "add", "$rT, $rA, $rB", IIC_IntSimple,
2176 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2177 let isCodeGenOnly = 1 in
2178 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2179 "add $rT, $rA, $rB", IIC_IntSimple,
2180 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2181 let isCommutable = 1 in
2182 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2183 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2184 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2185 PPC970_DGroup_Cracked;
2187 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2188 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2189 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2190 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2191 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2192 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2193 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2194 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2195 let isCommutable = 1 in {
2196 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2197 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2198 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2199 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2200 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2201 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2202 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2203 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2204 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2206 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2207 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2208 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2209 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2210 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2211 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2212 PPC970_DGroup_Cracked;
2213 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2214 "neg", "$rT, $rA", IIC_IntSimple,
2215 [(set i32:$rT, (ineg i32:$rA))]>;
2216 let Uses = [CARRY] in {
2217 let isCommutable = 1 in
2218 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2219 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2220 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2221 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2222 "addme", "$rT, $rA", IIC_IntGeneral,
2223 [(set i32:$rT, (adde i32:$rA, -1))]>;
2224 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2225 "addze", "$rT, $rA", IIC_IntGeneral,
2226 [(set i32:$rT, (adde i32:$rA, 0))]>;
2227 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2228 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2229 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2230 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2231 "subfme", "$rT, $rA", IIC_IntGeneral,
2232 [(set i32:$rT, (sube -1, i32:$rA))]>;
2233 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2234 "subfze", "$rT, $rA", IIC_IntGeneral,
2235 [(set i32:$rT, (sube 0, i32:$rA))]>;
2239 // A-Form instructions. Most of the instructions executed in the FPU are of
2242 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
2243 let Uses = [RM] in {
2244 let isCommutable = 1 in {
2245 defm FMADD : AForm_1r<63, 29,
2246 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2247 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2248 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2249 defm FMADDS : AForm_1r<59, 29,
2250 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2251 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2252 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2253 defm FMSUB : AForm_1r<63, 28,
2254 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2255 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2257 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2258 defm FMSUBS : AForm_1r<59, 28,
2259 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2260 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2262 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2263 defm FNMADD : AForm_1r<63, 31,
2264 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2265 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2267 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2268 defm FNMADDS : AForm_1r<59, 31,
2269 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2270 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2272 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2273 defm FNMSUB : AForm_1r<63, 30,
2274 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2275 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2276 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2277 (fneg f64:$FRB))))]>;
2278 defm FNMSUBS : AForm_1r<59, 30,
2279 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2280 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2281 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2282 (fneg f32:$FRB))))]>;
2285 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2286 // having 4 of these, force the comparison to always be an 8-byte double (code
2287 // should use an FMRSD if the input comparison value really wants to be a float)
2288 // and 4/8 byte forms for the result and operand type..
2289 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2290 defm FSELD : AForm_1r<63, 23,
2291 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2292 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2293 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2294 defm FSELS : AForm_1r<63, 23,
2295 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2296 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2297 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2298 let Uses = [RM] in {
2299 let isCommutable = 1 in {
2300 defm FADD : AForm_2r<63, 21,
2301 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2302 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2303 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2304 defm FADDS : AForm_2r<59, 21,
2305 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2306 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2307 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2309 defm FDIV : AForm_2r<63, 18,
2310 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2311 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2312 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2313 defm FDIVS : AForm_2r<59, 18,
2314 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2315 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2316 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2317 let isCommutable = 1 in {
2318 defm FMUL : AForm_3r<63, 25,
2319 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2320 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2321 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2322 defm FMULS : AForm_3r<59, 25,
2323 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2324 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2325 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2327 defm FSUB : AForm_2r<63, 20,
2328 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2329 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2330 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2331 defm FSUBS : AForm_2r<59, 20,
2332 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2333 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2334 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2338 let neverHasSideEffects = 1 in {
2339 let PPC970_Unit = 1 in { // FXU Operations.
2341 def ISEL : AForm_4<31, 15,
2342 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2343 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
2347 let PPC970_Unit = 1 in { // FXU Operations.
2348 // M-Form instructions. rotate and mask instructions.
2350 let isCommutable = 1 in {
2351 // RLWIMI can be commuted if the rotate amount is zero.
2352 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2353 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2354 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2355 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2356 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2358 let BaseName = "rlwinm" in {
2359 def RLWINM : MForm_2<21,
2360 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2361 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2364 def RLWINMo : MForm_2<21,
2365 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2366 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2367 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2369 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2370 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2371 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2374 } // neverHasSideEffects = 1
2376 //===----------------------------------------------------------------------===//
2377 // PowerPC Instruction Patterns
2380 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2381 def : Pat<(i32 imm:$imm),
2382 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2384 // Implement the 'not' operation with the NOR instruction.
2385 def i32not : OutPatFrag<(ops node:$in),
2387 def : Pat<(not i32:$in),
2390 // ADD an arbitrary immediate.
2391 def : Pat<(add i32:$in, imm:$imm),
2392 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2393 // OR an arbitrary immediate.
2394 def : Pat<(or i32:$in, imm:$imm),
2395 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2396 // XOR an arbitrary immediate.
2397 def : Pat<(xor i32:$in, imm:$imm),
2398 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2400 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2401 (SUBFIC $in, imm:$imm)>;
2404 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2405 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2406 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2407 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2410 def : Pat<(rotl i32:$in, i32:$sh),
2411 (RLWNM $in, $sh, 0, 31)>;
2412 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2413 (RLWINM $in, imm:$imm, 0, 31)>;
2416 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2417 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2420 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2421 (BL tglobaladdr:$dst)>;
2422 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2423 (BL texternalsym:$dst)>;
2426 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2427 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2429 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2430 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2432 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2433 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2437 // Hi and Lo for Darwin Global Addresses.
2438 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2439 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2440 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2441 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2442 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2443 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2444 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2445 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2446 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2447 (ADDIS $in, tglobaltlsaddr:$g)>;
2448 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2449 (ADDI $in, tglobaltlsaddr:$g)>;
2450 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2451 (ADDIS $in, tglobaladdr:$g)>;
2452 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2453 (ADDIS $in, tconstpool:$g)>;
2454 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2455 (ADDIS $in, tjumptable:$g)>;
2456 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2457 (ADDIS $in, tblockaddress:$g)>;
2459 // Support for thread-local storage.
2460 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2461 [(set i32:$rD, (PPCppc32GOT))]>;
2463 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2464 // This uses two output registers, the first as the real output, the second as a
2465 // temporary register, used internally in code generation.
2466 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2467 []>, NoEncode<"$rT">;
2469 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2472 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2473 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2474 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2476 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2479 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2480 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2483 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2484 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2487 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2488 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2491 (PPCgetTlsldAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2492 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2495 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2496 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2499 (PPCaddisDtprelHA i32:$reg,
2500 tglobaltlsaddr:$disp))]>;
2502 // Support for Position-independent code
2503 def LWZtoc: Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2506 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2507 // Get Global (GOT) Base Register offset, from the word immediately preceding
2508 // the function label.
2509 def GetGBRO: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#GetGBRO", []>;
2510 // Update the Global(GOT) Base Register with the above offset.
2511 def UpdateGBR: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2514 // Standard shifts. These are represented separately from the real shifts above
2515 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2517 def : Pat<(sra i32:$rS, i32:$rB),
2519 def : Pat<(srl i32:$rS, i32:$rB),
2521 def : Pat<(shl i32:$rS, i32:$rB),
2524 def : Pat<(zextloadi1 iaddr:$src),
2526 def : Pat<(zextloadi1 xaddr:$src),
2528 def : Pat<(extloadi1 iaddr:$src),
2530 def : Pat<(extloadi1 xaddr:$src),
2532 def : Pat<(extloadi8 iaddr:$src),
2534 def : Pat<(extloadi8 xaddr:$src),
2536 def : Pat<(extloadi16 iaddr:$src),
2538 def : Pat<(extloadi16 xaddr:$src),
2540 def : Pat<(f64 (extloadf32 iaddr:$src)),
2541 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2542 def : Pat<(f64 (extloadf32 xaddr:$src)),
2543 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2545 def : Pat<(f64 (fextend f32:$src)),
2546 (COPY_TO_REGCLASS $src, F8RC)>;
2548 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[IsNotBookE]>;
2549 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[IsBookE]>;
2551 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2552 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2553 (FNMSUB $A, $C, $B)>;
2554 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2555 (FNMSUB $A, $C, $B)>;
2556 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2557 (FNMSUBS $A, $C, $B)>;
2558 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2559 (FNMSUBS $A, $C, $B)>;
2561 // FCOPYSIGN's operand types need not agree.
2562 def : Pat<(fcopysign f64:$frB, f32:$frA),
2563 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2564 def : Pat<(fcopysign f32:$frB, f64:$frA),
2565 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2567 include "PPCInstrAltivec.td"
2568 include "PPCInstrSPE.td"
2569 include "PPCInstr64Bit.td"
2570 include "PPCInstrVSX.td"
2572 def crnot : OutPatFrag<(ops node:$in),
2574 def : Pat<(not i1:$in),
2577 // Patterns for arithmetic i1 operations.
2578 def : Pat<(add i1:$a, i1:$b),
2580 def : Pat<(sub i1:$a, i1:$b),
2582 def : Pat<(mul i1:$a, i1:$b),
2585 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2586 // (-1 is used to mean all bits set).
2587 def : Pat<(i1 -1), (CRSET)>;
2589 // i1 extensions, implemented in terms of isel.
2590 def : Pat<(i32 (zext i1:$in)),
2591 (SELECT_I4 $in, (LI 1), (LI 0))>;
2592 def : Pat<(i32 (sext i1:$in)),
2593 (SELECT_I4 $in, (LI -1), (LI 0))>;
2595 def : Pat<(i64 (zext i1:$in)),
2596 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2597 def : Pat<(i64 (sext i1:$in)),
2598 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2600 // FIXME: We should choose either a zext or a sext based on other constants
2602 def : Pat<(i32 (anyext i1:$in)),
2603 (SELECT_I4 $in, (LI 1), (LI 0))>;
2604 def : Pat<(i64 (anyext i1:$in)),
2605 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2607 // match setcc on i1 variables.
2608 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2610 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2612 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2614 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2616 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2618 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2620 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2622 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2624 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2626 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2629 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2630 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2631 // floating-point types.
2633 multiclass CRNotPat<dag pattern, dag result> {
2634 def : Pat<pattern, (crnot result)>;
2635 def : Pat<(not pattern), result>;
2637 // We can also fold the crnot into an extension:
2638 def : Pat<(i32 (zext pattern)),
2639 (SELECT_I4 result, (LI 0), (LI 1))>;
2640 def : Pat<(i32 (sext pattern)),
2641 (SELECT_I4 result, (LI 0), (LI -1))>;
2643 // We can also fold the crnot into an extension:
2644 def : Pat<(i64 (zext pattern)),
2645 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2646 def : Pat<(i64 (sext pattern)),
2647 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2649 // FIXME: We should choose either a zext or a sext based on other constants
2651 def : Pat<(i32 (anyext pattern)),
2652 (SELECT_I4 result, (LI 0), (LI 1))>;
2654 def : Pat<(i64 (anyext pattern)),
2655 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2658 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2659 // we need to write imm:$imm in the output patterns below, not just $imm, or
2660 // else the resulting matcher will not correctly add the immediate operand
2661 // (making it a register operand instead).
2664 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2665 OutPatFrag rfrag, OutPatFrag rfrag8> {
2666 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2668 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2670 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2671 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2672 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2673 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2675 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2677 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2679 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2680 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2681 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2682 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2685 // Note that we do all inversions below with i(32|64)not, instead of using
2686 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2687 // has 2-cycle latency.
2689 defm : ExtSetCCPat<SETEQ,
2690 PatFrag<(ops node:$in, node:$cc),
2691 (setcc $in, 0, $cc)>,
2692 OutPatFrag<(ops node:$in),
2693 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2694 OutPatFrag<(ops node:$in),
2695 (RLDICL (CNTLZD $in), 58, 63)> >;
2697 defm : ExtSetCCPat<SETNE,
2698 PatFrag<(ops node:$in, node:$cc),
2699 (setcc $in, 0, $cc)>,
2700 OutPatFrag<(ops node:$in),
2701 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2702 OutPatFrag<(ops node:$in),
2703 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2705 defm : ExtSetCCPat<SETLT,
2706 PatFrag<(ops node:$in, node:$cc),
2707 (setcc $in, 0, $cc)>,
2708 OutPatFrag<(ops node:$in),
2709 (RLWINM $in, 1, 31, 31)>,
2710 OutPatFrag<(ops node:$in),
2711 (RLDICL $in, 1, 63)> >;
2713 defm : ExtSetCCPat<SETGE,
2714 PatFrag<(ops node:$in, node:$cc),
2715 (setcc $in, 0, $cc)>,
2716 OutPatFrag<(ops node:$in),
2717 (RLWINM (i32not $in), 1, 31, 31)>,
2718 OutPatFrag<(ops node:$in),
2719 (RLDICL (i64not $in), 1, 63)> >;
2721 defm : ExtSetCCPat<SETGT,
2722 PatFrag<(ops node:$in, node:$cc),
2723 (setcc $in, 0, $cc)>,
2724 OutPatFrag<(ops node:$in),
2725 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2726 OutPatFrag<(ops node:$in),
2727 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2729 defm : ExtSetCCPat<SETLE,
2730 PatFrag<(ops node:$in, node:$cc),
2731 (setcc $in, 0, $cc)>,
2732 OutPatFrag<(ops node:$in),
2733 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2734 OutPatFrag<(ops node:$in),
2735 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2737 defm : ExtSetCCPat<SETLT,
2738 PatFrag<(ops node:$in, node:$cc),
2739 (setcc $in, -1, $cc)>,
2740 OutPatFrag<(ops node:$in),
2741 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2742 OutPatFrag<(ops node:$in),
2743 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2745 defm : ExtSetCCPat<SETGE,
2746 PatFrag<(ops node:$in, node:$cc),
2747 (setcc $in, -1, $cc)>,
2748 OutPatFrag<(ops node:$in),
2749 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2750 OutPatFrag<(ops node:$in),
2751 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2753 defm : ExtSetCCPat<SETGT,
2754 PatFrag<(ops node:$in, node:$cc),
2755 (setcc $in, -1, $cc)>,
2756 OutPatFrag<(ops node:$in),
2757 (RLWINM (i32not $in), 1, 31, 31)>,
2758 OutPatFrag<(ops node:$in),
2759 (RLDICL (i64not $in), 1, 63)> >;
2761 defm : ExtSetCCPat<SETLE,
2762 PatFrag<(ops node:$in, node:$cc),
2763 (setcc $in, -1, $cc)>,
2764 OutPatFrag<(ops node:$in),
2765 (RLWINM $in, 1, 31, 31)>,
2766 OutPatFrag<(ops node:$in),
2767 (RLDICL $in, 1, 63)> >;
2770 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2771 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2772 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2773 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2774 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2775 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2776 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2777 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2778 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2779 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2780 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2781 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2783 // For non-equality comparisons, the default code would materialize the
2784 // constant, then compare against it, like this:
2786 // ori r2, r2, 22136
2789 // Since we are just comparing for equality, we can emit this instead:
2790 // xoris r0,r3,0x1234
2791 // cmplwi cr0,r0,0x5678
2794 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2795 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2796 (LO16 imm:$imm)), sub_eq)>;
2798 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2799 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2800 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2801 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2802 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2803 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2804 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2805 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2806 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2807 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2808 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2809 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2811 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2812 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2813 (LO16 imm:$imm)), sub_eq)>;
2815 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
2816 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2817 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2818 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2819 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2820 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2821 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
2822 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2823 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2824 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2826 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2827 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2828 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
2829 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2830 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2831 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2832 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
2833 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2834 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2835 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2838 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
2839 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2840 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2841 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2842 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2843 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2844 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
2845 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2846 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
2847 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2848 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
2849 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2851 // For non-equality comparisons, the default code would materialize the
2852 // constant, then compare against it, like this:
2854 // ori r2, r2, 22136
2857 // Since we are just comparing for equality, we can emit this instead:
2858 // xoris r0,r3,0x1234
2859 // cmpldi cr0,r0,0x5678
2862 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
2863 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2864 (LO16 imm:$imm)), sub_eq)>;
2866 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
2867 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2868 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
2869 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2870 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
2871 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2872 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
2873 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2874 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
2875 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2876 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
2877 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2879 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
2880 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2881 (LO16 imm:$imm)), sub_eq)>;
2883 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
2884 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2885 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
2886 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2887 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
2888 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2889 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
2890 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2891 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
2892 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2894 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
2895 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2896 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
2897 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2898 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
2899 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2900 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
2901 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2902 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
2903 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2906 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
2907 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2908 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
2909 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2910 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
2911 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2912 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
2913 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2914 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
2915 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2916 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
2917 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2918 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
2919 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2921 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
2922 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2923 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
2924 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2925 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
2926 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2927 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
2928 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2929 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
2930 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2931 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
2932 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2933 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
2934 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2937 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
2938 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2939 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
2940 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2941 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
2942 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2943 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
2944 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2945 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
2946 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2947 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
2948 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2949 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
2950 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2952 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
2953 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2954 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
2955 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2956 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
2957 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2958 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
2959 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2960 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
2961 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2962 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
2963 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2964 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
2965 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2967 // match select on i1 variables:
2968 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
2969 (CROR (CRAND $cond , $tval),
2970 (CRAND (crnot $cond), $fval))>;
2972 // match selectcc on i1 variables:
2973 // select (lhs == rhs), tval, fval is:
2974 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
2975 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
2976 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
2977 (CRAND (CRORC $lhs, $rhs), $fval))>;
2978 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
2979 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
2980 (CRAND (CRANDC $lhs, $rhs), $fval))>;
2981 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
2982 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
2983 (CRAND (CRXOR $lhs, $rhs), $fval))>;
2984 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
2985 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
2986 (CRAND (CRANDC $rhs, $lhs), $fval))>;
2987 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
2988 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
2989 (CRAND (CRORC $rhs, $lhs), $fval))>;
2990 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
2991 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
2992 (CRAND (CRXOR $lhs, $rhs), $tval))>;
2994 // match selectcc on i1 variables with non-i1 output.
2995 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
2996 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
2997 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
2998 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
2999 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3000 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3001 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3002 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3003 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3004 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3005 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3006 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3008 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3009 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3010 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3011 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3012 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3013 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3014 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3015 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3016 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3017 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3018 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3019 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3021 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3022 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3023 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3024 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3025 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3026 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3027 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3028 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3029 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3030 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3031 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3032 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3034 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3035 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3036 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3037 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3038 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3039 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3040 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3041 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3042 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3043 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3044 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3045 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3047 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3048 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3049 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3050 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3051 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3052 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3053 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3054 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3055 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3056 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3057 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3058 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3060 let usesCustomInserter = 1 in {
3061 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3063 [(set i1:$dst, (trunc (not i32:$in)))]>;
3064 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3066 [(set i1:$dst, (trunc i32:$in))]>;
3068 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3070 [(set i1:$dst, (trunc (not i64:$in)))]>;
3071 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3073 [(set i1:$dst, (trunc i64:$in))]>;
3076 def : Pat<(i1 (not (trunc i32:$in))),
3077 (ANDIo_1_EQ_BIT $in)>;
3078 def : Pat<(i1 (not (trunc i64:$in))),
3079 (ANDIo_1_EQ_BIT8 $in)>;
3081 //===----------------------------------------------------------------------===//
3082 // PowerPC Instructions used for assembler/disassembler only
3085 // FIXME: For B=0 or B > 8, the registers following RT are used.
3086 // WARNING: Do not add patterns for this instruction without fixing this.
3087 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3088 "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3090 // FIXME: For B=0 or B > 8, the registers following RT are used.
3091 // WARNING: Do not add patterns for this instruction without fixing this.
3092 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3093 "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3095 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3096 "isync", IIC_SprISYNC, []>;
3098 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3099 "icbi $src", IIC_LdStICBI, []>;
3101 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3102 "eieio", IIC_LdStLoad, []>;
3104 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3105 "wait $L", IIC_LdStLoad, []>;
3107 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3108 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3110 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3111 "mtsr $SR, $RS", IIC_SprMTSR>;
3113 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3114 "mfsr $RS, $SR", IIC_SprMFSR>;
3116 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3117 "mtsrin $RS, $RB", IIC_SprMTSR>;
3119 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3120 "mfsrin $RS, $RB", IIC_SprMFSR>;
3122 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3123 "mtmsr $RS, $L", IIC_SprMTMSR>;
3125 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3126 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3130 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3131 Requires<[IsBookE]> {
3135 let Inst{21-30} = 163;
3138 def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3139 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3140 def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3141 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3143 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3144 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3145 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3146 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3148 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3149 "mfmsr $RT", IIC_SprMFMSR, []>;
3151 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3152 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3154 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3155 "slbie $RB", IIC_SprSLBIE, []>;
3157 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3158 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3160 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3161 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3163 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3165 def TLBIA : XForm_0<31, 370, (outs), (ins),
3166 "tlbia", IIC_SprTLBIA, []>;
3168 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3169 "tlbsync", IIC_SprTLBSYNC, []>;
3171 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3172 "tlbiel $RB", IIC_SprTLBIEL, []>;
3174 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3175 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3176 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3177 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3179 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3180 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3182 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3183 IIC_LdStLoad>, Requires<[IsBookE]>;
3185 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3186 IIC_LdStLoad>, Requires<[IsBookE]>;
3188 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3189 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3191 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3192 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3194 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3195 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3197 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3198 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3200 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3201 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3202 Requires<[IsPPC4xx]>;
3203 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3204 (ins gprc:$RST, gprc:$A, gprc:$B),
3205 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3206 Requires<[IsPPC4xx]>, isDOT;
3208 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3210 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3211 Requires<[IsBookE]>;
3212 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3213 Requires<[IsBookE]>;
3215 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3217 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3220 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3221 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3222 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3223 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3225 //===----------------------------------------------------------------------===//
3226 // PowerPC Assembler Instruction Aliases
3229 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3230 // These are aliases that require C++ handling to convert to the target
3231 // instruction, while InstAliases can be handled directly by tblgen.
3232 class PPCAsmPseudo<string asm, dag iops>
3234 let Namespace = "PPC";
3235 bit PPC64 = 0; // Default value, override with isPPC64
3237 let OutOperandList = (outs);
3238 let InOperandList = iops;
3240 let AsmString = asm;
3241 let isAsmParserOnly = 1;
3245 def : InstAlias<"sc", (SC 0)>;
3247 def : InstAlias<"sync", (SYNC 0)>, Requires<[IsNotBookE]>;
3248 def : InstAlias<"msync", (SYNC 0)>, Requires<[IsNotBookE]>;
3249 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[IsNotBookE]>;
3250 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[IsNotBookE]>;
3252 def : InstAlias<"wait", (WAIT 0)>;
3253 def : InstAlias<"waitrsv", (WAIT 1)>;
3254 def : InstAlias<"waitimpl", (WAIT 2)>;
3256 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3258 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3259 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3260 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3261 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3263 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3264 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3266 def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3267 def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3269 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3270 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3272 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3273 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3275 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3276 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3278 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3279 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3281 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3282 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3284 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3285 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3287 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3288 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3290 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3291 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3293 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3294 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3296 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3297 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3299 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3300 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3302 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3303 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3305 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3306 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3307 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3309 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3310 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3312 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3313 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3314 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3315 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3317 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3319 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3320 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3322 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3323 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3325 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3327 foreach BATR = 0-3 in {
3328 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3329 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3330 Requires<[IsPPC6xx]>;
3331 def : InstAlias<"mfdbatu $Rx, "#BATR,
3332 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3333 Requires<[IsPPC6xx]>;
3334 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3335 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3336 Requires<[IsPPC6xx]>;
3337 def : InstAlias<"mfdbatl $Rx, "#BATR,
3338 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3339 Requires<[IsPPC6xx]>;
3340 def : InstAlias<"mtibatu "#BATR#", $Rx",
3341 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3342 Requires<[IsPPC6xx]>;
3343 def : InstAlias<"mfibatu $Rx, "#BATR,
3344 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3345 Requires<[IsPPC6xx]>;
3346 def : InstAlias<"mtibatl "#BATR#", $Rx",
3347 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3348 Requires<[IsPPC6xx]>;
3349 def : InstAlias<"mfibatl $Rx, "#BATR,
3350 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3351 Requires<[IsPPC6xx]>;
3354 foreach BR = 0-7 in {
3355 def : InstAlias<"mfbr"#BR#" $Rx",
3356 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3357 Requires<[IsPPC4xx]>;
3358 def : InstAlias<"mtbr"#BR#" $Rx",
3359 (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3360 Requires<[IsPPC4xx]>;
3363 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3364 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3366 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3367 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3369 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3370 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3372 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3373 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3375 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3376 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3378 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3379 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3381 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3383 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3384 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3385 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3386 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3387 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3388 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3389 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3390 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3392 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3393 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3394 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3395 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3397 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3398 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3400 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3401 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3403 foreach SPRG = 0-3 in {
3404 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3405 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3406 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3407 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3409 foreach SPRG = 4-7 in {
3410 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3411 Requires<[IsBookE]>;
3412 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3413 Requires<[IsBookE]>;
3414 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3415 Requires<[IsBookE]>;
3416 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3417 Requires<[IsBookE]>;
3420 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3422 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3423 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3425 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3427 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3428 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3430 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3431 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3432 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3433 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3435 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3437 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3438 Requires<[IsPPC4xx]>;
3439 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3440 Requires<[IsPPC4xx]>;
3441 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3442 Requires<[IsPPC4xx]>;
3443 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3444 Requires<[IsPPC4xx]>;
3446 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3447 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3448 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3449 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3450 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3451 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3452 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3453 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3454 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3455 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3456 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3457 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3458 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3459 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3460 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3461 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3462 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3463 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3464 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3465 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3466 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3467 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3468 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3469 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3470 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3471 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3472 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3473 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3474 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3475 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3476 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3477 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3478 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3479 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3480 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3481 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3483 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3484 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3485 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3486 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3487 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3488 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3490 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3491 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3492 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3493 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3494 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3495 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3496 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3497 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3498 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3499 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3500 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3501 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3502 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3503 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3504 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3505 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3506 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3507 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3508 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3509 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3510 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3511 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3512 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3513 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3514 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3515 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3516 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3517 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3518 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3519 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3520 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3521 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3523 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3524 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3525 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3526 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3527 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3528 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3530 // These generic branch instruction forms are used for the assembler parser only.
3531 // Defs and Uses are conservative, since we don't know the BO value.
3532 let PPC970_Unit = 7 in {
3533 let Defs = [CTR], Uses = [CTR, RM] in {
3534 def gBC : BForm_3<16, 0, 0, (outs),
3535 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3536 "bc $bo, $bi, $dst">;
3537 def gBCA : BForm_3<16, 1, 0, (outs),
3538 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3539 "bca $bo, $bi, $dst">;
3541 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3542 def gBCL : BForm_3<16, 0, 1, (outs),
3543 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3544 "bcl $bo, $bi, $dst">;
3545 def gBCLA : BForm_3<16, 1, 1, (outs),
3546 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3547 "bcla $bo, $bi, $dst">;
3549 let Defs = [CTR], Uses = [CTR, LR, RM] in
3550 def gBCLR : XLForm_2<19, 16, 0, (outs),
3551 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3552 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3553 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3554 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3555 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3556 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3557 let Defs = [CTR], Uses = [CTR, LR, RM] in
3558 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3559 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3560 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3561 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3562 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3563 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3564 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3566 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3567 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3568 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3569 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3571 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3572 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3573 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3574 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3575 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3576 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3577 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3579 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3580 : BranchSimpleMnemonic1<name, pm, bo> {
3581 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3582 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3584 defm : BranchSimpleMnemonic2<"t", "", 12>;
3585 defm : BranchSimpleMnemonic2<"f", "", 4>;
3586 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3587 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3588 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3589 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3590 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3591 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3592 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3593 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3595 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3596 def : InstAlias<"b"#name#pm#" $cc, $dst",
3597 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3598 def : InstAlias<"b"#name#pm#" $dst",
3599 (BCC bibo, CR0, condbrtarget:$dst)>;
3601 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3602 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3603 def : InstAlias<"b"#name#"a"#pm#" $dst",
3604 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3606 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3607 (BCCLR bibo, crrc:$cc)>;
3608 def : InstAlias<"b"#name#"lr"#pm,
3611 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3612 (BCCCTR bibo, crrc:$cc)>;
3613 def : InstAlias<"b"#name#"ctr"#pm,
3614 (BCCCTR bibo, CR0)>;
3616 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3617 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3618 def : InstAlias<"b"#name#"l"#pm#" $dst",
3619 (BCCL bibo, CR0, condbrtarget:$dst)>;
3621 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3622 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3623 def : InstAlias<"b"#name#"la"#pm#" $dst",
3624 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3626 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3627 (BCCLRL bibo, crrc:$cc)>;
3628 def : InstAlias<"b"#name#"lrl"#pm,
3629 (BCCLRL bibo, CR0)>;
3631 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3632 (BCCCTRL bibo, crrc:$cc)>;
3633 def : InstAlias<"b"#name#"ctrl"#pm,
3634 (BCCCTRL bibo, CR0)>;
3636 multiclass BranchExtendedMnemonic<string name, int bibo> {
3637 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3638 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3639 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3641 defm : BranchExtendedMnemonic<"lt", 12>;
3642 defm : BranchExtendedMnemonic<"gt", 44>;
3643 defm : BranchExtendedMnemonic<"eq", 76>;
3644 defm : BranchExtendedMnemonic<"un", 108>;
3645 defm : BranchExtendedMnemonic<"so", 108>;
3646 defm : BranchExtendedMnemonic<"ge", 4>;
3647 defm : BranchExtendedMnemonic<"nl", 4>;
3648 defm : BranchExtendedMnemonic<"le", 36>;
3649 defm : BranchExtendedMnemonic<"ng", 36>;
3650 defm : BranchExtendedMnemonic<"ne", 68>;
3651 defm : BranchExtendedMnemonic<"nu", 100>;
3652 defm : BranchExtendedMnemonic<"ns", 100>;
3654 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3655 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3656 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3657 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3658 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3659 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3660 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3661 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3663 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3664 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3665 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3666 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3667 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3668 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3669 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3670 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3672 multiclass TrapExtendedMnemonic<string name, int to> {
3673 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3674 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3675 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3676 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3678 defm : TrapExtendedMnemonic<"lt", 16>;
3679 defm : TrapExtendedMnemonic<"le", 20>;
3680 defm : TrapExtendedMnemonic<"eq", 4>;
3681 defm : TrapExtendedMnemonic<"ge", 12>;
3682 defm : TrapExtendedMnemonic<"gt", 8>;
3683 defm : TrapExtendedMnemonic<"nl", 12>;
3684 defm : TrapExtendedMnemonic<"ne", 24>;
3685 defm : TrapExtendedMnemonic<"ng", 20>;
3686 defm : TrapExtendedMnemonic<"llt", 2>;
3687 defm : TrapExtendedMnemonic<"lle", 6>;
3688 defm : TrapExtendedMnemonic<"lge", 5>;
3689 defm : TrapExtendedMnemonic<"lgt", 1>;
3690 defm : TrapExtendedMnemonic<"lnl", 5>;
3691 defm : TrapExtendedMnemonic<"lng", 6>;
3692 defm : TrapExtendedMnemonic<"u", 31>;