1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
27 def SDT_PPCRetFlag : SDTypeProfile<0, 0, []>;
29 def SDT_PPCvperm : SDTypeProfile<1, 3, [
30 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
33 //===----------------------------------------------------------------------===//
34 // PowerPC specific DAG Nodes.
37 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
38 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
39 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
40 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
42 def PPCfsel : SDNode<"PPCISD::FSEL",
43 // Type constraint for fsel.
44 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
45 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
47 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
48 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
49 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
50 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
52 def PPClve_x : SDNode<"PPCISD::LVE_X", SDTLoad, [SDNPHasChain]>;
53 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
55 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
56 // amounts. These nodes are generated by the multi-precision shift code.
57 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
58 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
59 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
61 // These are target-independent nodes, but have target-specific formats.
62 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
63 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
65 def retflag : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag,
66 [SDNPHasChain, SDNPOptInFlag]>;
68 //===----------------------------------------------------------------------===//
69 // PowerPC specific transformation functions and pattern fragments.
72 def SHL32 : SDNodeXForm<imm, [{
73 // Transformation function: 31 - imm
74 return getI32Imm(31 - N->getValue());
77 def SHL64 : SDNodeXForm<imm, [{
78 // Transformation function: 63 - imm
79 return getI32Imm(63 - N->getValue());
82 def SRL32 : SDNodeXForm<imm, [{
83 // Transformation function: 32 - imm
84 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
87 def SRL64 : SDNodeXForm<imm, [{
88 // Transformation function: 64 - imm
89 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
92 def LO16 : SDNodeXForm<imm, [{
93 // Transformation function: get the low 16 bits.
94 return getI32Imm((unsigned short)N->getValue());
97 def HI16 : SDNodeXForm<imm, [{
98 // Transformation function: shift the immediate value down into the low bits.
99 return getI32Imm((unsigned)N->getValue() >> 16);
102 def HA16 : SDNodeXForm<imm, [{
103 // Transformation function: shift the immediate value down into the low bits.
104 signed int Val = N->getValue();
105 return getI32Imm((Val - (signed short)Val) >> 16);
109 def immSExt16 : PatLeaf<(imm), [{
110 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
111 // field. Used by instructions like 'addi'.
112 return (int)N->getValue() == (short)N->getValue();
114 def immZExt16 : PatLeaf<(imm), [{
115 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
116 // field. Used by instructions like 'ori'.
117 return (unsigned)N->getValue() == (unsigned short)N->getValue();
120 def imm16Shifted : PatLeaf<(imm), [{
121 // imm16Shifted predicate - True if only bits in the top 16-bits of the
122 // immediate are set. Used by instructions like 'addis'.
123 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
126 // VSPLT_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
127 def VSPLT_get_imm : SDNodeXForm<build_vector, [{
128 return getI32Imm(PPC::getVSPLTImmediate(N));
131 def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{
132 return PPC::isSplatShuffleMask(N);
135 //===----------------------------------------------------------------------===//
136 // PowerPC Flag Definitions.
138 class isPPC64 { bit PPC64 = 1; }
139 class isVMX { bit VMX = 1; }
141 list<Register> Defs = [CR0];
147 //===----------------------------------------------------------------------===//
148 // PowerPC Operand Definitions.
150 def u5imm : Operand<i32> {
151 let PrintMethod = "printU5ImmOperand";
153 def u6imm : Operand<i32> {
154 let PrintMethod = "printU6ImmOperand";
156 def s16imm : Operand<i32> {
157 let PrintMethod = "printS16ImmOperand";
159 def u16imm : Operand<i32> {
160 let PrintMethod = "printU16ImmOperand";
162 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
163 let PrintMethod = "printS16X4ImmOperand";
165 def target : Operand<OtherVT> {
166 let PrintMethod = "printBranchOperand";
168 def calltarget : Operand<i32> {
169 let PrintMethod = "printCallOperand";
171 def aaddr : Operand<i32> {
172 let PrintMethod = "printAbsAddrOperand";
174 def piclabel: Operand<i32> {
175 let PrintMethod = "printPICLabel";
177 def symbolHi: Operand<i32> {
178 let PrintMethod = "printSymbolHi";
180 def symbolLo: Operand<i32> {
181 let PrintMethod = "printSymbolLo";
183 def crbitm: Operand<i8> {
184 let PrintMethod = "printcrbitm";
187 def memri : Operand<i32> {
188 let PrintMethod = "printMemRegImm";
189 let NumMIOperands = 2;
190 let MIOperandInfo = (ops i32imm, GPRC);
192 def memrr : Operand<i32> {
193 let PrintMethod = "printMemRegReg";
194 let NumMIOperands = 2;
195 let MIOperandInfo = (ops GPRC, GPRC);
198 // Define PowerPC specific addressing mode.
199 def iaddr : ComplexPattern<i32, 2, "SelectAddrImm", []>;
200 def xaddr : ComplexPattern<i32, 2, "SelectAddrIdx", []>;
201 def xoaddr : ComplexPattern<i32, 2, "SelectAddrIdxOnly",[]>;
203 //===----------------------------------------------------------------------===//
204 // PowerPC Instruction Predicate Definitions.
205 def FPContractions : Predicate<"!NoExcessFPPrecision">;
207 //===----------------------------------------------------------------------===//
208 // PowerPC Instruction Definitions.
210 // Pseudo-instructions:
212 let hasCtrlDep = 1 in {
213 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
214 "; ADJCALLSTACKDOWN",
215 [(callseq_start imm:$amt)]>;
216 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
218 [(callseq_end imm:$amt)]>;
220 def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
221 "UPDATE_VRSAVE $rD, $rS", []>;
223 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
224 [(set GPRC:$rD, (undef))]>;
225 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8",
226 [(set F8RC:$rD, (undef))]>;
227 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; $rD = IMPLICIT_DEF_F4",
228 [(set F4RC:$rD, (undef))]>;
229 def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
230 [(set VRRC:$rD, (v4f32 (undef)))]>;
232 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
233 // scheduler into a branch sequence.
234 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
235 PPC970_Single = 1 in {
236 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
237 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
238 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
239 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
240 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
241 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
244 let isTerminator = 1, noResults = 1, PPC970_Unit = 7 in {
246 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
247 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
251 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
254 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
255 noResults = 1, PPC970_Unit = 7 in {
256 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$true),
257 "; COND_BRANCH", []>;
258 def B : IForm<18, 0, 0, (ops target:$dst),
262 // FIXME: 4*CR# needs to be added to the BI field!
263 // This will only work for CR0 as it stands now
264 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
265 "blt $crS, $block", BrB>;
266 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
267 "ble $crS, $block", BrB>;
268 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
269 "beq $crS, $block", BrB>;
270 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
271 "bge $crS, $block", BrB>;
272 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
273 "bgt $crS, $block", BrB>;
274 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
275 "bne $crS, $block", BrB>;
276 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
277 "bun $crS, $block", BrB>;
278 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
279 "bnu $crS, $block", BrB>;
282 let isCall = 1, noResults = 1, PPC970_Unit = 7,
283 // All calls clobber the non-callee saved registers...
284 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
285 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
286 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
288 CR0,CR1,CR5,CR6,CR7] in {
289 // Convenient aliases for call instructions
290 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
291 "bl $func", BrB, []>;
292 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
293 "bla $func", BrB, []>;
294 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB,
298 // D-Form instructions. Most instructions that perform an operation on a
299 // register and an immediate are of this type.
301 let isLoad = 1, PPC970_Unit = 2 in {
302 def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
303 "lbz $rD, $src", LdStGeneral,
304 [(set GPRC:$rD, (zextload iaddr:$src, i8))]>;
305 def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
306 "lha $rD, $src", LdStLHA,
307 [(set GPRC:$rD, (sextload iaddr:$src, i16))]>,
308 PPC970_DGroup_Cracked;
309 def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
310 "lhz $rD, $src", LdStGeneral,
311 [(set GPRC:$rD, (zextload iaddr:$src, i16))]>;
312 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
313 "lwz $rD, $src", LdStGeneral,
314 [(set GPRC:$rD, (load iaddr:$src))]>;
315 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
316 "lwzu $rD, $disp($rA)", LdStGeneral,
319 let PPC970_Unit = 1 in { // FXU Operations.
320 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
321 "addi $rD, $rA, $imm", IntGeneral,
322 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
323 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
324 "addic $rD, $rA, $imm", IntGeneral,
325 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
326 PPC970_DGroup_Cracked;
327 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
328 "addic. $rD, $rA, $imm", IntGeneral,
330 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
331 "addis $rD, $rA, $imm", IntGeneral,
332 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
333 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
334 "la $rD, $sym($rA)", IntGeneral,
335 [(set GPRC:$rD, (add GPRC:$rA,
336 (PPClo tglobaladdr:$sym, 0)))]>;
337 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
338 "mulli $rD, $rA, $imm", IntMulLI,
339 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
340 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
341 "subfic $rD, $rA, $imm", IntGeneral,
342 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
343 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
344 "li $rD, $imm", IntGeneral,
345 [(set GPRC:$rD, immSExt16:$imm)]>;
346 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
347 "lis $rD, $imm", IntGeneral,
348 [(set GPRC:$rD, imm16Shifted:$imm)]>;
350 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
351 def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
352 "stb $rS, $src", LdStGeneral,
353 [(truncstore GPRC:$rS, iaddr:$src, i8)]>;
354 def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
355 "sth $rS, $src", LdStGeneral,
356 [(truncstore GPRC:$rS, iaddr:$src, i16)]>;
357 def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
358 "stw $rS, $src", LdStGeneral,
359 [(store GPRC:$rS, iaddr:$src)]>;
360 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
361 "stwu $rS, $disp($rA)", LdStGeneral,
364 let PPC970_Unit = 1 in { // FXU Operations.
365 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
366 "andi. $dst, $src1, $src2", IntGeneral,
367 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
369 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
370 "andis. $dst, $src1, $src2", IntGeneral,
371 [(set GPRC:$dst, (and GPRC:$src1, imm16Shifted:$src2))]>,
373 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
374 "ori $dst, $src1, $src2", IntGeneral,
375 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
376 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
377 "oris $dst, $src1, $src2", IntGeneral,
378 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
379 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
380 "xori $dst, $src1, $src2", IntGeneral,
381 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
382 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
383 "xoris $dst, $src1, $src2", IntGeneral,
384 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
385 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
387 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
388 "cmpi $crD, $L, $rA, $imm", IntCompare>;
389 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
390 "cmpwi $crD, $rA, $imm", IntCompare>;
391 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
392 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
393 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
394 "cmpli $dst, $size, $src1, $src2", IntCompare>;
395 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
396 "cmplwi $dst, $src1, $src2", IntCompare>;
397 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
398 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
400 let isLoad = 1, PPC970_Unit = 2 in {
401 def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src),
402 "lfs $rD, $src", LdStLFDU,
403 [(set F4RC:$rD, (load iaddr:$src))]>;
404 def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src),
405 "lfd $rD, $src", LdStLFD,
406 [(set F8RC:$rD, (load iaddr:$src))]>;
408 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
409 def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst),
410 "stfs $rS, $dst", LdStUX,
411 [(store F4RC:$rS, iaddr:$dst)]>;
412 def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst),
413 "stfd $rS, $dst", LdStUX,
414 [(store F8RC:$rS, iaddr:$dst)]>;
417 // DS-Form instructions. Load/Store instructions available in PPC-64
419 let isLoad = 1, PPC970_Unit = 2 in {
420 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
421 "lwa $rT, $DS($rA)", LdStLWA,
422 []>, isPPC64, PPC970_DGroup_Cracked;
423 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
424 "ld $rT, $DS($rA)", LdStLD,
427 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
428 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
429 "std $rT, $DS($rA)", LdStSTD,
431 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
432 "stdu $rT, $DS($rA)", LdStSTD,
436 // X-Form instructions. Most instructions that perform an operation on a
437 // register and another register are of this type.
439 let isLoad = 1, PPC970_Unit = 2 in {
440 def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
441 "lbzx $rD, $src", LdStGeneral,
442 [(set GPRC:$rD, (zextload xaddr:$src, i8))]>;
443 def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
444 "lhax $rD, $src", LdStLHA,
445 [(set GPRC:$rD, (sextload xaddr:$src, i16))]>,
446 PPC970_DGroup_Cracked;
447 def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
448 "lhzx $rD, $src", LdStGeneral,
449 [(set GPRC:$rD, (zextload xaddr:$src, i16))]>;
450 def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
451 "lwax $rD, $src", LdStLHA,
452 [(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64,
453 PPC970_DGroup_Cracked;
454 def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
455 "lwzx $rD, $src", LdStGeneral,
456 [(set GPRC:$rD, (load xaddr:$src))]>;
457 def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
458 "ldx $rD, $src", LdStLD,
459 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
460 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
461 "lvebx $vD, $src", LdStGeneral,
463 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
464 "lvehx $vD, $src", LdStGeneral,
466 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
467 "lvewx $vD, $src", LdStGeneral,
468 [(set VRRC:$vD, (v4f32 (PPClve_x xoaddr:$src)))]>;
469 def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
470 "lvx $vD, $src", LdStGeneral,
471 [(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
473 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
474 "lvsl $vD, $base, $rA", LdStGeneral,
475 []>, PPC970_Unit_LSU;
476 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
477 "lvsl $vD, $base, $rA", LdStGeneral,
478 []>, PPC970_Unit_LSU;
479 let PPC970_Unit = 1 in { // FXU Operations.
480 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
481 "nand $rA, $rS, $rB", IntGeneral,
482 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
483 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
484 "and $rA, $rS, $rB", IntGeneral,
485 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
486 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
487 "and. $rA, $rS, $rB", IntGeneral,
489 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
490 "andc $rA, $rS, $rB", IntGeneral,
491 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
492 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
493 "or $rA, $rS, $rB", IntGeneral,
494 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
495 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
496 "or $rA, $rS, $rB", IntGeneral,
497 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
498 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
499 "or $rA, $rS, $rB", IntGeneral,
501 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
502 "or $rA, $rS, $rB", IntGeneral,
504 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
505 "nor $rA, $rS, $rB", IntGeneral,
506 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
507 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
508 "or. $rA, $rS, $rB", IntGeneral,
510 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
511 "orc $rA, $rS, $rB", IntGeneral,
512 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
513 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
514 "eqv $rA, $rS, $rB", IntGeneral,
515 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
516 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
517 "xor $rA, $rS, $rB", IntGeneral,
518 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
519 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
520 "sld $rA, $rS, $rB", IntRotateD,
521 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
522 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
523 "slw $rA, $rS, $rB", IntGeneral,
524 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
525 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
526 "srd $rA, $rS, $rB", IntRotateD,
527 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
528 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
529 "srw $rA, $rS, $rB", IntGeneral,
530 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
531 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
532 "srad $rA, $rS, $rB", IntRotateD,
533 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
534 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
535 "sraw $rA, $rS, $rB", IntShift,
536 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
538 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
539 def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
540 "stbx $rS, $dst", LdStGeneral,
541 [(truncstore GPRC:$rS, xaddr:$dst, i8)]>,
542 PPC970_DGroup_Cracked;
543 def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
544 "sthx $rS, $dst", LdStGeneral,
545 [(truncstore GPRC:$rS, xaddr:$dst, i16)]>,
546 PPC970_DGroup_Cracked;
547 def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
548 "stwx $rS, $dst", LdStGeneral,
549 [(store GPRC:$rS, xaddr:$dst)]>,
550 PPC970_DGroup_Cracked;
551 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
552 "stwux $rS, $rA, $rB", LdStGeneral,
554 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
555 "stdx $rS, $rA, $rB", LdStSTD,
556 []>, isPPC64, PPC970_DGroup_Cracked;
557 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
558 "stdux $rS, $rA, $rB", LdStSTD,
560 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
561 "stvebx $rS, $rA, $rB", LdStGeneral,
563 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
564 "stvehx $rS, $rA, $rB", LdStGeneral,
566 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
567 "stvewx $rS, $rA, $rB", LdStGeneral,
569 def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
570 "stvx $rS, $dst", LdStGeneral,
571 [(store (v4f32 VRRC:$rS), xoaddr:$dst)]>;
573 let PPC970_Unit = 1 in { // FXU Operations.
574 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
575 "srawi $rA, $rS, $SH", IntShift,
576 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
577 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
578 "cntlzw $rA, $rS", IntGeneral,
579 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
580 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
581 "extsb $rA, $rS", IntGeneral,
582 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
583 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
584 "extsh $rA, $rS", IntGeneral,
585 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
586 def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
587 "extsw $rA, $rS", IntGeneral,
588 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
589 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
590 "cmp $crD, $long, $rA, $rB", IntCompare>;
591 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
592 "cmpl $crD, $long, $rA, $rB", IntCompare>;
593 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
594 "cmpw $crD, $rA, $rB", IntCompare>;
595 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
596 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
597 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
598 "cmplw $crD, $rA, $rB", IntCompare>;
599 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
600 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
602 let PPC970_Unit = 3 in { // FPU Operations.
603 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
604 // "fcmpo $crD, $fA, $fB", FPCompare>;
605 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
606 "fcmpu $crD, $fA, $fB", FPCompare>;
607 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
608 "fcmpu $crD, $fA, $fB", FPCompare>;
610 let isLoad = 1, PPC970_Unit = 2 in {
611 def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
612 "lfsx $frD, $src", LdStLFDU,
613 [(set F4RC:$frD, (load xaddr:$src))]>;
614 def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
615 "lfdx $frD, $src", LdStLFDU,
616 [(set F8RC:$frD, (load xaddr:$src))]>;
618 let PPC970_Unit = 3 in { // FPU Operations.
619 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
620 "fcfid $frD, $frB", FPGeneral,
621 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
622 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
623 "fctidz $frD, $frB", FPGeneral,
624 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
625 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
626 "fctiwz $frD, $frB", FPGeneral,
627 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
628 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
629 "frsp $frD, $frB", FPGeneral,
630 [(set F4RC:$frD, (fround F8RC:$frB))]>;
631 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
632 "fsqrt $frD, $frB", FPSqrt,
633 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
634 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
635 "fsqrts $frD, $frB", FPSqrt,
636 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
639 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
641 /// Note that these are defined as pseudo-ops on the PPC970 because they are
642 /// often coallesced away and we don't want the dispatch group builder to think
643 /// that they will fill slots (which could cause the load of a LSU reject to
644 /// sneak into a d-group with a store).
645 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
646 "fmr $frD, $frB", FPGeneral,
647 []>, // (set F4RC:$frD, F4RC:$frB)
649 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
650 "fmr $frD, $frB", FPGeneral,
651 []>, // (set F8RC:$frD, F8RC:$frB)
653 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
654 "fmr $frD, $frB", FPGeneral,
655 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
658 let PPC970_Unit = 3 in { // FPU Operations.
659 // These are artificially split into two different forms, for 4/8 byte FP.
660 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
661 "fabs $frD, $frB", FPGeneral,
662 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
663 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
664 "fabs $frD, $frB", FPGeneral,
665 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
666 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
667 "fnabs $frD, $frB", FPGeneral,
668 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
669 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
670 "fnabs $frD, $frB", FPGeneral,
671 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
672 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
673 "fneg $frD, $frB", FPGeneral,
674 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
675 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
676 "fneg $frD, $frB", FPGeneral,
677 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
680 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
681 def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst),
682 "stfiwx $frS, $dst", LdStUX,
683 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
684 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
685 "stfsx $frS, $dst", LdStUX,
686 [(store F4RC:$frS, xaddr:$dst)]>;
687 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
688 "stfdx $frS, $dst", LdStUX,
689 [(store F8RC:$frS, xaddr:$dst)]>;
692 // XL-Form instructions. condition register logical ops.
694 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
695 "mcrf $BF, $BFA", BrMCR>,
696 PPC970_DGroup_First, PPC970_Unit_CRU;
698 // XFX-Form instructions. Instructions that deal with SPRs.
700 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>,
701 PPC970_DGroup_First, PPC970_Unit_FXU;
702 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>,
703 PPC970_DGroup_First, PPC970_Unit_FXU;
705 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>,
706 PPC970_DGroup_First, PPC970_Unit_FXU;
707 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>,
708 PPC970_DGroup_First, PPC970_Unit_FXU;
710 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
711 // a GPR on the PPC970. As such, copies in and out have the same performance
712 // characteristics as an OR instruction.
713 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS),
714 "mtspr 256, $rS", IntGeneral>,
715 PPC970_DGroup_Single, PPC970_Unit_FXU;
716 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT),
717 "mfspr $rT, 256", IntGeneral>,
718 PPC970_DGroup_First, PPC970_Unit_FXU;
720 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>,
721 PPC970_MicroCode, PPC970_Unit_CRU;
722 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
723 "mtcrf $FXM, $rS", BrMCRX>,
724 PPC970_MicroCode, PPC970_Unit_CRU;
725 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
726 "mfcr $rT, $FXM", SprMFCR>,
727 PPC970_DGroup_First, PPC970_Unit_CRU;
729 // XS-Form instructions. Just 'sradi'
731 let PPC970_Unit = 1 in { // FXU Operations.
732 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
733 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
735 // XO-Form instructions. Arithmetic instructions that can set overflow bit
737 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
738 "add $rT, $rA, $rB", IntGeneral,
739 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
740 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
741 "add $rT, $rA, $rB", IntGeneral,
742 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
743 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
744 "addc $rT, $rA, $rB", IntGeneral,
745 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
746 PPC970_DGroup_Cracked;
747 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
748 "adde $rT, $rA, $rB", IntGeneral,
749 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
750 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
751 "divd $rT, $rA, $rB", IntDivD,
752 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
753 PPC970_DGroup_First, PPC970_DGroup_Cracked;
754 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
755 "divdu $rT, $rA, $rB", IntDivD,
756 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
757 PPC970_DGroup_First, PPC970_DGroup_Cracked;
758 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
759 "divw $rT, $rA, $rB", IntDivW,
760 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
761 PPC970_DGroup_First, PPC970_DGroup_Cracked;
762 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
763 "divwu $rT, $rA, $rB", IntDivW,
764 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
765 PPC970_DGroup_First, PPC970_DGroup_Cracked;
766 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
767 "mulhd $rT, $rA, $rB", IntMulHW,
768 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
769 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
770 "mulhdu $rT, $rA, $rB", IntMulHWU,
771 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
772 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
773 "mulhw $rT, $rA, $rB", IntMulHW,
774 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
775 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
776 "mulhwu $rT, $rA, $rB", IntMulHWU,
777 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
778 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
779 "mulld $rT, $rA, $rB", IntMulHD,
780 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
781 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
782 "mullw $rT, $rA, $rB", IntMulHW,
783 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
784 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
785 "subf $rT, $rA, $rB", IntGeneral,
786 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
787 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
788 "subfc $rT, $rA, $rB", IntGeneral,
789 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
790 PPC970_DGroup_Cracked;
791 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
792 "subfe $rT, $rA, $rB", IntGeneral,
793 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
794 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
795 "addme $rT, $rA", IntGeneral,
796 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
797 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
798 "addze $rT, $rA", IntGeneral,
799 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
800 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
801 "neg $rT, $rA", IntGeneral,
802 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
803 def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA),
804 "subfme $rT, $rA", IntGeneral,
805 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
806 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
807 "subfze $rT, $rA", IntGeneral,
808 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
811 // A-Form instructions. Most of the instructions executed in the FPU are of
814 let PPC970_Unit = 3 in { // FPU Operations.
815 def FMADD : AForm_1<63, 29,
816 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
817 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
818 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
820 Requires<[FPContractions]>;
821 def FMADDS : AForm_1<59, 29,
822 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
823 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
824 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
826 Requires<[FPContractions]>;
827 def FMSUB : AForm_1<63, 28,
828 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
829 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
830 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
832 Requires<[FPContractions]>;
833 def FMSUBS : AForm_1<59, 28,
834 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
835 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
836 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
838 Requires<[FPContractions]>;
839 def FNMADD : AForm_1<63, 31,
840 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
841 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
842 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
844 Requires<[FPContractions]>;
845 def FNMADDS : AForm_1<59, 31,
846 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
847 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
848 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
850 Requires<[FPContractions]>;
851 def FNMSUB : AForm_1<63, 30,
852 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
853 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
854 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
856 Requires<[FPContractions]>;
857 def FNMSUBS : AForm_1<59, 30,
858 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
859 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
860 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
862 Requires<[FPContractions]>;
863 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
864 // having 4 of these, force the comparison to always be an 8-byte double (code
865 // should use an FMRSD if the input comparison value really wants to be a float)
866 // and 4/8 byte forms for the result and operand type..
867 def FSELD : AForm_1<63, 23,
868 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
869 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
870 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
871 def FSELS : AForm_1<63, 23,
872 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
873 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
874 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
875 def FADD : AForm_2<63, 21,
876 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
877 "fadd $FRT, $FRA, $FRB", FPGeneral,
878 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
879 def FADDS : AForm_2<59, 21,
880 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
881 "fadds $FRT, $FRA, $FRB", FPGeneral,
882 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
883 def FDIV : AForm_2<63, 18,
884 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
885 "fdiv $FRT, $FRA, $FRB", FPDivD,
886 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
887 def FDIVS : AForm_2<59, 18,
888 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
889 "fdivs $FRT, $FRA, $FRB", FPDivS,
890 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
891 def FMUL : AForm_3<63, 25,
892 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
893 "fmul $FRT, $FRA, $FRB", FPFused,
894 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
895 def FMULS : AForm_3<59, 25,
896 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
897 "fmuls $FRT, $FRA, $FRB", FPGeneral,
898 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
899 def FSUB : AForm_2<63, 20,
900 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
901 "fsub $FRT, $FRA, $FRB", FPGeneral,
902 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
903 def FSUBS : AForm_2<59, 20,
904 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
905 "fsubs $FRT, $FRA, $FRB", FPGeneral,
906 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
909 let PPC970_Unit = 1 in { // FXU Operations.
910 // M-Form instructions. rotate and mask instructions.
912 let isTwoAddress = 1, isCommutable = 1 in {
913 // RLWIMI can be commuted if the rotate amount is zero.
914 def RLWIMI : MForm_2<20,
915 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
916 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
917 []>, PPC970_DGroup_Cracked;
918 def RLDIMI : MDForm_1<30, 3,
919 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
920 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
923 def RLWINM : MForm_2<21,
924 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
925 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
927 def RLWINMo : MForm_2<21,
928 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
929 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
930 []>, isDOT, PPC970_DGroup_Cracked;
931 def RLWNM : MForm_2<23,
932 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
933 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
936 // MD-Form instructions. 64 bit rotate instructions.
938 def RLDICL : MDForm_1<30, 0,
939 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
940 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
942 def RLDICR : MDForm_1<30, 1,
943 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
944 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
949 let PPC970_Unit = 5 in { // VALU Operations.
950 // VA-Form instructions. 3-input AltiVec ops.
951 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
952 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
953 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
955 Requires<[FPContractions]>;
956 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
957 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
958 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA,
961 Requires<[FPContractions]>;
963 def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
964 "vperm $vD, $vA, $vB, $vC", VecPerm,
966 (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>;
969 // VX-Form instructions. AltiVec arithmetic ops.
970 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
971 "vaddfp $vD, $vA, $vB", VecFP,
972 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
973 def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
974 "vadduwm $vD, $vA, $vB", VecGeneral,
975 [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
976 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
977 "vcfsx $vD, $vB, $UIMM", VecFP,
979 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
980 "vcfux $vD, $vB, $UIMM", VecFP,
982 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
983 "vctsxs $vD, $vB, $UIMM", VecFP,
985 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
986 "vctuxs $vD, $vB, $UIMM", VecFP,
988 def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
989 "vexptefp $vD, $vB", VecFP,
991 def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
992 "vlogefp $vD, $vB", VecFP,
994 def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
995 "vmaxfp $vD, $vA, $vB", VecFP,
997 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
998 "vminfp $vD, $vA, $vB", VecFP,
1000 def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
1001 "vrefp $vD, $vB", VecFP,
1003 def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
1004 "vrfim $vD, $vB", VecFP,
1006 def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
1007 "vrfin $vD, $vB", VecFP,
1009 def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
1010 "vrfip $vD, $vB", VecFP,
1012 def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
1013 "vrfiz $vD, $vB", VecFP,
1015 def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
1016 "vrsqrtefp $vD, $vB", VecFP,
1018 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
1019 "vsubfp $vD, $vA, $vB", VecFP,
1020 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
1021 def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
1022 "vor $vD, $vA, $vB", VecFP,
1024 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
1025 "vxor $vD, $vA, $vB", VecFP,
1028 def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
1029 "vspltb $vD, $vB, $UIMM", VecPerm,
1031 def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
1032 "vsplth $vD, $vB, $UIMM", VecPerm,
1035 def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
1036 "vspltw $vD, $vB, $UIMM", VecPerm,
1037 [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
1038 VSPLT_shuffle_mask:$UIMM))]>;
1039 // FIXME: ALSO ADD SUPPORT FOR v4i32!
1041 // VX-Form Pseudo Instructions
1043 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
1044 "vxor $vD, $vD, $vD", VecFP,
1049 //===----------------------------------------------------------------------===//
1050 // DWARF Pseudo Instructions
1053 def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
1054 "; .loc $file, $line, $col",
1055 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
1058 def DWARF_LABEL : Pseudo<(ops i32imm:$id),
1060 [(dwarf_label (i32 imm:$id))]>;
1062 //===----------------------------------------------------------------------===//
1063 // PowerPC Instruction Patterns
1066 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1067 def : Pat<(i32 imm:$imm),
1068 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1070 // Implement the 'not' operation with the NOR instruction.
1071 def NOT : Pat<(not GPRC:$in),
1072 (NOR GPRC:$in, GPRC:$in)>;
1074 // ADD an arbitrary immediate.
1075 def : Pat<(add GPRC:$in, imm:$imm),
1076 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1077 // OR an arbitrary immediate.
1078 def : Pat<(or GPRC:$in, imm:$imm),
1079 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1080 // XOR an arbitrary immediate.
1081 def : Pat<(xor GPRC:$in, imm:$imm),
1082 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1084 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1085 (SUBFIC GPRC:$in, imm:$imm)>;
1087 // Return void support.
1088 def : Pat<(ret), (BLR)>;
1091 def : Pat<(i64 (zext GPRC:$in)),
1092 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
1093 def : Pat<(i64 (anyext GPRC:$in)),
1094 (OR4To8 GPRC:$in, GPRC:$in)>;
1095 def : Pat<(i32 (trunc G8RC:$in)),
1096 (OR8To4 G8RC:$in, G8RC:$in)>;
1099 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1100 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1101 def : Pat<(shl G8RC:$in, (i64 imm:$imm)),
1102 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
1104 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1105 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1106 def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
1107 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
1110 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1111 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1112 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1113 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1115 // Hi and Lo for Darwin Global Addresses.
1116 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1117 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1118 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1119 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1120 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1121 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1122 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1123 (ADDIS GPRC:$in, tconstpool:$g)>;
1125 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
1126 (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>;
1128 // Fused negative multiply subtract, alternate pattern
1129 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1130 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1131 Requires<[FPContractions]>;
1132 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1133 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1134 Requires<[FPContractions]>;
1136 // Fused multiply add and multiply sub for packed float. These are represented
1137 // separately from the real instructions above, for operations that must have
1138 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
1139 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
1140 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
1141 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
1142 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
1144 // Standard shifts. These are represented separately from the real shifts above
1145 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1147 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1148 (SRAW GPRC:$rS, GPRC:$rB)>;
1149 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1150 (SRW GPRC:$rS, GPRC:$rB)>;
1151 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1152 (SLW GPRC:$rS, GPRC:$rB)>;
1154 def : Pat<(i32 (zextload iaddr:$src, i1)),
1156 def : Pat<(i32 (zextload xaddr:$src, i1)),
1158 def : Pat<(i32 (extload iaddr:$src, i1)),
1160 def : Pat<(i32 (extload xaddr:$src, i1)),
1162 def : Pat<(i32 (extload iaddr:$src, i8)),
1164 def : Pat<(i32 (extload xaddr:$src, i8)),
1166 def : Pat<(i32 (extload iaddr:$src, i16)),
1168 def : Pat<(i32 (extload xaddr:$src, i16)),
1170 def : Pat<(f64 (extload iaddr:$src, f32)),
1171 (FMRSD (LFS iaddr:$src))>;
1172 def : Pat<(f64 (extload xaddr:$src, f32)),
1173 (FMRSD (LFSX xaddr:$src))>;
1175 def : Pat<(v4i32 (load xoaddr:$src)),
1176 (v4i32 (LVX xoaddr:$src))>;
1177 def : Pat<(v16i8 (load xoaddr:$src)),
1178 (v16i8 (LVX xoaddr:$src))>;
1181 def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
1182 (v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>;
1184 def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
1185 (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
1187 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
1188 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
1189 def : Pat<(v4i32 (PPClve_x xoaddr:$src)),
1190 (v4i32 (LVEWX xoaddr:$src))>;
1192 def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
1195 // Same as above, but using a temporary. FIXME: implement temporaries :)
1197 def : Pattern<(xor GPRC:$in, imm:$imm),
1198 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
1199 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;