1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
60 def tocentry32 : Operand<iPTR> {
61 let MIOperandInfo = (ops i32imm:$imm);
64 //===----------------------------------------------------------------------===//
65 // PowerPC specific DAG Nodes.
68 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
69 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
71 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
72 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
73 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
74 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
75 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
76 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
77 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
78 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
79 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
80 [SDNPHasChain, SDNPMayStore]>;
81 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
82 [SDNPHasChain, SDNPMayLoad]>;
83 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
84 [SDNPHasChain, SDNPMayLoad]>;
86 // Extract FPSCR (not modeled at the DAG level).
87 def PPCmffs : SDNode<"PPCISD::MFFS",
88 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
90 // Perform FADD in round-to-zero mode.
91 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
94 def PPCfsel : SDNode<"PPCISD::FSEL",
95 // Type constraint for fsel.
96 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
97 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
99 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
100 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
101 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
102 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
103 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
105 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
107 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
108 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
110 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
111 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
112 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
113 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
114 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
115 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
116 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
117 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
119 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
121 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
123 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
124 // amounts. These nodes are generated by the multi-precision shift code.
125 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
126 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
127 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
129 // These are target-independent nodes, but have target-specific formats.
130 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
131 [SDNPHasChain, SDNPOutGlue]>;
132 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
135 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
136 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
139 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
142 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
143 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
144 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
145 [SDNPHasChain, SDNPSideEffect,
146 SDNPInGlue, SDNPOutGlue]>;
147 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
149 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
150 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
153 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
154 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
156 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
157 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
159 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
160 SDTypeProfile<1, 1, [SDTCisInt<0>,
162 [SDNPHasChain, SDNPSideEffect]>;
163 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
164 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
165 [SDNPHasChain, SDNPSideEffect]>;
167 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
168 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
169 [SDNPHasChain, SDNPSideEffect]>;
171 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
172 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
174 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
175 [SDNPHasChain, SDNPOptInGlue]>;
177 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
178 [SDNPHasChain, SDNPMayLoad]>;
179 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
180 [SDNPHasChain, SDNPMayStore]>;
182 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
183 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
186 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
188 // Instructions to support atomic operations
189 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
190 [SDNPHasChain, SDNPMayLoad]>;
191 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
192 [SDNPHasChain, SDNPMayStore]>;
194 // Instructions to support medium and large code model
195 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
196 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
197 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
200 // Instructions to support dynamic alloca.
201 def SDTDynOp : SDTypeProfile<1, 2, []>;
202 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
204 //===----------------------------------------------------------------------===//
205 // PowerPC specific transformation functions and pattern fragments.
208 def SHL32 : SDNodeXForm<imm, [{
209 // Transformation function: 31 - imm
210 return getI32Imm(31 - N->getZExtValue());
213 def SRL32 : SDNodeXForm<imm, [{
214 // Transformation function: 32 - imm
215 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
218 def LO16 : SDNodeXForm<imm, [{
219 // Transformation function: get the low 16 bits.
220 return getI32Imm((unsigned short)N->getZExtValue());
223 def HI16 : SDNodeXForm<imm, [{
224 // Transformation function: shift the immediate value down into the low bits.
225 return getI32Imm((unsigned)N->getZExtValue() >> 16);
228 def HA16 : SDNodeXForm<imm, [{
229 // Transformation function: shift the immediate value down into the low bits.
230 signed int Val = N->getZExtValue();
231 return getI32Imm((Val - (signed short)Val) >> 16);
233 def MB : SDNodeXForm<imm, [{
234 // Transformation function: get the start bit of a mask
236 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
237 return getI32Imm(mb);
240 def ME : SDNodeXForm<imm, [{
241 // Transformation function: get the end bit of a mask
243 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
244 return getI32Imm(me);
246 def maskimm32 : PatLeaf<(imm), [{
247 // maskImm predicate - True if immediate is a run of ones.
249 if (N->getValueType(0) == MVT::i32)
250 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
255 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
256 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
257 // sign extended field. Used by instructions like 'addi'.
258 return (int32_t)Imm == (short)Imm;
260 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
261 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
262 // sign extended field. Used by instructions like 'addi'.
263 return (int64_t)Imm == (short)Imm;
265 def immZExt16 : PatLeaf<(imm), [{
266 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
267 // field. Used by instructions like 'ori'.
268 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
271 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
272 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
273 // identical in 32-bit mode, but in 64-bit mode, they return true if the
274 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
276 def imm16ShiftedZExt : PatLeaf<(imm), [{
277 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
278 // immediate are set. Used by instructions like 'xoris'.
279 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
282 def imm16ShiftedSExt : PatLeaf<(imm), [{
283 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
284 // immediate are set. Used by instructions like 'addis'. Identical to
285 // imm16ShiftedZExt in 32-bit mode.
286 if (N->getZExtValue() & 0xFFFF) return false;
287 if (N->getValueType(0) == MVT::i32)
289 // For 64-bit, make sure it is sext right.
290 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
293 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
294 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
295 // zero extended field.
296 return isUInt<32>(Imm);
299 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
300 // restricted memrix (4-aligned) constants are alignment sensitive. If these
301 // offsets are hidden behind TOC entries than the values of the lower-order
302 // bits cannot be checked directly. As a result, we need to also incorporate
303 // an alignment check into the relevant patterns.
305 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
306 return cast<LoadSDNode>(N)->getAlignment() >= 4;
308 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
309 (store node:$val, node:$ptr), [{
310 return cast<StoreSDNode>(N)->getAlignment() >= 4;
312 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
313 return cast<LoadSDNode>(N)->getAlignment() >= 4;
315 def aligned4pre_store : PatFrag<
316 (ops node:$val, node:$base, node:$offset),
317 (pre_store node:$val, node:$base, node:$offset), [{
318 return cast<StoreSDNode>(N)->getAlignment() >= 4;
321 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
322 return cast<LoadSDNode>(N)->getAlignment() < 4;
324 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
325 (store node:$val, node:$ptr), [{
326 return cast<StoreSDNode>(N)->getAlignment() < 4;
328 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
329 return cast<LoadSDNode>(N)->getAlignment() < 4;
332 //===----------------------------------------------------------------------===//
333 // PowerPC Flag Definitions.
335 class isPPC64 { bit PPC64 = 1; }
336 class isDOT { bit RC = 1; }
338 class RegConstraint<string C> {
339 string Constraints = C;
341 class NoEncode<string E> {
342 string DisableEncoding = E;
346 //===----------------------------------------------------------------------===//
347 // PowerPC Operand Definitions.
349 // In the default PowerPC assembler syntax, registers are specified simply
350 // by number, so they cannot be distinguished from immediate values (without
351 // looking at the opcode). This means that the default operand matching logic
352 // for the asm parser does not work, and we need to specify custom matchers.
353 // Since those can only be specified with RegisterOperand classes and not
354 // directly on the RegisterClass, all instructions patterns used by the asm
355 // parser need to use a RegisterOperand (instead of a RegisterClass) for
356 // all their register operands.
357 // For this purpose, we define one RegisterOperand for each RegisterClass,
358 // using the same name as the class, just in lower case.
360 def PPCRegGPRCAsmOperand : AsmOperandClass {
361 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
363 def gprc : RegisterOperand<GPRC> {
364 let ParserMatchClass = PPCRegGPRCAsmOperand;
366 def PPCRegG8RCAsmOperand : AsmOperandClass {
367 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
369 def g8rc : RegisterOperand<G8RC> {
370 let ParserMatchClass = PPCRegG8RCAsmOperand;
372 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
373 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
375 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
376 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
378 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
379 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
381 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
382 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
384 def PPCRegF8RCAsmOperand : AsmOperandClass {
385 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
387 def f8rc : RegisterOperand<F8RC> {
388 let ParserMatchClass = PPCRegF8RCAsmOperand;
390 def PPCRegF4RCAsmOperand : AsmOperandClass {
391 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
393 def f4rc : RegisterOperand<F4RC> {
394 let ParserMatchClass = PPCRegF4RCAsmOperand;
396 def PPCRegVRRCAsmOperand : AsmOperandClass {
397 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
399 def vrrc : RegisterOperand<VRRC> {
400 let ParserMatchClass = PPCRegVRRCAsmOperand;
402 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
403 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
405 def crbitrc : RegisterOperand<CRBITRC> {
406 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
408 def PPCRegCRRCAsmOperand : AsmOperandClass {
409 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
411 def crrc : RegisterOperand<CRRC> {
412 let ParserMatchClass = PPCRegCRRCAsmOperand;
415 def PPCU2ImmAsmOperand : AsmOperandClass {
416 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
417 let RenderMethod = "addImmOperands";
419 def u2imm : Operand<i32> {
420 let PrintMethod = "printU2ImmOperand";
421 let ParserMatchClass = PPCU2ImmAsmOperand;
423 def PPCS5ImmAsmOperand : AsmOperandClass {
424 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
425 let RenderMethod = "addImmOperands";
427 def s5imm : Operand<i32> {
428 let PrintMethod = "printS5ImmOperand";
429 let ParserMatchClass = PPCS5ImmAsmOperand;
430 let DecoderMethod = "decodeSImmOperand<5>";
432 def PPCU5ImmAsmOperand : AsmOperandClass {
433 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
434 let RenderMethod = "addImmOperands";
436 def u5imm : Operand<i32> {
437 let PrintMethod = "printU5ImmOperand";
438 let ParserMatchClass = PPCU5ImmAsmOperand;
439 let DecoderMethod = "decodeUImmOperand<5>";
441 def PPCU6ImmAsmOperand : AsmOperandClass {
442 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
443 let RenderMethod = "addImmOperands";
445 def u6imm : Operand<i32> {
446 let PrintMethod = "printU6ImmOperand";
447 let ParserMatchClass = PPCU6ImmAsmOperand;
448 let DecoderMethod = "decodeUImmOperand<6>";
450 def PPCS16ImmAsmOperand : AsmOperandClass {
451 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
452 let RenderMethod = "addImmOperands";
454 def s16imm : Operand<i32> {
455 let PrintMethod = "printS16ImmOperand";
456 let EncoderMethod = "getImm16Encoding";
457 let ParserMatchClass = PPCS16ImmAsmOperand;
458 let DecoderMethod = "decodeSImmOperand<16>";
460 def PPCU16ImmAsmOperand : AsmOperandClass {
461 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
462 let RenderMethod = "addImmOperands";
464 def u16imm : Operand<i32> {
465 let PrintMethod = "printU16ImmOperand";
466 let EncoderMethod = "getImm16Encoding";
467 let ParserMatchClass = PPCU16ImmAsmOperand;
468 let DecoderMethod = "decodeUImmOperand<16>";
470 def PPCS17ImmAsmOperand : AsmOperandClass {
471 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
472 let RenderMethod = "addImmOperands";
474 def s17imm : Operand<i32> {
475 // This operand type is used for addis/lis to allow the assembler parser
476 // to accept immediates in the range -65536..65535 for compatibility with
477 // the GNU assembler. The operand is treated as 16-bit otherwise.
478 let PrintMethod = "printS16ImmOperand";
479 let EncoderMethod = "getImm16Encoding";
480 let ParserMatchClass = PPCS17ImmAsmOperand;
481 let DecoderMethod = "decodeSImmOperand<16>";
483 def PPCDirectBrAsmOperand : AsmOperandClass {
484 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
485 let RenderMethod = "addBranchTargetOperands";
487 def directbrtarget : Operand<OtherVT> {
488 let PrintMethod = "printBranchOperand";
489 let EncoderMethod = "getDirectBrEncoding";
490 let ParserMatchClass = PPCDirectBrAsmOperand;
492 def absdirectbrtarget : Operand<OtherVT> {
493 let PrintMethod = "printAbsBranchOperand";
494 let EncoderMethod = "getAbsDirectBrEncoding";
495 let ParserMatchClass = PPCDirectBrAsmOperand;
497 def PPCCondBrAsmOperand : AsmOperandClass {
498 let Name = "CondBr"; let PredicateMethod = "isCondBr";
499 let RenderMethod = "addBranchTargetOperands";
501 def condbrtarget : Operand<OtherVT> {
502 let PrintMethod = "printBranchOperand";
503 let EncoderMethod = "getCondBrEncoding";
504 let ParserMatchClass = PPCCondBrAsmOperand;
506 def abscondbrtarget : Operand<OtherVT> {
507 let PrintMethod = "printAbsBranchOperand";
508 let EncoderMethod = "getAbsCondBrEncoding";
509 let ParserMatchClass = PPCCondBrAsmOperand;
511 def calltarget : Operand<iPTR> {
512 let PrintMethod = "printBranchOperand";
513 let EncoderMethod = "getDirectBrEncoding";
514 let ParserMatchClass = PPCDirectBrAsmOperand;
516 def abscalltarget : Operand<iPTR> {
517 let PrintMethod = "printAbsBranchOperand";
518 let EncoderMethod = "getAbsDirectBrEncoding";
519 let ParserMatchClass = PPCDirectBrAsmOperand;
521 def PPCCRBitMaskOperand : AsmOperandClass {
522 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
524 def crbitm: Operand<i8> {
525 let PrintMethod = "printcrbitm";
526 let EncoderMethod = "get_crbitm_encoding";
527 let DecoderMethod = "decodeCRBitMOperand";
528 let ParserMatchClass = PPCCRBitMaskOperand;
531 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
532 def PPCRegGxRCNoR0Operand : AsmOperandClass {
533 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
535 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
536 let ParserMatchClass = PPCRegGxRCNoR0Operand;
538 // A version of ptr_rc usable with the asm parser.
539 def PPCRegGxRCOperand : AsmOperandClass {
540 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
542 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
543 let ParserMatchClass = PPCRegGxRCOperand;
546 def PPCDispRIOperand : AsmOperandClass {
547 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
548 let RenderMethod = "addImmOperands";
550 def dispRI : Operand<iPTR> {
551 let ParserMatchClass = PPCDispRIOperand;
553 def PPCDispRIXOperand : AsmOperandClass {
554 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
555 let RenderMethod = "addImmOperands";
557 def dispRIX : Operand<iPTR> {
558 let ParserMatchClass = PPCDispRIXOperand;
561 def memri : Operand<iPTR> {
562 let PrintMethod = "printMemRegImm";
563 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
564 let EncoderMethod = "getMemRIEncoding";
565 let DecoderMethod = "decodeMemRIOperands";
567 def memrr : Operand<iPTR> {
568 let PrintMethod = "printMemRegReg";
569 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
571 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
572 let PrintMethod = "printMemRegImm";
573 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
574 let EncoderMethod = "getMemRIXEncoding";
575 let DecoderMethod = "decodeMemRIXOperands";
578 // A single-register address. This is used with the SjLj
579 // pseudo-instructions.
580 def memr : Operand<iPTR> {
581 let MIOperandInfo = (ops ptr_rc:$ptrreg);
583 def PPCTLSRegOperand : AsmOperandClass {
584 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
585 let RenderMethod = "addTLSRegOperands";
587 def tlsreg32 : Operand<i32> {
588 let EncoderMethod = "getTLSRegEncoding";
589 let ParserMatchClass = PPCTLSRegOperand;
591 def tlsgd32 : Operand<i32> {}
592 def tlscall32 : Operand<i32> {
593 let PrintMethod = "printTLSCall";
594 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
595 let EncoderMethod = "getTLSCallEncoding";
598 // PowerPC Predicate operand.
599 def pred : Operand<OtherVT> {
600 let PrintMethod = "printPredicateOperand";
601 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
604 // Define PowerPC specific addressing mode.
605 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
606 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
607 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
608 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
610 // The address in a single register. This is used with the SjLj
611 // pseudo-instructions.
612 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
614 /// This is just the offset part of iaddr, used for preinc.
615 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
617 //===----------------------------------------------------------------------===//
618 // PowerPC Instruction Predicate Definitions.
619 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
620 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
621 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
622 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
624 //===----------------------------------------------------------------------===//
625 // PowerPC Multiclass Definitions.
627 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
628 string asmbase, string asmstr, InstrItinClass itin,
630 let BaseName = asmbase in {
631 def NAME : XForm_6<opcode, xo, OOL, IOL,
632 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
633 pattern>, RecFormRel;
635 def o : XForm_6<opcode, xo, OOL, IOL,
636 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
637 []>, isDOT, RecFormRel;
641 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
642 string asmbase, string asmstr, InstrItinClass itin,
644 let BaseName = asmbase in {
645 let Defs = [CARRY] in
646 def NAME : XForm_6<opcode, xo, OOL, IOL,
647 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
648 pattern>, RecFormRel;
649 let Defs = [CARRY, CR0] in
650 def o : XForm_6<opcode, xo, OOL, IOL,
651 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
652 []>, isDOT, RecFormRel;
656 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
657 string asmbase, string asmstr, InstrItinClass itin,
659 let BaseName = asmbase in {
660 let Defs = [CARRY] in
661 def NAME : XForm_10<opcode, xo, OOL, IOL,
662 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
663 pattern>, RecFormRel;
664 let Defs = [CARRY, CR0] in
665 def o : XForm_10<opcode, xo, OOL, IOL,
666 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
667 []>, isDOT, RecFormRel;
671 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
672 string asmbase, string asmstr, InstrItinClass itin,
674 let BaseName = asmbase in {
675 def NAME : XForm_11<opcode, xo, OOL, IOL,
676 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
677 pattern>, RecFormRel;
679 def o : XForm_11<opcode, xo, OOL, IOL,
680 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
681 []>, isDOT, RecFormRel;
685 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
686 string asmbase, string asmstr, InstrItinClass itin,
688 let BaseName = asmbase in {
689 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
690 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
691 pattern>, RecFormRel;
693 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
694 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
695 []>, isDOT, RecFormRel;
699 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
700 string asmbase, string asmstr, InstrItinClass itin,
702 let BaseName = asmbase in {
703 let Defs = [CARRY] in
704 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
705 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
706 pattern>, RecFormRel;
707 let Defs = [CARRY, CR0] in
708 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
709 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
710 []>, isDOT, RecFormRel;
714 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
715 string asmbase, string asmstr, InstrItinClass itin,
717 let BaseName = asmbase in {
718 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
719 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
720 pattern>, RecFormRel;
722 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
723 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
724 []>, isDOT, RecFormRel;
728 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
729 string asmbase, string asmstr, InstrItinClass itin,
731 let BaseName = asmbase in {
732 let Defs = [CARRY] in
733 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
734 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
735 pattern>, RecFormRel;
736 let Defs = [CARRY, CR0] in
737 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
738 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
739 []>, isDOT, RecFormRel;
743 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
744 string asmbase, string asmstr, InstrItinClass itin,
746 let BaseName = asmbase in {
747 def NAME : MForm_2<opcode, OOL, IOL,
748 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
749 pattern>, RecFormRel;
751 def o : MForm_2<opcode, OOL, IOL,
752 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
753 []>, isDOT, RecFormRel;
757 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
758 string asmbase, string asmstr, InstrItinClass itin,
760 let BaseName = asmbase in {
761 def NAME : MDForm_1<opcode, xo, OOL, IOL,
762 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
763 pattern>, RecFormRel;
765 def o : MDForm_1<opcode, xo, OOL, IOL,
766 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
767 []>, isDOT, RecFormRel;
771 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
772 string asmbase, string asmstr, InstrItinClass itin,
774 let BaseName = asmbase in {
775 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
776 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
777 pattern>, RecFormRel;
779 def o : MDSForm_1<opcode, xo, OOL, IOL,
780 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
781 []>, isDOT, RecFormRel;
785 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
786 string asmbase, string asmstr, InstrItinClass itin,
788 let BaseName = asmbase in {
789 let Defs = [CARRY] in
790 def NAME : XSForm_1<opcode, xo, OOL, IOL,
791 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
792 pattern>, RecFormRel;
793 let Defs = [CARRY, CR0] in
794 def o : XSForm_1<opcode, xo, OOL, IOL,
795 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
796 []>, isDOT, RecFormRel;
800 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
801 string asmbase, string asmstr, InstrItinClass itin,
803 let BaseName = asmbase in {
804 def NAME : XForm_26<opcode, xo, OOL, IOL,
805 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
806 pattern>, RecFormRel;
808 def o : XForm_26<opcode, xo, OOL, IOL,
809 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
810 []>, isDOT, RecFormRel;
814 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
815 string asmbase, string asmstr, InstrItinClass itin,
817 let BaseName = asmbase in {
818 def NAME : XForm_28<opcode, xo, OOL, IOL,
819 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
820 pattern>, RecFormRel;
822 def o : XForm_28<opcode, xo, OOL, IOL,
823 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
824 []>, isDOT, RecFormRel;
828 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
829 string asmbase, string asmstr, InstrItinClass itin,
831 let BaseName = asmbase in {
832 def NAME : AForm_1<opcode, xo, OOL, IOL,
833 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
834 pattern>, RecFormRel;
836 def o : AForm_1<opcode, xo, OOL, IOL,
837 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
838 []>, isDOT, RecFormRel;
842 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
843 string asmbase, string asmstr, InstrItinClass itin,
845 let BaseName = asmbase in {
846 def NAME : AForm_2<opcode, xo, OOL, IOL,
847 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
848 pattern>, RecFormRel;
850 def o : AForm_2<opcode, xo, OOL, IOL,
851 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
852 []>, isDOT, RecFormRel;
856 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
857 string asmbase, string asmstr, InstrItinClass itin,
859 let BaseName = asmbase in {
860 def NAME : AForm_3<opcode, xo, OOL, IOL,
861 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
862 pattern>, RecFormRel;
864 def o : AForm_3<opcode, xo, OOL, IOL,
865 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
866 []>, isDOT, RecFormRel;
870 //===----------------------------------------------------------------------===//
871 // PowerPC Instruction Definitions.
873 // Pseudo-instructions:
875 let hasCtrlDep = 1 in {
876 let Defs = [R1], Uses = [R1] in {
877 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
878 [(callseq_start timm:$amt)]>;
879 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
880 [(callseq_end timm:$amt1, timm:$amt2)]>;
883 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
884 "UPDATE_VRSAVE $rD, $rS", []>;
887 let Defs = [R1], Uses = [R1] in
888 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
890 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
892 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
893 // instruction selection into a branch sequence.
894 let usesCustomInserter = 1, // Expanded after instruction selection.
895 PPC970_Single = 1 in {
896 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
897 // because either operand might become the first operand in an isel, and
898 // that operand cannot be r0.
899 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
900 gprc_nor0:$T, gprc_nor0:$F,
901 i32imm:$BROPC), "#SELECT_CC_I4",
903 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
904 g8rc_nox0:$T, g8rc_nox0:$F,
905 i32imm:$BROPC), "#SELECT_CC_I8",
907 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
908 i32imm:$BROPC), "#SELECT_CC_F4",
910 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
911 i32imm:$BROPC), "#SELECT_CC_F8",
913 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
914 i32imm:$BROPC), "#SELECT_CC_VRRC",
917 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
918 // register bit directly.
919 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
920 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
921 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
922 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
923 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
924 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
925 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
926 f4rc:$T, f4rc:$F), "#SELECT_F4",
927 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
928 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
929 f8rc:$T, f8rc:$F), "#SELECT_F8",
930 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
931 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
932 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
934 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
937 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
938 // scavenge a register for it.
939 let mayStore = 1 in {
940 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
942 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
946 // RESTORE_CR - Indicate that we're restoring the CR register (previously
947 // spilled), so we'll need to scavenge a register for it.
949 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
951 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
952 "#RESTORE_CRBIT", []>;
955 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
956 let isReturn = 1, Uses = [LR, RM] in
957 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
959 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
960 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
963 let isCodeGenOnly = 1 in {
964 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
965 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
968 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
969 "bcctr 12, $bi, 0", IIC_BrB, []>;
970 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
971 "bcctr 4, $bi, 0", IIC_BrB, []>;
977 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
980 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
981 let isBarrier = 1 in {
982 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
985 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
986 "ba $dst", IIC_BrB, []>;
989 // BCC represents an arbitrary conditional branch on a predicate.
990 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
991 // a two-value operand where a dag node expects two operands. :(
992 let isCodeGenOnly = 1 in {
993 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
994 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
995 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
996 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
997 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
999 let isReturn = 1, Uses = [LR, RM] in
1000 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1001 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1004 let isCodeGenOnly = 1 in {
1005 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1006 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1007 "bc 12, $bi, $dst">;
1009 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1010 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1013 let isReturn = 1, Uses = [LR, RM] in
1014 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1015 "bclr 12, $bi, 0", IIC_BrB, []>;
1016 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1017 "bclr 4, $bi, 0", IIC_BrB, []>;
1020 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1021 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1022 "bdzlr", IIC_BrB, []>;
1023 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1024 "bdnzlr", IIC_BrB, []>;
1025 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1026 "bdzlr+", IIC_BrB, []>;
1027 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1028 "bdnzlr+", IIC_BrB, []>;
1029 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1030 "bdzlr-", IIC_BrB, []>;
1031 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1032 "bdnzlr-", IIC_BrB, []>;
1035 let Defs = [CTR], Uses = [CTR] in {
1036 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1038 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1040 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1042 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1044 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1046 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1048 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1050 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1052 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1054 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1056 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1058 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1063 // The unconditional BCL used by the SjLj setjmp code.
1064 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1065 let Defs = [LR], Uses = [RM] in {
1066 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1067 "bcl 20, 31, $dst">;
1071 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1072 // Convenient aliases for call instructions
1073 let Uses = [RM] in {
1074 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1075 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1076 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1077 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1079 let isCodeGenOnly = 1 in {
1080 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1081 "bl $func", IIC_BrB, []>;
1082 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1083 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1084 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1085 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1087 def BCL : BForm_4<16, 12, 0, 1, (outs),
1088 (ins crbitrc:$bi, condbrtarget:$dst),
1089 "bcl 12, $bi, $dst">;
1090 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1091 (ins crbitrc:$bi, condbrtarget:$dst),
1092 "bcl 4, $bi, $dst">;
1095 let Uses = [CTR, RM] in {
1096 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1097 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1098 Requires<[In32BitMode]>;
1100 let isCodeGenOnly = 1 in {
1101 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1102 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1105 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1106 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1107 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1108 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1111 let Uses = [LR, RM] in {
1112 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1113 "blrl", IIC_BrB, []>;
1115 let isCodeGenOnly = 1 in {
1116 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1117 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1120 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1121 "bclrl 12, $bi, 0", IIC_BrB, []>;
1122 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1123 "bclrl 4, $bi, 0", IIC_BrB, []>;
1126 let Defs = [CTR], Uses = [CTR, RM] in {
1127 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1129 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1131 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1133 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1135 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1137 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1139 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1141 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1143 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1145 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1147 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1149 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1152 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1153 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1154 "bdzlrl", IIC_BrB, []>;
1155 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1156 "bdnzlrl", IIC_BrB, []>;
1157 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1158 "bdzlrl+", IIC_BrB, []>;
1159 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1160 "bdnzlrl+", IIC_BrB, []>;
1161 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1162 "bdzlrl-", IIC_BrB, []>;
1163 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1164 "bdnzlrl-", IIC_BrB, []>;
1168 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1169 def TCRETURNdi :Pseudo< (outs),
1170 (ins calltarget:$dst, i32imm:$offset),
1171 "#TC_RETURNd $dst $offset",
1175 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1176 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1177 "#TC_RETURNa $func $offset",
1178 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1180 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1181 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1182 "#TC_RETURNr $dst $offset",
1186 let isCodeGenOnly = 1 in {
1188 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1189 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1190 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1191 []>, Requires<[In32BitMode]>;
1193 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1194 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1195 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1199 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1200 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1201 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1207 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1209 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1210 "#EH_SJLJ_SETJMP32",
1211 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1212 Requires<[In32BitMode]>;
1213 let isTerminator = 1 in
1214 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1215 "#EH_SJLJ_LONGJMP32",
1216 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1217 Requires<[In32BitMode]>;
1220 let isBranch = 1, isTerminator = 1 in {
1221 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1222 "#EH_SjLj_Setup\t$dst", []>;
1226 let PPC970_Unit = 7 in {
1227 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1228 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1231 // DCB* instructions.
1232 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1233 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1234 PPC970_DGroup_Single;
1235 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1236 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1237 PPC970_DGroup_Single;
1238 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1239 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1240 PPC970_DGroup_Single;
1241 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1242 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1243 PPC970_DGroup_Single;
1244 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1245 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1246 PPC970_DGroup_Single;
1247 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1248 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1249 PPC970_DGroup_Single;
1250 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1251 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1252 PPC970_DGroup_Single;
1253 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1254 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1255 PPC970_DGroup_Single;
1257 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1258 (DCBT xoaddr:$dst)>;
1260 // Atomic operations
1261 let usesCustomInserter = 1 in {
1262 let Defs = [CR0] in {
1263 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1264 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1265 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1266 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1267 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1268 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1269 def ATOMIC_LOAD_AND_I8 : Pseudo<
1270 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1271 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1272 def ATOMIC_LOAD_OR_I8 : Pseudo<
1273 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1274 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1275 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1276 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1277 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1278 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1279 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1280 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1281 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1282 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1283 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1284 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1285 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1286 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1287 def ATOMIC_LOAD_AND_I16 : Pseudo<
1288 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1289 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1290 def ATOMIC_LOAD_OR_I16 : Pseudo<
1291 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1292 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1293 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1294 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1295 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1296 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1297 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1298 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1299 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1300 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1301 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1302 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1303 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1304 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1305 def ATOMIC_LOAD_AND_I32 : Pseudo<
1306 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1307 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1308 def ATOMIC_LOAD_OR_I32 : Pseudo<
1309 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1310 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1311 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1312 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1313 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1314 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1315 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1316 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1318 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1319 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1320 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1321 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1322 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1323 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1324 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1325 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1326 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1328 def ATOMIC_SWAP_I8 : Pseudo<
1329 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1330 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1331 def ATOMIC_SWAP_I16 : Pseudo<
1332 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1333 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1334 def ATOMIC_SWAP_I32 : Pseudo<
1335 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1336 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1340 // Instructions to support atomic operations
1341 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1342 "lwarx $rD, $src", IIC_LdStLWARX,
1343 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1346 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1347 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1348 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1351 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1352 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1354 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1355 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1356 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1357 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1358 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1359 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1360 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1361 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1363 //===----------------------------------------------------------------------===//
1364 // PPC32 Load Instructions.
1367 // Unindexed (r+i) Loads.
1368 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1369 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1370 "lbz $rD, $src", IIC_LdStLoad,
1371 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1372 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1373 "lha $rD, $src", IIC_LdStLHA,
1374 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1375 PPC970_DGroup_Cracked;
1376 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1377 "lhz $rD, $src", IIC_LdStLoad,
1378 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1379 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1380 "lwz $rD, $src", IIC_LdStLoad,
1381 [(set i32:$rD, (load iaddr:$src))]>;
1383 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1384 "lfs $rD, $src", IIC_LdStLFD,
1385 [(set f32:$rD, (load iaddr:$src))]>;
1386 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1387 "lfd $rD, $src", IIC_LdStLFD,
1388 [(set f64:$rD, (load iaddr:$src))]>;
1391 // Unindexed (r+i) Loads with Update (preinc).
1392 let mayLoad = 1, neverHasSideEffects = 1 in {
1393 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1394 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1395 []>, RegConstraint<"$addr.reg = $ea_result">,
1396 NoEncode<"$ea_result">;
1398 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1399 "lhau $rD, $addr", IIC_LdStLHAU,
1400 []>, RegConstraint<"$addr.reg = $ea_result">,
1401 NoEncode<"$ea_result">;
1403 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1404 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1405 []>, RegConstraint<"$addr.reg = $ea_result">,
1406 NoEncode<"$ea_result">;
1408 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1409 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1410 []>, RegConstraint<"$addr.reg = $ea_result">,
1411 NoEncode<"$ea_result">;
1413 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1414 "lfsu $rD, $addr", IIC_LdStLFDU,
1415 []>, RegConstraint<"$addr.reg = $ea_result">,
1416 NoEncode<"$ea_result">;
1418 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1419 "lfdu $rD, $addr", IIC_LdStLFDU,
1420 []>, RegConstraint<"$addr.reg = $ea_result">,
1421 NoEncode<"$ea_result">;
1424 // Indexed (r+r) Loads with Update (preinc).
1425 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1427 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1428 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1429 NoEncode<"$ea_result">;
1431 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1433 "lhaux $rD, $addr", IIC_LdStLHAUX,
1434 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1435 NoEncode<"$ea_result">;
1437 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1439 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1440 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1441 NoEncode<"$ea_result">;
1443 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1445 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1446 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1447 NoEncode<"$ea_result">;
1449 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1451 "lfsux $rD, $addr", IIC_LdStLFDUX,
1452 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1453 NoEncode<"$ea_result">;
1455 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1457 "lfdux $rD, $addr", IIC_LdStLFDUX,
1458 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1459 NoEncode<"$ea_result">;
1463 // Indexed (r+r) Loads.
1465 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1466 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1467 "lbzx $rD, $src", IIC_LdStLoad,
1468 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1469 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1470 "lhax $rD, $src", IIC_LdStLHA,
1471 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1472 PPC970_DGroup_Cracked;
1473 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1474 "lhzx $rD, $src", IIC_LdStLoad,
1475 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1476 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1477 "lwzx $rD, $src", IIC_LdStLoad,
1478 [(set i32:$rD, (load xaddr:$src))]>;
1481 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1482 "lhbrx $rD, $src", IIC_LdStLoad,
1483 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1484 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1485 "lwbrx $rD, $src", IIC_LdStLoad,
1486 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1488 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1489 "lfsx $frD, $src", IIC_LdStLFD,
1490 [(set f32:$frD, (load xaddr:$src))]>;
1491 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1492 "lfdx $frD, $src", IIC_LdStLFD,
1493 [(set f64:$frD, (load xaddr:$src))]>;
1495 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1496 "lfiwax $frD, $src", IIC_LdStLFD,
1497 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1498 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1499 "lfiwzx $frD, $src", IIC_LdStLFD,
1500 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1504 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1505 "lmw $rD, $src", IIC_LdStLMW, []>;
1507 //===----------------------------------------------------------------------===//
1508 // PPC32 Store Instructions.
1511 // Unindexed (r+i) Stores.
1512 let PPC970_Unit = 2 in {
1513 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1514 "stb $rS, $src", IIC_LdStStore,
1515 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1516 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1517 "sth $rS, $src", IIC_LdStStore,
1518 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1519 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1520 "stw $rS, $src", IIC_LdStStore,
1521 [(store i32:$rS, iaddr:$src)]>;
1522 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1523 "stfs $rS, $dst", IIC_LdStSTFD,
1524 [(store f32:$rS, iaddr:$dst)]>;
1525 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1526 "stfd $rS, $dst", IIC_LdStSTFD,
1527 [(store f64:$rS, iaddr:$dst)]>;
1530 // Unindexed (r+i) Stores with Update (preinc).
1531 let PPC970_Unit = 2, mayStore = 1 in {
1532 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1533 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1534 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1535 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1536 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1537 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1538 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1539 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1540 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1541 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1542 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1543 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1544 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1545 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1546 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1549 // Patterns to match the pre-inc stores. We can't put the patterns on
1550 // the instruction definitions directly as ISel wants the address base
1551 // and offset to be separate operands, not a single complex operand.
1552 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1553 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1554 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1555 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1556 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1557 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1558 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1559 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1560 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1561 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1563 // Indexed (r+r) Stores.
1564 let PPC970_Unit = 2 in {
1565 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1566 "stbx $rS, $dst", IIC_LdStStore,
1567 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1568 PPC970_DGroup_Cracked;
1569 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1570 "sthx $rS, $dst", IIC_LdStStore,
1571 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1572 PPC970_DGroup_Cracked;
1573 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1574 "stwx $rS, $dst", IIC_LdStStore,
1575 [(store i32:$rS, xaddr:$dst)]>,
1576 PPC970_DGroup_Cracked;
1578 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1579 "sthbrx $rS, $dst", IIC_LdStStore,
1580 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1581 PPC970_DGroup_Cracked;
1582 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1583 "stwbrx $rS, $dst", IIC_LdStStore,
1584 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1585 PPC970_DGroup_Cracked;
1587 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1588 "stfiwx $frS, $dst", IIC_LdStSTFD,
1589 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1591 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1592 "stfsx $frS, $dst", IIC_LdStSTFD,
1593 [(store f32:$frS, xaddr:$dst)]>;
1594 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1595 "stfdx $frS, $dst", IIC_LdStSTFD,
1596 [(store f64:$frS, xaddr:$dst)]>;
1599 // Indexed (r+r) Stores with Update (preinc).
1600 let PPC970_Unit = 2, mayStore = 1 in {
1601 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1602 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1603 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1604 PPC970_DGroup_Cracked;
1605 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1606 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1607 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1608 PPC970_DGroup_Cracked;
1609 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1610 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1611 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1612 PPC970_DGroup_Cracked;
1613 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1614 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1615 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1616 PPC970_DGroup_Cracked;
1617 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1618 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1619 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1620 PPC970_DGroup_Cracked;
1623 // Patterns to match the pre-inc stores. We can't put the patterns on
1624 // the instruction definitions directly as ISel wants the address base
1625 // and offset to be separate operands, not a single complex operand.
1626 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1627 (STBUX $rS, $ptrreg, $ptroff)>;
1628 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1629 (STHUX $rS, $ptrreg, $ptroff)>;
1630 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1631 (STWUX $rS, $ptrreg, $ptroff)>;
1632 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1633 (STFSUX $rS, $ptrreg, $ptroff)>;
1634 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1635 (STFDUX $rS, $ptrreg, $ptroff)>;
1638 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1639 "stmw $rS, $dst", IIC_LdStLMW, []>;
1641 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1642 "sync $L", IIC_LdStSync, []>, Requires<[IsNotBookE]>;
1644 let isCodeGenOnly = 1 in {
1645 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1646 "msync", IIC_LdStSync, []>, Requires<[IsBookE]> {
1651 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[IsNotBookE]>;
1652 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[IsBookE]>;
1654 //===----------------------------------------------------------------------===//
1655 // PPC32 Arithmetic Instructions.
1658 let PPC970_Unit = 1 in { // FXU Operations.
1659 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1660 "addi $rD, $rA, $imm", IIC_IntSimple,
1661 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1662 let BaseName = "addic" in {
1663 let Defs = [CARRY] in
1664 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1665 "addic $rD, $rA, $imm", IIC_IntGeneral,
1666 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1667 RecFormRel, PPC970_DGroup_Cracked;
1668 let Defs = [CARRY, CR0] in
1669 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1670 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1671 []>, isDOT, RecFormRel;
1673 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1674 "addis $rD, $rA, $imm", IIC_IntSimple,
1675 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1676 let isCodeGenOnly = 1 in
1677 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1678 "la $rD, $sym($rA)", IIC_IntGeneral,
1679 [(set i32:$rD, (add i32:$rA,
1680 (PPClo tglobaladdr:$sym, 0)))]>;
1681 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1682 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1683 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1684 let Defs = [CARRY] in
1685 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1686 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1687 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1689 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1690 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1691 "li $rD, $imm", IIC_IntSimple,
1692 [(set i32:$rD, imm32SExt16:$imm)]>;
1693 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1694 "lis $rD, $imm", IIC_IntSimple,
1695 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1699 let PPC970_Unit = 1 in { // FXU Operations.
1700 let Defs = [CR0] in {
1701 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1702 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1703 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1705 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1706 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1707 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1710 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1711 "ori $dst, $src1, $src2", IIC_IntSimple,
1712 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1713 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1714 "oris $dst, $src1, $src2", IIC_IntSimple,
1715 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1716 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1717 "xori $dst, $src1, $src2", IIC_IntSimple,
1718 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1719 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1720 "xoris $dst, $src1, $src2", IIC_IntSimple,
1721 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1723 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1725 let isCodeGenOnly = 1 in {
1726 // The POWER6 and POWER7 have special group-terminating nops.
1727 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1728 "ori 1, 1, 0", IIC_IntSimple, []>;
1729 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1730 "ori 2, 2, 0", IIC_IntSimple, []>;
1733 let isCompare = 1, neverHasSideEffects = 1 in {
1734 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1735 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1736 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1737 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1741 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1742 let isCommutable = 1 in {
1743 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1744 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1745 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1746 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1747 "and", "$rA, $rS, $rB", IIC_IntSimple,
1748 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1750 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1751 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1752 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1753 let isCommutable = 1 in {
1754 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1755 "or", "$rA, $rS, $rB", IIC_IntSimple,
1756 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1757 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1758 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1759 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1761 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1762 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1763 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1764 let isCommutable = 1 in {
1765 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1766 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1767 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1768 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1769 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1770 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1772 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1773 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1774 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1775 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1776 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1777 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1778 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1779 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1780 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1783 let PPC970_Unit = 1 in { // FXU Operations.
1784 let neverHasSideEffects = 1 in {
1785 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1786 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1787 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1788 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1789 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1790 [(set i32:$rA, (ctlz i32:$rS))]>;
1791 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1792 "extsb", "$rA, $rS", IIC_IntSimple,
1793 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1794 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1795 "extsh", "$rA, $rS", IIC_IntSimple,
1796 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1798 let isCompare = 1, neverHasSideEffects = 1 in {
1799 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1800 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1801 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1802 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1805 let PPC970_Unit = 3 in { // FPU Operations.
1806 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1807 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1808 let isCompare = 1, neverHasSideEffects = 1 in {
1809 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1810 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1811 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1812 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1813 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1816 let Uses = [RM] in {
1817 let neverHasSideEffects = 1 in {
1818 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1819 "fctiw", "$frD, $frB", IIC_FPGeneral,
1821 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1822 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1823 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1825 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1826 "frsp", "$frD, $frB", IIC_FPGeneral,
1827 [(set f32:$frD, (fround f64:$frB))]>;
1829 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1830 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1831 "frin", "$frD, $frB", IIC_FPGeneral,
1832 [(set f64:$frD, (frnd f64:$frB))]>;
1833 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1834 "frin", "$frD, $frB", IIC_FPGeneral,
1835 [(set f32:$frD, (frnd f32:$frB))]>;
1838 let neverHasSideEffects = 1 in {
1839 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1840 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1841 "frip", "$frD, $frB", IIC_FPGeneral,
1842 [(set f64:$frD, (fceil f64:$frB))]>;
1843 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1844 "frip", "$frD, $frB", IIC_FPGeneral,
1845 [(set f32:$frD, (fceil f32:$frB))]>;
1846 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1847 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1848 "friz", "$frD, $frB", IIC_FPGeneral,
1849 [(set f64:$frD, (ftrunc f64:$frB))]>;
1850 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1851 "friz", "$frD, $frB", IIC_FPGeneral,
1852 [(set f32:$frD, (ftrunc f32:$frB))]>;
1853 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1854 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1855 "frim", "$frD, $frB", IIC_FPGeneral,
1856 [(set f64:$frD, (ffloor f64:$frB))]>;
1857 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1858 "frim", "$frD, $frB", IIC_FPGeneral,
1859 [(set f32:$frD, (ffloor f32:$frB))]>;
1861 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1862 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1863 [(set f64:$frD, (fsqrt f64:$frB))]>;
1864 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1865 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1866 [(set f32:$frD, (fsqrt f32:$frB))]>;
1871 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1872 /// often coalesced away and we don't want the dispatch group builder to think
1873 /// that they will fill slots (which could cause the load of a LSU reject to
1874 /// sneak into a d-group with a store).
1875 let neverHasSideEffects = 1 in
1876 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1877 "fmr", "$frD, $frB", IIC_FPGeneral,
1878 []>, // (set f32:$frD, f32:$frB)
1881 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1882 // These are artificially split into two different forms, for 4/8 byte FP.
1883 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1884 "fabs", "$frD, $frB", IIC_FPGeneral,
1885 [(set f32:$frD, (fabs f32:$frB))]>;
1886 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1887 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1888 "fabs", "$frD, $frB", IIC_FPGeneral,
1889 [(set f64:$frD, (fabs f64:$frB))]>;
1890 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1891 "fnabs", "$frD, $frB", IIC_FPGeneral,
1892 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1893 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1894 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1895 "fnabs", "$frD, $frB", IIC_FPGeneral,
1896 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1897 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1898 "fneg", "$frD, $frB", IIC_FPGeneral,
1899 [(set f32:$frD, (fneg f32:$frB))]>;
1900 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1901 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1902 "fneg", "$frD, $frB", IIC_FPGeneral,
1903 [(set f64:$frD, (fneg f64:$frB))]>;
1905 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1906 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1907 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1908 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1909 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1910 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1911 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1913 // Reciprocal estimates.
1914 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1915 "fre", "$frD, $frB", IIC_FPGeneral,
1916 [(set f64:$frD, (PPCfre f64:$frB))]>;
1917 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1918 "fres", "$frD, $frB", IIC_FPGeneral,
1919 [(set f32:$frD, (PPCfre f32:$frB))]>;
1920 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1921 "frsqrte", "$frD, $frB", IIC_FPGeneral,
1922 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1923 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1924 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
1925 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1928 // XL-Form instructions. condition register logical ops.
1930 let neverHasSideEffects = 1 in
1931 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1932 "mcrf $BF, $BFA", IIC_BrMCR>,
1933 PPC970_DGroup_First, PPC970_Unit_CRU;
1935 let isCommutable = 1 in {
1936 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
1937 (ins crbitrc:$CRA, crbitrc:$CRB),
1938 "crand $CRD, $CRA, $CRB", IIC_BrCR,
1939 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
1941 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
1942 (ins crbitrc:$CRA, crbitrc:$CRB),
1943 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
1944 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
1946 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
1947 (ins crbitrc:$CRA, crbitrc:$CRB),
1948 "cror $CRD, $CRA, $CRB", IIC_BrCR,
1949 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
1951 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
1952 (ins crbitrc:$CRA, crbitrc:$CRB),
1953 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
1954 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
1956 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
1957 (ins crbitrc:$CRA, crbitrc:$CRB),
1958 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
1959 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
1961 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
1962 (ins crbitrc:$CRA, crbitrc:$CRB),
1963 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
1964 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
1967 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
1968 (ins crbitrc:$CRA, crbitrc:$CRB),
1969 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
1970 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
1972 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
1973 (ins crbitrc:$CRA, crbitrc:$CRB),
1974 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
1975 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
1977 let isCodeGenOnly = 1 in {
1978 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
1979 "creqv $dst, $dst, $dst", IIC_BrCR,
1980 [(set i1:$dst, 1)]>;
1982 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
1983 "crxor $dst, $dst, $dst", IIC_BrCR,
1984 [(set i1:$dst, 0)]>;
1986 let Defs = [CR1EQ], CRD = 6 in {
1987 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1988 "creqv 6, 6, 6", IIC_BrCR,
1991 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1992 "crxor 6, 6, 6", IIC_BrCR,
1997 // XFX-Form instructions. Instructions that deal with SPRs.
2000 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2001 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2002 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2003 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2005 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2006 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2008 let Uses = [CTR] in {
2009 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2010 "mfctr $rT", IIC_SprMFSPR>,
2011 PPC970_DGroup_First, PPC970_Unit_FXU;
2013 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2014 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2015 "mtctr $rS", IIC_SprMTSPR>,
2016 PPC970_DGroup_First, PPC970_Unit_FXU;
2018 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2019 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2020 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2021 "mtctr $rS", IIC_SprMTSPR>,
2022 PPC970_DGroup_First, PPC970_Unit_FXU;
2025 let Defs = [LR] in {
2026 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2027 "mtlr $rS", IIC_SprMTSPR>,
2028 PPC970_DGroup_First, PPC970_Unit_FXU;
2030 let Uses = [LR] in {
2031 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2032 "mflr $rT", IIC_SprMFSPR>,
2033 PPC970_DGroup_First, PPC970_Unit_FXU;
2036 let isCodeGenOnly = 1 in {
2037 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2038 // like a GPR on the PPC970. As such, copies in and out have the same
2039 // performance characteristics as an OR instruction.
2040 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2041 "mtspr 256, $rS", IIC_IntGeneral>,
2042 PPC970_DGroup_Single, PPC970_Unit_FXU;
2043 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2044 "mfspr $rT, 256", IIC_IntGeneral>,
2045 PPC970_DGroup_First, PPC970_Unit_FXU;
2047 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2048 (outs VRSAVERC:$reg), (ins gprc:$rS),
2049 "mtspr 256, $rS", IIC_IntGeneral>,
2050 PPC970_DGroup_Single, PPC970_Unit_FXU;
2051 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2052 (ins VRSAVERC:$reg),
2053 "mfspr $rT, 256", IIC_IntGeneral>,
2054 PPC970_DGroup_First, PPC970_Unit_FXU;
2057 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2058 // so we'll need to scavenge a register for it.
2060 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2061 "#SPILL_VRSAVE", []>;
2063 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2064 // spilled), so we'll need to scavenge a register for it.
2066 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2067 "#RESTORE_VRSAVE", []>;
2069 let neverHasSideEffects = 1 in {
2070 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2071 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2072 PPC970_DGroup_First, PPC970_Unit_CRU;
2074 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2075 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2076 PPC970_MicroCode, PPC970_Unit_CRU;
2078 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2079 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2080 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2081 PPC970_DGroup_First, PPC970_Unit_CRU;
2083 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2084 "mfcr $rT", IIC_SprMFCR>,
2085 PPC970_MicroCode, PPC970_Unit_CRU;
2086 } // neverHasSideEffects = 1
2088 // Pseudo instruction to perform FADD in round-to-zero mode.
2089 let usesCustomInserter = 1, Uses = [RM] in {
2090 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2091 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2094 // The above pseudo gets expanded to make use of the following instructions
2095 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2096 let Uses = [RM], Defs = [RM] in {
2097 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2098 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2099 PPC970_DGroup_Single, PPC970_Unit_FPU;
2100 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2101 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2102 PPC970_DGroup_Single, PPC970_Unit_FPU;
2103 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2104 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2105 PPC970_DGroup_Single, PPC970_Unit_FPU;
2107 let Uses = [RM] in {
2108 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2109 "mffs $rT", IIC_IntMFFS,
2110 [(set f64:$rT, (PPCmffs))]>,
2111 PPC970_DGroup_Single, PPC970_Unit_FPU;
2115 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
2116 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2117 let isCommutable = 1 in
2118 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2119 "add", "$rT, $rA, $rB", IIC_IntSimple,
2120 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2121 let isCodeGenOnly = 1 in
2122 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2123 "add $rT, $rA, $rB", IIC_IntSimple,
2124 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2125 let isCommutable = 1 in
2126 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2127 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2128 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2129 PPC970_DGroup_Cracked;
2131 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2132 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2133 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2134 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2135 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2136 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2137 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2138 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2139 let isCommutable = 1 in {
2140 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2141 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2142 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2143 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2144 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2145 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2146 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2147 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2148 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2150 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2151 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2152 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2153 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2154 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2155 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2156 PPC970_DGroup_Cracked;
2157 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2158 "neg", "$rT, $rA", IIC_IntSimple,
2159 [(set i32:$rT, (ineg i32:$rA))]>;
2160 let Uses = [CARRY] in {
2161 let isCommutable = 1 in
2162 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2163 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2164 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2165 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2166 "addme", "$rT, $rA", IIC_IntGeneral,
2167 [(set i32:$rT, (adde i32:$rA, -1))]>;
2168 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2169 "addze", "$rT, $rA", IIC_IntGeneral,
2170 [(set i32:$rT, (adde i32:$rA, 0))]>;
2171 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2172 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2173 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2174 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2175 "subfme", "$rT, $rA", IIC_IntGeneral,
2176 [(set i32:$rT, (sube -1, i32:$rA))]>;
2177 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2178 "subfze", "$rT, $rA", IIC_IntGeneral,
2179 [(set i32:$rT, (sube 0, i32:$rA))]>;
2183 // A-Form instructions. Most of the instructions executed in the FPU are of
2186 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
2187 let Uses = [RM] in {
2188 let isCommutable = 1 in {
2189 defm FMADD : AForm_1r<63, 29,
2190 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2191 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2192 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2193 defm FMADDS : AForm_1r<59, 29,
2194 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2195 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2196 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2197 defm FMSUB : AForm_1r<63, 28,
2198 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2199 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2201 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2202 defm FMSUBS : AForm_1r<59, 28,
2203 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2204 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2206 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2207 defm FNMADD : AForm_1r<63, 31,
2208 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2209 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2211 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2212 defm FNMADDS : AForm_1r<59, 31,
2213 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2214 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2216 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2217 defm FNMSUB : AForm_1r<63, 30,
2218 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2219 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2220 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2221 (fneg f64:$FRB))))]>;
2222 defm FNMSUBS : AForm_1r<59, 30,
2223 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2224 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2225 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2226 (fneg f32:$FRB))))]>;
2229 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2230 // having 4 of these, force the comparison to always be an 8-byte double (code
2231 // should use an FMRSD if the input comparison value really wants to be a float)
2232 // and 4/8 byte forms for the result and operand type..
2233 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2234 defm FSELD : AForm_1r<63, 23,
2235 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2236 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2237 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2238 defm FSELS : AForm_1r<63, 23,
2239 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2240 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2241 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2242 let Uses = [RM] in {
2243 let isCommutable = 1 in {
2244 defm FADD : AForm_2r<63, 21,
2245 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2246 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2247 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2248 defm FADDS : AForm_2r<59, 21,
2249 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2250 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2251 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2253 defm FDIV : AForm_2r<63, 18,
2254 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2255 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2256 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2257 defm FDIVS : AForm_2r<59, 18,
2258 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2259 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2260 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2261 let isCommutable = 1 in {
2262 defm FMUL : AForm_3r<63, 25,
2263 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2264 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2265 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2266 defm FMULS : AForm_3r<59, 25,
2267 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2268 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2269 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2271 defm FSUB : AForm_2r<63, 20,
2272 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2273 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2274 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2275 defm FSUBS : AForm_2r<59, 20,
2276 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2277 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2278 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2282 let neverHasSideEffects = 1 in {
2283 let PPC970_Unit = 1 in { // FXU Operations.
2285 def ISEL : AForm_4<31, 15,
2286 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2287 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
2291 let PPC970_Unit = 1 in { // FXU Operations.
2292 // M-Form instructions. rotate and mask instructions.
2294 let isCommutable = 1 in {
2295 // RLWIMI can be commuted if the rotate amount is zero.
2296 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2297 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2298 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2299 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2300 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2302 let BaseName = "rlwinm" in {
2303 def RLWINM : MForm_2<21,
2304 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2305 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2308 def RLWINMo : MForm_2<21,
2309 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2310 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2311 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2313 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2314 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2315 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2318 } // neverHasSideEffects = 1
2320 //===----------------------------------------------------------------------===//
2321 // PowerPC Instruction Patterns
2324 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2325 def : Pat<(i32 imm:$imm),
2326 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2328 // Implement the 'not' operation with the NOR instruction.
2329 def i32not : OutPatFrag<(ops node:$in),
2331 def : Pat<(not i32:$in),
2334 // ADD an arbitrary immediate.
2335 def : Pat<(add i32:$in, imm:$imm),
2336 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2337 // OR an arbitrary immediate.
2338 def : Pat<(or i32:$in, imm:$imm),
2339 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2340 // XOR an arbitrary immediate.
2341 def : Pat<(xor i32:$in, imm:$imm),
2342 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2344 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2345 (SUBFIC $in, imm:$imm)>;
2348 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2349 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2350 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2351 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2354 def : Pat<(rotl i32:$in, i32:$sh),
2355 (RLWNM $in, $sh, 0, 31)>;
2356 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2357 (RLWINM $in, imm:$imm, 0, 31)>;
2360 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2361 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2364 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2365 (BL tglobaladdr:$dst)>;
2366 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2367 (BL texternalsym:$dst)>;
2370 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2371 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2373 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2374 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2376 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2377 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2381 // Hi and Lo for Darwin Global Addresses.
2382 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2383 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2384 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2385 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2386 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2387 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2388 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2389 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2390 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2391 (ADDIS $in, tglobaltlsaddr:$g)>;
2392 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2393 (ADDI $in, tglobaltlsaddr:$g)>;
2394 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2395 (ADDIS $in, tglobaladdr:$g)>;
2396 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2397 (ADDIS $in, tconstpool:$g)>;
2398 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2399 (ADDIS $in, tjumptable:$g)>;
2400 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2401 (ADDIS $in, tblockaddress:$g)>;
2403 // Support for thread-local storage.
2404 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2405 [(set i32:$rD, (PPCppc32GOT))]>;
2407 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2408 // This uses two output registers, the first as the real output, the second as a
2409 // temporary register, used internally in code generation.
2410 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2411 []>, NoEncode<"$rT">;
2413 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2416 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2417 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2418 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2420 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2423 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2424 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2427 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2428 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2431 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2432 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2435 (PPCgetTlsldAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2436 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2439 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2440 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2443 (PPCaddisDtprelHA i32:$reg,
2444 tglobaltlsaddr:$disp))]>;
2446 // Support for Position-independent code
2447 def LWZtoc: Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2450 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2451 // Get Global (GOT) Base Register offset, from the word immediately preceding
2452 // the function label.
2453 def GetGBRO: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#GetGBRO", []>;
2454 // Update the Global(GOT) Base Register with the above offset.
2455 def UpdateGBR: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2458 // Standard shifts. These are represented separately from the real shifts above
2459 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2461 def : Pat<(sra i32:$rS, i32:$rB),
2463 def : Pat<(srl i32:$rS, i32:$rB),
2465 def : Pat<(shl i32:$rS, i32:$rB),
2468 def : Pat<(zextloadi1 iaddr:$src),
2470 def : Pat<(zextloadi1 xaddr:$src),
2472 def : Pat<(extloadi1 iaddr:$src),
2474 def : Pat<(extloadi1 xaddr:$src),
2476 def : Pat<(extloadi8 iaddr:$src),
2478 def : Pat<(extloadi8 xaddr:$src),
2480 def : Pat<(extloadi16 iaddr:$src),
2482 def : Pat<(extloadi16 xaddr:$src),
2484 def : Pat<(f64 (extloadf32 iaddr:$src)),
2485 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2486 def : Pat<(f64 (extloadf32 xaddr:$src)),
2487 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2489 def : Pat<(f64 (fextend f32:$src)),
2490 (COPY_TO_REGCLASS $src, F8RC)>;
2492 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[IsNotBookE]>;
2493 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[IsBookE]>;
2495 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2496 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2497 (FNMSUB $A, $C, $B)>;
2498 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2499 (FNMSUB $A, $C, $B)>;
2500 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2501 (FNMSUBS $A, $C, $B)>;
2502 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2503 (FNMSUBS $A, $C, $B)>;
2505 // FCOPYSIGN's operand types need not agree.
2506 def : Pat<(fcopysign f64:$frB, f32:$frA),
2507 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2508 def : Pat<(fcopysign f32:$frB, f64:$frA),
2509 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2511 include "PPCInstrAltivec.td"
2512 include "PPCInstr64Bit.td"
2513 include "PPCInstrVSX.td"
2515 def crnot : OutPatFrag<(ops node:$in),
2517 def : Pat<(not i1:$in),
2520 // Patterns for arithmetic i1 operations.
2521 def : Pat<(add i1:$a, i1:$b),
2523 def : Pat<(sub i1:$a, i1:$b),
2525 def : Pat<(mul i1:$a, i1:$b),
2528 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2529 // (-1 is used to mean all bits set).
2530 def : Pat<(i1 -1), (CRSET)>;
2532 // i1 extensions, implemented in terms of isel.
2533 def : Pat<(i32 (zext i1:$in)),
2534 (SELECT_I4 $in, (LI 1), (LI 0))>;
2535 def : Pat<(i32 (sext i1:$in)),
2536 (SELECT_I4 $in, (LI -1), (LI 0))>;
2538 def : Pat<(i64 (zext i1:$in)),
2539 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2540 def : Pat<(i64 (sext i1:$in)),
2541 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2543 // FIXME: We should choose either a zext or a sext based on other constants
2545 def : Pat<(i32 (anyext i1:$in)),
2546 (SELECT_I4 $in, (LI 1), (LI 0))>;
2547 def : Pat<(i64 (anyext i1:$in)),
2548 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2550 // match setcc on i1 variables.
2551 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2553 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2555 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2557 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2559 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2561 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2563 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2565 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2567 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2569 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2572 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2573 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2574 // floating-point types.
2576 multiclass CRNotPat<dag pattern, dag result> {
2577 def : Pat<pattern, (crnot result)>;
2578 def : Pat<(not pattern), result>;
2580 // We can also fold the crnot into an extension:
2581 def : Pat<(i32 (zext pattern)),
2582 (SELECT_I4 result, (LI 0), (LI 1))>;
2583 def : Pat<(i32 (sext pattern)),
2584 (SELECT_I4 result, (LI 0), (LI -1))>;
2586 // We can also fold the crnot into an extension:
2587 def : Pat<(i64 (zext pattern)),
2588 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2589 def : Pat<(i64 (sext pattern)),
2590 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2592 // FIXME: We should choose either a zext or a sext based on other constants
2594 def : Pat<(i32 (anyext pattern)),
2595 (SELECT_I4 result, (LI 0), (LI 1))>;
2597 def : Pat<(i64 (anyext pattern)),
2598 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2601 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2602 // we need to write imm:$imm in the output patterns below, not just $imm, or
2603 // else the resulting matcher will not correctly add the immediate operand
2604 // (making it a register operand instead).
2607 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2608 OutPatFrag rfrag, OutPatFrag rfrag8> {
2609 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2611 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2613 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2614 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2615 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2616 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2618 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2620 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2622 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2623 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2624 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2625 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2628 // Note that we do all inversions below with i(32|64)not, instead of using
2629 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2630 // has 2-cycle latency.
2632 defm : ExtSetCCPat<SETEQ,
2633 PatFrag<(ops node:$in, node:$cc),
2634 (setcc $in, 0, $cc)>,
2635 OutPatFrag<(ops node:$in),
2636 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2637 OutPatFrag<(ops node:$in),
2638 (RLDICL (CNTLZD $in), 58, 63)> >;
2640 defm : ExtSetCCPat<SETNE,
2641 PatFrag<(ops node:$in, node:$cc),
2642 (setcc $in, 0, $cc)>,
2643 OutPatFrag<(ops node:$in),
2644 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2645 OutPatFrag<(ops node:$in),
2646 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2648 defm : ExtSetCCPat<SETLT,
2649 PatFrag<(ops node:$in, node:$cc),
2650 (setcc $in, 0, $cc)>,
2651 OutPatFrag<(ops node:$in),
2652 (RLWINM $in, 1, 31, 31)>,
2653 OutPatFrag<(ops node:$in),
2654 (RLDICL $in, 1, 63)> >;
2656 defm : ExtSetCCPat<SETGE,
2657 PatFrag<(ops node:$in, node:$cc),
2658 (setcc $in, 0, $cc)>,
2659 OutPatFrag<(ops node:$in),
2660 (RLWINM (i32not $in), 1, 31, 31)>,
2661 OutPatFrag<(ops node:$in),
2662 (RLDICL (i64not $in), 1, 63)> >;
2664 defm : ExtSetCCPat<SETGT,
2665 PatFrag<(ops node:$in, node:$cc),
2666 (setcc $in, 0, $cc)>,
2667 OutPatFrag<(ops node:$in),
2668 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2669 OutPatFrag<(ops node:$in),
2670 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2672 defm : ExtSetCCPat<SETLE,
2673 PatFrag<(ops node:$in, node:$cc),
2674 (setcc $in, 0, $cc)>,
2675 OutPatFrag<(ops node:$in),
2676 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2677 OutPatFrag<(ops node:$in),
2678 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2680 defm : ExtSetCCPat<SETLT,
2681 PatFrag<(ops node:$in, node:$cc),
2682 (setcc $in, -1, $cc)>,
2683 OutPatFrag<(ops node:$in),
2684 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2685 OutPatFrag<(ops node:$in),
2686 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2688 defm : ExtSetCCPat<SETGE,
2689 PatFrag<(ops node:$in, node:$cc),
2690 (setcc $in, -1, $cc)>,
2691 OutPatFrag<(ops node:$in),
2692 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2693 OutPatFrag<(ops node:$in),
2694 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2696 defm : ExtSetCCPat<SETGT,
2697 PatFrag<(ops node:$in, node:$cc),
2698 (setcc $in, -1, $cc)>,
2699 OutPatFrag<(ops node:$in),
2700 (RLWINM (i32not $in), 1, 31, 31)>,
2701 OutPatFrag<(ops node:$in),
2702 (RLDICL (i64not $in), 1, 63)> >;
2704 defm : ExtSetCCPat<SETLE,
2705 PatFrag<(ops node:$in, node:$cc),
2706 (setcc $in, -1, $cc)>,
2707 OutPatFrag<(ops node:$in),
2708 (RLWINM $in, 1, 31, 31)>,
2709 OutPatFrag<(ops node:$in),
2710 (RLDICL $in, 1, 63)> >;
2713 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2714 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2715 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2716 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2717 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2718 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2719 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2720 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2721 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2722 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2723 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2724 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2726 // For non-equality comparisons, the default code would materialize the
2727 // constant, then compare against it, like this:
2729 // ori r2, r2, 22136
2732 // Since we are just comparing for equality, we can emit this instead:
2733 // xoris r0,r3,0x1234
2734 // cmplwi cr0,r0,0x5678
2737 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2738 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2739 (LO16 imm:$imm)), sub_eq)>;
2741 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2742 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2743 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2744 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2745 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2746 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2747 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2748 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2749 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2750 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2751 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2752 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2754 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2755 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2756 (LO16 imm:$imm)), sub_eq)>;
2758 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
2759 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2760 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2761 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2762 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2763 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2764 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
2765 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2766 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2767 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2769 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2770 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2771 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
2772 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2773 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2774 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2775 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
2776 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2777 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2778 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2781 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
2782 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2783 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2784 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2785 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2786 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2787 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
2788 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2789 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
2790 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2791 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
2792 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2794 // For non-equality comparisons, the default code would materialize the
2795 // constant, then compare against it, like this:
2797 // ori r2, r2, 22136
2800 // Since we are just comparing for equality, we can emit this instead:
2801 // xoris r0,r3,0x1234
2802 // cmpldi cr0,r0,0x5678
2805 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
2806 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2807 (LO16 imm:$imm)), sub_eq)>;
2809 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
2810 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2811 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
2812 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2813 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
2814 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2815 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
2816 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2817 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
2818 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2819 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
2820 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2822 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
2823 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2824 (LO16 imm:$imm)), sub_eq)>;
2826 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
2827 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2828 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
2829 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2830 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
2831 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2832 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
2833 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2834 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
2835 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2837 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
2838 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2839 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
2840 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2841 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
2842 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2843 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
2844 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2845 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
2846 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2849 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
2850 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2851 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
2852 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2853 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
2854 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2855 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
2856 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2857 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
2858 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2859 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
2860 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2861 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
2862 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2864 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
2865 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2866 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
2867 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2868 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
2869 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2870 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
2871 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2872 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
2873 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2874 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
2875 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2876 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
2877 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2880 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
2881 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2882 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
2883 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2884 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
2885 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2886 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
2887 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2888 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
2889 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2890 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
2891 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2892 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
2893 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2895 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
2896 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2897 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
2898 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2899 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
2900 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2901 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
2902 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2903 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
2904 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2905 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
2906 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2907 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
2908 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2910 // match select on i1 variables:
2911 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
2912 (CROR (CRAND $cond , $tval),
2913 (CRAND (crnot $cond), $fval))>;
2915 // match selectcc on i1 variables:
2916 // select (lhs == rhs), tval, fval is:
2917 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
2918 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
2919 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
2920 (CRAND (CRORC $lhs, $rhs), $fval))>;
2921 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
2922 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
2923 (CRAND (CRANDC $lhs, $rhs), $fval))>;
2924 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
2925 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
2926 (CRAND (CRXOR $lhs, $rhs), $fval))>;
2927 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
2928 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
2929 (CRAND (CRANDC $rhs, $lhs), $fval))>;
2930 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
2931 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
2932 (CRAND (CRORC $rhs, $lhs), $fval))>;
2933 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
2934 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
2935 (CRAND (CRXOR $lhs, $rhs), $tval))>;
2937 // match selectcc on i1 variables with non-i1 output.
2938 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
2939 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
2940 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
2941 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
2942 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
2943 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
2944 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
2945 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
2946 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
2947 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
2948 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
2949 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
2951 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
2952 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
2953 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
2954 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
2955 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
2956 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
2957 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
2958 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
2959 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
2960 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
2961 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
2962 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
2964 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
2965 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
2966 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
2967 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
2968 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
2969 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
2970 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
2971 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
2972 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
2973 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
2974 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
2975 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
2977 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
2978 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
2979 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
2980 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
2981 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
2982 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
2983 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
2984 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
2985 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
2986 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
2987 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
2988 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
2990 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
2991 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
2992 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
2993 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
2994 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
2995 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
2996 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
2997 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
2998 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
2999 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3000 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3001 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3003 let usesCustomInserter = 1 in {
3004 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3006 [(set i1:$dst, (trunc (not i32:$in)))]>;
3007 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3009 [(set i1:$dst, (trunc i32:$in))]>;
3011 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3013 [(set i1:$dst, (trunc (not i64:$in)))]>;
3014 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3016 [(set i1:$dst, (trunc i64:$in))]>;
3019 def : Pat<(i1 (not (trunc i32:$in))),
3020 (ANDIo_1_EQ_BIT $in)>;
3021 def : Pat<(i1 (not (trunc i64:$in))),
3022 (ANDIo_1_EQ_BIT8 $in)>;
3024 //===----------------------------------------------------------------------===//
3025 // PowerPC Instructions used for assembler/disassembler only
3028 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3029 "isync", IIC_SprISYNC, []>;
3031 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3032 "icbi $src", IIC_LdStICBI, []>;
3034 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3035 "eieio", IIC_LdStLoad, []>;
3037 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3038 "wait $L", IIC_LdStLoad, []>;
3040 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3041 "mtmsr $RS, $L", IIC_SprMTMSR>;
3043 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3044 "mfmsr $RT", IIC_SprMFMSR, []>;
3046 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3047 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3049 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3050 "slbie $RB", IIC_SprSLBIE, []>;
3052 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3053 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3055 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3056 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3058 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3060 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3061 "tlbsync", IIC_SprTLBSYNC, []>;
3063 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3064 "tlbiel $RB", IIC_SprTLBIEL, []>;
3066 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3067 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3069 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_BrB, []>;
3071 //===----------------------------------------------------------------------===//
3072 // PowerPC Assembler Instruction Aliases
3075 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3076 // These are aliases that require C++ handling to convert to the target
3077 // instruction, while InstAliases can be handled directly by tblgen.
3078 class PPCAsmPseudo<string asm, dag iops>
3080 let Namespace = "PPC";
3081 bit PPC64 = 0; // Default value, override with isPPC64
3083 let OutOperandList = (outs);
3084 let InOperandList = iops;
3086 let AsmString = asm;
3087 let isAsmParserOnly = 1;
3091 def : InstAlias<"sc", (SC 0)>;
3093 def : InstAlias<"sync", (SYNC 0)>, Requires<[IsNotBookE]>;
3094 def : InstAlias<"msync", (SYNC 0)>, Requires<[IsNotBookE]>;
3095 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[IsNotBookE]>;
3096 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[IsNotBookE]>;
3098 def : InstAlias<"wait", (WAIT 0)>;
3099 def : InstAlias<"waitrsv", (WAIT 1)>;
3100 def : InstAlias<"waitimpl", (WAIT 2)>;
3102 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3103 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3104 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3105 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3107 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3108 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3110 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3111 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3113 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3115 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3116 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3118 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3119 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3121 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3123 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3125 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3126 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3127 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3128 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3129 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3130 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3131 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3132 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3134 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3135 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3136 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3137 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3139 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3140 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3142 def : InstAlias<"mfsprg $RT, 0", (MFSPR gprc:$RT, 272)>;
3143 def : InstAlias<"mfsprg $RT, 1", (MFSPR gprc:$RT, 273)>;
3144 def : InstAlias<"mfsprg $RT, 2", (MFSPR gprc:$RT, 274)>;
3145 def : InstAlias<"mfsprg $RT, 3", (MFSPR gprc:$RT, 275)>;
3147 def : InstAlias<"mfsprg0 $RT", (MFSPR gprc:$RT, 272)>;
3148 def : InstAlias<"mfsprg1 $RT", (MFSPR gprc:$RT, 273)>;
3149 def : InstAlias<"mfsprg2 $RT", (MFSPR gprc:$RT, 274)>;
3150 def : InstAlias<"mfsprg3 $RT", (MFSPR gprc:$RT, 275)>;
3152 def : InstAlias<"mtsprg 0, $RT", (MTSPR 272, gprc:$RT)>;
3153 def : InstAlias<"mtsprg 1, $RT", (MTSPR 273, gprc:$RT)>;
3154 def : InstAlias<"mtsprg 2, $RT", (MTSPR 274, gprc:$RT)>;
3155 def : InstAlias<"mtsprg 3, $RT", (MTSPR 275, gprc:$RT)>;
3157 def : InstAlias<"mtsprg0 $RT", (MTSPR 272, gprc:$RT)>;
3158 def : InstAlias<"mtsprg1 $RT", (MTSPR 273, gprc:$RT)>;
3159 def : InstAlias<"mtsprg2 $RT", (MTSPR 274, gprc:$RT)>;
3160 def : InstAlias<"mtsprg3 $RT", (MTSPR 275, gprc:$RT)>;
3162 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3164 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3165 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3167 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3169 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3170 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3172 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3173 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3174 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3175 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3177 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3179 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3180 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3181 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3182 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3183 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3184 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3185 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3186 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3187 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3188 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3189 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3190 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3191 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3192 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3193 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3194 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3195 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3196 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3197 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3198 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3199 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3200 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3201 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3202 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3203 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3204 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3205 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3206 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3207 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3208 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3209 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3210 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3211 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3212 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3213 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3214 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3216 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3217 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3218 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3219 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3220 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3221 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3223 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3224 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3225 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3226 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3227 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3228 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3229 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3230 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3231 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3232 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3233 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3234 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3235 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3236 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3237 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3238 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3239 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3240 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3241 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3242 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3243 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3244 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3245 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3246 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3247 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3248 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3249 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3250 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3251 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3252 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3253 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3254 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3256 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3257 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3258 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3259 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3260 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3261 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3263 // These generic branch instruction forms are used for the assembler parser only.
3264 // Defs and Uses are conservative, since we don't know the BO value.
3265 let PPC970_Unit = 7 in {
3266 let Defs = [CTR], Uses = [CTR, RM] in {
3267 def gBC : BForm_3<16, 0, 0, (outs),
3268 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3269 "bc $bo, $bi, $dst">;
3270 def gBCA : BForm_3<16, 1, 0, (outs),
3271 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3272 "bca $bo, $bi, $dst">;
3274 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3275 def gBCL : BForm_3<16, 0, 1, (outs),
3276 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3277 "bcl $bo, $bi, $dst">;
3278 def gBCLA : BForm_3<16, 1, 1, (outs),
3279 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3280 "bcla $bo, $bi, $dst">;
3282 let Defs = [CTR], Uses = [CTR, LR, RM] in
3283 def gBCLR : XLForm_2<19, 16, 0, (outs),
3284 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3285 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3286 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3287 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3288 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3289 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3290 let Defs = [CTR], Uses = [CTR, LR, RM] in
3291 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3292 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3293 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3294 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3295 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3296 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3297 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3299 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3300 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3301 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3302 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3304 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3305 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3306 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3307 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3308 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3309 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3310 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3312 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3313 : BranchSimpleMnemonic1<name, pm, bo> {
3314 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3315 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3317 defm : BranchSimpleMnemonic2<"t", "", 12>;
3318 defm : BranchSimpleMnemonic2<"f", "", 4>;
3319 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3320 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3321 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3322 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3323 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3324 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3325 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3326 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3328 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3329 def : InstAlias<"b"#name#pm#" $cc, $dst",
3330 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3331 def : InstAlias<"b"#name#pm#" $dst",
3332 (BCC bibo, CR0, condbrtarget:$dst)>;
3334 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3335 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3336 def : InstAlias<"b"#name#"a"#pm#" $dst",
3337 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3339 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3340 (BCCLR bibo, crrc:$cc)>;
3341 def : InstAlias<"b"#name#"lr"#pm,
3344 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3345 (BCCCTR bibo, crrc:$cc)>;
3346 def : InstAlias<"b"#name#"ctr"#pm,
3347 (BCCCTR bibo, CR0)>;
3349 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3350 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3351 def : InstAlias<"b"#name#"l"#pm#" $dst",
3352 (BCCL bibo, CR0, condbrtarget:$dst)>;
3354 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3355 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3356 def : InstAlias<"b"#name#"la"#pm#" $dst",
3357 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3359 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3360 (BCCLRL bibo, crrc:$cc)>;
3361 def : InstAlias<"b"#name#"lrl"#pm,
3362 (BCCLRL bibo, CR0)>;
3364 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3365 (BCCCTRL bibo, crrc:$cc)>;
3366 def : InstAlias<"b"#name#"ctrl"#pm,
3367 (BCCCTRL bibo, CR0)>;
3369 multiclass BranchExtendedMnemonic<string name, int bibo> {
3370 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3371 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3372 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3374 defm : BranchExtendedMnemonic<"lt", 12>;
3375 defm : BranchExtendedMnemonic<"gt", 44>;
3376 defm : BranchExtendedMnemonic<"eq", 76>;
3377 defm : BranchExtendedMnemonic<"un", 108>;
3378 defm : BranchExtendedMnemonic<"so", 108>;
3379 defm : BranchExtendedMnemonic<"ge", 4>;
3380 defm : BranchExtendedMnemonic<"nl", 4>;
3381 defm : BranchExtendedMnemonic<"le", 36>;
3382 defm : BranchExtendedMnemonic<"ng", 36>;
3383 defm : BranchExtendedMnemonic<"ne", 68>;
3384 defm : BranchExtendedMnemonic<"nu", 100>;
3385 defm : BranchExtendedMnemonic<"ns", 100>;
3387 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3388 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3389 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3390 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3391 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3392 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3393 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3394 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3396 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3397 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3398 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3399 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3400 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3401 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3402 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3403 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3405 multiclass TrapExtendedMnemonic<string name, int to> {
3406 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3407 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3408 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3409 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3411 defm : TrapExtendedMnemonic<"lt", 16>;
3412 defm : TrapExtendedMnemonic<"le", 20>;
3413 defm : TrapExtendedMnemonic<"eq", 4>;
3414 defm : TrapExtendedMnemonic<"ge", 12>;
3415 defm : TrapExtendedMnemonic<"gt", 8>;
3416 defm : TrapExtendedMnemonic<"nl", 12>;
3417 defm : TrapExtendedMnemonic<"ne", 24>;
3418 defm : TrapExtendedMnemonic<"ng", 20>;
3419 defm : TrapExtendedMnemonic<"llt", 2>;
3420 defm : TrapExtendedMnemonic<"lle", 6>;
3421 defm : TrapExtendedMnemonic<"lge", 5>;
3422 defm : TrapExtendedMnemonic<"lgt", 1>;
3423 defm : TrapExtendedMnemonic<"lnl", 5>;
3424 defm : TrapExtendedMnemonic<"lng", 6>;
3425 defm : TrapExtendedMnemonic<"u", 31>;