2 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
4 // The LLVM Compiler Infrastructure
6 // This file was developed by the LLVM research group and is distributed under
7 // the University of Illinois Open Source License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the subset of the 32-bit PowerPC instruction set, as used
12 // by the PowerPC instruction selector.
14 //===----------------------------------------------------------------------===//
16 include "PowerPCInstrFormats.td"
18 let isTerminator = 1 in {
20 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, 0, 0, (ops), "blr">;
21 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, 0, 0, (ops), "bctr">;
24 def u5imm : Operand<i8> {
25 let PrintMethod = "printU5ImmOperand";
27 def u6imm : Operand<i8> {
28 let PrintMethod = "printU6ImmOperand";
30 def s16imm : Operand<i16> {
31 let PrintMethod = "printS16ImmOperand";
33 def u16imm : Operand<i16> {
34 let PrintMethod = "printU16ImmOperand";
36 def target : Operand<i32> {
37 let PrintMethod = "printBranchOperand";
39 def piclabel: Operand<i32> {
40 let PrintMethod = "printPICLabel";
42 def symbolHi: Operand<i32> {
43 let PrintMethod = "printSymbolHi";
45 def symbolLo: Operand<i32> {
46 let PrintMethod = "printSymbolLo";
49 // Pseudo-instructions:
50 def PHI : Pseudo<(ops), "; PHI">;
52 def ADJCALLSTACKDOWN : Pseudo<(ops), "; ADJCALLSTACKDOWN">;
53 def ADJCALLSTACKUP : Pseudo<(ops), "; ADJCALLSTACKUP">;
55 def IMPLICIT_DEF : Pseudo<(ops), "; IMPLICIT_DEF">;
58 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
60 let isBranch = 1, isTerminator = 1 in {
61 def COND_BRANCH : Pseudo<(ops), "; COND_BRANCH">;
62 def B : IForm<18, 0, 0, 0, 0, (ops target:$func), "b $func">;
63 //def BA : IForm<18, 1, 0, 0, 0, (ops target:$func), "ba $func">;
64 def BL : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
65 //def BLA : IForm<18, 1, 1, 0, 0, (ops target:$func), "bla $func">;
67 // FIXME: 4*CR# needs to be added to the BI field!
68 // This will only work for CR0 as it stands now
69 def BLT : BForm_ext<16, 0, 0, 12, 0, 0, 0, (ops CRRC:$crS, target:$block),
71 def BLE : BForm_ext<16, 0, 0, 4, 1, 0, 0, (ops CRRC:$crS, target:$block),
73 def BEQ : BForm_ext<16, 0, 0, 12, 2, 0, 0, (ops CRRC:$crS, target:$block),
75 def BGE : BForm_ext<16, 0, 0, 4, 0, 0, 0, (ops CRRC:$crS, target:$block),
77 def BGT : BForm_ext<16, 0, 0, 12, 1, 0, 0, (ops CRRC:$crS, target:$block),
79 def BNE : BForm_ext<16, 0, 0, 4, 2, 0, 0, (ops CRRC:$crS, target:$block),
83 let isBranch = 1, isTerminator = 1, isCall = 1,
84 // All calls clobber the non-callee saved registers...
85 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
86 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
88 CR0,CR1,CR5,CR6,CR7] in {
89 // Convenient aliases for call instructions
90 def CALLpcrel : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
91 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1, 0, 0, (ops), "bctrl">;
94 // D-Form instructions. Most instructions that perform an operation on a
95 // register and an immediate are of this type.
98 def LBZ : DForm_1<34, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
99 "lbz $rD, $disp($rA)">;
100 def LHA : DForm_1<42, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
101 "lha $rD, $disp($rA)">;
102 def LHZ : DForm_1<40, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
103 "lhz $rD, $disp($rA)">;
104 def LMW : DForm_1<46, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
105 "lmw $rD, $disp($rA)">;
106 def LWZ : DForm_1<32, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
107 "lwz $rD, $disp($rA)">;
108 def LWZU : DForm_1<35, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
109 "lwzu $rD, $disp($rA)">;
111 def ADDI : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
112 "addi $rD, $rA, $imm">;
113 def ADDIC : DForm_2<12, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
114 "addic $rD, $rA, $imm">;
115 def ADDICo : DForm_2<13, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
116 "addic. $rD, $rA, $imm">;
117 def ADDIS : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
118 "addis $rD, $rA, $imm">;
119 def LA : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
120 "la $rD, $sym($rA)">;
121 def LOADHiAddr : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym),
122 "addis $rD, $rA, $sym">;
123 def MULLI : DForm_2< 7, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
124 "mulli $rD, $rA, $imm">;
125 def SUBFIC : DForm_2< 8, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
126 "subfic $rD, $rA, $imm">;
127 def LI : DForm_2_r0<14, 0, 0, (ops GPRC:$rD, s16imm:$imm),
129 def LIS : DForm_2_r0<15, 0, 0, (ops GPRC:$rD, s16imm:$imm),
132 def STMW : DForm_3<47, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
133 "stmw $rS, $disp($rA)">;
134 def STB : DForm_3<38, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
135 "stb $rS, $disp($rA)">;
136 def STH : DForm_3<44, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
137 "sth $rS, $disp($rA)">;
138 def STW : DForm_3<36, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
139 "stw $rS, $disp($rA)">;
140 def STWU : DForm_3<37, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
141 "stwu $rS, $disp($rA)">;
143 def ANDIo : DForm_4<28, 0, 0,
144 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
145 "andi. $dst, $src1, $src2">;
146 def ANDISo : DForm_4<29, 0, 0,
147 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
148 "andis. $dst, $src1, $src2">;
149 def ORI : DForm_4<24, 0, 0,
150 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
151 "ori $dst, $src1, $src2">;
152 def ORIS : DForm_4<25, 0, 0,
153 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
154 "oris $dst, $src1, $src2">;
155 def XORI : DForm_4<26, 0, 0,
156 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
157 "xori $dst, $src1, $src2">;
158 def XORIS : DForm_4<27, 0, 0,
159 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
160 "xoris $dst, $src1, $src2">;
161 def NOP : DForm_4_zero<24, 0, 0, (ops), "nop">;
162 def CMPI : DForm_5<11, 0, 0, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
163 "cmpi $crD, $L, $rA, $imm">;
164 def CMPWI : DForm_5_ext<11, 0, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
165 "cmpwi $crD, $rA, $imm">;
166 def CMPDI : DForm_5_ext<11, 1, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
167 "cmpdi $crD, $rA, $imm">;
168 def CMPLI : DForm_6<10, 0, 0,
169 (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
170 "cmpli $dst, $size, $src1, $src2">;
171 def CMPLWI : DForm_6_ext<10, 0, 0,
172 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
173 "cmplwi $dst, $src1, $src2">;
174 def CMPLDI : DForm_6_ext<10, 1, 0,
175 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
176 "cmpldi $dst, $src1, $src2">;
178 def LFS : DForm_8<48, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
179 "lfs $rD, $disp($rA)">;
180 def LFD : DForm_8<50, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
181 "lfd $rD, $disp($rA)">;
184 def STFS : DForm_9<52, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
185 "stfs $rS, $disp($rA)">;
186 def STFD : DForm_9<54, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
187 "stfd $rS, $disp($rA)">;
190 // DS-Form instructions. Load/Store instructions available in PPC-64
193 def LWA : DSForm_1<58, 2, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
194 "lwa $rT, $DS($rA)">;
195 def LD : DSForm_2<58, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
199 def STD : DSForm_2<62, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
200 "std $rT, $DS($rA)">;
201 def STDU : DSForm_2<62, 1, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
202 "stdu $rT, $DS($rA)">;
205 // X-Form instructions. Most instructions that perform an operation on a
206 // register and another register are of this type.
209 def LBZX : XForm_1<31, 87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
210 "lbzx $dst, $base, $index">;
211 def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
212 "lhax $dst, $base, $index">;
213 def LHZX : XForm_1<31, 279, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
214 "lhzx $dst, $base, $index">;
215 def LWAX : XForm_1<31, 341, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
216 "lwax $dst, $base, $index">;
217 def LWZX : XForm_1<31, 23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
218 "lwzx $dst, $base, $index">;
219 def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
220 "ldx $dst, $base, $index">;
222 def MFCR : XForm_5<31, 19, 0, 0, (ops GPRC:$dst), "mfcr $dst">;
223 def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
224 "and $rA, $rS, $rB">;
225 def ANDC : XForm_6<31, 60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
226 "andc $rA, $rS, $rB">;
227 def EQV : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
228 "eqv $rA, $rS, $rB">;
229 def NAND : XForm_6<31, 476, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
230 "nand $rA, $rS, $rB">;
231 def NOR : XForm_6<31, 124, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
232 "nor $rA, $rS, $rB">;
233 def OR : XForm_6<31, 444, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
235 def ORo : XForm_6<31, 444, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
236 "or. $rA, $rS, $rB">;
237 def ORC : XForm_6<31, 412, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
238 "orc $rA, $rS, $rB">;
239 def SLD : XForm_6<31, 27, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
240 "sld $rA, $rS, $rB">;
241 def SLW : XForm_6<31, 24, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
242 "slw $rA, $rS, $rB">;
243 def SRD : XForm_6<31, 539, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
244 "srd $rA, $rS, $rB">;
245 def SRW : XForm_6<31, 536, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
246 "srw $rA, $rS, $rB">;
247 def SRAD : XForm_6<31, 794, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
248 "srad $rA, $rS, $rB">;
249 def SRAW : XForm_6<31, 792, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
250 "sraw $rA, $rS, $rB">;
251 def XOR : XForm_6<31, 316, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
252 "xor $rA, $rS, $rB">;
254 def STBX : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
255 "stbx $rS, $rA, $rB">;
256 def STHX : XForm_8<31, 407, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
257 "sthx $rS, $rA, $rB">;
258 def STWX : XForm_8<31, 151, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
259 "stwx $rS, $rA, $rB">;
260 def STWUX : XForm_8<31, 183, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
261 "stwux $rS, $rA, $rB">;
262 def STDX : XForm_8<31, 149, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
263 "stdx $rS, $rA, $rB">;
264 def STDUX : XForm_8<31, 181, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
265 "stdux $rS, $rA, $rB">;
267 def SRAWI : XForm_10<31, 824, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
268 "srawi $rA, $rS, $SH">;
269 def CNTLZW : XForm_11<31, 26, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
271 def EXTSB : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
273 def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
275 def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS),
277 def CMP : XForm_16<31, 0, 0, 0,
278 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
279 "cmp $crD, $long, $rA, $rB">;
280 def CMPL : XForm_16<31, 32, 0, 0,
281 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
282 "cmpl $crD, $long, $rA, $rB">;
283 def CMPW : XForm_16_ext<31, 0, 0, 0,
284 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
285 "cmpw $crD, $rA, $rB">;
286 def CMPD : XForm_16_ext<31, 0, 1, 0,
287 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
288 "cmpd $crD, $rA, $rB">;
289 def CMPLW : XForm_16_ext<31, 32, 0, 0,
290 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
291 "cmplw $crD, $rA, $rB">;
292 def CMPLD : XForm_16_ext<31, 32, 1, 0,
293 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
294 "cmpld $crD, $rA, $rB">;
295 def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
296 "fcmpu $crD, $fA, $fB">;
298 def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
299 "lfsx $dst, $base, $index">;
300 def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
301 "lfdx $dst, $base, $index">;
303 def FCFID : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
305 def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
306 "fctidz $frD, $frB">;
307 def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
308 "fctiwz $frD, $frB">;
309 def FMR : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
311 def FNEG : XForm_26<63, 40, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
313 def FRSP : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
316 def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
317 "stfsx $frS, $rA, $rB">;
318 def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
319 "stfdx $frS, $rA, $rB">;
322 // XL-Form instructions. condition register logical ops.
324 def CRAND : XLForm_1<19, 257, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
326 def CRANDC : XLForm_1<19, 129, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
327 "crandc $D, $A, $B">;
328 def CRNOR : XLForm_1<19, 33, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
330 def CROR : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
333 // XFX-Form instructions. Instructions that deal with SPRs
335 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
336 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
337 // which means the SPR value needs to be multiplied by a factor of 32.
338 def MFCTR : XFXForm_1_ext<31, 339, 288, 0, 0, (ops GPRC:$rT), "mfctr $rT">;
339 def MFLR : XFXForm_1_ext<31, 339, 256, 0, 0, (ops GPRC:$rT), "mflr $rT">;
340 def MTCTR : XFXForm_7_ext<31, 467, 288, 0, 0, (ops GPRC:$rS), "mtctr $rS">;
341 def MTLR : XFXForm_7_ext<31, 467, 256, 0, 0, (ops GPRC:$rS), "mtlr $rS">;
344 // XS-Form instructions. Just 'sradi'
346 def SRADI : XSForm_1<31, 413, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
347 "sradi $rA, $rS, $SH">;
349 // XO-Form instructions. Arithmetic instructions that can set overflow bit
351 def ADD : XOForm_1<31, 266, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
352 "add $rT, $rA, $rB">;
353 def ADDC : XOForm_1<31, 10, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
354 "addc $rT, $rA, $rB">;
355 def ADDE : XOForm_1<31, 138, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
356 "adde $rT, $rA, $rB">;
357 def DIVD : XOForm_1<31, 489, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
358 "divd $rT, $rA, $rB">;
359 def DIVDU : XOForm_1<31, 457, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
360 "divdu $rT, $rA, $rB">;
361 def DIVW : XOForm_1<31, 491, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
362 "divw $rT, $rA, $rB">;
363 def DIVWU : XOForm_1<31, 459, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
364 "divwu $rT, $rA, $rB">;
365 def MULHWU : XOForm_1<31, 11, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
366 "mulhwu $rT, $rA, $rB">;
367 def MULLD : XOForm_1<31, 233, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
368 "mulld $rT, $rA, $rB">;
369 def MULLW : XOForm_1<31, 235, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
370 "mullw $rT, $rA, $rB">;
371 def SUBF : XOForm_1<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
372 "subf $rT, $rA, $rB">;
373 def SUBFC : XOForm_1<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
374 "subfc $rT, $rA, $rB">;
375 def SUBFE : XOForm_1<31, 136, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
376 "subfe $rT, $rA, $rB">;
377 def SUB : XOForm_1r<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
378 "sub $rT, $rA, $rB">;
379 def SUBC : XOForm_1r<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
380 "subc $rT, $rA, $rB">;
381 def ADDME : XOForm_3<31, 234, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
383 def ADDZE : XOForm_3<31, 202, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
385 def NEG : XOForm_3<31, 104, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
387 def SUBFZE : XOForm_3<31, 200, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
390 // A-Form instructions. Most of the instructions executed in the FPU are of
393 def FMADD : AForm_1<63, 29, 0, 0, 0,
394 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
395 "fmadd $FRT, $FRA, $FRC, $FRB">;
396 def FSEL : AForm_1<63, 23, 0, 0, 0,
397 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
398 "fsel $FRT, $FRA, $FRC, $FRB">;
399 def FADD : AForm_2<63, 21, 0, 0, 0,
400 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
401 "fadd $FRT, $FRA, $FRB">;
402 def FADDS : AForm_2<59, 21, 0, 0, 0,
403 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
404 "fadds $FRT, $FRA, $FRB">;
405 def FDIV : AForm_2<63, 18, 0, 0, 0,
406 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
407 "fdiv $FRT, $FRA, $FRB">;
408 def FDIVS : AForm_2<59, 18, 0, 0, 0,
409 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
410 "fdivs $FRT, $FRA, $FRB">;
411 def FMUL : AForm_3<63, 25, 0, 0, 0,
412 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
413 "fmul $FRT, $FRA, $FRB">;
414 def FMULS : AForm_3<59, 25, 0, 0, 0,
415 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
416 "fmuls $FRT, $FRA, $FRB">;
417 def FSUB : AForm_2<63, 20, 0, 0, 0,
418 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
419 "fsub $FRT, $FRA, $FRB">;
420 def FSUBS : AForm_2<59, 20, 0, 0, 0,
421 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
422 "fsubs $FRT, $FRA, $FRB">;
424 // M-Form instructions. rotate and mask instructions.
426 let isTwoAddress = 1 in {
427 def RLWIMI : MForm_2<20, 0, 0, 0,
428 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
429 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
431 def RLWINM : MForm_2<21, 0, 0, 0,
432 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
433 "rlwinm $rA, $rS, $SH, $MB, $ME">;
436 // MD-Form instructions. 64 bit rotate instructions.
438 def RLDICL : MDForm_1<30, 0, 0, 1, 0,
439 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
440 "rldicl $rA, $rS, $SH, $MB">;
441 def RLDICR : MDForm_1<30, 1, 0, 1, 0,
442 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
443 "rldicr $rA, $rS, $SH, $ME">;
445 def PowerPCInstrInfo : InstrInfo {
448 let TSFlagsFields = [ "VMX", "PPC64" ];
449 let TSFlagsShifts = [ 0, 1 ];
451 let isLittleEndianEncoding = 1;