2 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
4 // The LLVM Compiler Infrastructure
6 // This file was developed by the LLVM research group and is distributed under
7 // the University of Illinois Open Source License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the subset of the 32-bit PowerPC instruction set, as used
12 // by the PowerPC instruction selector.
14 //===----------------------------------------------------------------------===//
16 include "PowerPCInstrFormats.td"
18 let isTerminator = 1 in {
20 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, 0, 0, (ops), "blr">;
21 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, 0, 0, (ops), "bctr">;
24 def u5imm : Operand<i8> {
25 let PrintMethod = "printU5ImmOperand";
27 def u6imm : Operand<i8> {
28 let PrintMethod = "printU6ImmOperand";
30 def s16imm : Operand<i16> {
31 let PrintMethod = "printS16ImmOperand";
33 def u16imm : Operand<i16> {
34 let PrintMethod = "printU16ImmOperand";
36 def target : Operand<i32> {
37 let PrintMethod = "printBranchOperand";
39 def piclabel: Operand<i32> {
40 let PrintMethod = "printPICLabel";
42 def symbolHi: Operand<i32> {
43 let PrintMethod = "printSymbolHi";
45 def symbolLo: Operand<i32> {
46 let PrintMethod = "printSymbolLo";
49 // Pseudo-instructions:
50 def PHI : Pseudo<(ops), "; PHI">;
52 def ADJCALLSTACKDOWN : Pseudo<(ops), "; ADJCALLSTACKDOWN">;
53 def ADJCALLSTACKUP : Pseudo<(ops), "; ADJCALLSTACKUP">;
55 def IMPLICIT_DEF : Pseudo<(ops), "; IMPLICIT_DEF">;
56 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
58 let isBranch = 1, isTerminator = 1 in {
59 def COND_BRANCH : Pseudo<(ops), "; COND_BRANCH">;
60 def B : IForm<18, 0, 0, 0, 0, (ops target:$func), "b $func">;
61 //def BA : IForm<18, 1, 0, 0, 0, (ops target:$func), "ba $func">;
62 def BL : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
63 //def BLA : IForm<18, 1, 1, 0, 0, (ops target:$func), "bla $func">;
65 // FIXME: 4*CR# needs to be added to the BI field!
66 // This will only work for CR0 as it stands now
67 def BLT : BForm_ext<16, 0, 0, 12, 0, 0, 0, (ops CRRC:$crS, target:$block),
69 def BLE : BForm_ext<16, 0, 0, 4, 1, 0, 0, (ops CRRC:$crS, target:$block),
71 def BEQ : BForm_ext<16, 0, 0, 12, 2, 0, 0, (ops CRRC:$crS, target:$block),
73 def BGE : BForm_ext<16, 0, 0, 4, 0, 0, 0, (ops CRRC:$crS, target:$block),
75 def BGT : BForm_ext<16, 0, 0, 12, 1, 0, 0, (ops CRRC:$crS, target:$block),
77 def BNE : BForm_ext<16, 0, 0, 4, 2, 0, 0, (ops CRRC:$crS, target:$block),
81 let isBranch = 1, isTerminator = 1, isCall = 1,
82 // All calls clobber the non-callee saved registers...
83 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
84 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
86 CR0,CR1,CR5,CR6,CR7] in {
87 // Convenient aliases for call instructions
88 def CALLpcrel : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
89 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1, 0, 0, (ops), "bctrl">;
92 // D-Form instructions. Most instructions that perform an operation on a
93 // register and an immediate are of this type.
96 def LBZ : DForm_1<34, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
97 "lbz $rD, $disp($rA)">;
98 def LHA : DForm_1<42, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
99 "lha $rD, $disp($rA)">;
100 def LHZ : DForm_1<40, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
101 "lhz $rD, $disp($rA)">;
102 def LMW : DForm_1<46, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
103 "lmw $rD, $disp($rA)">;
104 def LWZ : DForm_1<32, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
105 "lwz $rD, $disp($rA)">;
106 def LWZU : DForm_1<35, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
107 "lwzu $rD, $disp($rA)">;
109 def ADDI : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
110 "addi $rD, $rA, $imm">;
111 def ADDIC : DForm_2<12, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
112 "addic $rD, $rA, $imm">;
113 def ADDICo : DForm_2<13, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
114 "addic. $rD, $rA, $imm">;
115 def ADDIS : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
116 "addis $rD, $rA, $imm">;
117 def LA : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
118 "la $rD, $sym($rA)">;
119 def LOADHiAddr : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym),
120 "addis $rD, $rA, $sym">;
121 def MULLI : DForm_2< 7, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
122 "mulli $rD, $rA, $imm">;
123 def SUBFIC : DForm_2< 8, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
124 "subfic $rD, $rA, $imm">;
125 def LI : DForm_2_r0<14, 0, 0, (ops GPRC:$rD, s16imm:$imm),
127 def LIS : DForm_2_r0<15, 0, 0, (ops GPRC:$rD, s16imm:$imm),
130 def STMW : DForm_3<47, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
131 "stmw $rS, $disp($rA)">;
132 def STB : DForm_3<38, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
133 "stb $rS, $disp($rA)">;
134 def STH : DForm_3<44, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
135 "sth $rS, $disp($rA)">;
136 def STW : DForm_3<36, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
137 "stw $rS, $disp($rA)">;
138 def STWU : DForm_3<37, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
139 "stwu $rS, $disp($rA)">;
141 def ANDIo : DForm_4<28, 0, 0,
142 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
143 "andi. $dst, $src1, $src2">;
144 def ANDISo : DForm_4<29, 0, 0,
145 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
146 "andis. $dst, $src1, $src2">;
147 def ORI : DForm_4<24, 0, 0,
148 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
149 "ori $dst, $src1, $src2">;
150 def ORIS : DForm_4<25, 0, 0,
151 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
152 "oris $dst, $src1, $src2">;
153 def XORI : DForm_4<26, 0, 0,
154 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
155 "xori $dst, $src1, $src2">;
156 def XORIS : DForm_4<27, 0, 0,
157 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
158 "xoris $dst, $src1, $src2">;
159 def NOP : DForm_4_zero<24, 0, 0, (ops), "nop">;
160 def CMPI : DForm_5<11, 0, 0, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
161 "cmpi $crD, $L, $rA, $imm">;
162 def CMPWI : DForm_5_ext<11, 0, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
163 "cmpwi $crD, $rA, $imm">;
164 def CMPDI : DForm_5_ext<11, 1, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
165 "cmpdi $crD, $rA, $imm">;
166 def CMPLI : DForm_6<10, 0, 0,
167 (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
168 "cmpli $dst, $size, $src1, $src2">;
169 def CMPLWI : DForm_6_ext<10, 0, 0,
170 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
171 "cmplwi $dst, $src1, $src2">;
172 def CMPLDI : DForm_6_ext<10, 1, 0,
173 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
174 "cmpldi $dst, $src1, $src2">;
176 def LFS : DForm_8<48, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
177 "lfs $rD, $disp($rA)">;
178 def LFD : DForm_8<50, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
179 "lfd $rD, $disp($rA)">;
182 def STFS : DForm_9<52, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
183 "stfs $rS, $disp($rA)">;
184 def STFD : DForm_9<54, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
185 "stfd $rS, $disp($rA)">;
188 // DS-Form instructions. Load/Store instructions available in PPC-64
191 def LWA : DSForm_1<58, 2, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
192 "lwa $rT, $DS($rA)">;
193 def LD : DSForm_2<58, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
197 def STD : DSForm_2<62, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
198 "std $rT, $DS($rA)">;
199 def STDU : DSForm_2<62, 1, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
200 "stdu $rT, $DS($rA)">;
203 // X-Form instructions. Most instructions that perform an operation on a
204 // register and another register are of this type.
207 def LBZX : XForm_1<31, 87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
208 "lbzx $dst, $base, $index">;
209 def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
210 "lhax $dst, $base, $index">;
211 def LHZX : XForm_1<31, 279, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
212 "lhzx $dst, $base, $index">;
213 def LWAX : XForm_1<31, 341, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
214 "lwax $dst, $base, $index">;
215 def LWZX : XForm_1<31, 23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
216 "lwzx $dst, $base, $index">;
217 def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
218 "ldx $dst, $base, $index">;
220 def MFCR : XForm_5<31, 19, 0, 0, (ops GPRC:$dst), "mfcr $dst">;
221 def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
222 "and $rA, $rS, $rB">;
223 def ANDC : XForm_6<31, 60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
224 "andc $rA, $rS, $rB">;
225 def EQV : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
226 "eqv $rA, $rS, $rB">;
227 def NAND : XForm_6<31, 476, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
228 "nand $rA, $rS, $rB">;
229 def NOR : XForm_6<31, 124, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
230 "nor $rA, $rS, $rB">;
231 def OR : XForm_6<31, 444, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
233 def ORo : XForm_6<31, 444, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
234 "or. $rA, $rS, $rB">;
235 def ORC : XForm_6<31, 412, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
236 "orc $rA, $rS, $rB">;
237 def SLD : XForm_6<31, 27, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
238 "sld $rA, $rS, $rB">;
239 def SLW : XForm_6<31, 24, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
240 "slw $rA, $rS, $rB">;
241 def SRD : XForm_6<31, 539, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
242 "srd $rA, $rS, $rB">;
243 def SRW : XForm_6<31, 536, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
244 "srw $rA, $rS, $rB">;
245 def SRAD : XForm_6<31, 794, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
246 "srad $rA, $rS, $rB">;
247 def SRAW : XForm_6<31, 792, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
248 "sraw $rA, $rS, $rB">;
249 def XOR : XForm_6<31, 316, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
250 "xor $rA, $rS, $rB">;
252 def STBX : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
253 "stbx $rS, $rA, $rB">;
254 def STHX : XForm_8<31, 407, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
255 "sthx $rS, $rA, $rB">;
256 def STWX : XForm_8<31, 151, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
257 "stwx $rS, $rA, $rB">;
258 def STWUX : XForm_8<31, 183, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
259 "stwux $rS, $rA, $rB">;
260 def STDX : XForm_8<31, 149, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
261 "stdx $rS, $rA, $rB">;
262 def STDUX : XForm_8<31, 181, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
263 "stdux $rS, $rA, $rB">;
265 def SRAWI : XForm_10<31, 824, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
266 "srawi $rA, $rS, $SH">;
267 def CNTLZW : XForm_11<31, 26, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
269 def EXTSB : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
271 def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
273 def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS),
275 def CMP : XForm_16<31, 0, 0, 0,
276 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
277 "cmp $crD, $long, $rA, $rB">;
278 def CMPL : XForm_16<31, 32, 0, 0,
279 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
280 "cmpl $crD, $long, $rA, $rB">;
281 def CMPW : XForm_16_ext<31, 0, 0, 0,
282 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
283 "cmpw $crD, $rA, $rB">;
284 def CMPD : XForm_16_ext<31, 0, 1, 0,
285 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
286 "cmpd $crD, $rA, $rB">;
287 def CMPLW : XForm_16_ext<31, 32, 0, 0,
288 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
289 "cmplw $crD, $rA, $rB">;
290 def CMPLD : XForm_16_ext<31, 32, 1, 0,
291 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
292 "cmpld $crD, $rA, $rB">;
293 def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
294 "fcmpu $crD, $fA, $fB">;
296 def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
297 "lfsx $dst, $base, $index">;
298 def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
299 "lfdx $dst, $base, $index">;
301 def FCFID : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
303 def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
304 "fctidz $frD, $frB">;
305 def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
306 "fctiwz $frD, $frB">;
307 def FMR : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
309 def FNEG : XForm_26<63, 40, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
311 def FRSP : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
314 def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
315 "stfsx $frS, $rA, $rB">;
316 def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
317 "stfdx $frS, $rA, $rB">;
320 // XL-Form instructions. condition register logical ops.
322 def CRAND : XLForm_1<19, 257, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
324 def CRANDC : XLForm_1<19, 129, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
325 "crandc $D, $A, $B">;
326 def CRNOR : XLForm_1<19, 33, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
328 def CROR : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
331 // XFX-Form instructions. Instructions that deal with SPRs
333 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
334 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
335 // which means the SPR value needs to be multiplied by a factor of 32.
336 def MFCTR : XFXForm_1_ext<31, 339, 288, 0, 0, (ops GPRC:$rT), "mfctr $rT">;
337 def MFLR : XFXForm_1_ext<31, 339, 256, 0, 0, (ops GPRC:$rT), "mflr $rT">;
338 def MTCTR : XFXForm_7_ext<31, 467, 288, 0, 0, (ops GPRC:$rS), "mtctr $rS">;
339 def MTLR : XFXForm_7_ext<31, 467, 256, 0, 0, (ops GPRC:$rS), "mtlr $rS">;
342 // XS-Form instructions. Just 'sradi'
344 def SRADI : XSForm_1<31, 413, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
345 "sradi $rA, $rS, $SH">;
347 // XO-Form instructions. Arithmetic instructions that can set overflow bit
349 def ADD : XOForm_1<31, 266, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
350 "add $rT, $rA, $rB">;
351 def ADDC : XOForm_1<31, 10, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
352 "addc $rT, $rA, $rB">;
353 def ADDE : XOForm_1<31, 138, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
354 "adde $rT, $rA, $rB">;
355 def DIVD : XOForm_1<31, 489, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
356 "divd $rT, $rA, $rB">;
357 def DIVDU : XOForm_1<31, 457, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
358 "divdu $rT, $rA, $rB">;
359 def DIVW : XOForm_1<31, 491, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
360 "divw $rT, $rA, $rB">;
361 def DIVWU : XOForm_1<31, 459, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
362 "divwu $rT, $rA, $rB">;
363 def MULHWU : XOForm_1<31, 11, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
364 "mulhwu $rT, $rA, $rB">;
365 def MULLD : XOForm_1<31, 233, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
366 "mulld $rT, $rA, $rB">;
367 def MULLW : XOForm_1<31, 235, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
368 "mullw $rT, $rA, $rB">;
369 def SUBF : XOForm_1<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
370 "subf $rT, $rA, $rB">;
371 def SUBFC : XOForm_1<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
372 "subfc $rT, $rA, $rB">;
373 def SUBFE : XOForm_1<31, 136, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
374 "subfe $rT, $rA, $rB">;
375 def SUB : XOForm_1r<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
376 "sub $rT, $rA, $rB">;
377 def SUBC : XOForm_1r<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
378 "subc $rT, $rA, $rB">;
379 def ADDME : XOForm_3<31, 234, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
381 def ADDZE : XOForm_3<31, 202, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
383 def NEG : XOForm_3<31, 104, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
385 def SUBFZE : XOForm_3<31, 200, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
388 // A-Form instructions. Most of the instructions executed in the FPU are of
391 def FMADD : AForm_1<63, 29, 0, 0, 0,
392 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
393 "fmadd $FRT, $FRA, $FRC, $FRB">;
394 def FSEL : AForm_1<63, 23, 0, 0, 0,
395 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
396 "fsel $FRT, $FRA, $FRC, $FRB">;
397 def FADD : AForm_2<63, 21, 0, 0, 0,
398 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
399 "fadd $FRT, $FRA, $FRB">;
400 def FADDS : AForm_2<59, 21, 0, 0, 0,
401 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
402 "fadds $FRT, $FRA, $FRB">;
403 def FDIV : AForm_2<63, 18, 0, 0, 0,
404 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
405 "fdiv $FRT, $FRA, $FRB">;
406 def FDIVS : AForm_2<59, 18, 0, 0, 0,
407 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
408 "fdivs $FRT, $FRA, $FRB">;
409 def FMUL : AForm_3<63, 25, 0, 0, 0,
410 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
411 "fmul $FRT, $FRA, $FRB">;
412 def FMULS : AForm_3<59, 25, 0, 0, 0,
413 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
414 "fmuls $FRT, $FRA, $FRB">;
415 def FSUB : AForm_2<63, 20, 0, 0, 0,
416 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
417 "fsub $FRT, $FRA, $FRB">;
418 def FSUBS : AForm_2<59, 20, 0, 0, 0,
419 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
420 "fsubs $FRT, $FRA, $FRB">;
422 // M-Form instructions. rotate and mask instructions.
424 let isTwoAddress = 1 in {
425 def RLWIMI : MForm_2<20, 0, 0, 0,
426 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
427 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
429 def RLWINM : MForm_2<21, 0, 0, 0,
430 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
431 "rlwinm $rA, $rS, $SH, $MB, $ME">;
434 // MD-Form instructions. 64 bit rotate instructions.
436 def RLDICL : MDForm_1<30, 0, 0, 1, 0,
437 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
438 "rldicl $rA, $rS, $SH, $MB">;
439 def RLDICR : MDForm_1<30, 1, 0, 1, 0,
440 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
441 "rldicr $rA, $rS, $SH, $ME">;