1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 2, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
57 //===----------------------------------------------------------------------===//
58 // PowerPC specific DAG Nodes.
61 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
62 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
63 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
64 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
65 [SDNPHasChain, SDNPMayStore]>;
67 // This sequence is used for long double->int conversions. It changes the
68 // bits in the FPSCR which is not modelled.
69 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
71 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
72 [SDNPInGlue, SDNPOutGlue]>;
73 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
74 [SDNPInGlue, SDNPOutGlue]>;
75 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
76 [SDNPInGlue, SDNPOutGlue]>;
77 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
78 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
82 def PPCfsel : SDNode<"PPCISD::FSEL",
83 // Type constraint for fsel.
84 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
85 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
87 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
88 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
89 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
90 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
91 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
93 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
94 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
96 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
97 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
98 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
99 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
100 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
101 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
102 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
103 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
105 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
107 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
109 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
110 // amounts. These nodes are generated by the multi-precision shift code.
111 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
112 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
113 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
115 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
116 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
117 [SDNPHasChain, SDNPMayStore]>;
119 // These are target-independent nodes, but have target-specific formats.
120 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
121 [SDNPHasChain, SDNPOutGlue]>;
122 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
123 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
125 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
126 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
127 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
129 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
132 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
134 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
135 [SDNPHasChain, SDNPSideEffect,
136 SDNPInGlue, SDNPOutGlue]>;
137 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
138 [SDNPHasChain, SDNPSideEffect,
139 SDNPInGlue, SDNPOutGlue]>;
140 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
141 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
142 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
143 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
146 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
147 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
149 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
150 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
152 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
153 SDTypeProfile<1, 1, [SDTCisInt<0>,
155 [SDNPHasChain, SDNPSideEffect]>;
156 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
157 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
158 [SDNPHasChain, SDNPSideEffect]>;
160 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
161 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
163 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
164 [SDNPHasChain, SDNPOptInGlue]>;
166 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
167 [SDNPHasChain, SDNPMayLoad]>;
168 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
169 [SDNPHasChain, SDNPMayStore]>;
171 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
172 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
173 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
174 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
175 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
177 // Instructions to support atomic operations
178 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
179 [SDNPHasChain, SDNPMayLoad]>;
180 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
181 [SDNPHasChain, SDNPMayStore]>;
183 // Instructions to support medium and large code model
184 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
185 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
186 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
189 // Instructions to support dynamic alloca.
190 def SDTDynOp : SDTypeProfile<1, 2, []>;
191 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
193 //===----------------------------------------------------------------------===//
194 // PowerPC specific transformation functions and pattern fragments.
197 def SHL32 : SDNodeXForm<imm, [{
198 // Transformation function: 31 - imm
199 return getI32Imm(31 - N->getZExtValue());
202 def SRL32 : SDNodeXForm<imm, [{
203 // Transformation function: 32 - imm
204 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
207 def LO16 : SDNodeXForm<imm, [{
208 // Transformation function: get the low 16 bits.
209 return getI32Imm((unsigned short)N->getZExtValue());
212 def HI16 : SDNodeXForm<imm, [{
213 // Transformation function: shift the immediate value down into the low bits.
214 return getI32Imm((unsigned)N->getZExtValue() >> 16);
217 def HA16 : SDNodeXForm<imm, [{
218 // Transformation function: shift the immediate value down into the low bits.
219 signed int Val = N->getZExtValue();
220 return getI32Imm((Val - (signed short)Val) >> 16);
222 def MB : SDNodeXForm<imm, [{
223 // Transformation function: get the start bit of a mask
225 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
226 return getI32Imm(mb);
229 def ME : SDNodeXForm<imm, [{
230 // Transformation function: get the end bit of a mask
232 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
233 return getI32Imm(me);
235 def maskimm32 : PatLeaf<(imm), [{
236 // maskImm predicate - True if immediate is a run of ones.
238 if (N->getValueType(0) == MVT::i32)
239 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
244 def immSExt16 : PatLeaf<(imm), [{
245 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
246 // field. Used by instructions like 'addi'.
247 if (N->getValueType(0) == MVT::i32)
248 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
250 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
252 def immZExt16 : PatLeaf<(imm), [{
253 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
254 // field. Used by instructions like 'ori'.
255 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
258 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
259 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
260 // identical in 32-bit mode, but in 64-bit mode, they return true if the
261 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
263 def imm16ShiftedZExt : PatLeaf<(imm), [{
264 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
265 // immediate are set. Used by instructions like 'xoris'.
266 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
269 def imm16ShiftedSExt : PatLeaf<(imm), [{
270 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
271 // immediate are set. Used by instructions like 'addis'. Identical to
272 // imm16ShiftedZExt in 32-bit mode.
273 if (N->getZExtValue() & 0xFFFF) return false;
274 if (N->getValueType(0) == MVT::i32)
276 // For 64-bit, make sure it is sext right.
277 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
280 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
281 // restricted memrix (offset/4) constants are alignment sensitive. If these
282 // offsets are hidden behind TOC entries than the values of the lower-order
283 // bits cannot be checked directly. As a result, we need to also incorporate
284 // an alignment check into the relevant patterns.
286 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
287 return cast<LoadSDNode>(N)->getAlignment() >= 4;
289 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
290 (store node:$val, node:$ptr), [{
291 return cast<StoreSDNode>(N)->getAlignment() >= 4;
293 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
294 return cast<LoadSDNode>(N)->getAlignment() >= 4;
296 def aligned4pre_store : PatFrag<
297 (ops node:$val, node:$base, node:$offset),
298 (pre_store node:$val, node:$base, node:$offset), [{
299 return cast<StoreSDNode>(N)->getAlignment() >= 4;
302 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
303 return cast<LoadSDNode>(N)->getAlignment() < 4;
305 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
306 (store node:$val, node:$ptr), [{
307 return cast<StoreSDNode>(N)->getAlignment() < 4;
309 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
310 return cast<LoadSDNode>(N)->getAlignment() < 4;
313 //===----------------------------------------------------------------------===//
314 // PowerPC Flag Definitions.
316 class isPPC64 { bit PPC64 = 1; }
318 list<Register> Defs = [CR0];
322 class RegConstraint<string C> {
323 string Constraints = C;
325 class NoEncode<string E> {
326 string DisableEncoding = E;
330 //===----------------------------------------------------------------------===//
331 // PowerPC Operand Definitions.
333 def s5imm : Operand<i32> {
334 let PrintMethod = "printS5ImmOperand";
336 def u5imm : Operand<i32> {
337 let PrintMethod = "printU5ImmOperand";
339 def u6imm : Operand<i32> {
340 let PrintMethod = "printU6ImmOperand";
342 def s16imm : Operand<i32> {
343 let PrintMethod = "printS16ImmOperand";
345 def u16imm : Operand<i32> {
346 let PrintMethod = "printU16ImmOperand";
348 def directbrtarget : Operand<OtherVT> {
349 let PrintMethod = "printBranchOperand";
350 let EncoderMethod = "getDirectBrEncoding";
352 def condbrtarget : Operand<OtherVT> {
353 let PrintMethod = "printBranchOperand";
354 let EncoderMethod = "getCondBrEncoding";
356 def calltarget : Operand<iPTR> {
357 let EncoderMethod = "getDirectBrEncoding";
359 def aaddr : Operand<iPTR> {
360 let PrintMethod = "printAbsAddrOperand";
362 def symbolHi: Operand<i32> {
363 let PrintMethod = "printSymbolHi";
364 let EncoderMethod = "getHA16Encoding";
366 def symbolLo: Operand<i32> {
367 let PrintMethod = "printSymbolLo";
368 let EncoderMethod = "getLO16Encoding";
370 def crbitm: Operand<i8> {
371 let PrintMethod = "printcrbitm";
372 let EncoderMethod = "get_crbitm_encoding";
375 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
376 def ptr_rc_nor0 : PointerLikeRegClass<1>;
378 def memri : Operand<iPTR> {
379 let PrintMethod = "printMemRegImm";
380 let MIOperandInfo = (ops symbolLo:$imm, ptr_rc_nor0:$reg);
381 let EncoderMethod = "getMemRIEncoding";
383 def memrr : Operand<iPTR> {
384 let PrintMethod = "printMemRegReg";
385 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc:$offreg);
387 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
388 let PrintMethod = "printMemRegImmShifted";
389 let MIOperandInfo = (ops symbolLo:$imm, ptr_rc_nor0:$reg);
390 let EncoderMethod = "getMemRIXEncoding";
393 // A single-register address. This is used with the SjLj
394 // pseudo-instructions.
395 def memr : Operand<iPTR> {
396 let MIOperandInfo = (ops ptr_rc:$ptrreg);
399 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
400 // that doesn't matter.
401 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
402 (ops (i32 20), (i32 zero_reg))> {
403 let PrintMethod = "printPredicateOperand";
406 // Define PowerPC specific addressing mode.
407 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
408 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
409 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
410 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
412 // The address in a single register. This is used with the SjLj
413 // pseudo-instructions.
414 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
416 /// This is just the offset part of iaddr, used for preinc.
417 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
419 //===----------------------------------------------------------------------===//
420 // PowerPC Instruction Predicate Definitions.
421 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
422 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
423 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
425 //===----------------------------------------------------------------------===//
426 // PowerPC Instruction Definitions.
428 // Pseudo-instructions:
430 let hasCtrlDep = 1 in {
431 let Defs = [R1], Uses = [R1] in {
432 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
433 [(callseq_start timm:$amt)]>;
434 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
435 [(callseq_end timm:$amt1, timm:$amt2)]>;
438 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
439 "UPDATE_VRSAVE $rD, $rS", []>;
442 let Defs = [R1], Uses = [R1] in
443 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "#DYNALLOC",
445 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
447 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
448 // instruction selection into a branch sequence.
449 let usesCustomInserter = 1, // Expanded after instruction selection.
450 PPC970_Single = 1 in {
451 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
452 i32imm:$BROPC), "#SELECT_CC_I4",
454 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
455 i32imm:$BROPC), "#SELECT_CC_I8",
457 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
458 i32imm:$BROPC), "#SELECT_CC_F4",
460 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
461 i32imm:$BROPC), "#SELECT_CC_F8",
463 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
464 i32imm:$BROPC), "#SELECT_CC_VRRC",
468 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
469 // scavenge a register for it.
471 def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
474 // RESTORE_CR - Indicate that we're restoring the CR register (previously
475 // spilled), so we'll need to scavenge a register for it.
477 def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
480 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
481 let isCodeGenOnly = 1, isReturn = 1, Uses = [LR, RM] in
482 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
483 "b${p:cc}lr ${p:reg}", BrB,
485 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
486 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
490 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
493 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
494 let isBarrier = 1 in {
495 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
500 // BCC represents an arbitrary conditional branch on a predicate.
501 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
502 // a two-value operand where a dag node expects two operands. :(
503 let isCodeGenOnly = 1 in
504 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
505 "b${cond:cc} ${cond:reg}, $dst"
506 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
508 let Defs = [CTR], Uses = [CTR] in {
509 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
511 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
516 // The direct BCL used by the SjLj setjmp code.
517 let isCall = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
518 let Defs = [LR], Uses = [RM] in {
519 def BCL : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
524 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
525 // Convenient aliases for call instructions
527 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
528 "bl $func", BrB, []>; // See Pat patterns below.
529 def BLA : IForm<18, 1, 1, (outs), (ins aaddr:$func),
530 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
532 let Uses = [CTR, RM] in {
533 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
534 "bctrl", BrB, [(PPCbctrl)]>,
535 Requires<[In32BitMode]>;
539 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
540 def TCRETURNdi :Pseudo< (outs),
541 (ins calltarget:$dst, i32imm:$offset),
542 "#TC_RETURNd $dst $offset",
546 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
547 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
548 "#TC_RETURNa $func $offset",
549 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
551 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
552 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
553 "#TC_RETURNr $dst $offset",
557 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
558 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
559 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
560 Requires<[In32BitMode]>;
564 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
565 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
566 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
571 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
572 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
573 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
577 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
578 usesCustomInserter = 1 in {
579 def EH_SjLj_SetJmp32 : Pseudo<(outs GPRC:$dst), (ins memr:$buf),
581 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
582 Requires<[In32BitMode]>;
583 let isTerminator = 1 in
584 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
585 "#EH_SJLJ_LONGJMP32",
586 [(PPCeh_sjlj_longjmp addr:$buf)]>,
587 Requires<[In32BitMode]>;
590 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
591 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
592 "#EH_SjLj_Setup\t$dst", []>;
595 // DCB* instructions.
596 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
597 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
598 PPC970_DGroup_Single;
599 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
600 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
601 PPC970_DGroup_Single;
602 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
603 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
604 PPC970_DGroup_Single;
605 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
606 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
607 PPC970_DGroup_Single;
608 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
609 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
610 PPC970_DGroup_Single;
611 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
612 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
613 PPC970_DGroup_Single;
614 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
615 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
616 PPC970_DGroup_Single;
617 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
618 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
619 PPC970_DGroup_Single;
621 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
625 let usesCustomInserter = 1 in {
626 let Defs = [CR0] in {
627 def ATOMIC_LOAD_ADD_I8 : Pseudo<
628 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I8",
629 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
630 def ATOMIC_LOAD_SUB_I8 : Pseudo<
631 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I8",
632 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
633 def ATOMIC_LOAD_AND_I8 : Pseudo<
634 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I8",
635 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
636 def ATOMIC_LOAD_OR_I8 : Pseudo<
637 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I8",
638 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
639 def ATOMIC_LOAD_XOR_I8 : Pseudo<
640 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "ATOMIC_LOAD_XOR_I8",
641 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
642 def ATOMIC_LOAD_NAND_I8 : Pseudo<
643 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I8",
644 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
645 def ATOMIC_LOAD_ADD_I16 : Pseudo<
646 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I16",
647 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
648 def ATOMIC_LOAD_SUB_I16 : Pseudo<
649 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I16",
650 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
651 def ATOMIC_LOAD_AND_I16 : Pseudo<
652 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I16",
653 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
654 def ATOMIC_LOAD_OR_I16 : Pseudo<
655 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I16",
656 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
657 def ATOMIC_LOAD_XOR_I16 : Pseudo<
658 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I16",
659 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
660 def ATOMIC_LOAD_NAND_I16 : Pseudo<
661 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I16",
662 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
663 def ATOMIC_LOAD_ADD_I32 : Pseudo<
664 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I32",
665 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
666 def ATOMIC_LOAD_SUB_I32 : Pseudo<
667 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I32",
668 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
669 def ATOMIC_LOAD_AND_I32 : Pseudo<
670 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I32",
671 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
672 def ATOMIC_LOAD_OR_I32 : Pseudo<
673 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I32",
674 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
675 def ATOMIC_LOAD_XOR_I32 : Pseudo<
676 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I32",
677 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
678 def ATOMIC_LOAD_NAND_I32 : Pseudo<
679 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I32",
680 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
682 def ATOMIC_CMP_SWAP_I8 : Pseudo<
683 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I8",
684 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
685 def ATOMIC_CMP_SWAP_I16 : Pseudo<
686 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
687 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
688 def ATOMIC_CMP_SWAP_I32 : Pseudo<
689 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
690 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
692 def ATOMIC_SWAP_I8 : Pseudo<
693 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_i8",
694 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
695 def ATOMIC_SWAP_I16 : Pseudo<
696 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I16",
697 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
698 def ATOMIC_SWAP_I32 : Pseudo<
699 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I32",
700 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
704 // Instructions to support atomic operations
705 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
706 "lwarx $rD, $src", LdStLWARX,
707 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
710 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
711 "stwcx. $rS, $dst", LdStSTWCX,
712 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
715 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
716 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
718 //===----------------------------------------------------------------------===//
719 // PPC32 Load Instructions.
722 // Unindexed (r+i) Loads.
723 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
724 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
725 "lbz $rD, $src", LdStLoad,
726 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
727 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
728 "lha $rD, $src", LdStLHA,
729 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
730 PPC970_DGroup_Cracked;
731 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
732 "lhz $rD, $src", LdStLoad,
733 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
734 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
735 "lwz $rD, $src", LdStLoad,
736 [(set i32:$rD, (load iaddr:$src))]>;
738 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
739 "lfs $rD, $src", LdStLFD,
740 [(set f32:$rD, (load iaddr:$src))]>;
741 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
742 "lfd $rD, $src", LdStLFD,
743 [(set f64:$rD, (load iaddr:$src))]>;
746 // Unindexed (r+i) Loads with Update (preinc).
748 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
749 "lbzu $rD, $addr", LdStLoadUpd,
750 []>, RegConstraint<"$addr.reg = $ea_result">,
751 NoEncode<"$ea_result">;
753 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
754 "lhau $rD, $addr", LdStLHAU,
755 []>, RegConstraint<"$addr.reg = $ea_result">,
756 NoEncode<"$ea_result">;
758 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
759 "lhzu $rD, $addr", LdStLoadUpd,
760 []>, RegConstraint<"$addr.reg = $ea_result">,
761 NoEncode<"$ea_result">;
763 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
764 "lwzu $rD, $addr", LdStLoadUpd,
765 []>, RegConstraint<"$addr.reg = $ea_result">,
766 NoEncode<"$ea_result">;
768 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
769 "lfsu $rD, $addr", LdStLFDU,
770 []>, RegConstraint<"$addr.reg = $ea_result">,
771 NoEncode<"$ea_result">;
773 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
774 "lfdu $rD, $addr", LdStLFDU,
775 []>, RegConstraint<"$addr.reg = $ea_result">,
776 NoEncode<"$ea_result">;
779 // Indexed (r+r) Loads with Update (preinc).
780 def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
782 "lbzux $rD, $addr", LdStLoadUpd,
783 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
784 NoEncode<"$ea_result">;
786 def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
788 "lhaux $rD, $addr", LdStLHAU,
789 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
790 NoEncode<"$ea_result">;
792 def LHZUX : XForm_1<31, 311, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
794 "lhzux $rD, $addr", LdStLoadUpd,
795 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
796 NoEncode<"$ea_result">;
798 def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
800 "lwzux $rD, $addr", LdStLoadUpd,
801 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
802 NoEncode<"$ea_result">;
804 def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc_nor0:$ea_result),
806 "lfsux $rD, $addr", LdStLFDU,
807 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
808 NoEncode<"$ea_result">;
810 def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc_nor0:$ea_result),
812 "lfdux $rD, $addr", LdStLFDU,
813 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
814 NoEncode<"$ea_result">;
818 // Indexed (r+r) Loads.
820 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
821 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
822 "lbzx $rD, $src", LdStLoad,
823 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
824 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
825 "lhax $rD, $src", LdStLHA,
826 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
827 PPC970_DGroup_Cracked;
828 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
829 "lhzx $rD, $src", LdStLoad,
830 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
831 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
832 "lwzx $rD, $src", LdStLoad,
833 [(set i32:$rD, (load xaddr:$src))]>;
836 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
837 "lhbrx $rD, $src", LdStLoad,
838 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
839 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
840 "lwbrx $rD, $src", LdStLoad,
841 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
843 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
844 "lfsx $frD, $src", LdStLFD,
845 [(set f32:$frD, (load xaddr:$src))]>;
846 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
847 "lfdx $frD, $src", LdStLFD,
848 [(set f64:$frD, (load xaddr:$src))]>;
851 //===----------------------------------------------------------------------===//
852 // PPC32 Store Instructions.
855 // Unindexed (r+i) Stores.
856 let PPC970_Unit = 2 in {
857 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
858 "stb $rS, $src", LdStStore,
859 [(truncstorei8 i32:$rS, iaddr:$src)]>;
860 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
861 "sth $rS, $src", LdStStore,
862 [(truncstorei16 i32:$rS, iaddr:$src)]>;
863 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
864 "stw $rS, $src", LdStStore,
865 [(store i32:$rS, iaddr:$src)]>;
866 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
867 "stfs $rS, $dst", LdStSTFD,
868 [(store f32:$rS, iaddr:$dst)]>;
869 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
870 "stfd $rS, $dst", LdStSTFD,
871 [(store f64:$rS, iaddr:$dst)]>;
874 // Unindexed (r+i) Stores with Update (preinc).
875 let PPC970_Unit = 2, mayStore = 1 in {
876 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
877 "stbu $rS, $dst", LdStStoreUpd, []>,
878 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
879 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
880 "sthu $rS, $dst", LdStStoreUpd, []>,
881 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
882 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
883 "stwu $rS, $dst", LdStStoreUpd, []>,
884 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
885 def STFSU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memri:$dst),
886 "stfsu $rS, $dst", LdStSTFDU, []>,
887 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
888 def STFDU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memri:$dst),
889 "stfdu $rS, $dst", LdStSTFDU, []>,
890 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
893 // Patterns to match the pre-inc stores. We can't put the patterns on
894 // the instruction definitions directly as ISel wants the address base
895 // and offset to be separate operands, not a single complex operand.
896 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
897 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
898 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
899 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
900 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
901 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
902 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
903 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
904 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
905 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
907 // Indexed (r+r) Stores.
908 let PPC970_Unit = 2 in {
909 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
910 "stbx $rS, $dst", LdStStore,
911 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
912 PPC970_DGroup_Cracked;
913 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
914 "sthx $rS, $dst", LdStStore,
915 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
916 PPC970_DGroup_Cracked;
917 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
918 "stwx $rS, $dst", LdStStore,
919 [(store i32:$rS, xaddr:$dst)]>,
920 PPC970_DGroup_Cracked;
922 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
923 "sthbrx $rS, $dst", LdStStore,
924 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
925 PPC970_DGroup_Cracked;
926 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
927 "stwbrx $rS, $dst", LdStStore,
928 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
929 PPC970_DGroup_Cracked;
931 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
932 "stfiwx $frS, $dst", LdStSTFD,
933 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
935 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
936 "stfsx $frS, $dst", LdStSTFD,
937 [(store f32:$frS, xaddr:$dst)]>;
938 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
939 "stfdx $frS, $dst", LdStSTFD,
940 [(store f64:$frS, xaddr:$dst)]>;
943 // Indexed (r+r) Stores with Update (preinc).
944 let PPC970_Unit = 2, mayStore = 1 in {
945 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
946 "stbux $rS, $dst", LdStStoreUpd, []>,
947 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
948 PPC970_DGroup_Cracked;
949 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
950 "sthux $rS, $dst", LdStStoreUpd, []>,
951 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
952 PPC970_DGroup_Cracked;
953 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
954 "stwux $rS, $dst", LdStStoreUpd, []>,
955 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
956 PPC970_DGroup_Cracked;
957 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memrr:$dst),
958 "stfsux $rS, $dst", LdStSTFDU, []>,
959 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
960 PPC970_DGroup_Cracked;
961 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memrr:$dst),
962 "stfdux $rS, $dst", LdStSTFDU, []>,
963 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
964 PPC970_DGroup_Cracked;
967 // Patterns to match the pre-inc stores. We can't put the patterns on
968 // the instruction definitions directly as ISel wants the address base
969 // and offset to be separate operands, not a single complex operand.
970 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
971 (STBUX $rS, $ptrreg, $ptroff)>;
972 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
973 (STHUX $rS, $ptrreg, $ptroff)>;
974 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
975 (STWUX $rS, $ptrreg, $ptroff)>;
976 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
977 (STFSUX $rS, $ptrreg, $ptroff)>;
978 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
979 (STFDUX $rS, $ptrreg, $ptroff)>;
981 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
985 //===----------------------------------------------------------------------===//
986 // PPC32 Arithmetic Instructions.
989 let PPC970_Unit = 1 in { // FXU Operations.
990 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, s16imm:$imm),
991 "addi $rD, $rA, $imm", IntSimple,
992 [(set i32:$rD, (add i32:$rA, immSExt16:$imm))]>;
993 def ADDIL : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$imm),
994 "addi $rD, $rA, $imm", IntSimple,
995 [(set i32:$rD, (add i32:$rA, immSExt16:$imm))]>;
996 let Defs = [CARRY] in {
997 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
998 "addic $rD, $rA, $imm", IntGeneral,
999 [(set i32:$rD, (addc i32:$rA, immSExt16:$imm))]>,
1000 PPC970_DGroup_Cracked;
1001 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1002 "addic. $rD, $rA, $imm", IntGeneral,
1005 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolHi:$imm),
1006 "addis $rD, $rA, $imm", IntSimple,
1007 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1008 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$sym),
1009 "la $rD, $sym($rA)", IntGeneral,
1010 [(set i32:$rD, (add i32:$rA,
1011 (PPClo tglobaladdr:$sym, 0)))]>;
1012 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1013 "mulli $rD, $rA, $imm", IntMulLI,
1014 [(set i32:$rD, (mul i32:$rA, immSExt16:$imm))]>;
1015 let Defs = [CARRY] in {
1016 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1017 "subfic $rD, $rA, $imm", IntGeneral,
1018 [(set i32:$rD, (subc immSExt16:$imm, i32:$rA))]>;
1021 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1022 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
1023 "li $rD, $imm", IntSimple,
1024 [(set i32:$rD, immSExt16:$imm)]>;
1025 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
1026 "lis $rD, $imm", IntSimple,
1027 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1031 let PPC970_Unit = 1 in { // FXU Operations.
1032 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1033 "andi. $dst, $src1, $src2", IntGeneral,
1034 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1036 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1037 "andis. $dst, $src1, $src2", IntGeneral,
1038 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1040 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1041 "ori $dst, $src1, $src2", IntSimple,
1042 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1043 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1044 "oris $dst, $src1, $src2", IntSimple,
1045 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1046 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1047 "xori $dst, $src1, $src2", IntSimple,
1048 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1049 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1050 "xoris $dst, $src1, $src2", IntSimple,
1051 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1052 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1054 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
1055 "cmpwi $crD, $rA, $imm", IntCompare>;
1056 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1057 "cmplwi $dst, $src1, $src2", IntCompare>;
1061 let PPC970_Unit = 1 in { // FXU Operations.
1062 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1063 "nand $rA, $rS, $rB", IntSimple,
1064 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1065 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1066 "and $rA, $rS, $rB", IntSimple,
1067 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1068 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1069 "andc $rA, $rS, $rB", IntSimple,
1070 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1071 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1072 "or $rA, $rS, $rB", IntSimple,
1073 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1074 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1075 "nor $rA, $rS, $rB", IntSimple,
1076 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1077 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1078 "orc $rA, $rS, $rB", IntSimple,
1079 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1080 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1081 "eqv $rA, $rS, $rB", IntSimple,
1082 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1083 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1084 "xor $rA, $rS, $rB", IntSimple,
1085 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1086 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1087 "slw $rA, $rS, $rB", IntGeneral,
1088 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1089 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1090 "srw $rA, $rS, $rB", IntGeneral,
1091 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1092 let Defs = [CARRY] in {
1093 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1094 "sraw $rA, $rS, $rB", IntShift,
1095 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1099 let PPC970_Unit = 1 in { // FXU Operations.
1100 let Defs = [CARRY] in {
1101 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
1102 "srawi $rA, $rS, $SH", IntShift,
1103 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1105 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
1106 "cntlzw $rA, $rS", IntGeneral,
1107 [(set i32:$rA, (ctlz i32:$rS))]>;
1108 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
1109 "extsb $rA, $rS", IntSimple,
1110 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1111 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
1112 "extsh $rA, $rS", IntSimple,
1113 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1115 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1116 "cmpw $crD, $rA, $rB", IntCompare>;
1117 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1118 "cmplw $crD, $rA, $rB", IntCompare>;
1120 let PPC970_Unit = 3 in { // FPU Operations.
1121 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1122 // "fcmpo $crD, $fA, $fB", FPCompare>;
1123 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
1124 "fcmpu $crD, $fA, $fB", FPCompare>;
1125 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
1126 "fcmpu $crD, $fA, $fB", FPCompare>;
1128 let Uses = [RM] in {
1129 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
1130 "fctiwz $frD, $frB", FPGeneral,
1131 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1132 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
1133 "frsp $frD, $frB", FPGeneral,
1134 [(set f32:$frD, (fround f64:$frB))]>;
1135 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1136 "fsqrt $frD, $frB", FPSqrt,
1137 [(set f64:$frD, (fsqrt f64:$frB))]>;
1138 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1139 "fsqrts $frD, $frB", FPSqrt,
1140 [(set f32:$frD, (fsqrt f32:$frB))]>;
1144 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1145 /// often coalesced away and we don't want the dispatch group builder to think
1146 /// that they will fill slots (which could cause the load of a LSU reject to
1147 /// sneak into a d-group with a store).
1148 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1149 "fmr $frD, $frB", FPGeneral,
1150 []>, // (set f32:$frD, f32:$frB)
1153 let PPC970_Unit = 3 in { // FPU Operations.
1154 // These are artificially split into two different forms, for 4/8 byte FP.
1155 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1156 "fabs $frD, $frB", FPGeneral,
1157 [(set f32:$frD, (fabs f32:$frB))]>;
1158 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1159 "fabs $frD, $frB", FPGeneral,
1160 [(set f64:$frD, (fabs f64:$frB))]>;
1161 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1162 "fnabs $frD, $frB", FPGeneral,
1163 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1164 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1165 "fnabs $frD, $frB", FPGeneral,
1166 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1167 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1168 "fneg $frD, $frB", FPGeneral,
1169 [(set f32:$frD, (fneg f32:$frB))]>;
1170 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1171 "fneg $frD, $frB", FPGeneral,
1172 [(set f64:$frD, (fneg f64:$frB))]>;
1176 // XL-Form instructions. condition register logical ops.
1178 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1179 "mcrf $BF, $BFA", BrMCR>,
1180 PPC970_DGroup_First, PPC970_Unit_CRU;
1182 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1183 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1184 "creqv $CRD, $CRA, $CRB", BrCR,
1187 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1188 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1189 "cror $CRD, $CRA, $CRB", BrCR,
1192 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1193 "creqv $dst, $dst, $dst", BrCR,
1196 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins),
1197 "crxor $dst, $dst, $dst", BrCR,
1200 let Defs = [CR1EQ], CRD = 6 in {
1201 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1202 "creqv 6, 6, 6", BrCR,
1205 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1206 "crxor 6, 6, 6", BrCR,
1210 // XFX-Form instructions. Instructions that deal with SPRs.
1212 let Uses = [CTR] in {
1213 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1214 "mfctr $rT", SprMFSPR>,
1215 PPC970_DGroup_First, PPC970_Unit_FXU;
1217 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1218 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1219 "mtctr $rS", SprMTSPR>,
1220 PPC970_DGroup_First, PPC970_Unit_FXU;
1223 let Defs = [LR] in {
1224 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1225 "mtlr $rS", SprMTSPR>,
1226 PPC970_DGroup_First, PPC970_Unit_FXU;
1228 let Uses = [LR] in {
1229 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1230 "mflr $rT", SprMFSPR>,
1231 PPC970_DGroup_First, PPC970_Unit_FXU;
1234 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1235 // a GPR on the PPC970. As such, copies in and out have the same performance
1236 // characteristics as an OR instruction.
1237 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1238 "mtspr 256, $rS", IntGeneral>,
1239 PPC970_DGroup_Single, PPC970_Unit_FXU;
1240 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1241 "mfspr $rT, 256", IntGeneral>,
1242 PPC970_DGroup_First, PPC970_Unit_FXU;
1244 let isCodeGenOnly = 1 in {
1245 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1246 (outs VRSAVERC:$reg), (ins GPRC:$rS),
1247 "mtspr 256, $rS", IntGeneral>,
1248 PPC970_DGroup_Single, PPC970_Unit_FXU;
1249 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT),
1250 (ins VRSAVERC:$reg),
1251 "mfspr $rT, 256", IntGeneral>,
1252 PPC970_DGroup_First, PPC970_Unit_FXU;
1255 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1256 // so we'll need to scavenge a register for it.
1258 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1259 "#SPILL_VRSAVE", []>;
1261 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1262 // spilled), so we'll need to scavenge a register for it.
1264 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1265 "#RESTORE_VRSAVE", []>;
1267 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
1268 "mtcrf $FXM, $rS", BrMCRX>,
1269 PPC970_MicroCode, PPC970_Unit_CRU;
1271 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1272 // declaring that here gives the local register allocator problems with this:
1274 // MFCR <kill of whatever preg got assigned to vreg>
1275 // while not declaring it breaks DeadMachineInstructionElimination.
1276 // As it turns out, in all cases where we currently use this,
1277 // we're only interested in one subregister of it. Represent this in the
1278 // instruction to keep the register allocator from becoming confused.
1280 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1281 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1282 "#MFCRpseud", SprMFCR>,
1283 PPC970_MicroCode, PPC970_Unit_CRU;
1285 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1286 "mfcr $rT", SprMFCR>,
1287 PPC970_MicroCode, PPC970_Unit_CRU;
1289 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1290 "mfocrf $rT, $FXM", SprMFCR>,
1291 PPC970_DGroup_First, PPC970_Unit_CRU;
1293 // Instructions to manipulate FPSCR. Only long double handling uses these.
1294 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1296 let Uses = [RM], Defs = [RM] in {
1297 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1298 "mtfsb0 $FM", IntMTFSB0,
1299 [(PPCmtfsb0 (i32 imm:$FM))]>,
1300 PPC970_DGroup_Single, PPC970_Unit_FPU;
1301 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1302 "mtfsb1 $FM", IntMTFSB0,
1303 [(PPCmtfsb1 (i32 imm:$FM))]>,
1304 PPC970_DGroup_Single, PPC970_Unit_FPU;
1305 // MTFSF does not actually produce an FP result. We pretend it copies
1306 // input reg B to the output. If we didn't do this it would look like the
1307 // instruction had no outputs (because we aren't modelling the FPSCR) and
1308 // it would be deleted.
1309 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1310 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1311 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1312 [(set f64:$FRA, (PPCmtfsf (i32 imm:$FM),
1313 f64:$rT, f64:$FRB))]>,
1314 PPC970_DGroup_Single, PPC970_Unit_FPU;
1316 let Uses = [RM] in {
1317 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1318 "mffs $rT", IntMFFS,
1319 [(set f64:$rT, (PPCmffs))]>,
1320 PPC970_DGroup_Single, PPC970_Unit_FPU;
1321 def FADDrtz: AForm_2<63, 21,
1322 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1323 "fadd $FRT, $FRA, $FRB", FPAddSub,
1324 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>,
1325 PPC970_DGroup_Single, PPC970_Unit_FPU;
1329 let PPC970_Unit = 1 in { // FXU Operations.
1331 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1333 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1334 "add $rT, $rA, $rB", IntSimple,
1335 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
1336 let Defs = [CARRY] in {
1337 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1338 "addc $rT, $rA, $rB", IntGeneral,
1339 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
1340 PPC970_DGroup_Cracked;
1342 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1343 "divw $rT, $rA, $rB", IntDivW,
1344 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
1345 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1346 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1347 "divwu $rT, $rA, $rB", IntDivW,
1348 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
1349 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1350 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1351 "mulhw $rT, $rA, $rB", IntMulHW,
1352 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
1353 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1354 "mulhwu $rT, $rA, $rB", IntMulHWU,
1355 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
1356 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1357 "mullw $rT, $rA, $rB", IntMulHW,
1358 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
1359 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1360 "subf $rT, $rA, $rB", IntGeneral,
1361 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
1362 let Defs = [CARRY] in {
1363 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1364 "subfc $rT, $rA, $rB", IntGeneral,
1365 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
1366 PPC970_DGroup_Cracked;
1368 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1369 "neg $rT, $rA", IntSimple,
1370 [(set i32:$rT, (ineg i32:$rA))]>;
1371 let Uses = [CARRY], Defs = [CARRY] in {
1372 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1373 "adde $rT, $rA, $rB", IntGeneral,
1374 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
1375 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1376 "addme $rT, $rA", IntGeneral,
1377 [(set i32:$rT, (adde i32:$rA, -1))]>;
1378 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1379 "addze $rT, $rA", IntGeneral,
1380 [(set i32:$rT, (adde i32:$rA, 0))]>;
1381 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1382 "subfe $rT, $rA, $rB", IntGeneral,
1383 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
1384 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1385 "subfme $rT, $rA", IntGeneral,
1386 [(set i32:$rT, (sube -1, i32:$rA))]>;
1387 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1388 "subfze $rT, $rA", IntGeneral,
1389 [(set i32:$rT, (sube 0, i32:$rA))]>;
1393 // A-Form instructions. Most of the instructions executed in the FPU are of
1396 let PPC970_Unit = 3 in { // FPU Operations.
1397 let Uses = [RM] in {
1398 def FMADD : AForm_1<63, 29,
1399 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1400 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1401 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
1402 def FMADDS : AForm_1<59, 29,
1403 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1404 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1405 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
1406 def FMSUB : AForm_1<63, 28,
1407 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1408 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1410 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
1411 def FMSUBS : AForm_1<59, 28,
1412 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1413 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1415 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
1416 def FNMADD : AForm_1<63, 31,
1417 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1418 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1420 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
1421 def FNMADDS : AForm_1<59, 31,
1422 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1423 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1425 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
1426 def FNMSUB : AForm_1<63, 30,
1427 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1428 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1429 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
1430 (fneg f64:$FRB))))]>;
1431 def FNMSUBS : AForm_1<59, 30,
1432 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1433 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1434 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
1435 (fneg f32:$FRB))))]>;
1437 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1438 // having 4 of these, force the comparison to always be an 8-byte double (code
1439 // should use an FMRSD if the input comparison value really wants to be a float)
1440 // and 4/8 byte forms for the result and operand type..
1441 def FSELD : AForm_1<63, 23,
1442 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1443 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1444 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
1445 def FSELS : AForm_1<63, 23,
1446 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1447 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1448 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
1449 let Uses = [RM] in {
1450 def FADD : AForm_2<63, 21,
1451 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1452 "fadd $FRT, $FRA, $FRB", FPAddSub,
1453 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
1454 def FADDS : AForm_2<59, 21,
1455 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1456 "fadds $FRT, $FRA, $FRB", FPGeneral,
1457 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
1458 def FDIV : AForm_2<63, 18,
1459 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1460 "fdiv $FRT, $FRA, $FRB", FPDivD,
1461 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
1462 def FDIVS : AForm_2<59, 18,
1463 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1464 "fdivs $FRT, $FRA, $FRB", FPDivS,
1465 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
1466 def FMUL : AForm_3<63, 25,
1467 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC),
1468 "fmul $FRT, $FRA, $FRC", FPFused,
1469 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
1470 def FMULS : AForm_3<59, 25,
1471 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC),
1472 "fmuls $FRT, $FRA, $FRC", FPGeneral,
1473 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
1474 def FSUB : AForm_2<63, 20,
1475 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1476 "fsub $FRT, $FRA, $FRB", FPAddSub,
1477 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
1478 def FSUBS : AForm_2<59, 20,
1479 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1480 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1481 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
1485 let PPC970_Unit = 1 in { // FXU Operations.
1486 def ISEL : AForm_4<31, 15,
1487 (outs GPRC:$rT), (ins GPRC_NOR0:$rA, GPRC:$rB, pred:$cond),
1488 "isel $rT, $rA, $rB, $cond", IntGeneral,
1492 let PPC970_Unit = 1 in { // FXU Operations.
1493 // M-Form instructions. rotate and mask instructions.
1495 let isCommutable = 1 in {
1496 // RLWIMI can be commuted if the rotate amount is zero.
1497 def RLWIMI : MForm_2<20,
1498 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1499 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1500 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1503 def RLWINM : MForm_2<21,
1504 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1505 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1507 def RLWINMo : MForm_2<21,
1508 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1509 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1510 []>, isDOT, PPC970_DGroup_Cracked;
1511 def RLWNM : MForm_2<23,
1512 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1513 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1518 //===----------------------------------------------------------------------===//
1519 // PowerPC Instruction Patterns
1522 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1523 def : Pat<(i32 imm:$imm),
1524 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1526 // Implement the 'not' operation with the NOR instruction.
1527 def NOT : Pat<(not i32:$in),
1530 // ADD an arbitrary immediate.
1531 def : Pat<(add i32:$in, imm:$imm),
1532 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1533 // OR an arbitrary immediate.
1534 def : Pat<(or i32:$in, imm:$imm),
1535 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1536 // XOR an arbitrary immediate.
1537 def : Pat<(xor i32:$in, imm:$imm),
1538 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1540 def : Pat<(sub immSExt16:$imm, i32:$in),
1541 (SUBFIC $in, imm:$imm)>;
1544 def : Pat<(shl i32:$in, (i32 imm:$imm)),
1545 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
1546 def : Pat<(srl i32:$in, (i32 imm:$imm)),
1547 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
1550 def : Pat<(rotl i32:$in, i32:$sh),
1551 (RLWNM $in, $sh, 0, 31)>;
1552 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
1553 (RLWINM $in, imm:$imm, 0, 31)>;
1556 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
1557 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1560 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
1561 (BL tglobaladdr:$dst)>;
1562 def : Pat<(PPCcall (i32 texternalsym:$dst)),
1563 (BL texternalsym:$dst)>;
1566 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1567 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1569 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1570 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1572 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1573 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1577 // Hi and Lo for Darwin Global Addresses.
1578 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1579 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1580 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1581 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1582 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1583 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1584 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1585 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1586 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
1587 (ADDIS $in, tglobaltlsaddr:$g)>;
1588 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
1589 (ADDIL $in, tglobaltlsaddr:$g)>;
1590 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
1591 (ADDIS $in, tglobaladdr:$g)>;
1592 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
1593 (ADDIS $in, tconstpool:$g)>;
1594 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
1595 (ADDIS $in, tjumptable:$g)>;
1596 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
1597 (ADDIS $in, tblockaddress:$g)>;
1599 // Standard shifts. These are represented separately from the real shifts above
1600 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1602 def : Pat<(sra i32:$rS, i32:$rB),
1604 def : Pat<(srl i32:$rS, i32:$rB),
1606 def : Pat<(shl i32:$rS, i32:$rB),
1609 def : Pat<(zextloadi1 iaddr:$src),
1611 def : Pat<(zextloadi1 xaddr:$src),
1613 def : Pat<(extloadi1 iaddr:$src),
1615 def : Pat<(extloadi1 xaddr:$src),
1617 def : Pat<(extloadi8 iaddr:$src),
1619 def : Pat<(extloadi8 xaddr:$src),
1621 def : Pat<(extloadi16 iaddr:$src),
1623 def : Pat<(extloadi16 xaddr:$src),
1625 def : Pat<(f64 (extloadf32 iaddr:$src)),
1626 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1627 def : Pat<(f64 (extloadf32 xaddr:$src)),
1628 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1630 def : Pat<(f64 (fextend f32:$src)),
1631 (COPY_TO_REGCLASS $src, F8RC)>;
1634 def : Pat<(membarrier (i32 imm /*ll*/),
1638 (i32 imm /*device*/)),
1641 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
1643 include "PPCInstrAltivec.td"
1644 include "PPCInstr64Bit.td"