1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 3, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 4, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
45 def SDT_PPCatomic_load_add : SDTypeProfile<1, 2, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>
48 def SDT_PPCatomic_cmp_swap : SDTypeProfile<1, 3, [
49 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>, SDTCisInt<3>
51 def SDT_PPCatomic_swap : SDTypeProfile<1, 2, [
52 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>
55 def SDT_PPClarx : SDTypeProfile<1, 1, [
56 SDTCisInt<0>, SDTCisPtrTy<1>
58 def SDT_PPCstcx : SDTypeProfile<0, 2, [
59 SDTCisInt<0>, SDTCisPtrTy<1>
62 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
63 SDTCisPtrTy<0>, SDTCisVT<1, i32>
66 //===----------------------------------------------------------------------===//
67 // PowerPC specific DAG Nodes.
70 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
71 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
72 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
73 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
74 [SDNPHasChain, SDNPMayStore]>;
76 // This sequence is used for long double->int conversions. It changes the
77 // bits in the FPSCR which is not modelled.
78 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
80 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
81 [SDNPInFlag, SDNPOutFlag]>;
82 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
83 [SDNPInFlag, SDNPOutFlag]>;
84 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
85 [SDNPInFlag, SDNPOutFlag]>;
86 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
87 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
91 def PPCfsel : SDNode<"PPCISD::FSEL",
92 // Type constraint for fsel.
93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
96 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
97 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
98 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
99 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
101 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
103 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
104 // amounts. These nodes are generated by the multi-precision shift code.
105 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
106 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
107 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
109 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
110 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
111 [SDNPHasChain, SDNPMayStore]>;
113 // These are target-independent nodes, but have target-specific formats.
114 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
115 [SDNPHasChain, SDNPOutFlag]>;
116 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
117 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
119 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
120 def PPCcall_Macho : SDNode<"PPCISD::CALL_Macho", SDT_PPCCall,
121 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
122 def PPCcall_ELF : SDNode<"PPCISD::CALL_ELF", SDT_PPCCall,
123 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
124 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
125 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
126 def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTNone,
127 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
129 def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTNone,
130 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
132 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
133 [SDNPHasChain, SDNPOptInFlag]>;
135 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
136 [SDNPHasChain, SDNPOptInFlag]>;
138 def PPCtailcall : SDNode<"PPCISD::TAILCALL", SDT_PPCCall,
139 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
141 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
142 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
144 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
145 [SDNPHasChain, SDNPOptInFlag]>;
147 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
148 [SDNPHasChain, SDNPMayLoad]>;
149 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
150 [SDNPHasChain, SDNPMayStore]>;
153 def PPCatomic_load_add : SDNode<"PPCISD::ATOMIC_LOAD_ADD",
154 SDT_PPCatomic_load_add,
155 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
156 def PPCatomic_cmp_swap : SDNode<"PPCISD::ATOMIC_CMP_SWAP",
157 SDT_PPCatomic_cmp_swap,
158 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
159 def PPCatomic_swap : SDNode<"PPCISD::ATOMIC_SWAP",
161 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
163 // Instructions to support atomic operations
164 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
165 [SDNPHasChain, SDNPMayLoad]>;
166 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
167 [SDNPHasChain, SDNPMayStore]>;
169 // Instructions to support dynamic alloca.
170 def SDTDynOp : SDTypeProfile<1, 2, []>;
171 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
173 //===----------------------------------------------------------------------===//
174 // PowerPC specific transformation functions and pattern fragments.
177 def SHL32 : SDNodeXForm<imm, [{
178 // Transformation function: 31 - imm
179 return getI32Imm(31 - N->getValue());
182 def SRL32 : SDNodeXForm<imm, [{
183 // Transformation function: 32 - imm
184 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
187 def LO16 : SDNodeXForm<imm, [{
188 // Transformation function: get the low 16 bits.
189 return getI32Imm((unsigned short)N->getValue());
192 def HI16 : SDNodeXForm<imm, [{
193 // Transformation function: shift the immediate value down into the low bits.
194 return getI32Imm((unsigned)N->getValue() >> 16);
197 def HA16 : SDNodeXForm<imm, [{
198 // Transformation function: shift the immediate value down into the low bits.
199 signed int Val = N->getValue();
200 return getI32Imm((Val - (signed short)Val) >> 16);
202 def MB : SDNodeXForm<imm, [{
203 // Transformation function: get the start bit of a mask
205 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
206 return getI32Imm(mb);
209 def ME : SDNodeXForm<imm, [{
210 // Transformation function: get the end bit of a mask
212 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
213 return getI32Imm(me);
215 def maskimm32 : PatLeaf<(imm), [{
216 // maskImm predicate - True if immediate is a run of ones.
218 if (N->getValueType(0) == MVT::i32)
219 return isRunOfOnes((unsigned)N->getValue(), mb, me);
224 def immSExt16 : PatLeaf<(imm), [{
225 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
226 // field. Used by instructions like 'addi'.
227 if (N->getValueType(0) == MVT::i32)
228 return (int32_t)N->getValue() == (short)N->getValue();
230 return (int64_t)N->getValue() == (short)N->getValue();
232 def immZExt16 : PatLeaf<(imm), [{
233 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
234 // field. Used by instructions like 'ori'.
235 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
238 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
239 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
240 // identical in 32-bit mode, but in 64-bit mode, they return true if the
241 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
243 def imm16ShiftedZExt : PatLeaf<(imm), [{
244 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
245 // immediate are set. Used by instructions like 'xoris'.
246 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
249 def imm16ShiftedSExt : PatLeaf<(imm), [{
250 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
251 // immediate are set. Used by instructions like 'addis'. Identical to
252 // imm16ShiftedZExt in 32-bit mode.
253 if (N->getValue() & 0xFFFF) return false;
254 if (N->getValueType(0) == MVT::i32)
256 // For 64-bit, make sure it is sext right.
257 return N->getValue() == (uint64_t)(int)N->getValue();
261 //===----------------------------------------------------------------------===//
262 // PowerPC Flag Definitions.
264 class isPPC64 { bit PPC64 = 1; }
266 list<Register> Defs = [CR0];
270 class RegConstraint<string C> {
271 string Constraints = C;
273 class NoEncode<string E> {
274 string DisableEncoding = E;
278 //===----------------------------------------------------------------------===//
279 // PowerPC Operand Definitions.
281 def s5imm : Operand<i32> {
282 let PrintMethod = "printS5ImmOperand";
284 def u5imm : Operand<i32> {
285 let PrintMethod = "printU5ImmOperand";
287 def u6imm : Operand<i32> {
288 let PrintMethod = "printU6ImmOperand";
290 def s16imm : Operand<i32> {
291 let PrintMethod = "printS16ImmOperand";
293 def u16imm : Operand<i32> {
294 let PrintMethod = "printU16ImmOperand";
296 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
297 let PrintMethod = "printS16X4ImmOperand";
299 def target : Operand<OtherVT> {
300 let PrintMethod = "printBranchOperand";
302 def calltarget : Operand<iPTR> {
303 let PrintMethod = "printCallOperand";
305 def aaddr : Operand<iPTR> {
306 let PrintMethod = "printAbsAddrOperand";
308 def piclabel: Operand<iPTR> {
309 let PrintMethod = "printPICLabel";
311 def symbolHi: Operand<i32> {
312 let PrintMethod = "printSymbolHi";
314 def symbolLo: Operand<i32> {
315 let PrintMethod = "printSymbolLo";
317 def crbitm: Operand<i8> {
318 let PrintMethod = "printcrbitm";
321 def memri : Operand<iPTR> {
322 let PrintMethod = "printMemRegImm";
323 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
325 def memrr : Operand<iPTR> {
326 let PrintMethod = "printMemRegReg";
327 let MIOperandInfo = (ops ptr_rc, ptr_rc);
329 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
330 let PrintMethod = "printMemRegImmShifted";
331 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
334 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
335 // that doesn't matter.
336 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
337 (ops (i32 20), (i32 zero_reg))> {
338 let PrintMethod = "printPredicateOperand";
341 // Define PowerPC specific addressing mode.
342 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
343 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
344 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
345 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
347 /// This is just the offset part of iaddr, used for preinc.
348 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
350 //===----------------------------------------------------------------------===//
351 // PowerPC Instruction Predicate Definitions.
352 def FPContractions : Predicate<"!NoExcessFPPrecision">;
353 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
354 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
357 //===----------------------------------------------------------------------===//
358 // PowerPC Instruction Definitions.
360 // Pseudo-instructions:
362 let hasCtrlDep = 1 in {
363 let Defs = [R1], Uses = [R1] in {
364 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
365 "${:comment} ADJCALLSTACKDOWN",
366 [(callseq_start imm:$amt)]>;
367 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
368 "${:comment} ADJCALLSTACKUP",
369 [(callseq_end imm:$amt1, imm:$amt2)]>;
372 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
373 "UPDATE_VRSAVE $rD, $rS", []>;
376 let Defs = [R1], Uses = [R1] in
377 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
378 "${:comment} DYNALLOC $result, $negsize, $fpsi",
380 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
382 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
383 // scheduler into a branch sequence.
384 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
385 PPC970_Single = 1 in {
386 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
387 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
389 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
390 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
392 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
393 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
395 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
396 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
398 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
399 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
403 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
404 // scavenge a register for it.
405 def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F),
406 "${:comment} SPILL_CR $cond $F", []>;
408 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
410 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
411 "b${p:cc}lr ${p:reg}", BrB,
413 let isBranch = 1, isIndirectBranch = 1 in
414 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
418 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
421 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
422 let isBarrier = 1 in {
423 def B : IForm<18, 0, 0, (outs), (ins target:$dst),
428 // BCC represents an arbitrary conditional branch on a predicate.
429 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
430 // a two-value operand where a dag node expects two operands. :(
431 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst),
432 "b${cond:cc} ${cond:reg}, $dst"
433 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
437 let isCall = 1, PPC970_Unit = 7,
438 // All calls clobber the non-callee saved registers...
439 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
440 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
441 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
444 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
445 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
446 // Convenient aliases for call instructions
447 def BL_Macho : IForm<18, 0, 1,
448 (outs), (ins calltarget:$func, variable_ops),
449 "bl $func", BrB, []>; // See Pat patterns below.
450 def BLA_Macho : IForm<18, 1, 1,
451 (outs), (ins aaddr:$func, variable_ops),
452 "bla $func", BrB, [(PPCcall_Macho (i32 imm:$func))]>;
453 def BCTRL_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
454 (outs), (ins variable_ops),
456 [(PPCbctrl_Macho)]>, Requires<[In32BitMode]>;
460 let isCall = 1, PPC970_Unit = 7,
461 // All calls clobber the non-callee saved registers...
462 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
463 F0,F1,F2,F3,F4,F5,F6,F7,F8,
464 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
467 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
468 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
469 // Convenient aliases for call instructions
470 def BL_ELF : IForm<18, 0, 1,
471 (outs), (ins calltarget:$func, variable_ops),
472 "bl $func", BrB, []>; // See Pat patterns below.
473 def BLA_ELF : IForm<18, 1, 1,
474 (outs), (ins aaddr:$func, variable_ops),
476 [(PPCcall_ELF (i32 imm:$func))]>;
477 def BCTRL_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
478 (outs), (ins variable_ops),
480 [(PPCbctrl_ELF)]>, Requires<[In32BitMode]>;
484 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
485 def TCRETURNdi :Pseudo< (outs),
486 (ins calltarget:$dst, i32imm:$offset, variable_ops),
487 "#TC_RETURNd $dst $offset",
491 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
492 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
493 "#TC_RETURNa $func $offset",
494 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
496 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
497 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops),
498 "#TC_RETURNr $dst $offset",
502 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
503 isIndirectBranch = 1, isCall = 1, isReturn = 1 in
504 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
505 Requires<[In32BitMode]>;
509 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
510 isBarrier = 1, isCall = 1, isReturn = 1 in
511 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
516 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
517 isBarrier = 1, isCall = 1, isReturn = 1 in
518 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
523 // DCB* instructions.
524 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
525 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
526 PPC970_DGroup_Single;
527 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
528 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
529 PPC970_DGroup_Single;
530 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
531 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
532 PPC970_DGroup_Single;
533 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
534 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
535 PPC970_DGroup_Single;
536 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
537 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
538 PPC970_DGroup_Single;
539 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
540 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
541 PPC970_DGroup_Single;
542 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
543 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
544 PPC970_DGroup_Single;
545 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
546 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
547 PPC970_DGroup_Single;
550 let usesCustomDAGSchedInserter = 1 in {
551 let Uses = [CR0] in {
552 def ATOMIC_LOAD_ADD_I32 : Pseudo<
553 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
554 "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
555 [(set GPRC:$dst, (PPCatomic_load_add xoaddr:$ptr, GPRC:$incr))]>;
556 def ATOMIC_SWAP_I32 : Pseudo<
557 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
558 "${:comment} ATOMIC_SWAP_I32 PSEUDO!",
559 [(set GPRC:$dst, (PPCatomic_swap xoaddr:$ptr, GPRC:$new))]>;
561 let Uses = [CR0, CR1] in {
562 def ATOMIC_CMP_SWAP_I32 : Pseudo<
563 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
564 "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
566 (PPCatomic_cmp_swap xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
570 // Instructions to support atomic operations
571 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
572 "lwarx $rD, $src", LdStLWARX,
573 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
576 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
577 "stwcx. $rS, $dst", LdStSTWCX,
578 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
581 let isBarrier = 1, hasCtrlDep = 1 in
582 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>;
584 //===----------------------------------------------------------------------===//
585 // PPC32 Load Instructions.
588 // Unindexed (r+i) Loads.
589 let isSimpleLoad = 1, PPC970_Unit = 2 in {
590 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
591 "lbz $rD, $src", LdStGeneral,
592 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
593 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
594 "lha $rD, $src", LdStLHA,
595 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
596 PPC970_DGroup_Cracked;
597 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
598 "lhz $rD, $src", LdStGeneral,
599 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
600 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
601 "lwz $rD, $src", LdStGeneral,
602 [(set GPRC:$rD, (load iaddr:$src))]>;
604 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
605 "lfs $rD, $src", LdStLFDU,
606 [(set F4RC:$rD, (load iaddr:$src))]>;
607 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
608 "lfd $rD, $src", LdStLFD,
609 [(set F8RC:$rD, (load iaddr:$src))]>;
612 // Unindexed (r+i) Loads with Update (preinc).
613 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
614 "lbzu $rD, $addr", LdStGeneral,
615 []>, RegConstraint<"$addr.reg = $ea_result">,
616 NoEncode<"$ea_result">;
618 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
619 "lhau $rD, $addr", LdStGeneral,
620 []>, RegConstraint<"$addr.reg = $ea_result">,
621 NoEncode<"$ea_result">;
623 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
624 "lhzu $rD, $addr", LdStGeneral,
625 []>, RegConstraint<"$addr.reg = $ea_result">,
626 NoEncode<"$ea_result">;
628 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
629 "lwzu $rD, $addr", LdStGeneral,
630 []>, RegConstraint<"$addr.reg = $ea_result">,
631 NoEncode<"$ea_result">;
633 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
634 "lfs $rD, $addr", LdStLFDU,
635 []>, RegConstraint<"$addr.reg = $ea_result">,
636 NoEncode<"$ea_result">;
638 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
639 "lfd $rD, $addr", LdStLFD,
640 []>, RegConstraint<"$addr.reg = $ea_result">,
641 NoEncode<"$ea_result">;
644 // Indexed (r+r) Loads.
646 let isSimpleLoad = 1, PPC970_Unit = 2 in {
647 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
648 "lbzx $rD, $src", LdStGeneral,
649 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
650 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
651 "lhax $rD, $src", LdStLHA,
652 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
653 PPC970_DGroup_Cracked;
654 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
655 "lhzx $rD, $src", LdStGeneral,
656 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
657 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
658 "lwzx $rD, $src", LdStGeneral,
659 [(set GPRC:$rD, (load xaddr:$src))]>;
662 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
663 "lhbrx $rD, $src", LdStGeneral,
664 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
665 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
666 "lwbrx $rD, $src", LdStGeneral,
667 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
669 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
670 "lfsx $frD, $src", LdStLFDU,
671 [(set F4RC:$frD, (load xaddr:$src))]>;
672 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
673 "lfdx $frD, $src", LdStLFDU,
674 [(set F8RC:$frD, (load xaddr:$src))]>;
677 //===----------------------------------------------------------------------===//
678 // PPC32 Store Instructions.
681 // Unindexed (r+i) Stores.
682 let PPC970_Unit = 2 in {
683 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
684 "stb $rS, $src", LdStGeneral,
685 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
686 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
687 "sth $rS, $src", LdStGeneral,
688 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
689 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
690 "stw $rS, $src", LdStGeneral,
691 [(store GPRC:$rS, iaddr:$src)]>;
692 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
693 "stfs $rS, $dst", LdStUX,
694 [(store F4RC:$rS, iaddr:$dst)]>;
695 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
696 "stfd $rS, $dst", LdStUX,
697 [(store F8RC:$rS, iaddr:$dst)]>;
700 // Unindexed (r+i) Stores with Update (preinc).
701 let PPC970_Unit = 2 in {
702 def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
703 symbolLo:$ptroff, ptr_rc:$ptrreg),
704 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
705 [(set ptr_rc:$ea_res,
706 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
707 iaddroff:$ptroff))]>,
708 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
709 def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
710 symbolLo:$ptroff, ptr_rc:$ptrreg),
711 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
712 [(set ptr_rc:$ea_res,
713 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
714 iaddroff:$ptroff))]>,
715 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
716 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
717 symbolLo:$ptroff, ptr_rc:$ptrreg),
718 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
719 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
720 iaddroff:$ptroff))]>,
721 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
722 def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
723 symbolLo:$ptroff, ptr_rc:$ptrreg),
724 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
725 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
726 iaddroff:$ptroff))]>,
727 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
728 def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
729 symbolLo:$ptroff, ptr_rc:$ptrreg),
730 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
731 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
732 iaddroff:$ptroff))]>,
733 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
737 // Indexed (r+r) Stores.
739 let PPC970_Unit = 2 in {
740 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
741 "stbx $rS, $dst", LdStGeneral,
742 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
743 PPC970_DGroup_Cracked;
744 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
745 "sthx $rS, $dst", LdStGeneral,
746 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
747 PPC970_DGroup_Cracked;
748 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
749 "stwx $rS, $dst", LdStGeneral,
750 [(store GPRC:$rS, xaddr:$dst)]>,
751 PPC970_DGroup_Cracked;
753 let mayStore = 1 in {
754 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
755 "stwux $rS, $rA, $rB", LdStGeneral,
758 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
759 "sthbrx $rS, $dst", LdStGeneral,
760 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
761 PPC970_DGroup_Cracked;
762 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
763 "stwbrx $rS, $dst", LdStGeneral,
764 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
765 PPC970_DGroup_Cracked;
767 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
768 "stfiwx $frS, $dst", LdStUX,
769 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
771 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
772 "stfsx $frS, $dst", LdStUX,
773 [(store F4RC:$frS, xaddr:$dst)]>;
774 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
775 "stfdx $frS, $dst", LdStUX,
776 [(store F8RC:$frS, xaddr:$dst)]>;
780 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
784 //===----------------------------------------------------------------------===//
785 // PPC32 Arithmetic Instructions.
788 let PPC970_Unit = 1 in { // FXU Operations.
789 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
790 "addi $rD, $rA, $imm", IntGeneral,
791 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
792 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
793 "addic $rD, $rA, $imm", IntGeneral,
794 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
795 PPC970_DGroup_Cracked;
796 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
797 "addic. $rD, $rA, $imm", IntGeneral,
799 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
800 "addis $rD, $rA, $imm", IntGeneral,
801 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
802 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
803 "la $rD, $sym($rA)", IntGeneral,
804 [(set GPRC:$rD, (add GPRC:$rA,
805 (PPClo tglobaladdr:$sym, 0)))]>;
806 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
807 "mulli $rD, $rA, $imm", IntMulLI,
808 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
809 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
810 "subfic $rD, $rA, $imm", IntGeneral,
811 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
813 let isReMaterializable = 1 in {
814 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
815 "li $rD, $imm", IntGeneral,
816 [(set GPRC:$rD, immSExt16:$imm)]>;
817 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
818 "lis $rD, $imm", IntGeneral,
819 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
823 let PPC970_Unit = 1 in { // FXU Operations.
824 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
825 "andi. $dst, $src1, $src2", IntGeneral,
826 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
828 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
829 "andis. $dst, $src1, $src2", IntGeneral,
830 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
832 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
833 "ori $dst, $src1, $src2", IntGeneral,
834 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
835 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
836 "oris $dst, $src1, $src2", IntGeneral,
837 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
838 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
839 "xori $dst, $src1, $src2", IntGeneral,
840 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
841 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
842 "xoris $dst, $src1, $src2", IntGeneral,
843 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
844 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
846 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
847 "cmpwi $crD, $rA, $imm", IntCompare>;
848 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
849 "cmplwi $dst, $src1, $src2", IntCompare>;
853 let PPC970_Unit = 1 in { // FXU Operations.
854 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
855 "nand $rA, $rS, $rB", IntGeneral,
856 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
857 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
858 "and $rA, $rS, $rB", IntGeneral,
859 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
860 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
861 "andc $rA, $rS, $rB", IntGeneral,
862 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
863 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
864 "or $rA, $rS, $rB", IntGeneral,
865 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
866 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
867 "nor $rA, $rS, $rB", IntGeneral,
868 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
869 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
870 "orc $rA, $rS, $rB", IntGeneral,
871 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
872 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
873 "eqv $rA, $rS, $rB", IntGeneral,
874 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
875 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
876 "xor $rA, $rS, $rB", IntGeneral,
877 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
878 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
879 "slw $rA, $rS, $rB", IntGeneral,
880 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
881 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
882 "srw $rA, $rS, $rB", IntGeneral,
883 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
884 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
885 "sraw $rA, $rS, $rB", IntShift,
886 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
889 let PPC970_Unit = 1 in { // FXU Operations.
890 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
891 "srawi $rA, $rS, $SH", IntShift,
892 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
893 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
894 "cntlzw $rA, $rS", IntGeneral,
895 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
896 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
897 "extsb $rA, $rS", IntGeneral,
898 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
899 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
900 "extsh $rA, $rS", IntGeneral,
901 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
903 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
904 "cmpw $crD, $rA, $rB", IntCompare>;
905 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
906 "cmplw $crD, $rA, $rB", IntCompare>;
908 let PPC970_Unit = 3 in { // FPU Operations.
909 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
910 // "fcmpo $crD, $fA, $fB", FPCompare>;
911 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
912 "fcmpu $crD, $fA, $fB", FPCompare>;
913 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
914 "fcmpu $crD, $fA, $fB", FPCompare>;
916 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
917 "fctiwz $frD, $frB", FPGeneral,
918 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
919 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
920 "frsp $frD, $frB", FPGeneral,
921 [(set F4RC:$frD, (fround F8RC:$frB))]>;
922 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
923 "fsqrt $frD, $frB", FPSqrt,
924 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
925 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
926 "fsqrts $frD, $frB", FPSqrt,
927 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
930 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
932 /// Note that these are defined as pseudo-ops on the PPC970 because they are
933 /// often coalesced away and we don't want the dispatch group builder to think
934 /// that they will fill slots (which could cause the load of a LSU reject to
935 /// sneak into a d-group with a store).
936 def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
937 "fmr $frD, $frB", FPGeneral,
938 []>, // (set F4RC:$frD, F4RC:$frB)
940 def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB),
941 "fmr $frD, $frB", FPGeneral,
942 []>, // (set F8RC:$frD, F8RC:$frB)
944 def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB),
945 "fmr $frD, $frB", FPGeneral,
946 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
949 let PPC970_Unit = 3 in { // FPU Operations.
950 // These are artificially split into two different forms, for 4/8 byte FP.
951 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
952 "fabs $frD, $frB", FPGeneral,
953 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
954 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
955 "fabs $frD, $frB", FPGeneral,
956 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
957 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
958 "fnabs $frD, $frB", FPGeneral,
959 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
960 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
961 "fnabs $frD, $frB", FPGeneral,
962 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
963 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
964 "fneg $frD, $frB", FPGeneral,
965 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
966 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
967 "fneg $frD, $frB", FPGeneral,
968 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
972 // XL-Form instructions. condition register logical ops.
974 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
975 "mcrf $BF, $BFA", BrMCR>,
976 PPC970_DGroup_First, PPC970_Unit_CRU;
978 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
979 (ins CRBITRC:$CRA, CRBITRC:$CRB),
980 "creqv $CRD, $CRA, $CRB", BrCR,
983 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
984 (ins CRBITRC:$CRA, CRBITRC:$CRB),
985 "cror $CRD, $CRA, $CRB", BrCR,
988 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
989 "creqv $dst, $dst, $dst", BrCR,
992 // XFX-Form instructions. Instructions that deal with SPRs.
994 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
995 "mfctr $rT", SprMFSPR>,
996 PPC970_DGroup_First, PPC970_Unit_FXU;
997 let Pattern = [(PPCmtctr GPRC:$rS)] in {
998 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
999 "mtctr $rS", SprMTSPR>,
1000 PPC970_DGroup_First, PPC970_Unit_FXU;
1003 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1004 "mtlr $rS", SprMTSPR>,
1005 PPC970_DGroup_First, PPC970_Unit_FXU;
1006 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1007 "mflr $rT", SprMFSPR>,
1008 PPC970_DGroup_First, PPC970_Unit_FXU;
1010 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1011 // a GPR on the PPC970. As such, copies in and out have the same performance
1012 // characteristics as an OR instruction.
1013 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1014 "mtspr 256, $rS", IntGeneral>,
1015 PPC970_DGroup_Single, PPC970_Unit_FXU;
1016 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1017 "mfspr $rT, 256", IntGeneral>,
1018 PPC970_DGroup_First, PPC970_Unit_FXU;
1020 def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
1021 "mtcrf $FXM, $rS", BrMCRX>,
1022 PPC970_MicroCode, PPC970_Unit_CRU;
1023 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>,
1024 PPC970_MicroCode, PPC970_Unit_CRU;
1025 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1026 "mfcr $rT, $FXM", SprMFCR>,
1027 PPC970_DGroup_First, PPC970_Unit_CRU;
1029 // Instructions to manipulate FPSCR. Only long double handling uses these.
1030 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1032 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1033 "mffs $rT", IntMFFS,
1034 [(set F8RC:$rT, (PPCmffs))]>,
1035 PPC970_DGroup_Single, PPC970_Unit_FPU;
1036 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1037 "mtfsb0 $FM", IntMTFSB0,
1038 [(PPCmtfsb0 (i32 imm:$FM))]>,
1039 PPC970_DGroup_Single, PPC970_Unit_FPU;
1040 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1041 "mtfsb1 $FM", IntMTFSB0,
1042 [(PPCmtfsb1 (i32 imm:$FM))]>,
1043 PPC970_DGroup_Single, PPC970_Unit_FPU;
1044 def FADDrtz: AForm_2<63, 21,
1045 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1046 "fadd $FRT, $FRA, $FRB", FPGeneral,
1047 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1048 PPC970_DGroup_Single, PPC970_Unit_FPU;
1049 // MTFSF does not actually produce an FP result. We pretend it copies
1050 // input reg B to the output. If we didn't do this it would look like the
1051 // instruction had no outputs (because we aren't modelling the FPSCR) and
1052 // it would be deleted.
1053 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1054 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1055 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1056 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1057 F8RC:$rT, F8RC:$FRB))]>,
1058 PPC970_DGroup_Single, PPC970_Unit_FPU;
1060 let PPC970_Unit = 1 in { // FXU Operations.
1062 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1064 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1065 "add $rT, $rA, $rB", IntGeneral,
1066 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1067 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1068 "addc $rT, $rA, $rB", IntGeneral,
1069 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1070 PPC970_DGroup_Cracked;
1071 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1072 "adde $rT, $rA, $rB", IntGeneral,
1073 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1074 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1075 "divw $rT, $rA, $rB", IntDivW,
1076 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1077 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1078 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1079 "divwu $rT, $rA, $rB", IntDivW,
1080 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1081 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1082 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1083 "mulhw $rT, $rA, $rB", IntMulHW,
1084 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1085 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1086 "mulhwu $rT, $rA, $rB", IntMulHWU,
1087 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1088 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1089 "mullw $rT, $rA, $rB", IntMulHW,
1090 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1091 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1092 "subf $rT, $rA, $rB", IntGeneral,
1093 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1094 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1095 "subfc $rT, $rA, $rB", IntGeneral,
1096 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1097 PPC970_DGroup_Cracked;
1098 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1099 "subfe $rT, $rA, $rB", IntGeneral,
1100 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1101 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1102 "addme $rT, $rA", IntGeneral,
1103 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
1104 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1105 "addze $rT, $rA", IntGeneral,
1106 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1107 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1108 "neg $rT, $rA", IntGeneral,
1109 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1110 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1111 "subfme $rT, $rA", IntGeneral,
1112 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
1113 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1114 "subfze $rT, $rA", IntGeneral,
1115 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1118 // A-Form instructions. Most of the instructions executed in the FPU are of
1121 let PPC970_Unit = 3 in { // FPU Operations.
1122 def FMADD : AForm_1<63, 29,
1123 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1124 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1125 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1127 Requires<[FPContractions]>;
1128 def FMADDS : AForm_1<59, 29,
1129 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1130 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1131 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1133 Requires<[FPContractions]>;
1134 def FMSUB : AForm_1<63, 28,
1135 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1136 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1137 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1139 Requires<[FPContractions]>;
1140 def FMSUBS : AForm_1<59, 28,
1141 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1142 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1143 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1145 Requires<[FPContractions]>;
1146 def FNMADD : AForm_1<63, 31,
1147 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1148 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1149 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1151 Requires<[FPContractions]>;
1152 def FNMADDS : AForm_1<59, 31,
1153 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1154 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1155 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1157 Requires<[FPContractions]>;
1158 def FNMSUB : AForm_1<63, 30,
1159 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1160 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1161 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1163 Requires<[FPContractions]>;
1164 def FNMSUBS : AForm_1<59, 30,
1165 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1166 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1167 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1169 Requires<[FPContractions]>;
1170 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1171 // having 4 of these, force the comparison to always be an 8-byte double (code
1172 // should use an FMRSD if the input comparison value really wants to be a float)
1173 // and 4/8 byte forms for the result and operand type..
1174 def FSELD : AForm_1<63, 23,
1175 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1176 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1177 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1178 def FSELS : AForm_1<63, 23,
1179 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1180 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1181 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1182 def FADD : AForm_2<63, 21,
1183 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1184 "fadd $FRT, $FRA, $FRB", FPGeneral,
1185 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1186 def FADDS : AForm_2<59, 21,
1187 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1188 "fadds $FRT, $FRA, $FRB", FPGeneral,
1189 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1190 def FDIV : AForm_2<63, 18,
1191 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1192 "fdiv $FRT, $FRA, $FRB", FPDivD,
1193 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1194 def FDIVS : AForm_2<59, 18,
1195 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1196 "fdivs $FRT, $FRA, $FRB", FPDivS,
1197 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1198 def FMUL : AForm_3<63, 25,
1199 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1200 "fmul $FRT, $FRA, $FRB", FPFused,
1201 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1202 def FMULS : AForm_3<59, 25,
1203 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1204 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1205 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1206 def FSUB : AForm_2<63, 20,
1207 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1208 "fsub $FRT, $FRA, $FRB", FPGeneral,
1209 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1210 def FSUBS : AForm_2<59, 20,
1211 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1212 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1213 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1216 let PPC970_Unit = 1 in { // FXU Operations.
1217 // M-Form instructions. rotate and mask instructions.
1219 let isCommutable = 1 in {
1220 // RLWIMI can be commuted if the rotate amount is zero.
1221 def RLWIMI : MForm_2<20,
1222 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1223 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1224 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1227 def RLWINM : MForm_2<21,
1228 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1229 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1231 def RLWINMo : MForm_2<21,
1232 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1233 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1234 []>, isDOT, PPC970_DGroup_Cracked;
1235 def RLWNM : MForm_2<23,
1236 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1237 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1242 //===----------------------------------------------------------------------===//
1243 // DWARF Pseudo Instructions
1246 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
1247 "${:comment} .loc $file, $line, $col",
1248 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
1251 //===----------------------------------------------------------------------===//
1252 // PowerPC Instruction Patterns
1255 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1256 def : Pat<(i32 imm:$imm),
1257 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1259 // Implement the 'not' operation with the NOR instruction.
1260 def NOT : Pat<(not GPRC:$in),
1261 (NOR GPRC:$in, GPRC:$in)>;
1263 // ADD an arbitrary immediate.
1264 def : Pat<(add GPRC:$in, imm:$imm),
1265 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1266 // OR an arbitrary immediate.
1267 def : Pat<(or GPRC:$in, imm:$imm),
1268 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1269 // XOR an arbitrary immediate.
1270 def : Pat<(xor GPRC:$in, imm:$imm),
1271 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1273 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1274 (SUBFIC GPRC:$in, imm:$imm)>;
1277 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1278 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1279 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1280 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1283 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1284 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1285 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1286 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1289 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1290 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1293 def : Pat<(PPCcall_Macho (i32 tglobaladdr:$dst)),
1294 (BL_Macho tglobaladdr:$dst)>;
1295 def : Pat<(PPCcall_Macho (i32 texternalsym:$dst)),
1296 (BL_Macho texternalsym:$dst)>;
1297 def : Pat<(PPCcall_ELF (i32 tglobaladdr:$dst)),
1298 (BL_ELF tglobaladdr:$dst)>;
1299 def : Pat<(PPCcall_ELF (i32 texternalsym:$dst)),
1300 (BL_ELF texternalsym:$dst)>;
1303 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1304 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1306 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1307 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1309 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1310 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1314 // Hi and Lo for Darwin Global Addresses.
1315 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1316 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1317 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1318 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1319 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1320 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1321 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1322 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1323 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1324 (ADDIS GPRC:$in, tconstpool:$g)>;
1325 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1326 (ADDIS GPRC:$in, tjumptable:$g)>;
1328 // Fused negative multiply subtract, alternate pattern
1329 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1330 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1331 Requires<[FPContractions]>;
1332 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1333 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1334 Requires<[FPContractions]>;
1336 // Standard shifts. These are represented separately from the real shifts above
1337 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1339 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1340 (SRAW GPRC:$rS, GPRC:$rB)>;
1341 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1342 (SRW GPRC:$rS, GPRC:$rB)>;
1343 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1344 (SLW GPRC:$rS, GPRC:$rB)>;
1346 def : Pat<(zextloadi1 iaddr:$src),
1348 def : Pat<(zextloadi1 xaddr:$src),
1350 def : Pat<(extloadi1 iaddr:$src),
1352 def : Pat<(extloadi1 xaddr:$src),
1354 def : Pat<(extloadi8 iaddr:$src),
1356 def : Pat<(extloadi8 xaddr:$src),
1358 def : Pat<(extloadi16 iaddr:$src),
1360 def : Pat<(extloadi16 xaddr:$src),
1362 def : Pat<(extloadf32 iaddr:$src),
1363 (FMRSD (LFS iaddr:$src))>;
1364 def : Pat<(extloadf32 xaddr:$src),
1365 (FMRSD (LFSX xaddr:$src))>;
1368 def : Pat<(membarrier (i32 imm:$ll),
1375 include "PPCInstrAltivec.td"
1376 include "PPCInstr64Bit.td"