1 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PowerPCInstrFormats.td"
17 class isPPC64 { bit PPC64 = 1; }
18 class isVMX { bit VMX = 1; }
20 list<Register> Defs = [CR0];
24 let isTerminator = 1 in {
26 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
27 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
30 def u5imm : Operand<i8> {
31 let PrintMethod = "printU5ImmOperand";
33 def u6imm : Operand<i8> {
34 let PrintMethod = "printU6ImmOperand";
36 def s16imm : Operand<i16> {
37 let PrintMethod = "printS16ImmOperand";
39 def u16imm : Operand<i16> {
40 let PrintMethod = "printU16ImmOperand";
42 def target : Operand<i32> {
43 let PrintMethod = "printBranchOperand";
45 def piclabel: Operand<i32> {
46 let PrintMethod = "printPICLabel";
48 def symbolHi: Operand<i32> {
49 let PrintMethod = "printSymbolHi";
51 def symbolLo: Operand<i32> {
52 let PrintMethod = "printSymbolLo";
54 def crbit: Operand<i8> {
55 let PrintMethod = "printcrbit";
57 def crbitm: Operand<i8> {
58 let PrintMethod = "printcrbitm";
61 // Pseudo-instructions:
62 def PHI : Pseudo<(ops variable_ops), "; PHI">;
64 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm), "; ADJCALLSTACKDOWN">;
65 def ADJCALLSTACKUP : Pseudo<(ops u16imm), "; ADJCALLSTACKUP">;
67 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
68 def IMPLICIT_DEF_FP : Pseudo<(ops FPRC:$rD), "; %rD = IMPLICIT_DEF_FP">;
70 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
71 // scheduler into a branch sequence.
72 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
73 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
74 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
75 def SELECT_CC_FP : Pseudo<(ops FPRC:$dst, CRRC:$cond, FPRC:$T, FPRC:$F,
76 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
81 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
83 let isBranch = 1, isTerminator = 1 in {
84 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm, target:$true, target:$false),
86 def B : IForm<18, 0, 0, (ops target:$func), "b $func">;
87 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">;
88 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">;
89 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">;
91 // FIXME: 4*CR# needs to be added to the BI field!
92 // This will only work for CR0 as it stands now
93 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
95 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
97 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
99 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
101 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
103 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
108 // All calls clobber the non-callee saved registers...
109 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
110 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
112 CR0,CR1,CR5,CR6,CR7] in {
113 // Convenient aliases for call instructions
114 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">;
115 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
116 (ops variable_ops), "bctrl">;
119 // D-Form instructions. Most instructions that perform an operation on a
120 // register and an immediate are of this type.
123 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
124 "lbz $rD, $disp($rA)">;
125 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
126 "lha $rD, $disp($rA)">;
127 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
128 "lhz $rD, $disp($rA)">;
129 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
130 "lmw $rD, $disp($rA)">;
131 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
132 "lwz $rD, $disp($rA)">;
133 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
134 "lwzu $rD, $disp($rA)">;
136 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
137 "addi $rD, $rA, $imm">;
138 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
139 "addic $rD, $rA, $imm">;
140 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
141 "addic. $rD, $rA, $imm">;
142 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
143 "addis $rD, $rA, $imm">;
144 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
145 "la $rD, $sym($rA)">;
146 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
147 "mulli $rD, $rA, $imm">;
148 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
149 "subfic $rD, $rA, $imm">;
150 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
152 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
155 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
156 "stmw $rS, $disp($rA)">;
157 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
158 "stb $rS, $disp($rA)">;
159 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
160 "sth $rS, $disp($rA)">;
161 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
162 "stw $rS, $disp($rA)">;
163 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
164 "stwu $rS, $disp($rA)">;
166 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
167 "andi. $dst, $src1, $src2">, isDOT;
168 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
169 "andis. $dst, $src1, $src2">, isDOT;
170 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
171 "ori $dst, $src1, $src2">;
172 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
173 "oris $dst, $src1, $src2">;
174 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
175 "xori $dst, $src1, $src2">;
176 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
177 "xoris $dst, $src1, $src2">;
178 def NOP : DForm_4_zero<24, (ops), "nop">;
179 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
180 "cmpi $crD, $L, $rA, $imm">;
181 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
182 "cmpwi $crD, $rA, $imm">;
183 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
184 "cmpdi $crD, $rA, $imm">, isPPC64;
185 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
186 "cmpli $dst, $size, $src1, $src2">;
187 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
188 "cmplwi $dst, $src1, $src2">;
189 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
190 "cmpldi $dst, $src1, $src2">, isPPC64;
192 def LFS : DForm_8<48, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
193 "lfs $rD, $disp($rA)">;
194 def LFD : DForm_8<50, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
195 "lfd $rD, $disp($rA)">;
198 def STFS : DForm_9<52, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
199 "stfs $rS, $disp($rA)">;
200 def STFD : DForm_9<54, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
201 "stfd $rS, $disp($rA)">;
204 // DS-Form instructions. Load/Store instructions available in PPC-64
207 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
208 "lwa $rT, $DS($rA)">, isPPC64;
209 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
210 "ld $rT, $DS($rA)">, isPPC64;
213 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
214 "std $rT, $DS($rA)">, isPPC64;
215 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
216 "stdu $rT, $DS($rA)">, isPPC64;
219 // X-Form instructions. Most instructions that perform an operation on a
220 // register and another register are of this type.
223 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
224 "lbzx $dst, $base, $index">;
225 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
226 "lhax $dst, $base, $index">;
227 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
228 "lhzx $dst, $base, $index">;
229 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
230 "lwax $dst, $base, $index">, isPPC64;
231 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
232 "lwzx $dst, $base, $index">;
233 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
234 "ldx $dst, $base, $index">, isPPC64;
236 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
237 "and $rA, $rS, $rB">;
238 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
239 "and. $rA, $rS, $rB">, isDOT;
240 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
241 "andc $rA, $rS, $rB">;
242 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
243 "eqv $rA, $rS, $rB">;
244 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
245 "nand $rA, $rS, $rB">;
246 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
247 "nor $rA, $rS, $rB">;
248 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
250 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
251 "or. $rA, $rS, $rB">, isDOT;
252 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
253 "orc $rA, $rS, $rB">;
254 def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
255 "sld $rA, $rS, $rB">, isPPC64;
256 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
257 "slw $rA, $rS, $rB">;
258 def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
259 "srd $rA, $rS, $rB">, isPPC64;
260 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
261 "srw $rA, $rS, $rB">;
262 def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
263 "srad $rA, $rS, $rB">, isPPC64;
264 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
265 "sraw $rA, $rS, $rB">;
266 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
267 "xor $rA, $rS, $rB">;
269 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
270 "stbx $rS, $rA, $rB">;
271 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
272 "sthx $rS, $rA, $rB">;
273 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
274 "stwx $rS, $rA, $rB">;
275 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
276 "stwux $rS, $rA, $rB">;
277 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
278 "stdx $rS, $rA, $rB">, isPPC64;
279 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
280 "stdux $rS, $rA, $rB">, isPPC64;
282 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
283 "srawi $rA, $rS, $SH">;
284 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
286 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
288 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
290 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
291 "extsw $rA, $rS">, isPPC64;
292 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
293 "cmp $crD, $long, $rA, $rB">;
294 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
295 "cmpl $crD, $long, $rA, $rB">;
296 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
297 "cmpw $crD, $rA, $rB">;
298 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
299 "cmpd $crD, $rA, $rB">, isPPC64;
300 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
301 "cmplw $crD, $rA, $rB">;
302 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
303 "cmpld $crD, $rA, $rB">, isPPC64;
304 def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
305 "fcmpo $crD, $fA, $fB">;
306 def FCMPU : XForm_17<63, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
307 "fcmpu $crD, $fA, $fB">;
309 def LFSX : XForm_25<31, 535, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
310 "lfsx $dst, $base, $index">;
311 def LFDX : XForm_25<31, 599, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
312 "lfdx $dst, $base, $index">;
314 def FCFID : XForm_26<63, 846, (ops FPRC:$frD, FPRC:$frB),
315 "fcfid $frD, $frB">, isPPC64;
316 def FCTIDZ : XForm_26<63, 815, (ops FPRC:$frD, FPRC:$frB),
317 "fctidz $frD, $frB">, isPPC64;
318 def FCTIWZ : XForm_26<63, 15, (ops FPRC:$frD, FPRC:$frB),
319 "fctiwz $frD, $frB">;
320 def FABS : XForm_26<63, 264, (ops FPRC:$frD, FPRC:$frB),
322 def FMR : XForm_26<63, 72, (ops FPRC:$frD, FPRC:$frB),
324 def FNABS : XForm_26<63, 136, (ops FPRC:$frD, FPRC:$frB),
326 def FNEG : XForm_26<63, 40, (ops FPRC:$frD, FPRC:$frB),
328 def FRSP : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
330 def FSQRT : XForm_26<63, 22, (ops FPRC:$frD, FPRC:$frB),
332 def FSQRTS : XForm_26<59, 22, (ops FPRC:$frD, FPRC:$frB),
333 "fsqrts $frD, $frB">;
336 def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
337 "stfsx $frS, $rA, $rB">;
338 def STFDX : XForm_28<31, 727, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
339 "stfdx $frS, $rA, $rB">;
342 // XL-Form instructions. condition register logical ops.
344 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
347 // XFX-Form instructions. Instructions that deal with SPRs
349 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
350 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
351 // which means the SPR value needs to be multiplied by a factor of 32.
352 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
353 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
354 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
355 def MTCRF : XFXForm_5<31, 144, (ops CRRC:$FXM, GPRC:$rS),
357 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
359 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
360 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
362 // XS-Form instructions. Just 'sradi'
364 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
365 "sradi $rA, $rS, $SH">, isPPC64;
367 // XO-Form instructions. Arithmetic instructions that can set overflow bit
369 def ADD : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
370 "add $rT, $rA, $rB">;
371 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
372 "addc $rT, $rA, $rB">;
373 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
374 "adde $rT, $rA, $rB">;
375 def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
376 "divd $rT, $rA, $rB">, isPPC64;
377 def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
378 "divdu $rT, $rA, $rB">, isPPC64;
379 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
380 "divw $rT, $rA, $rB">;
381 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
382 "divwu $rT, $rA, $rB">;
383 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
384 "mulhw $rT, $rA, $rB">;
385 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
386 "mulhwu $rT, $rA, $rB">;
387 def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
388 "mulld $rT, $rA, $rB">, isPPC64;
389 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
390 "mullw $rT, $rA, $rB">;
391 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
392 "subf $rT, $rA, $rB">;
393 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
394 "subfc $rT, $rA, $rB">;
395 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
396 "subfe $rT, $rA, $rB">;
397 def SUB : XOForm_1r<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
398 "sub $rT, $rA, $rB">;
399 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
401 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
403 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
405 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
408 // A-Form instructions. Most of the instructions executed in the FPU are of
411 def FMADD : AForm_1<63, 29,
412 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
413 "fmadd $FRT, $FRA, $FRC, $FRB">;
414 def FMADDS : AForm_1<59, 29,
415 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
416 "fmadds $FRT, $FRA, $FRC, $FRB">;
417 def FMSUB : AForm_1<63, 28,
418 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
419 "fmsub $FRT, $FRA, $FRC, $FRB">;
420 def FMSUBS : AForm_1<59, 28,
421 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
422 "fmsubs $FRT, $FRA, $FRC, $FRB">;
423 def FNMADD : AForm_1<63, 31,
424 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
425 "fnmadd $FRT, $FRA, $FRC, $FRB">;
426 def FNMADDS : AForm_1<59, 31,
427 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
428 "fnmadds $FRT, $FRA, $FRC, $FRB">;
429 def FNMSUB : AForm_1<63, 30,
430 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
431 "fnmsub $FRT, $FRA, $FRC, $FRB">;
432 def FNMSUBS : AForm_1<59, 30,
433 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
434 "fnmsubs $FRT, $FRA, $FRC, $FRB">;
435 def FSEL : AForm_1<63, 23,
436 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
437 "fsel $FRT, $FRA, $FRC, $FRB">;
438 def FADD : AForm_2<63, 21,
439 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
440 "fadd $FRT, $FRA, $FRB">;
441 def FADDS : AForm_2<59, 21,
442 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
443 "fadds $FRT, $FRA, $FRB">;
444 def FDIV : AForm_2<63, 18,
445 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
446 "fdiv $FRT, $FRA, $FRB">;
447 def FDIVS : AForm_2<59, 18,
448 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
449 "fdivs $FRT, $FRA, $FRB">;
450 def FMUL : AForm_3<63, 25,
451 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
452 "fmul $FRT, $FRA, $FRB">;
453 def FMULS : AForm_3<59, 25,
454 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
455 "fmuls $FRT, $FRA, $FRB">;
456 def FSUB : AForm_2<63, 20,
457 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
458 "fsub $FRT, $FRA, $FRB">;
459 def FSUBS : AForm_2<59, 20,
460 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
461 "fsubs $FRT, $FRA, $FRB">;
463 // M-Form instructions. rotate and mask instructions.
465 let isTwoAddress = 1 in {
466 def RLWIMI : MForm_2<20,
467 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
468 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
470 def RLWINM : MForm_2<21,
471 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
472 "rlwinm $rA, $rS, $SH, $MB, $ME">;
473 def RLWINMo : MForm_2<21,
474 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
475 "rlwinm. $rA, $rS, $SH, $MB, $ME">, isDOT;
476 def RLWNM : MForm_2<23,
477 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
478 "rlwnm $rA, $rS, $rB, $MB, $ME">;
480 // MD-Form instructions. 64 bit rotate instructions.
482 def RLDICL : MDForm_1<30, 0,
483 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
484 "rldicl $rA, $rS, $SH, $MB">, isPPC64;
485 def RLDICR : MDForm_1<30, 1,
486 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
487 "rldicr $rA, $rS, $SH, $ME">, isPPC64;
489 def PowerPCInstrInfo : InstrInfo {
492 let TSFlagsFields = [ "VMX", "PPC64" ];
493 let TSFlagsShifts = [ 0, 1 ];
495 let isLittleEndianEncoding = 1;