1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
61 //===----------------------------------------------------------------------===//
62 // PowerPC specific DAG Nodes.
65 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
66 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
68 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
69 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
70 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
71 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
72 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
73 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
74 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
75 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
76 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
77 [SDNPHasChain, SDNPMayStore]>;
78 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
79 [SDNPHasChain, SDNPMayLoad]>;
80 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
81 [SDNPHasChain, SDNPMayLoad]>;
83 // Extract FPSCR (not modeled at the DAG level).
84 def PPCmffs : SDNode<"PPCISD::MFFS",
85 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
87 // Perform FADD in round-to-zero mode.
88 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
91 def PPCfsel : SDNode<"PPCISD::FSEL",
92 // Type constraint for fsel.
93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
96 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
97 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
98 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
99 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
100 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
102 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
103 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
105 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
106 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
107 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
108 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
109 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
110 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
111 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
112 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
114 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
116 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
118 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
119 // amounts. These nodes are generated by the multi-precision shift code.
120 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
121 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
122 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
124 // These are target-independent nodes, but have target-specific formats.
125 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
126 [SDNPHasChain, SDNPOutGlue]>;
127 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
130 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
131 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
134 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
137 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
139 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
140 [SDNPHasChain, SDNPSideEffect,
141 SDNPInGlue, SDNPOutGlue]>;
142 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
143 [SDNPHasChain, SDNPSideEffect,
144 SDNPInGlue, SDNPOutGlue]>;
145 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
147 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
151 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
152 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
154 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
157 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
158 SDTypeProfile<1, 1, [SDTCisInt<0>,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
162 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
166 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
167 [SDNPHasChain, SDNPSideEffect]>;
169 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
170 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
172 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
173 [SDNPHasChain, SDNPOptInGlue]>;
175 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
176 [SDNPHasChain, SDNPMayLoad]>;
177 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
178 [SDNPHasChain, SDNPMayStore]>;
180 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
181 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
182 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
183 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
186 // Instructions to support atomic operations
187 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
188 [SDNPHasChain, SDNPMayLoad]>;
189 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
190 [SDNPHasChain, SDNPMayStore]>;
192 // Instructions to support medium and large code model
193 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
194 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
195 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
198 // Instructions to support dynamic alloca.
199 def SDTDynOp : SDTypeProfile<1, 2, []>;
200 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
202 //===----------------------------------------------------------------------===//
203 // PowerPC specific transformation functions and pattern fragments.
206 def SHL32 : SDNodeXForm<imm, [{
207 // Transformation function: 31 - imm
208 return getI32Imm(31 - N->getZExtValue());
211 def SRL32 : SDNodeXForm<imm, [{
212 // Transformation function: 32 - imm
213 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
216 def LO16 : SDNodeXForm<imm, [{
217 // Transformation function: get the low 16 bits.
218 return getI32Imm((unsigned short)N->getZExtValue());
221 def HI16 : SDNodeXForm<imm, [{
222 // Transformation function: shift the immediate value down into the low bits.
223 return getI32Imm((unsigned)N->getZExtValue() >> 16);
226 def HA16 : SDNodeXForm<imm, [{
227 // Transformation function: shift the immediate value down into the low bits.
228 signed int Val = N->getZExtValue();
229 return getI32Imm((Val - (signed short)Val) >> 16);
231 def MB : SDNodeXForm<imm, [{
232 // Transformation function: get the start bit of a mask
234 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
235 return getI32Imm(mb);
238 def ME : SDNodeXForm<imm, [{
239 // Transformation function: get the end bit of a mask
241 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
242 return getI32Imm(me);
244 def maskimm32 : PatLeaf<(imm), [{
245 // maskImm predicate - True if immediate is a run of ones.
247 if (N->getValueType(0) == MVT::i32)
248 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
253 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
254 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
255 // sign extended field. Used by instructions like 'addi'.
256 return (int32_t)Imm == (short)Imm;
258 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
259 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
260 // sign extended field. Used by instructions like 'addi'.
261 return (int64_t)Imm == (short)Imm;
263 def immZExt16 : PatLeaf<(imm), [{
264 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
265 // field. Used by instructions like 'ori'.
266 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
269 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
270 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
271 // identical in 32-bit mode, but in 64-bit mode, they return true if the
272 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
274 def imm16ShiftedZExt : PatLeaf<(imm), [{
275 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
276 // immediate are set. Used by instructions like 'xoris'.
277 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
280 def imm16ShiftedSExt : PatLeaf<(imm), [{
281 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
282 // immediate are set. Used by instructions like 'addis'. Identical to
283 // imm16ShiftedZExt in 32-bit mode.
284 if (N->getZExtValue() & 0xFFFF) return false;
285 if (N->getValueType(0) == MVT::i32)
287 // For 64-bit, make sure it is sext right.
288 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
291 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
292 // restricted memrix (4-aligned) constants are alignment sensitive. If these
293 // offsets are hidden behind TOC entries than the values of the lower-order
294 // bits cannot be checked directly. As a result, we need to also incorporate
295 // an alignment check into the relevant patterns.
297 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
298 return cast<LoadSDNode>(N)->getAlignment() >= 4;
300 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
301 (store node:$val, node:$ptr), [{
302 return cast<StoreSDNode>(N)->getAlignment() >= 4;
304 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
305 return cast<LoadSDNode>(N)->getAlignment() >= 4;
307 def aligned4pre_store : PatFrag<
308 (ops node:$val, node:$base, node:$offset),
309 (pre_store node:$val, node:$base, node:$offset), [{
310 return cast<StoreSDNode>(N)->getAlignment() >= 4;
313 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
314 return cast<LoadSDNode>(N)->getAlignment() < 4;
316 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
317 (store node:$val, node:$ptr), [{
318 return cast<StoreSDNode>(N)->getAlignment() < 4;
320 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
321 return cast<LoadSDNode>(N)->getAlignment() < 4;
324 //===----------------------------------------------------------------------===//
325 // PowerPC Flag Definitions.
327 class isPPC64 { bit PPC64 = 1; }
328 class isDOT { bit RC = 1; }
330 class RegConstraint<string C> {
331 string Constraints = C;
333 class NoEncode<string E> {
334 string DisableEncoding = E;
338 //===----------------------------------------------------------------------===//
339 // PowerPC Operand Definitions.
341 // In the default PowerPC assembler syntax, registers are specified simply
342 // by number, so they cannot be distinguished from immediate values (without
343 // looking at the opcode). This means that the default operand matching logic
344 // for the asm parser does not work, and we need to specify custom matchers.
345 // Since those can only be specified with RegisterOperand classes and not
346 // directly on the RegisterClass, all instructions patterns used by the asm
347 // parser need to use a RegisterOperand (instead of a RegisterClass) for
348 // all their register operands.
349 // For this purpose, we define one RegisterOperand for each RegisterClass,
350 // using the same name as the class, just in lower case.
352 def PPCRegGPRCAsmOperand : AsmOperandClass {
353 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
355 def gprc : RegisterOperand<GPRC> {
356 let ParserMatchClass = PPCRegGPRCAsmOperand;
358 def PPCRegG8RCAsmOperand : AsmOperandClass {
359 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
361 def g8rc : RegisterOperand<G8RC> {
362 let ParserMatchClass = PPCRegG8RCAsmOperand;
364 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
365 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
367 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
368 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
370 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
371 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
373 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
374 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
376 def PPCRegF8RCAsmOperand : AsmOperandClass {
377 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
379 def f8rc : RegisterOperand<F8RC> {
380 let ParserMatchClass = PPCRegF8RCAsmOperand;
382 def PPCRegF4RCAsmOperand : AsmOperandClass {
383 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
385 def f4rc : RegisterOperand<F4RC> {
386 let ParserMatchClass = PPCRegF4RCAsmOperand;
388 def PPCRegVRRCAsmOperand : AsmOperandClass {
389 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
391 def vrrc : RegisterOperand<VRRC> {
392 let ParserMatchClass = PPCRegVRRCAsmOperand;
394 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
395 let Name = "RegCRBITRC"; let PredicateMethod = "isRegNumber";
397 def crbitrc : RegisterOperand<CRBITRC> {
398 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
400 def PPCRegCRRCAsmOperand : AsmOperandClass {
401 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
403 def crrc : RegisterOperand<CRRC> {
404 let ParserMatchClass = PPCRegCRRCAsmOperand;
407 def PPCS5ImmAsmOperand : AsmOperandClass {
408 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
409 let RenderMethod = "addImmOperands";
411 def s5imm : Operand<i32> {
412 let PrintMethod = "printS5ImmOperand";
413 let ParserMatchClass = PPCS5ImmAsmOperand;
415 def PPCU5ImmAsmOperand : AsmOperandClass {
416 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
417 let RenderMethod = "addImmOperands";
419 def u5imm : Operand<i32> {
420 let PrintMethod = "printU5ImmOperand";
421 let ParserMatchClass = PPCU5ImmAsmOperand;
423 def PPCU6ImmAsmOperand : AsmOperandClass {
424 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
425 let RenderMethod = "addImmOperands";
427 def u6imm : Operand<i32> {
428 let PrintMethod = "printU6ImmOperand";
429 let ParserMatchClass = PPCU6ImmAsmOperand;
431 def PPCS16ImmAsmOperand : AsmOperandClass {
432 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
433 let RenderMethod = "addImmOperands";
435 def s16imm : Operand<i32> {
436 let PrintMethod = "printS16ImmOperand";
437 let ParserMatchClass = PPCS16ImmAsmOperand;
439 def PPCU16ImmAsmOperand : AsmOperandClass {
440 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
441 let RenderMethod = "addImmOperands";
443 def u16imm : Operand<i32> {
444 let PrintMethod = "printU16ImmOperand";
445 let ParserMatchClass = PPCU16ImmAsmOperand;
447 def directbrtarget : Operand<OtherVT> {
448 let PrintMethod = "printBranchOperand";
449 let EncoderMethod = "getDirectBrEncoding";
451 def condbrtarget : Operand<OtherVT> {
452 let PrintMethod = "printBranchOperand";
453 let EncoderMethod = "getCondBrEncoding";
455 def calltarget : Operand<iPTR> {
456 let EncoderMethod = "getDirectBrEncoding";
458 def aaddr : Operand<iPTR> {
459 let PrintMethod = "printAbsAddrOperand";
461 def symbolHi: Operand<i32> {
462 let PrintMethod = "printS16ImmOperand";
463 let EncoderMethod = "getS16ImmEncoding";
464 let ParserMatchClass = PPCS16ImmAsmOperand;
466 def symbolLo: Operand<i32> {
467 let PrintMethod = "printS16ImmOperand";
468 let EncoderMethod = "getS16ImmEncoding";
469 let ParserMatchClass = PPCS16ImmAsmOperand;
471 def PPCCRBitMaskOperand : AsmOperandClass {
472 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
474 def crbitm: Operand<i8> {
475 let PrintMethod = "printcrbitm";
476 let EncoderMethod = "get_crbitm_encoding";
477 let ParserMatchClass = PPCCRBitMaskOperand;
480 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
481 def PPCRegGxRCNoR0Operand : AsmOperandClass {
482 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
484 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
485 let ParserMatchClass = PPCRegGxRCNoR0Operand;
487 // A version of ptr_rc usable with the asm parser.
488 def PPCRegGxRCOperand : AsmOperandClass {
489 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
491 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
492 let ParserMatchClass = PPCRegGxRCOperand;
495 def PPCDispRIOperand : AsmOperandClass {
496 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
497 let RenderMethod = "addImmOperands";
499 def dispRI : Operand<iPTR> {
500 let ParserMatchClass = PPCDispRIOperand;
502 def PPCDispRIXOperand : AsmOperandClass {
503 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
504 let RenderMethod = "addImmOperands";
506 def dispRIX : Operand<iPTR> {
507 let ParserMatchClass = PPCDispRIXOperand;
510 def memri : Operand<iPTR> {
511 let PrintMethod = "printMemRegImm";
512 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
513 let EncoderMethod = "getMemRIEncoding";
515 def memrr : Operand<iPTR> {
516 let PrintMethod = "printMemRegReg";
517 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
519 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
520 let PrintMethod = "printMemRegImm";
521 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
522 let EncoderMethod = "getMemRIXEncoding";
525 // A single-register address. This is used with the SjLj
526 // pseudo-instructions.
527 def memr : Operand<iPTR> {
528 let MIOperandInfo = (ops ptr_rc:$ptrreg);
531 // PowerPC Predicate operand.
532 def pred : Operand<OtherVT> {
533 let PrintMethod = "printPredicateOperand";
534 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
537 // Define PowerPC specific addressing mode.
538 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
539 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
540 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
541 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
543 // The address in a single register. This is used with the SjLj
544 // pseudo-instructions.
545 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
547 /// This is just the offset part of iaddr, used for preinc.
548 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
550 //===----------------------------------------------------------------------===//
551 // PowerPC Instruction Predicate Definitions.
552 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
553 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
554 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
556 //===----------------------------------------------------------------------===//
557 // PowerPC Multiclass Definitions.
559 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
560 string asmbase, string asmstr, InstrItinClass itin,
562 let BaseName = asmbase in {
563 def NAME : XForm_6<opcode, xo, OOL, IOL,
564 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
565 pattern>, RecFormRel;
567 def o : XForm_6<opcode, xo, OOL, IOL,
568 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
569 []>, isDOT, RecFormRel;
573 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
574 string asmbase, string asmstr, InstrItinClass itin,
576 let BaseName = asmbase in {
577 let Defs = [CARRY] in
578 def NAME : XForm_6<opcode, xo, OOL, IOL,
579 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
580 pattern>, RecFormRel;
581 let Defs = [CARRY, CR0] in
582 def o : XForm_6<opcode, xo, OOL, IOL,
583 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
584 []>, isDOT, RecFormRel;
588 multiclass XForm_10r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
589 string asmbase, string asmstr, InstrItinClass itin,
591 let BaseName = asmbase in {
592 def NAME : XForm_10<opcode, xo, OOL, IOL,
593 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
594 pattern>, RecFormRel;
596 def o : XForm_10<opcode, xo, OOL, IOL,
597 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
598 []>, isDOT, RecFormRel;
602 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
603 string asmbase, string asmstr, InstrItinClass itin,
605 let BaseName = asmbase in {
606 let Defs = [CARRY] in
607 def NAME : XForm_10<opcode, xo, OOL, IOL,
608 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
609 pattern>, RecFormRel;
610 let Defs = [CARRY, CR0] in
611 def o : XForm_10<opcode, xo, OOL, IOL,
612 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
613 []>, isDOT, RecFormRel;
617 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
618 string asmbase, string asmstr, InstrItinClass itin,
620 let BaseName = asmbase in {
621 def NAME : XForm_11<opcode, xo, OOL, IOL,
622 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
623 pattern>, RecFormRel;
625 def o : XForm_11<opcode, xo, OOL, IOL,
626 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
627 []>, isDOT, RecFormRel;
631 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
632 string asmbase, string asmstr, InstrItinClass itin,
634 let BaseName = asmbase in {
635 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
636 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
637 pattern>, RecFormRel;
639 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
640 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
641 []>, isDOT, RecFormRel;
645 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
646 string asmbase, string asmstr, InstrItinClass itin,
648 let BaseName = asmbase in {
649 let Defs = [CARRY] in
650 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
651 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
652 pattern>, RecFormRel;
653 let Defs = [CARRY, CR0] in
654 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
655 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
656 []>, isDOT, RecFormRel;
660 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
661 string asmbase, string asmstr, InstrItinClass itin,
663 let BaseName = asmbase in {
664 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
665 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
666 pattern>, RecFormRel;
668 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
669 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
670 []>, isDOT, RecFormRel;
674 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
675 string asmbase, string asmstr, InstrItinClass itin,
677 let BaseName = asmbase in {
678 let Defs = [CARRY] in
679 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
680 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
681 pattern>, RecFormRel;
682 let Defs = [CARRY, CR0] in
683 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
684 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
685 []>, isDOT, RecFormRel;
689 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
690 string asmbase, string asmstr, InstrItinClass itin,
692 let BaseName = asmbase in {
693 def NAME : MForm_2<opcode, OOL, IOL,
694 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
695 pattern>, RecFormRel;
697 def o : MForm_2<opcode, OOL, IOL,
698 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
699 []>, isDOT, RecFormRel;
703 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
704 string asmbase, string asmstr, InstrItinClass itin,
706 let BaseName = asmbase in {
707 def NAME : MDForm_1<opcode, xo, OOL, IOL,
708 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
709 pattern>, RecFormRel;
711 def o : MDForm_1<opcode, xo, OOL, IOL,
712 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
713 []>, isDOT, RecFormRel;
717 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
718 string asmbase, string asmstr, InstrItinClass itin,
720 let BaseName = asmbase in {
721 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
722 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
723 pattern>, RecFormRel;
725 def o : MDSForm_1<opcode, xo, OOL, IOL,
726 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
727 []>, isDOT, RecFormRel;
731 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
732 string asmbase, string asmstr, InstrItinClass itin,
734 let BaseName = asmbase in {
735 let Defs = [CARRY] in
736 def NAME : XSForm_1<opcode, xo, OOL, IOL,
737 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
738 pattern>, RecFormRel;
739 let Defs = [CARRY, CR0] in
740 def o : XSForm_1<opcode, xo, OOL, IOL,
741 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
742 []>, isDOT, RecFormRel;
746 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
747 string asmbase, string asmstr, InstrItinClass itin,
749 let BaseName = asmbase in {
750 def NAME : XForm_26<opcode, xo, OOL, IOL,
751 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
752 pattern>, RecFormRel;
754 def o : XForm_26<opcode, xo, OOL, IOL,
755 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
756 []>, isDOT, RecFormRel;
760 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
761 string asmbase, string asmstr, InstrItinClass itin,
763 let BaseName = asmbase in {
764 def NAME : AForm_1<opcode, xo, OOL, IOL,
765 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
766 pattern>, RecFormRel;
768 def o : AForm_1<opcode, xo, OOL, IOL,
769 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
770 []>, isDOT, RecFormRel;
774 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
775 string asmbase, string asmstr, InstrItinClass itin,
777 let BaseName = asmbase in {
778 def NAME : AForm_2<opcode, xo, OOL, IOL,
779 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
780 pattern>, RecFormRel;
782 def o : AForm_2<opcode, xo, OOL, IOL,
783 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
784 []>, isDOT, RecFormRel;
788 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
789 string asmbase, string asmstr, InstrItinClass itin,
791 let BaseName = asmbase in {
792 def NAME : AForm_3<opcode, xo, OOL, IOL,
793 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
794 pattern>, RecFormRel;
796 def o : AForm_3<opcode, xo, OOL, IOL,
797 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
798 []>, isDOT, RecFormRel;
802 //===----------------------------------------------------------------------===//
803 // PowerPC Instruction Definitions.
805 // Pseudo-instructions:
807 let hasCtrlDep = 1 in {
808 let Defs = [R1], Uses = [R1] in {
809 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
810 [(callseq_start timm:$amt)]>;
811 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
812 [(callseq_end timm:$amt1, timm:$amt2)]>;
815 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
816 "UPDATE_VRSAVE $rD, $rS", []>;
819 let Defs = [R1], Uses = [R1] in
820 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
822 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
824 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
825 // instruction selection into a branch sequence.
826 let usesCustomInserter = 1, // Expanded after instruction selection.
827 PPC970_Single = 1 in {
828 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
829 // because either operand might become the first operand in an isel, and
830 // that operand cannot be r0.
831 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
832 gprc_nor0:$T, gprc_nor0:$F,
833 i32imm:$BROPC), "#SELECT_CC_I4",
835 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
836 g8rc_nox0:$T, g8rc_nox0:$F,
837 i32imm:$BROPC), "#SELECT_CC_I8",
839 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
840 i32imm:$BROPC), "#SELECT_CC_F4",
842 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
843 i32imm:$BROPC), "#SELECT_CC_F8",
845 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
846 i32imm:$BROPC), "#SELECT_CC_VRRC",
850 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
851 // scavenge a register for it.
853 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
856 // RESTORE_CR - Indicate that we're restoring the CR register (previously
857 // spilled), so we'll need to scavenge a register for it.
859 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
862 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
863 let isReturn = 1, Uses = [LR, RM] in
864 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", BrB,
866 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
867 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
869 let isCodeGenOnly = 1 in
870 def BCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
871 "b${cond:cc}ctr ${cond:reg}", BrB, []>;
876 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
879 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
880 let isBarrier = 1 in {
881 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
886 // BCC represents an arbitrary conditional branch on a predicate.
887 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
888 // a two-value operand where a dag node expects two operands. :(
889 let isCodeGenOnly = 1 in {
890 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
891 "b${cond:cc} ${cond:reg}, $dst"
892 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
893 let isReturn = 1, Uses = [LR, RM] in
894 def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
895 "b${cond:cc}lr ${cond:reg}", BrB, []>;
897 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
898 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
900 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
905 let Defs = [CTR], Uses = [CTR] in {
906 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
908 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
913 // The unconditional BCL used by the SjLj setjmp code.
914 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
915 let Defs = [LR], Uses = [RM] in {
916 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
921 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
922 // Convenient aliases for call instructions
924 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
925 "bl $func", BrB, []>; // See Pat patterns below.
926 def BLA : IForm<18, 1, 1, (outs), (ins aaddr:$func),
927 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
929 let Uses = [CTR, RM] in {
930 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
931 "bctrl", BrB, [(PPCbctrl)]>,
932 Requires<[In32BitMode]>;
934 let isCodeGenOnly = 1 in
935 def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
936 "b${cond:cc}ctrl ${cond:reg}", BrB, []>;
940 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
941 def TCRETURNdi :Pseudo< (outs),
942 (ins calltarget:$dst, i32imm:$offset),
943 "#TC_RETURNd $dst $offset",
947 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
948 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
949 "#TC_RETURNa $func $offset",
950 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
952 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
953 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
954 "#TC_RETURNr $dst $offset",
958 let isCodeGenOnly = 1 in {
960 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
961 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
962 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
963 Requires<[In32BitMode]>;
967 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
968 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
969 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
975 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
976 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
977 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
981 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
982 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
984 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
985 Requires<[In32BitMode]>;
986 let isTerminator = 1 in
987 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
988 "#EH_SJLJ_LONGJMP32",
989 [(PPCeh_sjlj_longjmp addr:$buf)]>,
990 Requires<[In32BitMode]>;
993 let isBranch = 1, isTerminator = 1 in {
994 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
995 "#EH_SjLj_Setup\t$dst", []>;
999 let PPC970_Unit = 7 in {
1000 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1001 "sc $lev", BrB, [(PPCsc (i32 imm:$lev))]>;
1004 // DCB* instructions.
1005 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
1006 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1007 PPC970_DGroup_Single;
1008 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
1009 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1010 PPC970_DGroup_Single;
1011 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
1012 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1013 PPC970_DGroup_Single;
1014 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
1015 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1016 PPC970_DGroup_Single;
1017 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
1018 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1019 PPC970_DGroup_Single;
1020 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
1021 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1022 PPC970_DGroup_Single;
1023 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
1024 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1025 PPC970_DGroup_Single;
1026 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
1027 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1028 PPC970_DGroup_Single;
1030 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1031 (DCBT xoaddr:$dst)>;
1033 // Atomic operations
1034 let usesCustomInserter = 1 in {
1035 let Defs = [CR0] in {
1036 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1037 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1038 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1039 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1040 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1041 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1042 def ATOMIC_LOAD_AND_I8 : Pseudo<
1043 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1044 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1045 def ATOMIC_LOAD_OR_I8 : Pseudo<
1046 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1047 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1048 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1049 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1050 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1051 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1052 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1053 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1054 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1055 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1056 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1057 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1058 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1059 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1060 def ATOMIC_LOAD_AND_I16 : Pseudo<
1061 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1062 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1063 def ATOMIC_LOAD_OR_I16 : Pseudo<
1064 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1065 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1066 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1067 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1068 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1069 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1070 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1071 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1072 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1073 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1074 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1075 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1076 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1077 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1078 def ATOMIC_LOAD_AND_I32 : Pseudo<
1079 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1080 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1081 def ATOMIC_LOAD_OR_I32 : Pseudo<
1082 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1083 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1084 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1085 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1086 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1087 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1088 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1089 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1091 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1092 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1093 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1094 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1095 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1096 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1097 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1098 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1099 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1101 def ATOMIC_SWAP_I8 : Pseudo<
1102 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1103 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1104 def ATOMIC_SWAP_I16 : Pseudo<
1105 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1106 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1107 def ATOMIC_SWAP_I32 : Pseudo<
1108 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1109 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1113 // Instructions to support atomic operations
1114 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1115 "lwarx $rD, $src", LdStLWARX,
1116 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1119 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1120 "stwcx. $rS, $dst", LdStSTWCX,
1121 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1124 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1125 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
1127 //===----------------------------------------------------------------------===//
1128 // PPC32 Load Instructions.
1131 // Unindexed (r+i) Loads.
1132 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1133 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1134 "lbz $rD, $src", LdStLoad,
1135 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1136 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1137 "lha $rD, $src", LdStLHA,
1138 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1139 PPC970_DGroup_Cracked;
1140 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1141 "lhz $rD, $src", LdStLoad,
1142 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1143 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1144 "lwz $rD, $src", LdStLoad,
1145 [(set i32:$rD, (load iaddr:$src))]>;
1147 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1148 "lfs $rD, $src", LdStLFD,
1149 [(set f32:$rD, (load iaddr:$src))]>;
1150 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1151 "lfd $rD, $src", LdStLFD,
1152 [(set f64:$rD, (load iaddr:$src))]>;
1155 // Unindexed (r+i) Loads with Update (preinc).
1156 let mayLoad = 1, neverHasSideEffects = 1 in {
1157 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1158 "lbzu $rD, $addr", LdStLoadUpd,
1159 []>, RegConstraint<"$addr.reg = $ea_result">,
1160 NoEncode<"$ea_result">;
1162 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1163 "lhau $rD, $addr", LdStLHAU,
1164 []>, RegConstraint<"$addr.reg = $ea_result">,
1165 NoEncode<"$ea_result">;
1167 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1168 "lhzu $rD, $addr", LdStLoadUpd,
1169 []>, RegConstraint<"$addr.reg = $ea_result">,
1170 NoEncode<"$ea_result">;
1172 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1173 "lwzu $rD, $addr", LdStLoadUpd,
1174 []>, RegConstraint<"$addr.reg = $ea_result">,
1175 NoEncode<"$ea_result">;
1177 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1178 "lfsu $rD, $addr", LdStLFDU,
1179 []>, RegConstraint<"$addr.reg = $ea_result">,
1180 NoEncode<"$ea_result">;
1182 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1183 "lfdu $rD, $addr", LdStLFDU,
1184 []>, RegConstraint<"$addr.reg = $ea_result">,
1185 NoEncode<"$ea_result">;
1188 // Indexed (r+r) Loads with Update (preinc).
1189 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1191 "lbzux $rD, $addr", LdStLoadUpd,
1192 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1193 NoEncode<"$ea_result">;
1195 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1197 "lhaux $rD, $addr", LdStLHAU,
1198 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1199 NoEncode<"$ea_result">;
1201 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1203 "lhzux $rD, $addr", LdStLoadUpd,
1204 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1205 NoEncode<"$ea_result">;
1207 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1209 "lwzux $rD, $addr", LdStLoadUpd,
1210 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1211 NoEncode<"$ea_result">;
1213 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1215 "lfsux $rD, $addr", LdStLFDU,
1216 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1217 NoEncode<"$ea_result">;
1219 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1221 "lfdux $rD, $addr", LdStLFDU,
1222 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1223 NoEncode<"$ea_result">;
1227 // Indexed (r+r) Loads.
1229 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1230 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1231 "lbzx $rD, $src", LdStLoad,
1232 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1233 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1234 "lhax $rD, $src", LdStLHA,
1235 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1236 PPC970_DGroup_Cracked;
1237 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1238 "lhzx $rD, $src", LdStLoad,
1239 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1240 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1241 "lwzx $rD, $src", LdStLoad,
1242 [(set i32:$rD, (load xaddr:$src))]>;
1245 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1246 "lhbrx $rD, $src", LdStLoad,
1247 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1248 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1249 "lwbrx $rD, $src", LdStLoad,
1250 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1252 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1253 "lfsx $frD, $src", LdStLFD,
1254 [(set f32:$frD, (load xaddr:$src))]>;
1255 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1256 "lfdx $frD, $src", LdStLFD,
1257 [(set f64:$frD, (load xaddr:$src))]>;
1259 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1260 "lfiwax $frD, $src", LdStLFD,
1261 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1262 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1263 "lfiwzx $frD, $src", LdStLFD,
1264 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1267 //===----------------------------------------------------------------------===//
1268 // PPC32 Store Instructions.
1271 // Unindexed (r+i) Stores.
1272 let PPC970_Unit = 2 in {
1273 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1274 "stb $rS, $src", LdStStore,
1275 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1276 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1277 "sth $rS, $src", LdStStore,
1278 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1279 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1280 "stw $rS, $src", LdStStore,
1281 [(store i32:$rS, iaddr:$src)]>;
1282 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1283 "stfs $rS, $dst", LdStSTFD,
1284 [(store f32:$rS, iaddr:$dst)]>;
1285 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1286 "stfd $rS, $dst", LdStSTFD,
1287 [(store f64:$rS, iaddr:$dst)]>;
1290 // Unindexed (r+i) Stores with Update (preinc).
1291 let PPC970_Unit = 2, mayStore = 1 in {
1292 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1293 "stbu $rS, $dst", LdStStoreUpd, []>,
1294 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1295 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1296 "sthu $rS, $dst", LdStStoreUpd, []>,
1297 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1298 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1299 "stwu $rS, $dst", LdStStoreUpd, []>,
1300 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1301 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1302 "stfsu $rS, $dst", LdStSTFDU, []>,
1303 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1304 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1305 "stfdu $rS, $dst", LdStSTFDU, []>,
1306 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1309 // Patterns to match the pre-inc stores. We can't put the patterns on
1310 // the instruction definitions directly as ISel wants the address base
1311 // and offset to be separate operands, not a single complex operand.
1312 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1313 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1314 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1315 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1316 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1317 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1318 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1319 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1320 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1321 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1323 // Indexed (r+r) Stores.
1324 let PPC970_Unit = 2 in {
1325 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1326 "stbx $rS, $dst", LdStStore,
1327 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1328 PPC970_DGroup_Cracked;
1329 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1330 "sthx $rS, $dst", LdStStore,
1331 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1332 PPC970_DGroup_Cracked;
1333 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1334 "stwx $rS, $dst", LdStStore,
1335 [(store i32:$rS, xaddr:$dst)]>,
1336 PPC970_DGroup_Cracked;
1338 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1339 "sthbrx $rS, $dst", LdStStore,
1340 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1341 PPC970_DGroup_Cracked;
1342 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1343 "stwbrx $rS, $dst", LdStStore,
1344 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1345 PPC970_DGroup_Cracked;
1347 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1348 "stfiwx $frS, $dst", LdStSTFD,
1349 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1351 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1352 "stfsx $frS, $dst", LdStSTFD,
1353 [(store f32:$frS, xaddr:$dst)]>;
1354 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1355 "stfdx $frS, $dst", LdStSTFD,
1356 [(store f64:$frS, xaddr:$dst)]>;
1359 // Indexed (r+r) Stores with Update (preinc).
1360 let PPC970_Unit = 2, mayStore = 1 in {
1361 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1362 "stbux $rS, $dst", LdStStoreUpd, []>,
1363 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1364 PPC970_DGroup_Cracked;
1365 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1366 "sthux $rS, $dst", LdStStoreUpd, []>,
1367 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1368 PPC970_DGroup_Cracked;
1369 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1370 "stwux $rS, $dst", LdStStoreUpd, []>,
1371 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1372 PPC970_DGroup_Cracked;
1373 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1374 "stfsux $rS, $dst", LdStSTFDU, []>,
1375 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1376 PPC970_DGroup_Cracked;
1377 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1378 "stfdux $rS, $dst", LdStSTFDU, []>,
1379 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1380 PPC970_DGroup_Cracked;
1383 // Patterns to match the pre-inc stores. We can't put the patterns on
1384 // the instruction definitions directly as ISel wants the address base
1385 // and offset to be separate operands, not a single complex operand.
1386 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1387 (STBUX $rS, $ptrreg, $ptroff)>;
1388 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1389 (STHUX $rS, $ptrreg, $ptroff)>;
1390 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1391 (STWUX $rS, $ptrreg, $ptroff)>;
1392 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1393 (STFSUX $rS, $ptrreg, $ptroff)>;
1394 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1395 (STFDUX $rS, $ptrreg, $ptroff)>;
1397 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
1401 //===----------------------------------------------------------------------===//
1402 // PPC32 Arithmetic Instructions.
1405 let PPC970_Unit = 1 in { // FXU Operations.
1406 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, symbolLo:$imm),
1407 "addi $rD, $rA, $imm", IntSimple,
1408 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1409 let BaseName = "addic" in {
1410 let Defs = [CARRY] in
1411 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1412 "addic $rD, $rA, $imm", IntGeneral,
1413 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1414 RecFormRel, PPC970_DGroup_Cracked;
1415 let Defs = [CARRY, CR0] in
1416 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1417 "addic. $rD, $rA, $imm", IntGeneral,
1418 []>, isDOT, RecFormRel;
1420 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, symbolHi:$imm),
1421 "addis $rD, $rA, $imm", IntSimple,
1422 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1423 let isCodeGenOnly = 1 in
1424 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, symbolLo:$sym),
1425 "la $rD, $sym($rA)", IntGeneral,
1426 [(set i32:$rD, (add i32:$rA,
1427 (PPClo tglobaladdr:$sym, 0)))]>;
1428 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1429 "mulli $rD, $rA, $imm", IntMulLI,
1430 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1431 let Defs = [CARRY] in
1432 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1433 "subfic $rD, $rA, $imm", IntGeneral,
1434 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1436 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1437 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins symbolLo:$imm),
1438 "li $rD, $imm", IntSimple,
1439 [(set i32:$rD, imm32SExt16:$imm)]>;
1440 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins symbolHi:$imm),
1441 "lis $rD, $imm", IntSimple,
1442 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1446 let PPC970_Unit = 1 in { // FXU Operations.
1447 let Defs = [CR0] in {
1448 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1449 "andi. $dst, $src1, $src2", IntGeneral,
1450 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1452 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1453 "andis. $dst, $src1, $src2", IntGeneral,
1454 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1457 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1458 "ori $dst, $src1, $src2", IntSimple,
1459 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1460 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1461 "oris $dst, $src1, $src2", IntSimple,
1462 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1463 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1464 "xori $dst, $src1, $src2", IntSimple,
1465 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1466 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1467 "xoris $dst, $src1, $src2", IntSimple,
1468 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1469 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1471 let isCompare = 1, neverHasSideEffects = 1 in {
1472 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1473 "cmpwi $crD, $rA, $imm", IntCompare>;
1474 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1475 "cmplwi $dst, $src1, $src2", IntCompare>;
1479 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1480 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1481 "nand", "$rA, $rS, $rB", IntSimple,
1482 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1483 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1484 "and", "$rA, $rS, $rB", IntSimple,
1485 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1486 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1487 "andc", "$rA, $rS, $rB", IntSimple,
1488 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1489 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1490 "or", "$rA, $rS, $rB", IntSimple,
1491 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1492 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1493 "nor", "$rA, $rS, $rB", IntSimple,
1494 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1495 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1496 "orc", "$rA, $rS, $rB", IntSimple,
1497 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1498 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1499 "eqv", "$rA, $rS, $rB", IntSimple,
1500 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1501 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1502 "xor", "$rA, $rS, $rB", IntSimple,
1503 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1504 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1505 "slw", "$rA, $rS, $rB", IntGeneral,
1506 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1507 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1508 "srw", "$rA, $rS, $rB", IntGeneral,
1509 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1510 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1511 "sraw", "$rA, $rS, $rB", IntShift,
1512 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1515 let PPC970_Unit = 1 in { // FXU Operations.
1516 let neverHasSideEffects = 1 in {
1517 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1518 "srawi", "$rA, $rS, $SH", IntShift,
1519 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1520 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1521 "cntlzw", "$rA, $rS", IntGeneral,
1522 [(set i32:$rA, (ctlz i32:$rS))]>;
1523 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1524 "extsb", "$rA, $rS", IntSimple,
1525 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1526 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1527 "extsh", "$rA, $rS", IntSimple,
1528 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1530 let isCompare = 1, neverHasSideEffects = 1 in {
1531 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1532 "cmpw $crD, $rA, $rB", IntCompare>;
1533 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1534 "cmplw $crD, $rA, $rB", IntCompare>;
1537 let PPC970_Unit = 3 in { // FPU Operations.
1538 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1539 // "fcmpo $crD, $fA, $fB", FPCompare>;
1540 let isCompare = 1, neverHasSideEffects = 1 in {
1541 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1542 "fcmpu $crD, $fA, $fB", FPCompare>;
1543 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1544 "fcmpu $crD, $fA, $fB", FPCompare>;
1547 let Uses = [RM] in {
1548 let neverHasSideEffects = 1 in {
1549 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1550 "fctiwz", "$frD, $frB", FPGeneral,
1551 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1553 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1554 "frsp", "$frD, $frB", FPGeneral,
1555 [(set f32:$frD, (fround f64:$frB))]>;
1557 // The frin -> nearbyint mapping is valid only in fast-math mode.
1558 let Interpretation64Bit = 1 in
1559 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1560 "frin", "$frD, $frB", FPGeneral,
1561 [(set f64:$frD, (fnearbyint f64:$frB))]>;
1562 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1563 "frin", "$frD, $frB", FPGeneral,
1564 [(set f32:$frD, (fnearbyint f32:$frB))]>;
1567 // These pseudos expand to rint but also set FE_INEXACT when the result does
1568 // not equal the argument.
1569 let usesCustomInserter = 1, Defs = [RM] in { // FIXME: Model FPSCR!
1570 def FRINDrint : Pseudo<(outs f8rc:$frD), (ins f8rc:$frB),
1571 "#FRINDrint", [(set f64:$frD, (frint f64:$frB))]>;
1572 def FRINSrint : Pseudo<(outs f4rc:$frD), (ins f4rc:$frB),
1573 "#FRINSrint", [(set f32:$frD, (frint f32:$frB))]>;
1576 let neverHasSideEffects = 1 in {
1577 let Interpretation64Bit = 1 in
1578 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1579 "frip", "$frD, $frB", FPGeneral,
1580 [(set f64:$frD, (fceil f64:$frB))]>;
1581 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1582 "frip", "$frD, $frB", FPGeneral,
1583 [(set f32:$frD, (fceil f32:$frB))]>;
1584 let Interpretation64Bit = 1 in
1585 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1586 "friz", "$frD, $frB", FPGeneral,
1587 [(set f64:$frD, (ftrunc f64:$frB))]>;
1588 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1589 "friz", "$frD, $frB", FPGeneral,
1590 [(set f32:$frD, (ftrunc f32:$frB))]>;
1591 let Interpretation64Bit = 1 in
1592 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1593 "frim", "$frD, $frB", FPGeneral,
1594 [(set f64:$frD, (ffloor f64:$frB))]>;
1595 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1596 "frim", "$frD, $frB", FPGeneral,
1597 [(set f32:$frD, (ffloor f32:$frB))]>;
1599 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1600 "fsqrt", "$frD, $frB", FPSqrt,
1601 [(set f64:$frD, (fsqrt f64:$frB))]>;
1602 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1603 "fsqrts", "$frD, $frB", FPSqrt,
1604 [(set f32:$frD, (fsqrt f32:$frB))]>;
1609 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1610 /// often coalesced away and we don't want the dispatch group builder to think
1611 /// that they will fill slots (which could cause the load of a LSU reject to
1612 /// sneak into a d-group with a store).
1613 let neverHasSideEffects = 1 in
1614 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1615 "fmr", "$frD, $frB", FPGeneral,
1616 []>, // (set f32:$frD, f32:$frB)
1619 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1620 // These are artificially split into two different forms, for 4/8 byte FP.
1621 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1622 "fabs", "$frD, $frB", FPGeneral,
1623 [(set f32:$frD, (fabs f32:$frB))]>;
1624 let Interpretation64Bit = 1 in
1625 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1626 "fabs", "$frD, $frB", FPGeneral,
1627 [(set f64:$frD, (fabs f64:$frB))]>;
1628 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1629 "fnabs", "$frD, $frB", FPGeneral,
1630 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1631 let Interpretation64Bit = 1 in
1632 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1633 "fnabs", "$frD, $frB", FPGeneral,
1634 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1635 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1636 "fneg", "$frD, $frB", FPGeneral,
1637 [(set f32:$frD, (fneg f32:$frB))]>;
1638 let Interpretation64Bit = 1 in
1639 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1640 "fneg", "$frD, $frB", FPGeneral,
1641 [(set f64:$frD, (fneg f64:$frB))]>;
1643 // Reciprocal estimates.
1644 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1645 "fre", "$frD, $frB", FPGeneral,
1646 [(set f64:$frD, (PPCfre f64:$frB))]>;
1647 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1648 "fres", "$frD, $frB", FPGeneral,
1649 [(set f32:$frD, (PPCfre f32:$frB))]>;
1650 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1651 "frsqrte", "$frD, $frB", FPGeneral,
1652 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1653 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1654 "frsqrtes", "$frD, $frB", FPGeneral,
1655 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1658 // XL-Form instructions. condition register logical ops.
1660 let neverHasSideEffects = 1 in
1661 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1662 "mcrf $BF, $BFA", BrMCR>,
1663 PPC970_DGroup_First, PPC970_Unit_CRU;
1665 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
1666 (ins crbitrc:$CRA, crbitrc:$CRB),
1667 "creqv $CRD, $CRA, $CRB", BrCR,
1670 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
1671 (ins crbitrc:$CRA, crbitrc:$CRB),
1672 "cror $CRD, $CRA, $CRB", BrCR,
1675 let isCodeGenOnly = 1 in {
1676 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
1677 "creqv $dst, $dst, $dst", BrCR,
1680 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
1681 "crxor $dst, $dst, $dst", BrCR,
1684 let Defs = [CR1EQ], CRD = 6 in {
1685 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1686 "creqv 6, 6, 6", BrCR,
1689 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1690 "crxor 6, 6, 6", BrCR,
1695 // XFX-Form instructions. Instructions that deal with SPRs.
1697 let Uses = [CTR] in {
1698 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
1699 "mfctr $rT", SprMFSPR>,
1700 PPC970_DGroup_First, PPC970_Unit_FXU;
1702 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1703 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1704 "mtctr $rS", SprMTSPR>,
1705 PPC970_DGroup_First, PPC970_Unit_FXU;
1707 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
1708 let Pattern = [(int_ppc_mtctr i32:$rS)] in
1709 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1710 "mtctr $rS", SprMTSPR>,
1711 PPC970_DGroup_First, PPC970_Unit_FXU;
1714 let Defs = [LR] in {
1715 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
1716 "mtlr $rS", SprMTSPR>,
1717 PPC970_DGroup_First, PPC970_Unit_FXU;
1719 let Uses = [LR] in {
1720 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
1721 "mflr $rT", SprMFSPR>,
1722 PPC970_DGroup_First, PPC970_Unit_FXU;
1725 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1726 // a GPR on the PPC970. As such, copies in and out have the same performance
1727 // characteristics as an OR instruction.
1728 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
1729 "mtspr 256, $rS", IntGeneral>,
1730 PPC970_DGroup_Single, PPC970_Unit_FXU;
1731 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
1732 "mfspr $rT, 256", IntGeneral>,
1733 PPC970_DGroup_First, PPC970_Unit_FXU;
1735 let isCodeGenOnly = 1 in {
1736 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1737 (outs VRSAVERC:$reg), (ins gprc:$rS),
1738 "mtspr 256, $rS", IntGeneral>,
1739 PPC970_DGroup_Single, PPC970_Unit_FXU;
1740 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
1741 (ins VRSAVERC:$reg),
1742 "mfspr $rT, 256", IntGeneral>,
1743 PPC970_DGroup_First, PPC970_Unit_FXU;
1746 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1747 // so we'll need to scavenge a register for it.
1749 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1750 "#SPILL_VRSAVE", []>;
1752 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1753 // spilled), so we'll need to scavenge a register for it.
1755 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1756 "#RESTORE_VRSAVE", []>;
1758 let neverHasSideEffects = 1 in {
1759 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins gprc:$rS),
1760 "mtcrf $FXM, $rS", BrMCRX>,
1761 PPC970_MicroCode, PPC970_Unit_CRU;
1763 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1764 // declaring that here gives the local register allocator problems with this:
1766 // MFCR <kill of whatever preg got assigned to vreg>
1767 // while not declaring it breaks DeadMachineInstructionElimination.
1768 // As it turns out, in all cases where we currently use this,
1769 // we're only interested in one subregister of it. Represent this in the
1770 // instruction to keep the register allocator from becoming confused.
1772 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1773 let isCodeGenOnly = 1 in
1774 def MFCRpseud: XFXForm_3<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
1775 "#MFCRpseud", SprMFCR>,
1776 PPC970_MicroCode, PPC970_Unit_CRU;
1778 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
1779 "mfocrf $rT, $FXM", SprMFCR>,
1780 PPC970_DGroup_First, PPC970_Unit_CRU;
1781 } // neverHasSideEffects = 1
1783 let neverHasSideEffects = 1 in
1784 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
1785 "mfcr $rT", SprMFCR>,
1786 PPC970_MicroCode, PPC970_Unit_CRU;
1788 // Pseudo instruction to perform FADD in round-to-zero mode.
1789 let usesCustomInserter = 1, Uses = [RM] in {
1790 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
1791 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
1794 // The above pseudo gets expanded to make use of the following instructions
1795 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
1796 let Uses = [RM], Defs = [RM] in {
1797 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1798 "mtfsb0 $FM", IntMTFSB0, []>,
1799 PPC970_DGroup_Single, PPC970_Unit_FPU;
1800 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1801 "mtfsb1 $FM", IntMTFSB0, []>,
1802 PPC970_DGroup_Single, PPC970_Unit_FPU;
1803 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
1804 "mtfsf $FM, $rT", IntMTFSB0, []>,
1805 PPC970_DGroup_Single, PPC970_Unit_FPU;
1807 let Uses = [RM] in {
1808 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
1809 "mffs $rT", IntMFFS,
1810 [(set f64:$rT, (PPCmffs))]>,
1811 PPC970_DGroup_Single, PPC970_Unit_FPU;
1815 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1816 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1818 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1819 "add", "$rT, $rA, $rB", IntSimple,
1820 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
1821 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1822 "addc", "$rT, $rA, $rB", IntGeneral,
1823 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
1824 PPC970_DGroup_Cracked;
1825 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1826 "divw", "$rT, $rA, $rB", IntDivW,
1827 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
1828 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1829 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1830 "divwu", "$rT, $rA, $rB", IntDivW,
1831 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
1832 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1833 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1834 "mulhw", "$rT, $rA, $rB", IntMulHW,
1835 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
1836 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1837 "mulhwu", "$rT, $rA, $rB", IntMulHWU,
1838 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
1839 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1840 "mullw", "$rT, $rA, $rB", IntMulHW,
1841 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
1842 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1843 "subf", "$rT, $rA, $rB", IntGeneral,
1844 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
1845 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1846 "subfc", "$rT, $rA, $rB", IntGeneral,
1847 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
1848 PPC970_DGroup_Cracked;
1849 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
1850 "neg", "$rT, $rA", IntSimple,
1851 [(set i32:$rT, (ineg i32:$rA))]>;
1852 let Uses = [CARRY] in {
1853 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1854 "adde", "$rT, $rA, $rB", IntGeneral,
1855 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
1856 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
1857 "addme", "$rT, $rA", IntGeneral,
1858 [(set i32:$rT, (adde i32:$rA, -1))]>;
1859 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
1860 "addze", "$rT, $rA", IntGeneral,
1861 [(set i32:$rT, (adde i32:$rA, 0))]>;
1862 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1863 "subfe", "$rT, $rA, $rB", IntGeneral,
1864 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
1865 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
1866 "subfme", "$rT, $rA", IntGeneral,
1867 [(set i32:$rT, (sube -1, i32:$rA))]>;
1868 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
1869 "subfze", "$rT, $rA", IntGeneral,
1870 [(set i32:$rT, (sube 0, i32:$rA))]>;
1874 // A-Form instructions. Most of the instructions executed in the FPU are of
1877 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1878 let Uses = [RM] in {
1879 defm FMADD : AForm_1r<63, 29,
1880 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
1881 "fmadd", "$FRT, $FRA, $FRC, $FRB", FPFused,
1882 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
1883 defm FMADDS : AForm_1r<59, 29,
1884 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
1885 "fmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1886 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
1887 defm FMSUB : AForm_1r<63, 28,
1888 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
1889 "fmsub", "$FRT, $FRA, $FRC, $FRB", FPFused,
1891 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
1892 defm FMSUBS : AForm_1r<59, 28,
1893 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
1894 "fmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1896 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
1897 defm FNMADD : AForm_1r<63, 31,
1898 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
1899 "fnmadd", "$FRT, $FRA, $FRC, $FRB", FPFused,
1901 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
1902 defm FNMADDS : AForm_1r<59, 31,
1903 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
1904 "fnmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1906 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
1907 defm FNMSUB : AForm_1r<63, 30,
1908 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
1909 "fnmsub", "$FRT, $FRA, $FRC, $FRB", FPFused,
1910 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
1911 (fneg f64:$FRB))))]>;
1912 defm FNMSUBS : AForm_1r<59, 30,
1913 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
1914 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1915 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
1916 (fneg f32:$FRB))))]>;
1918 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1919 // having 4 of these, force the comparison to always be an 8-byte double (code
1920 // should use an FMRSD if the input comparison value really wants to be a float)
1921 // and 4/8 byte forms for the result and operand type..
1922 let Interpretation64Bit = 1 in
1923 defm FSELD : AForm_1r<63, 23,
1924 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
1925 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1926 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
1927 defm FSELS : AForm_1r<63, 23,
1928 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
1929 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1930 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
1931 let Uses = [RM] in {
1932 defm FADD : AForm_2r<63, 21,
1933 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
1934 "fadd", "$FRT, $FRA, $FRB", FPAddSub,
1935 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
1936 defm FADDS : AForm_2r<59, 21,
1937 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
1938 "fadds", "$FRT, $FRA, $FRB", FPGeneral,
1939 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
1940 defm FDIV : AForm_2r<63, 18,
1941 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
1942 "fdiv", "$FRT, $FRA, $FRB", FPDivD,
1943 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
1944 defm FDIVS : AForm_2r<59, 18,
1945 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
1946 "fdivs", "$FRT, $FRA, $FRB", FPDivS,
1947 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
1948 defm FMUL : AForm_3r<63, 25,
1949 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
1950 "fmul", "$FRT, $FRA, $FRC", FPFused,
1951 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
1952 defm FMULS : AForm_3r<59, 25,
1953 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
1954 "fmuls", "$FRT, $FRA, $FRC", FPGeneral,
1955 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
1956 defm FSUB : AForm_2r<63, 20,
1957 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
1958 "fsub", "$FRT, $FRA, $FRB", FPAddSub,
1959 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
1960 defm FSUBS : AForm_2r<59, 20,
1961 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
1962 "fsubs", "$FRT, $FRA, $FRB", FPGeneral,
1963 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
1967 let neverHasSideEffects = 1 in {
1968 let PPC970_Unit = 1 in { // FXU Operations.
1970 def ISEL : AForm_4<31, 15,
1971 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
1972 "isel $rT, $rA, $rB, $cond", IntGeneral,
1976 let PPC970_Unit = 1 in { // FXU Operations.
1977 // M-Form instructions. rotate and mask instructions.
1979 let isCommutable = 1 in {
1980 // RLWIMI can be commuted if the rotate amount is zero.
1981 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
1982 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
1983 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", IntRotate,
1984 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1987 let BaseName = "rlwinm" in {
1988 def RLWINM : MForm_2<21,
1989 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1990 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1993 def RLWINMo : MForm_2<21,
1994 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1995 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1996 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
1998 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
1999 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2000 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IntGeneral,
2003 } // neverHasSideEffects = 1
2005 //===----------------------------------------------------------------------===//
2006 // PowerPC Instruction Patterns
2009 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2010 def : Pat<(i32 imm:$imm),
2011 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2013 // Implement the 'not' operation with the NOR instruction.
2014 def NOT : Pat<(not i32:$in),
2017 // ADD an arbitrary immediate.
2018 def : Pat<(add i32:$in, imm:$imm),
2019 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2020 // OR an arbitrary immediate.
2021 def : Pat<(or i32:$in, imm:$imm),
2022 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2023 // XOR an arbitrary immediate.
2024 def : Pat<(xor i32:$in, imm:$imm),
2025 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2027 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2028 (SUBFIC $in, imm:$imm)>;
2031 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2032 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2033 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2034 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2037 def : Pat<(rotl i32:$in, i32:$sh),
2038 (RLWNM $in, $sh, 0, 31)>;
2039 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2040 (RLWINM $in, imm:$imm, 0, 31)>;
2043 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2044 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2047 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2048 (BL tglobaladdr:$dst)>;
2049 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2050 (BL texternalsym:$dst)>;
2053 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2054 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2056 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2057 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2059 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2060 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2064 // Hi and Lo for Darwin Global Addresses.
2065 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2066 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2067 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2068 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2069 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2070 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2071 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2072 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2073 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2074 (ADDIS $in, tglobaltlsaddr:$g)>;
2075 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2076 (ADDI $in, tglobaltlsaddr:$g)>;
2077 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2078 (ADDIS $in, tglobaladdr:$g)>;
2079 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2080 (ADDIS $in, tconstpool:$g)>;
2081 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2082 (ADDIS $in, tjumptable:$g)>;
2083 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2084 (ADDIS $in, tblockaddress:$g)>;
2086 // Standard shifts. These are represented separately from the real shifts above
2087 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2089 def : Pat<(sra i32:$rS, i32:$rB),
2091 def : Pat<(srl i32:$rS, i32:$rB),
2093 def : Pat<(shl i32:$rS, i32:$rB),
2096 def : Pat<(zextloadi1 iaddr:$src),
2098 def : Pat<(zextloadi1 xaddr:$src),
2100 def : Pat<(extloadi1 iaddr:$src),
2102 def : Pat<(extloadi1 xaddr:$src),
2104 def : Pat<(extloadi8 iaddr:$src),
2106 def : Pat<(extloadi8 xaddr:$src),
2108 def : Pat<(extloadi16 iaddr:$src),
2110 def : Pat<(extloadi16 xaddr:$src),
2112 def : Pat<(f64 (extloadf32 iaddr:$src)),
2113 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2114 def : Pat<(f64 (extloadf32 xaddr:$src)),
2115 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2117 def : Pat<(f64 (fextend f32:$src)),
2118 (COPY_TO_REGCLASS $src, F8RC)>;
2120 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
2122 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2123 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2124 (FNMSUB $A, $C, $B)>;
2125 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2126 (FNMSUB $A, $C, $B)>;
2127 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2128 (FNMSUBS $A, $C, $B)>;
2129 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2130 (FNMSUBS $A, $C, $B)>;
2132 include "PPCInstrAltivec.td"
2133 include "PPCInstr64Bit.td"
2136 //===----------------------------------------------------------------------===//
2137 // PowerPC Instructions used for assembler/disassembler only
2140 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
2141 "isync", SprISYNC, []>;
2143 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
2144 "icbi $src", LdStICBI, []>;
2146 //===----------------------------------------------------------------------===//
2147 // PowerPC Assembler Instruction Aliases
2150 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
2151 // These are aliases that require C++ handling to convert to the target
2152 // instruction, while InstAliases can be handled directly by tblgen.
2153 class PPCAsmPseudo<string asm, dag iops>
2155 let Namespace = "PPC";
2156 bit PPC64 = 0; // Default value, override with isPPC64
2158 let OutOperandList = (outs);
2159 let InOperandList = iops;
2161 let AsmString = asm;
2162 let isAsmParserOnly = 1;
2166 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2168 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
2169 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2170 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
2171 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2172 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
2173 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2174 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
2175 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2177 def : InstAlias<"blt $cc, $dst", (BCC 12, crrc:$cc, condbrtarget:$dst)>;
2178 def : InstAlias<"bgt $cc, $dst", (BCC 44, crrc:$cc, condbrtarget:$dst)>;
2179 def : InstAlias<"beq $cc, $dst", (BCC 76, crrc:$cc, condbrtarget:$dst)>;
2180 def : InstAlias<"bun $cc, $dst", (BCC 108, crrc:$cc, condbrtarget:$dst)>;
2181 def : InstAlias<"bso $cc, $dst", (BCC 108, crrc:$cc, condbrtarget:$dst)>;
2182 def : InstAlias<"bge $cc, $dst", (BCC 4, crrc:$cc, condbrtarget:$dst)>;
2183 def : InstAlias<"bnl $cc, $dst", (BCC 4, crrc:$cc, condbrtarget:$dst)>;
2184 def : InstAlias<"ble $cc, $dst", (BCC 36, crrc:$cc, condbrtarget:$dst)>;
2185 def : InstAlias<"bng $cc, $dst", (BCC 36, crrc:$cc, condbrtarget:$dst)>;
2186 def : InstAlias<"bne $cc, $dst", (BCC 68, crrc:$cc, condbrtarget:$dst)>;
2187 def : InstAlias<"bnu $cc, $dst", (BCC 100, crrc:$cc, condbrtarget:$dst)>;
2188 def : InstAlias<"bns $cc, $dst", (BCC 100, crrc:$cc, condbrtarget:$dst)>;
2190 def : InstAlias<"bltlr $cc", (BCLR 12, crrc:$cc)>;
2191 def : InstAlias<"bgtlr $cc", (BCLR 44, crrc:$cc)>;
2192 def : InstAlias<"beqlr $cc", (BCLR 76, crrc:$cc)>;
2193 def : InstAlias<"bunlr $cc", (BCLR 108, crrc:$cc)>;
2194 def : InstAlias<"bsolr $cc", (BCLR 108, crrc:$cc)>;
2195 def : InstAlias<"bgelr $cc", (BCLR 4, crrc:$cc)>;
2196 def : InstAlias<"bnllr $cc", (BCLR 4, crrc:$cc)>;
2197 def : InstAlias<"blelr $cc", (BCLR 36, crrc:$cc)>;
2198 def : InstAlias<"bnglr $cc", (BCLR 36, crrc:$cc)>;
2199 def : InstAlias<"bnelr $cc", (BCLR 68, crrc:$cc)>;
2200 def : InstAlias<"bnulr $cc", (BCLR 100, crrc:$cc)>;
2201 def : InstAlias<"bnslr $cc", (BCLR 100, crrc:$cc)>;
2203 def : InstAlias<"bltctr $cc", (BCCTR 12, crrc:$cc)>;
2204 def : InstAlias<"bgtctr $cc", (BCCTR 44, crrc:$cc)>;
2205 def : InstAlias<"beqctr $cc", (BCCTR 76, crrc:$cc)>;
2206 def : InstAlias<"bunctr $cc", (BCCTR 108, crrc:$cc)>;
2207 def : InstAlias<"bsoctr $cc", (BCCTR 108, crrc:$cc)>;
2208 def : InstAlias<"bgectr $cc", (BCCTR 4, crrc:$cc)>;
2209 def : InstAlias<"bnlctr $cc", (BCCTR 4, crrc:$cc)>;
2210 def : InstAlias<"blectr $cc", (BCCTR 36, crrc:$cc)>;
2211 def : InstAlias<"bngctr $cc", (BCCTR 36, crrc:$cc)>;
2212 def : InstAlias<"bnectr $cc", (BCCTR 68, crrc:$cc)>;
2213 def : InstAlias<"bnuctr $cc", (BCCTR 100, crrc:$cc)>;
2214 def : InstAlias<"bnsctr $cc", (BCCTR 100, crrc:$cc)>;
2216 def : InstAlias<"bltctrl $cc", (BCCTRL 12, crrc:$cc)>;
2217 def : InstAlias<"bgtctrl $cc", (BCCTRL 44, crrc:$cc)>;
2218 def : InstAlias<"beqctrl $cc", (BCCTRL 76, crrc:$cc)>;
2219 def : InstAlias<"bunctrl $cc", (BCCTRL 108, crrc:$cc)>;
2220 def : InstAlias<"bsoctrl $cc", (BCCTRL 108, crrc:$cc)>;
2221 def : InstAlias<"bgectrl $cc", (BCCTRL 4, crrc:$cc)>;
2222 def : InstAlias<"bnlctrl $cc", (BCCTRL 4, crrc:$cc)>;
2223 def : InstAlias<"blectrl $cc", (BCCTRL 36, crrc:$cc)>;
2224 def : InstAlias<"bngctrl $cc", (BCCTRL 36, crrc:$cc)>;
2225 def : InstAlias<"bnectrl $cc", (BCCTRL 68, crrc:$cc)>;
2226 def : InstAlias<"bnuctrl $cc", (BCCTRL 100, crrc:$cc)>;
2227 def : InstAlias<"bnsctrl $cc", (BCCTRL 100, crrc:$cc)>;