1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
50 SDTCisPtrTy<0>, SDTCisVT<1, i32>
53 def tocentry32 : Operand<iPTR> {
54 let MIOperandInfo = (ops i32imm:$imm);
57 def SDT_PPCqvfperm : SDTypeProfile<1, 3, [
58 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>
60 def SDT_PPCqvgpci : SDTypeProfile<1, 1, [
61 SDTCisVec<0>, SDTCisInt<1>
63 def SDT_PPCqvaligni : SDTypeProfile<1, 3, [
64 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>
66 def SDT_PPCqvesplati : SDTypeProfile<1, 2, [
67 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
70 def SDT_PPCqbflt : SDTypeProfile<1, 1, [
71 SDTCisVec<0>, SDTCisVec<1>
74 def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
75 SDTCisVec<0>, SDTCisPtrTy<1>
78 //===----------------------------------------------------------------------===//
79 // PowerPC specific DAG Nodes.
82 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
83 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
85 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
86 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
87 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
88 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
89 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
90 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
91 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
92 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
93 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
94 [SDNPHasChain, SDNPMayStore]>;
95 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
96 [SDNPHasChain, SDNPMayLoad]>;
97 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
98 [SDNPHasChain, SDNPMayLoad]>;
100 // Extract FPSCR (not modeled at the DAG level).
101 def PPCmffs : SDNode<"PPCISD::MFFS",
102 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
104 // Perform FADD in round-to-zero mode.
105 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
108 def PPCfsel : SDNode<"PPCISD::FSEL",
109 // Type constraint for fsel.
110 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
111 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
113 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
114 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
115 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp,
116 [SDNPMayLoad, SDNPMemOperand]>;
117 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
118 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
120 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
122 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
123 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
125 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
126 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
127 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
128 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
129 def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
130 SDTypeProfile<1, 3, [
131 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
132 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
133 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
134 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
135 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
136 def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
137 SDTypeProfile<1, 3, [
138 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
139 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
140 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
141 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
143 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
145 def PPCqvfperm : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
146 def PPCqvgpci : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
147 def PPCqvaligni : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
148 def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;
150 def PPCqbflt : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>;
152 def PPCqvlfsb : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb,
153 [SDNPHasChain, SDNPMayLoad]>;
155 def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
157 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
158 // amounts. These nodes are generated by the multi-precision shift code.
159 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
160 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
161 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
163 // These are target-independent nodes, but have target-specific formats.
164 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
165 [SDNPHasChain, SDNPOutGlue]>;
166 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
167 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
169 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
170 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
171 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
173 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
174 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
176 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
177 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
178 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
179 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
181 def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
182 SDTypeProfile<0, 1, []>,
183 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
186 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
187 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
189 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
190 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
192 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
193 SDTypeProfile<1, 1, [SDTCisInt<0>,
195 [SDNPHasChain, SDNPSideEffect]>;
196 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
197 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
198 [SDNPHasChain, SDNPSideEffect]>;
200 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
201 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
202 [SDNPHasChain, SDNPSideEffect]>;
204 def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone,
205 [SDNPHasChain, SDNPSideEffect]>;
206 def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>;
207 def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc,
208 [SDNPHasChain, SDNPSideEffect]>;
210 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
211 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
213 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
214 [SDNPHasChain, SDNPOptInGlue]>;
216 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
217 [SDNPHasChain, SDNPMayLoad]>;
218 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
219 [SDNPHasChain, SDNPMayStore]>;
221 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
222 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
223 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
224 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
225 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
227 // Instructions to support dynamic alloca.
228 def SDTDynOp : SDTypeProfile<1, 2, []>;
229 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
231 //===----------------------------------------------------------------------===//
232 // PowerPC specific transformation functions and pattern fragments.
235 def SHL32 : SDNodeXForm<imm, [{
236 // Transformation function: 31 - imm
237 return getI32Imm(31 - N->getZExtValue(), SDLoc(N));
240 def SRL32 : SDNodeXForm<imm, [{
241 // Transformation function: 32 - imm
242 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N))
243 : getI32Imm(0, SDLoc(N));
246 def LO16 : SDNodeXForm<imm, [{
247 // Transformation function: get the low 16 bits.
248 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N));
251 def HI16 : SDNodeXForm<imm, [{
252 // Transformation function: shift the immediate value down into the low bits.
253 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N));
256 def HA16 : SDNodeXForm<imm, [{
257 // Transformation function: shift the immediate value down into the low bits.
258 signed int Val = N->getZExtValue();
259 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
261 def MB : SDNodeXForm<imm, [{
262 // Transformation function: get the start bit of a mask
264 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
265 return getI32Imm(mb, SDLoc(N));
268 def ME : SDNodeXForm<imm, [{
269 // Transformation function: get the end bit of a mask
271 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
272 return getI32Imm(me, SDLoc(N));
274 def maskimm32 : PatLeaf<(imm), [{
275 // maskImm predicate - True if immediate is a run of ones.
277 if (N->getValueType(0) == MVT::i32)
278 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
283 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
284 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
285 // sign extended field. Used by instructions like 'addi'.
286 return (int32_t)Imm == (short)Imm;
288 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
289 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
290 // sign extended field. Used by instructions like 'addi'.
291 return (int64_t)Imm == (short)Imm;
293 def immZExt16 : PatLeaf<(imm), [{
294 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
295 // field. Used by instructions like 'ori'.
296 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
299 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
300 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
301 // identical in 32-bit mode, but in 64-bit mode, they return true if the
302 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
304 def imm16ShiftedZExt : PatLeaf<(imm), [{
305 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
306 // immediate are set. Used by instructions like 'xoris'.
307 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
310 def imm16ShiftedSExt : PatLeaf<(imm), [{
311 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
312 // immediate are set. Used by instructions like 'addis'. Identical to
313 // imm16ShiftedZExt in 32-bit mode.
314 if (N->getZExtValue() & 0xFFFF) return false;
315 if (N->getValueType(0) == MVT::i32)
317 // For 64-bit, make sure it is sext right.
318 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
321 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
322 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
323 // zero extended field.
324 return isUInt<32>(Imm);
327 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
328 // restricted memrix (4-aligned) constants are alignment sensitive. If these
329 // offsets are hidden behind TOC entries than the values of the lower-order
330 // bits cannot be checked directly. As a result, we need to also incorporate
331 // an alignment check into the relevant patterns.
333 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
334 return cast<LoadSDNode>(N)->getAlignment() >= 4;
336 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
337 (store node:$val, node:$ptr), [{
338 return cast<StoreSDNode>(N)->getAlignment() >= 4;
340 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
341 return cast<LoadSDNode>(N)->getAlignment() >= 4;
343 def aligned4pre_store : PatFrag<
344 (ops node:$val, node:$base, node:$offset),
345 (pre_store node:$val, node:$base, node:$offset), [{
346 return cast<StoreSDNode>(N)->getAlignment() >= 4;
349 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
350 return cast<LoadSDNode>(N)->getAlignment() < 4;
352 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
353 (store node:$val, node:$ptr), [{
354 return cast<StoreSDNode>(N)->getAlignment() < 4;
356 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
357 return cast<LoadSDNode>(N)->getAlignment() < 4;
360 //===----------------------------------------------------------------------===//
361 // PowerPC Flag Definitions.
363 class isPPC64 { bit PPC64 = 1; }
364 class isDOT { bit RC = 1; }
366 class RegConstraint<string C> {
367 string Constraints = C;
369 class NoEncode<string E> {
370 string DisableEncoding = E;
374 //===----------------------------------------------------------------------===//
375 // PowerPC Operand Definitions.
377 // In the default PowerPC assembler syntax, registers are specified simply
378 // by number, so they cannot be distinguished from immediate values (without
379 // looking at the opcode). This means that the default operand matching logic
380 // for the asm parser does not work, and we need to specify custom matchers.
381 // Since those can only be specified with RegisterOperand classes and not
382 // directly on the RegisterClass, all instructions patterns used by the asm
383 // parser need to use a RegisterOperand (instead of a RegisterClass) for
384 // all their register operands.
385 // For this purpose, we define one RegisterOperand for each RegisterClass,
386 // using the same name as the class, just in lower case.
388 def PPCRegGPRCAsmOperand : AsmOperandClass {
389 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
391 def gprc : RegisterOperand<GPRC> {
392 let ParserMatchClass = PPCRegGPRCAsmOperand;
394 def PPCRegG8RCAsmOperand : AsmOperandClass {
395 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
397 def g8rc : RegisterOperand<G8RC> {
398 let ParserMatchClass = PPCRegG8RCAsmOperand;
400 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
401 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
403 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
404 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
406 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
407 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
409 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
410 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
412 def PPCRegF8RCAsmOperand : AsmOperandClass {
413 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
415 def f8rc : RegisterOperand<F8RC> {
416 let ParserMatchClass = PPCRegF8RCAsmOperand;
418 def PPCRegF4RCAsmOperand : AsmOperandClass {
419 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
421 def f4rc : RegisterOperand<F4RC> {
422 let ParserMatchClass = PPCRegF4RCAsmOperand;
424 def PPCRegVRRCAsmOperand : AsmOperandClass {
425 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
427 def vrrc : RegisterOperand<VRRC> {
428 let ParserMatchClass = PPCRegVRRCAsmOperand;
430 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
431 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
433 def crbitrc : RegisterOperand<CRBITRC> {
434 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
436 def PPCRegCRRCAsmOperand : AsmOperandClass {
437 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
439 def crrc : RegisterOperand<CRRC> {
440 let ParserMatchClass = PPCRegCRRCAsmOperand;
442 def crrc0 : RegisterOperand<CRRC0> {
443 let ParserMatchClass = PPCRegCRRCAsmOperand;
446 def PPCU1ImmAsmOperand : AsmOperandClass {
447 let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
448 let RenderMethod = "addImmOperands";
450 def u1imm : Operand<i32> {
451 let PrintMethod = "printU1ImmOperand";
452 let ParserMatchClass = PPCU1ImmAsmOperand;
455 def PPCU2ImmAsmOperand : AsmOperandClass {
456 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
457 let RenderMethod = "addImmOperands";
459 def u2imm : Operand<i32> {
460 let PrintMethod = "printU2ImmOperand";
461 let ParserMatchClass = PPCU2ImmAsmOperand;
464 def PPCU3ImmAsmOperand : AsmOperandClass {
465 let Name = "U3Imm"; let PredicateMethod = "isU3Imm";
466 let RenderMethod = "addImmOperands";
468 def u3imm : Operand<i32> {
469 let PrintMethod = "printU3ImmOperand";
470 let ParserMatchClass = PPCU3ImmAsmOperand;
473 def PPCU4ImmAsmOperand : AsmOperandClass {
474 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
475 let RenderMethod = "addImmOperands";
477 def u4imm : Operand<i32> {
478 let PrintMethod = "printU4ImmOperand";
479 let ParserMatchClass = PPCU4ImmAsmOperand;
481 def PPCS5ImmAsmOperand : AsmOperandClass {
482 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
483 let RenderMethod = "addImmOperands";
485 def s5imm : Operand<i32> {
486 let PrintMethod = "printS5ImmOperand";
487 let ParserMatchClass = PPCS5ImmAsmOperand;
488 let DecoderMethod = "decodeSImmOperand<5>";
490 def PPCU5ImmAsmOperand : AsmOperandClass {
491 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
492 let RenderMethod = "addImmOperands";
494 def u5imm : Operand<i32> {
495 let PrintMethod = "printU5ImmOperand";
496 let ParserMatchClass = PPCU5ImmAsmOperand;
497 let DecoderMethod = "decodeUImmOperand<5>";
499 def PPCU6ImmAsmOperand : AsmOperandClass {
500 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
501 let RenderMethod = "addImmOperands";
503 def u6imm : Operand<i32> {
504 let PrintMethod = "printU6ImmOperand";
505 let ParserMatchClass = PPCU6ImmAsmOperand;
506 let DecoderMethod = "decodeUImmOperand<6>";
508 def PPCU10ImmAsmOperand : AsmOperandClass {
509 let Name = "U10Imm"; let PredicateMethod = "isU10Imm";
510 let RenderMethod = "addImmOperands";
512 def u10imm : Operand<i32> {
513 let PrintMethod = "printU10ImmOperand";
514 let ParserMatchClass = PPCU10ImmAsmOperand;
515 let DecoderMethod = "decodeUImmOperand<10>";
517 def PPCU12ImmAsmOperand : AsmOperandClass {
518 let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
519 let RenderMethod = "addImmOperands";
521 def u12imm : Operand<i32> {
522 let PrintMethod = "printU12ImmOperand";
523 let ParserMatchClass = PPCU12ImmAsmOperand;
524 let DecoderMethod = "decodeUImmOperand<12>";
526 def PPCS16ImmAsmOperand : AsmOperandClass {
527 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
528 let RenderMethod = "addS16ImmOperands";
530 def s16imm : Operand<i32> {
531 let PrintMethod = "printS16ImmOperand";
532 let EncoderMethod = "getImm16Encoding";
533 let ParserMatchClass = PPCS16ImmAsmOperand;
534 let DecoderMethod = "decodeSImmOperand<16>";
536 def PPCU16ImmAsmOperand : AsmOperandClass {
537 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
538 let RenderMethod = "addU16ImmOperands";
540 def u16imm : Operand<i32> {
541 let PrintMethod = "printU16ImmOperand";
542 let EncoderMethod = "getImm16Encoding";
543 let ParserMatchClass = PPCU16ImmAsmOperand;
544 let DecoderMethod = "decodeUImmOperand<16>";
546 def PPCS17ImmAsmOperand : AsmOperandClass {
547 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
548 let RenderMethod = "addS16ImmOperands";
550 def s17imm : Operand<i32> {
551 // This operand type is used for addis/lis to allow the assembler parser
552 // to accept immediates in the range -65536..65535 for compatibility with
553 // the GNU assembler. The operand is treated as 16-bit otherwise.
554 let PrintMethod = "printS16ImmOperand";
555 let EncoderMethod = "getImm16Encoding";
556 let ParserMatchClass = PPCS17ImmAsmOperand;
557 let DecoderMethod = "decodeSImmOperand<16>";
559 def PPCDirectBrAsmOperand : AsmOperandClass {
560 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
561 let RenderMethod = "addBranchTargetOperands";
563 def directbrtarget : Operand<OtherVT> {
564 let PrintMethod = "printBranchOperand";
565 let EncoderMethod = "getDirectBrEncoding";
566 let ParserMatchClass = PPCDirectBrAsmOperand;
568 def absdirectbrtarget : Operand<OtherVT> {
569 let PrintMethod = "printAbsBranchOperand";
570 let EncoderMethod = "getAbsDirectBrEncoding";
571 let ParserMatchClass = PPCDirectBrAsmOperand;
573 def PPCCondBrAsmOperand : AsmOperandClass {
574 let Name = "CondBr"; let PredicateMethod = "isCondBr";
575 let RenderMethod = "addBranchTargetOperands";
577 def condbrtarget : Operand<OtherVT> {
578 let PrintMethod = "printBranchOperand";
579 let EncoderMethod = "getCondBrEncoding";
580 let ParserMatchClass = PPCCondBrAsmOperand;
582 def abscondbrtarget : Operand<OtherVT> {
583 let PrintMethod = "printAbsBranchOperand";
584 let EncoderMethod = "getAbsCondBrEncoding";
585 let ParserMatchClass = PPCCondBrAsmOperand;
587 def calltarget : Operand<iPTR> {
588 let PrintMethod = "printBranchOperand";
589 let EncoderMethod = "getDirectBrEncoding";
590 let ParserMatchClass = PPCDirectBrAsmOperand;
592 def abscalltarget : Operand<iPTR> {
593 let PrintMethod = "printAbsBranchOperand";
594 let EncoderMethod = "getAbsDirectBrEncoding";
595 let ParserMatchClass = PPCDirectBrAsmOperand;
597 def PPCCRBitMaskOperand : AsmOperandClass {
598 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
600 def crbitm: Operand<i8> {
601 let PrintMethod = "printcrbitm";
602 let EncoderMethod = "get_crbitm_encoding";
603 let DecoderMethod = "decodeCRBitMOperand";
604 let ParserMatchClass = PPCCRBitMaskOperand;
607 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
608 def PPCRegGxRCNoR0Operand : AsmOperandClass {
609 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
611 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
612 let ParserMatchClass = PPCRegGxRCNoR0Operand;
614 // A version of ptr_rc usable with the asm parser.
615 def PPCRegGxRCOperand : AsmOperandClass {
616 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
618 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
619 let ParserMatchClass = PPCRegGxRCOperand;
622 def PPCDispRIOperand : AsmOperandClass {
623 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
624 let RenderMethod = "addS16ImmOperands";
626 def dispRI : Operand<iPTR> {
627 let ParserMatchClass = PPCDispRIOperand;
629 def PPCDispRIXOperand : AsmOperandClass {
630 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
631 let RenderMethod = "addImmOperands";
633 def dispRIX : Operand<iPTR> {
634 let ParserMatchClass = PPCDispRIXOperand;
636 def PPCDispSPE8Operand : AsmOperandClass {
637 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
638 let RenderMethod = "addImmOperands";
640 def dispSPE8 : Operand<iPTR> {
641 let ParserMatchClass = PPCDispSPE8Operand;
643 def PPCDispSPE4Operand : AsmOperandClass {
644 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
645 let RenderMethod = "addImmOperands";
647 def dispSPE4 : Operand<iPTR> {
648 let ParserMatchClass = PPCDispSPE4Operand;
650 def PPCDispSPE2Operand : AsmOperandClass {
651 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
652 let RenderMethod = "addImmOperands";
654 def dispSPE2 : Operand<iPTR> {
655 let ParserMatchClass = PPCDispSPE2Operand;
658 def memri : Operand<iPTR> {
659 let PrintMethod = "printMemRegImm";
660 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
661 let EncoderMethod = "getMemRIEncoding";
662 let DecoderMethod = "decodeMemRIOperands";
664 def memrr : Operand<iPTR> {
665 let PrintMethod = "printMemRegReg";
666 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
668 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
669 let PrintMethod = "printMemRegImm";
670 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
671 let EncoderMethod = "getMemRIXEncoding";
672 let DecoderMethod = "decodeMemRIXOperands";
674 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
675 let PrintMethod = "printMemRegImm";
676 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
677 let EncoderMethod = "getSPE8DisEncoding";
679 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
680 let PrintMethod = "printMemRegImm";
681 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
682 let EncoderMethod = "getSPE4DisEncoding";
684 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
685 let PrintMethod = "printMemRegImm";
686 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
687 let EncoderMethod = "getSPE2DisEncoding";
690 // A single-register address. This is used with the SjLj
691 // pseudo-instructions.
692 def memr : Operand<iPTR> {
693 let MIOperandInfo = (ops ptr_rc:$ptrreg);
695 def PPCTLSRegOperand : AsmOperandClass {
696 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
697 let RenderMethod = "addTLSRegOperands";
699 def tlsreg32 : Operand<i32> {
700 let EncoderMethod = "getTLSRegEncoding";
701 let ParserMatchClass = PPCTLSRegOperand;
703 def tlsgd32 : Operand<i32> {}
704 def tlscall32 : Operand<i32> {
705 let PrintMethod = "printTLSCall";
706 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
707 let EncoderMethod = "getTLSCallEncoding";
710 // PowerPC Predicate operand.
711 def pred : Operand<OtherVT> {
712 let PrintMethod = "printPredicateOperand";
713 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
716 // Define PowerPC specific addressing mode.
717 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
718 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
719 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
720 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
722 // The address in a single register. This is used with the SjLj
723 // pseudo-instructions.
724 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
726 /// This is just the offset part of iaddr, used for preinc.
727 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
729 //===----------------------------------------------------------------------===//
730 // PowerPC Instruction Predicate Definitions.
731 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
732 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
733 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
734 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
735 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
736 def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
737 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
738 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
739 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
740 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
741 def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
742 def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
743 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
744 def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">;
745 def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
746 def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
748 //===----------------------------------------------------------------------===//
749 // PowerPC Multiclass Definitions.
751 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
752 string asmbase, string asmstr, InstrItinClass itin,
754 let BaseName = asmbase in {
755 def NAME : XForm_6<opcode, xo, OOL, IOL,
756 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
757 pattern>, RecFormRel;
759 def o : XForm_6<opcode, xo, OOL, IOL,
760 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
761 []>, isDOT, RecFormRel;
765 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
766 string asmbase, string asmstr, InstrItinClass itin,
768 let BaseName = asmbase in {
769 let Defs = [CARRY] in
770 def NAME : XForm_6<opcode, xo, OOL, IOL,
771 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
772 pattern>, RecFormRel;
773 let Defs = [CARRY, CR0] in
774 def o : XForm_6<opcode, xo, OOL, IOL,
775 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
776 []>, isDOT, RecFormRel;
780 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
781 string asmbase, string asmstr, InstrItinClass itin,
783 let BaseName = asmbase in {
784 let Defs = [CARRY] in
785 def NAME : XForm_10<opcode, xo, OOL, IOL,
786 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
787 pattern>, RecFormRel;
788 let Defs = [CARRY, CR0] in
789 def o : XForm_10<opcode, xo, OOL, IOL,
790 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
791 []>, isDOT, RecFormRel;
795 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
796 string asmbase, string asmstr, InstrItinClass itin,
798 let BaseName = asmbase in {
799 def NAME : XForm_11<opcode, xo, OOL, IOL,
800 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
801 pattern>, RecFormRel;
803 def o : XForm_11<opcode, xo, OOL, IOL,
804 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
805 []>, isDOT, RecFormRel;
809 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
810 string asmbase, string asmstr, InstrItinClass itin,
812 let BaseName = asmbase in {
813 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
814 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
815 pattern>, RecFormRel;
817 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
818 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
819 []>, isDOT, RecFormRel;
823 // Multiclass for instructions for which the non record form is not cracked
824 // and the record form is cracked (i.e. divw, mullw, etc.)
825 multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
826 string asmbase, string asmstr, InstrItinClass itin,
828 let BaseName = asmbase in {
829 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
830 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
831 pattern>, RecFormRel;
833 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
834 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
835 []>, isDOT, RecFormRel, PPC970_DGroup_First,
836 PPC970_DGroup_Cracked;
840 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
841 string asmbase, string asmstr, InstrItinClass itin,
843 let BaseName = asmbase in {
844 let Defs = [CARRY] in
845 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
846 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
847 pattern>, RecFormRel;
848 let Defs = [CARRY, CR0] in
849 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
850 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
851 []>, isDOT, RecFormRel;
855 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
856 string asmbase, string asmstr, InstrItinClass itin,
858 let BaseName = asmbase in {
859 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
860 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
861 pattern>, RecFormRel;
863 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
864 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
865 []>, isDOT, RecFormRel;
869 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
870 string asmbase, string asmstr, InstrItinClass itin,
872 let BaseName = asmbase in {
873 let Defs = [CARRY] in
874 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
875 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
876 pattern>, RecFormRel;
877 let Defs = [CARRY, CR0] in
878 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
879 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
880 []>, isDOT, RecFormRel;
884 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
885 string asmbase, string asmstr, InstrItinClass itin,
887 let BaseName = asmbase in {
888 def NAME : MForm_2<opcode, OOL, IOL,
889 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
890 pattern>, RecFormRel;
892 def o : MForm_2<opcode, OOL, IOL,
893 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
894 []>, isDOT, RecFormRel;
898 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
899 string asmbase, string asmstr, InstrItinClass itin,
901 let BaseName = asmbase in {
902 def NAME : MDForm_1<opcode, xo, OOL, IOL,
903 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
904 pattern>, RecFormRel;
906 def o : MDForm_1<opcode, xo, OOL, IOL,
907 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
908 []>, isDOT, RecFormRel;
912 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
913 string asmbase, string asmstr, InstrItinClass itin,
915 let BaseName = asmbase in {
916 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
917 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
918 pattern>, RecFormRel;
920 def o : MDSForm_1<opcode, xo, OOL, IOL,
921 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
922 []>, isDOT, RecFormRel;
926 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
927 string asmbase, string asmstr, InstrItinClass itin,
929 let BaseName = asmbase in {
930 let Defs = [CARRY] in
931 def NAME : XSForm_1<opcode, xo, OOL, IOL,
932 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
933 pattern>, RecFormRel;
934 let Defs = [CARRY, CR0] in
935 def o : XSForm_1<opcode, xo, OOL, IOL,
936 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
937 []>, isDOT, RecFormRel;
941 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
942 string asmbase, string asmstr, InstrItinClass itin,
944 let BaseName = asmbase in {
945 def NAME : XForm_26<opcode, xo, OOL, IOL,
946 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
947 pattern>, RecFormRel;
949 def o : XForm_26<opcode, xo, OOL, IOL,
950 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
951 []>, isDOT, RecFormRel;
955 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
956 string asmbase, string asmstr, InstrItinClass itin,
958 let BaseName = asmbase in {
959 def NAME : XForm_28<opcode, xo, OOL, IOL,
960 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
961 pattern>, RecFormRel;
963 def o : XForm_28<opcode, xo, OOL, IOL,
964 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
965 []>, isDOT, RecFormRel;
969 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
970 string asmbase, string asmstr, InstrItinClass itin,
972 let BaseName = asmbase in {
973 def NAME : AForm_1<opcode, xo, OOL, IOL,
974 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
975 pattern>, RecFormRel;
977 def o : AForm_1<opcode, xo, OOL, IOL,
978 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
979 []>, isDOT, RecFormRel;
983 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
984 string asmbase, string asmstr, InstrItinClass itin,
986 let BaseName = asmbase in {
987 def NAME : AForm_2<opcode, xo, OOL, IOL,
988 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
989 pattern>, RecFormRel;
991 def o : AForm_2<opcode, xo, OOL, IOL,
992 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
993 []>, isDOT, RecFormRel;
997 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
998 string asmbase, string asmstr, InstrItinClass itin,
1000 let BaseName = asmbase in {
1001 def NAME : AForm_3<opcode, xo, OOL, IOL,
1002 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1003 pattern>, RecFormRel;
1005 def o : AForm_3<opcode, xo, OOL, IOL,
1006 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1007 []>, isDOT, RecFormRel;
1011 //===----------------------------------------------------------------------===//
1012 // PowerPC Instruction Definitions.
1014 // Pseudo-instructions:
1016 let hasCtrlDep = 1 in {
1017 let Defs = [R1], Uses = [R1] in {
1018 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
1019 [(callseq_start timm:$amt)]>;
1020 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
1021 [(callseq_end timm:$amt1, timm:$amt2)]>;
1024 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1025 "UPDATE_VRSAVE $rD, $rS", []>;
1028 let Defs = [R1], Uses = [R1] in
1029 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1031 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
1033 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
1034 // instruction selection into a branch sequence.
1035 let usesCustomInserter = 1, // Expanded after instruction selection.
1036 PPC970_Single = 1 in {
1037 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
1038 // because either operand might become the first operand in an isel, and
1039 // that operand cannot be r0.
1040 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1041 gprc_nor0:$T, gprc_nor0:$F,
1042 i32imm:$BROPC), "#SELECT_CC_I4",
1044 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1045 g8rc_nox0:$T, g8rc_nox0:$F,
1046 i32imm:$BROPC), "#SELECT_CC_I8",
1048 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1049 i32imm:$BROPC), "#SELECT_CC_F4",
1051 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1052 i32imm:$BROPC), "#SELECT_CC_F8",
1054 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1055 i32imm:$BROPC), "#SELECT_CC_VRRC",
1058 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
1059 // register bit directly.
1060 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1061 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
1062 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
1063 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1064 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
1065 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
1066 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1067 f4rc:$T, f4rc:$F), "#SELECT_F4",
1068 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
1069 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1070 f8rc:$T, f8rc:$F), "#SELECT_F8",
1071 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1072 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1073 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
1075 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
1078 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
1079 // scavenge a register for it.
1080 let mayStore = 1 in {
1081 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1083 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1084 "#SPILL_CRBIT", []>;
1087 // RESTORE_CR - Indicate that we're restoring the CR register (previously
1088 // spilled), so we'll need to scavenge a register for it.
1089 let mayLoad = 1 in {
1090 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1092 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1093 "#RESTORE_CRBIT", []>;
1096 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1097 let isReturn = 1, Uses = [LR, RM] in
1098 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1099 [(retflag)]>, Requires<[In32BitMode]>;
1100 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1101 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1104 let isCodeGenOnly = 1 in {
1105 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1106 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1109 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1110 "bcctr 12, $bi, 0", IIC_BrB, []>;
1111 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1112 "bcctr 4, $bi, 0", IIC_BrB, []>;
1118 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1121 def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1124 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1125 let isBarrier = 1 in {
1126 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1129 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1130 "ba $dst", IIC_BrB, []>;
1133 // BCC represents an arbitrary conditional branch on a predicate.
1134 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1135 // a two-value operand where a dag node expects two operands. :(
1136 let isCodeGenOnly = 1 in {
1137 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1138 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1139 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1140 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1141 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1143 let isReturn = 1, Uses = [LR, RM] in
1144 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1145 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1148 let isCodeGenOnly = 1 in {
1149 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1150 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1151 "bc 12, $bi, $dst">;
1153 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1154 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1157 let isReturn = 1, Uses = [LR, RM] in
1158 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1159 "bclr 12, $bi, 0", IIC_BrB, []>;
1160 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1161 "bclr 4, $bi, 0", IIC_BrB, []>;
1164 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1165 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1166 "bdzlr", IIC_BrB, []>;
1167 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1168 "bdnzlr", IIC_BrB, []>;
1169 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1170 "bdzlr+", IIC_BrB, []>;
1171 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1172 "bdnzlr+", IIC_BrB, []>;
1173 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1174 "bdzlr-", IIC_BrB, []>;
1175 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1176 "bdnzlr-", IIC_BrB, []>;
1179 let Defs = [CTR], Uses = [CTR] in {
1180 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1182 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1184 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1186 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1188 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1190 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1192 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1194 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1196 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1198 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1200 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1202 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1207 // The unconditional BCL used by the SjLj setjmp code.
1208 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1209 let Defs = [LR], Uses = [RM] in {
1210 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1211 "bcl 20, 31, $dst">;
1215 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1216 // Convenient aliases for call instructions
1217 let Uses = [RM] in {
1218 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1219 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1220 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1221 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1223 let isCodeGenOnly = 1 in {
1224 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1225 "bl $func", IIC_BrB, []>;
1226 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1227 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1228 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1229 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1231 def BCL : BForm_4<16, 12, 0, 1, (outs),
1232 (ins crbitrc:$bi, condbrtarget:$dst),
1233 "bcl 12, $bi, $dst">;
1234 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1235 (ins crbitrc:$bi, condbrtarget:$dst),
1236 "bcl 4, $bi, $dst">;
1239 let Uses = [CTR, RM] in {
1240 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1241 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1242 Requires<[In32BitMode]>;
1244 let isCodeGenOnly = 1 in {
1245 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1246 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1249 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1250 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1251 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1252 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1255 let Uses = [LR, RM] in {
1256 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1257 "blrl", IIC_BrB, []>;
1259 let isCodeGenOnly = 1 in {
1260 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1261 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1264 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1265 "bclrl 12, $bi, 0", IIC_BrB, []>;
1266 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1267 "bclrl 4, $bi, 0", IIC_BrB, []>;
1270 let Defs = [CTR], Uses = [CTR, RM] in {
1271 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1273 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1275 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1277 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1279 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1281 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1283 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1285 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1287 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1289 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1291 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1293 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1296 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1297 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1298 "bdzlrl", IIC_BrB, []>;
1299 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1300 "bdnzlrl", IIC_BrB, []>;
1301 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1302 "bdzlrl+", IIC_BrB, []>;
1303 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1304 "bdnzlrl+", IIC_BrB, []>;
1305 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1306 "bdzlrl-", IIC_BrB, []>;
1307 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1308 "bdnzlrl-", IIC_BrB, []>;
1312 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1313 def TCRETURNdi :Pseudo< (outs),
1314 (ins calltarget:$dst, i32imm:$offset),
1315 "#TC_RETURNd $dst $offset",
1319 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1320 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1321 "#TC_RETURNa $func $offset",
1322 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1324 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1325 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1326 "#TC_RETURNr $dst $offset",
1330 let isCodeGenOnly = 1 in {
1332 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1333 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1334 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1335 []>, Requires<[In32BitMode]>;
1337 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1338 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1339 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1343 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1344 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1345 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1351 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1353 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1354 "#EH_SJLJ_SETJMP32",
1355 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1356 Requires<[In32BitMode]>;
1357 let isTerminator = 1 in
1358 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1359 "#EH_SJLJ_LONGJMP32",
1360 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1361 Requires<[In32BitMode]>;
1364 let isBranch = 1, isTerminator = 1 in {
1365 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1366 "#EH_SjLj_Setup\t$dst", []>;
1370 let PPC970_Unit = 7 in {
1371 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1372 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1375 // Branch history rolling buffer.
1376 def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB,
1378 PPC970_DGroup_Single;
1379 // The $dmy argument used for MFBHRBE is not needed; however, including
1380 // it avoids automatic generation of PPCFastISel::fastEmit_i(), which
1381 // interferes with necessary special handling (see PPCFastISel.cpp).
1382 def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD),
1383 (ins u10imm:$imm, u10imm:$dmy),
1384 "mfbhrbe $rD, $imm", IIC_BrB,
1386 (PPCmfbhrbe imm:$imm, imm:$dmy))]>,
1387 PPC970_DGroup_First;
1389 def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm",
1390 IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
1391 PPC970_DGroup_Single;
1393 // DCB* instructions.
1394 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1395 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1396 PPC970_DGroup_Single;
1397 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1398 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1399 PPC970_DGroup_Single;
1400 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1401 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1402 PPC970_DGroup_Single;
1403 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1404 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1405 PPC970_DGroup_Single;
1406 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1407 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1408 PPC970_DGroup_Single;
1409 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1410 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1411 PPC970_DGroup_Single;
1413 let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
1414 def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst),
1415 "dcbt $dst, $TH", IIC_LdStDCBF, []>,
1416 PPC970_DGroup_Single;
1417 def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst),
1418 "dcbtst $dst, $TH", IIC_LdStDCBF, []>,
1419 PPC970_DGroup_Single;
1420 } // hasSideEffects = 0
1422 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1423 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1425 def : Pat<(int_ppc_dcbt xoaddr:$dst),
1426 (DCBT 0, xoaddr:$dst)>;
1427 def : Pat<(int_ppc_dcbtst xoaddr:$dst),
1428 (DCBTST 0, xoaddr:$dst)>;
1430 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1431 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads
1432 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1433 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores
1434 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1435 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1437 // Atomic operations
1438 let usesCustomInserter = 1 in {
1439 let Defs = [CR0] in {
1440 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1441 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1442 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1443 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1444 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1445 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1446 def ATOMIC_LOAD_AND_I8 : Pseudo<
1447 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1448 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1449 def ATOMIC_LOAD_OR_I8 : Pseudo<
1450 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1451 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1452 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1453 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1454 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1455 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1456 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1457 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1458 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1459 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1460 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1461 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1462 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1463 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1464 def ATOMIC_LOAD_AND_I16 : Pseudo<
1465 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1466 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1467 def ATOMIC_LOAD_OR_I16 : Pseudo<
1468 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1469 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1470 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1471 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1472 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1473 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1474 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1475 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1476 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1477 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1478 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1479 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1480 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1481 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1482 def ATOMIC_LOAD_AND_I32 : Pseudo<
1483 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1484 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1485 def ATOMIC_LOAD_OR_I32 : Pseudo<
1486 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1487 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1488 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1489 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1490 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1491 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1492 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1493 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1495 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1496 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1497 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1498 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1499 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1500 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1501 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1502 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1503 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1505 def ATOMIC_SWAP_I8 : Pseudo<
1506 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1507 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1508 def ATOMIC_SWAP_I16 : Pseudo<
1509 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1510 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1511 def ATOMIC_SWAP_I32 : Pseudo<
1512 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1513 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1517 // Instructions to support atomic operations
1518 let mayLoad = 1, hasSideEffects = 0 in {
1519 def LBARX : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
1520 "lbarx $rD, $src", IIC_LdStLWARX, []>,
1521 Requires<[HasPartwordAtomics]>;
1523 def LHARX : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src),
1524 "lharx $rD, $src", IIC_LdStLWARX, []>,
1525 Requires<[HasPartwordAtomics]>;
1527 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1528 "lwarx $rD, $src", IIC_LdStLWARX, []>;
1530 // Instructions to support lock versions of atomics
1531 // (EH=1 - see Power ISA 2.07 Book II 4.4.2)
1532 def LBARXL : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
1533 "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1534 Requires<[HasPartwordAtomics]>;
1536 def LHARXL : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src),
1537 "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1538 Requires<[HasPartwordAtomics]>;
1540 def LWARXL : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1541 "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
1544 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {
1545 def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
1546 "stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
1547 isDOT, Requires<[HasPartwordAtomics]>;
1549 def STHCX : XForm_1<31, 726, (outs), (ins gprc:$rS, memrr:$dst),
1550 "sthcx. $rS, $dst", IIC_LdStSTWCX, []>,
1551 isDOT, Requires<[HasPartwordAtomics]>;
1553 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1554 "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
1557 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1558 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1560 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1561 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1562 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1563 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1564 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1565 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1566 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1567 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1569 //===----------------------------------------------------------------------===//
1570 // PPC32 Load Instructions.
1573 // Unindexed (r+i) Loads.
1574 let PPC970_Unit = 2 in {
1575 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1576 "lbz $rD, $src", IIC_LdStLoad,
1577 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1578 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1579 "lha $rD, $src", IIC_LdStLHA,
1580 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1581 PPC970_DGroup_Cracked;
1582 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1583 "lhz $rD, $src", IIC_LdStLoad,
1584 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1585 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1586 "lwz $rD, $src", IIC_LdStLoad,
1587 [(set i32:$rD, (load iaddr:$src))]>;
1589 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1590 "lfs $rD, $src", IIC_LdStLFD,
1591 [(set f32:$rD, (load iaddr:$src))]>;
1592 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1593 "lfd $rD, $src", IIC_LdStLFD,
1594 [(set f64:$rD, (load iaddr:$src))]>;
1597 // Unindexed (r+i) Loads with Update (preinc).
1598 let mayLoad = 1, hasSideEffects = 0 in {
1599 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1600 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1601 []>, RegConstraint<"$addr.reg = $ea_result">,
1602 NoEncode<"$ea_result">;
1604 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1605 "lhau $rD, $addr", IIC_LdStLHAU,
1606 []>, RegConstraint<"$addr.reg = $ea_result">,
1607 NoEncode<"$ea_result">;
1609 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1610 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1611 []>, RegConstraint<"$addr.reg = $ea_result">,
1612 NoEncode<"$ea_result">;
1614 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1615 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1616 []>, RegConstraint<"$addr.reg = $ea_result">,
1617 NoEncode<"$ea_result">;
1619 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1620 "lfsu $rD, $addr", IIC_LdStLFDU,
1621 []>, RegConstraint<"$addr.reg = $ea_result">,
1622 NoEncode<"$ea_result">;
1624 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1625 "lfdu $rD, $addr", IIC_LdStLFDU,
1626 []>, RegConstraint<"$addr.reg = $ea_result">,
1627 NoEncode<"$ea_result">;
1630 // Indexed (r+r) Loads with Update (preinc).
1631 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1633 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1634 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1635 NoEncode<"$ea_result">;
1637 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1639 "lhaux $rD, $addr", IIC_LdStLHAUX,
1640 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1641 NoEncode<"$ea_result">;
1643 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1645 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1646 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1647 NoEncode<"$ea_result">;
1649 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1651 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1652 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1653 NoEncode<"$ea_result">;
1655 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1657 "lfsux $rD, $addr", IIC_LdStLFDUX,
1658 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1659 NoEncode<"$ea_result">;
1661 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1663 "lfdux $rD, $addr", IIC_LdStLFDUX,
1664 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1665 NoEncode<"$ea_result">;
1669 // Indexed (r+r) Loads.
1671 let PPC970_Unit = 2 in {
1672 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1673 "lbzx $rD, $src", IIC_LdStLoad,
1674 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1675 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1676 "lhax $rD, $src", IIC_LdStLHA,
1677 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1678 PPC970_DGroup_Cracked;
1679 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1680 "lhzx $rD, $src", IIC_LdStLoad,
1681 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1682 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1683 "lwzx $rD, $src", IIC_LdStLoad,
1684 [(set i32:$rD, (load xaddr:$src))]>;
1687 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1688 "lhbrx $rD, $src", IIC_LdStLoad,
1689 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1690 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1691 "lwbrx $rD, $src", IIC_LdStLoad,
1692 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1694 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1695 "lfsx $frD, $src", IIC_LdStLFD,
1696 [(set f32:$frD, (load xaddr:$src))]>;
1697 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1698 "lfdx $frD, $src", IIC_LdStLFD,
1699 [(set f64:$frD, (load xaddr:$src))]>;
1701 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1702 "lfiwax $frD, $src", IIC_LdStLFD,
1703 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1704 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1705 "lfiwzx $frD, $src", IIC_LdStLFD,
1706 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1710 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1711 "lmw $rD, $src", IIC_LdStLMW, []>;
1713 //===----------------------------------------------------------------------===//
1714 // PPC32 Store Instructions.
1717 // Unindexed (r+i) Stores.
1718 let PPC970_Unit = 2 in {
1719 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1720 "stb $rS, $src", IIC_LdStStore,
1721 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1722 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1723 "sth $rS, $src", IIC_LdStStore,
1724 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1725 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1726 "stw $rS, $src", IIC_LdStStore,
1727 [(store i32:$rS, iaddr:$src)]>;
1728 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1729 "stfs $rS, $dst", IIC_LdStSTFD,
1730 [(store f32:$rS, iaddr:$dst)]>;
1731 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1732 "stfd $rS, $dst", IIC_LdStSTFD,
1733 [(store f64:$rS, iaddr:$dst)]>;
1736 // Unindexed (r+i) Stores with Update (preinc).
1737 let PPC970_Unit = 2, mayStore = 1 in {
1738 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1739 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1740 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1741 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1742 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1743 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1744 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1745 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1746 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1747 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1748 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1749 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1750 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1751 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1752 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1755 // Patterns to match the pre-inc stores. We can't put the patterns on
1756 // the instruction definitions directly as ISel wants the address base
1757 // and offset to be separate operands, not a single complex operand.
1758 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1759 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1760 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1761 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1762 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1763 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1764 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1765 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1766 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1767 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1769 // Indexed (r+r) Stores.
1770 let PPC970_Unit = 2 in {
1771 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1772 "stbx $rS, $dst", IIC_LdStStore,
1773 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1774 PPC970_DGroup_Cracked;
1775 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1776 "sthx $rS, $dst", IIC_LdStStore,
1777 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1778 PPC970_DGroup_Cracked;
1779 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1780 "stwx $rS, $dst", IIC_LdStStore,
1781 [(store i32:$rS, xaddr:$dst)]>,
1782 PPC970_DGroup_Cracked;
1784 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1785 "sthbrx $rS, $dst", IIC_LdStStore,
1786 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1787 PPC970_DGroup_Cracked;
1788 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1789 "stwbrx $rS, $dst", IIC_LdStStore,
1790 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1791 PPC970_DGroup_Cracked;
1793 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1794 "stfiwx $frS, $dst", IIC_LdStSTFD,
1795 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1797 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1798 "stfsx $frS, $dst", IIC_LdStSTFD,
1799 [(store f32:$frS, xaddr:$dst)]>;
1800 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1801 "stfdx $frS, $dst", IIC_LdStSTFD,
1802 [(store f64:$frS, xaddr:$dst)]>;
1805 // Indexed (r+r) Stores with Update (preinc).
1806 let PPC970_Unit = 2, mayStore = 1 in {
1807 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1808 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1809 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1810 PPC970_DGroup_Cracked;
1811 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1812 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1813 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1814 PPC970_DGroup_Cracked;
1815 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1816 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1817 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1818 PPC970_DGroup_Cracked;
1819 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1820 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1821 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1822 PPC970_DGroup_Cracked;
1823 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1824 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1825 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1826 PPC970_DGroup_Cracked;
1829 // Patterns to match the pre-inc stores. We can't put the patterns on
1830 // the instruction definitions directly as ISel wants the address base
1831 // and offset to be separate operands, not a single complex operand.
1832 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1833 (STBUX $rS, $ptrreg, $ptroff)>;
1834 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1835 (STHUX $rS, $ptrreg, $ptroff)>;
1836 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1837 (STWUX $rS, $ptrreg, $ptroff)>;
1838 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1839 (STFSUX $rS, $ptrreg, $ptroff)>;
1840 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1841 (STFDUX $rS, $ptrreg, $ptroff)>;
1844 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1845 "stmw $rS, $dst", IIC_LdStLMW, []>;
1847 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1848 "sync $L", IIC_LdStSync, []>;
1850 let isCodeGenOnly = 1 in {
1851 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1852 "msync", IIC_LdStSync, []> {
1857 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>;
1858 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1859 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1860 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1862 //===----------------------------------------------------------------------===//
1863 // PPC32 Arithmetic Instructions.
1866 let PPC970_Unit = 1 in { // FXU Operations.
1867 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1868 "addi $rD, $rA, $imm", IIC_IntSimple,
1869 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1870 let BaseName = "addic" in {
1871 let Defs = [CARRY] in
1872 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1873 "addic $rD, $rA, $imm", IIC_IntGeneral,
1874 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1875 RecFormRel, PPC970_DGroup_Cracked;
1876 let Defs = [CARRY, CR0] in
1877 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1878 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1879 []>, isDOT, RecFormRel;
1881 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1882 "addis $rD, $rA, $imm", IIC_IntSimple,
1883 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1884 let isCodeGenOnly = 1 in
1885 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1886 "la $rD, $sym($rA)", IIC_IntGeneral,
1887 [(set i32:$rD, (add i32:$rA,
1888 (PPClo tglobaladdr:$sym, 0)))]>;
1889 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1890 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1891 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1892 let Defs = [CARRY] in
1893 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1894 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1895 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1897 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1898 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1899 "li $rD, $imm", IIC_IntSimple,
1900 [(set i32:$rD, imm32SExt16:$imm)]>;
1901 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1902 "lis $rD, $imm", IIC_IntSimple,
1903 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1907 let PPC970_Unit = 1 in { // FXU Operations.
1908 let Defs = [CR0] in {
1909 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1910 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1911 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1913 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1914 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1915 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1918 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1919 "ori $dst, $src1, $src2", IIC_IntSimple,
1920 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1921 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1922 "oris $dst, $src1, $src2", IIC_IntSimple,
1923 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1924 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1925 "xori $dst, $src1, $src2", IIC_IntSimple,
1926 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1927 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1928 "xoris $dst, $src1, $src2", IIC_IntSimple,
1929 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1931 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1933 let isCodeGenOnly = 1 in {
1934 // The POWER6 and POWER7 have special group-terminating nops.
1935 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1936 "ori 1, 1, 0", IIC_IntSimple, []>;
1937 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1938 "ori 2, 2, 0", IIC_IntSimple, []>;
1941 let isCompare = 1, hasSideEffects = 0 in {
1942 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1943 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1944 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1945 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1949 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
1950 let isCommutable = 1 in {
1951 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1952 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1953 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1954 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1955 "and", "$rA, $rS, $rB", IIC_IntSimple,
1956 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1958 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1959 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1960 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1961 let isCommutable = 1 in {
1962 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1963 "or", "$rA, $rS, $rB", IIC_IntSimple,
1964 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1965 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1966 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1967 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1969 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1970 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1971 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1972 let isCommutable = 1 in {
1973 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1974 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1975 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1976 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1977 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1978 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1980 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1981 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1982 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1983 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1984 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1985 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1986 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1987 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1988 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1991 let PPC970_Unit = 1 in { // FXU Operations.
1992 let hasSideEffects = 0 in {
1993 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1994 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1995 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1996 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1997 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1998 [(set i32:$rA, (ctlz i32:$rS))]>;
1999 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
2000 "extsb", "$rA, $rS", IIC_IntSimple,
2001 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
2002 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
2003 "extsh", "$rA, $rS", IIC_IntSimple,
2004 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
2006 let isCommutable = 1 in
2007 def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2008 "cmpb $rA, $rS, $rB", IIC_IntGeneral,
2009 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
2011 let isCompare = 1, hasSideEffects = 0 in {
2012 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2013 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
2014 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2015 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
2018 let PPC970_Unit = 3 in { // FPU Operations.
2019 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
2020 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
2021 let isCompare = 1, hasSideEffects = 0 in {
2022 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
2023 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2024 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2025 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
2026 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2029 let Uses = [RM] in {
2030 let hasSideEffects = 0 in {
2031 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
2032 "fctiw", "$frD, $frB", IIC_FPGeneral,
2034 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
2035 "fctiwz", "$frD, $frB", IIC_FPGeneral,
2036 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
2038 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
2039 "frsp", "$frD, $frB", IIC_FPGeneral,
2040 [(set f32:$frD, (fround f64:$frB))]>;
2042 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2043 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
2044 "frin", "$frD, $frB", IIC_FPGeneral,
2045 [(set f64:$frD, (frnd f64:$frB))]>;
2046 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
2047 "frin", "$frD, $frB", IIC_FPGeneral,
2048 [(set f32:$frD, (frnd f32:$frB))]>;
2051 let hasSideEffects = 0 in {
2052 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2053 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
2054 "frip", "$frD, $frB", IIC_FPGeneral,
2055 [(set f64:$frD, (fceil f64:$frB))]>;
2056 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
2057 "frip", "$frD, $frB", IIC_FPGeneral,
2058 [(set f32:$frD, (fceil f32:$frB))]>;
2059 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2060 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
2061 "friz", "$frD, $frB", IIC_FPGeneral,
2062 [(set f64:$frD, (ftrunc f64:$frB))]>;
2063 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
2064 "friz", "$frD, $frB", IIC_FPGeneral,
2065 [(set f32:$frD, (ftrunc f32:$frB))]>;
2066 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2067 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
2068 "frim", "$frD, $frB", IIC_FPGeneral,
2069 [(set f64:$frD, (ffloor f64:$frB))]>;
2070 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
2071 "frim", "$frD, $frB", IIC_FPGeneral,
2072 [(set f32:$frD, (ffloor f32:$frB))]>;
2074 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
2075 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
2076 [(set f64:$frD, (fsqrt f64:$frB))]>;
2077 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
2078 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
2079 [(set f32:$frD, (fsqrt f32:$frB))]>;
2084 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
2085 /// often coalesced away and we don't want the dispatch group builder to think
2086 /// that they will fill slots (which could cause the load of a LSU reject to
2087 /// sneak into a d-group with a store).
2088 let hasSideEffects = 0 in
2089 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
2090 "fmr", "$frD, $frB", IIC_FPGeneral,
2091 []>, // (set f32:$frD, f32:$frB)
2094 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2095 // These are artificially split into two different forms, for 4/8 byte FP.
2096 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
2097 "fabs", "$frD, $frB", IIC_FPGeneral,
2098 [(set f32:$frD, (fabs f32:$frB))]>;
2099 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2100 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
2101 "fabs", "$frD, $frB", IIC_FPGeneral,
2102 [(set f64:$frD, (fabs f64:$frB))]>;
2103 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
2104 "fnabs", "$frD, $frB", IIC_FPGeneral,
2105 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
2106 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2107 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
2108 "fnabs", "$frD, $frB", IIC_FPGeneral,
2109 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
2110 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
2111 "fneg", "$frD, $frB", IIC_FPGeneral,
2112 [(set f32:$frD, (fneg f32:$frB))]>;
2113 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2114 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
2115 "fneg", "$frD, $frB", IIC_FPGeneral,
2116 [(set f64:$frD, (fneg f64:$frB))]>;
2118 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
2119 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2120 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
2121 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2122 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
2123 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2124 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
2126 // Reciprocal estimates.
2127 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
2128 "fre", "$frD, $frB", IIC_FPGeneral,
2129 [(set f64:$frD, (PPCfre f64:$frB))]>;
2130 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
2131 "fres", "$frD, $frB", IIC_FPGeneral,
2132 [(set f32:$frD, (PPCfre f32:$frB))]>;
2133 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
2134 "frsqrte", "$frD, $frB", IIC_FPGeneral,
2135 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2136 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2137 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2138 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2141 // XL-Form instructions. condition register logical ops.
2143 let hasSideEffects = 0 in
2144 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2145 "mcrf $BF, $BFA", IIC_BrMCR>,
2146 PPC970_DGroup_First, PPC970_Unit_CRU;
2148 // FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2149 // condition-register logical instructions have preferred forms. Specifically,
2150 // it is preferred that the bit specified by the BT field be in the same
2151 // condition register as that specified by the bit BB. We might want to account
2152 // for this via hinting the register allocator and anti-dep breakers, or we
2153 // could constrain the register class to force this constraint and then loosen
2154 // it during register allocation via convertToThreeAddress or some similar
2157 let isCommutable = 1 in {
2158 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
2159 (ins crbitrc:$CRA, crbitrc:$CRB),
2160 "crand $CRD, $CRA, $CRB", IIC_BrCR,
2161 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2163 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2164 (ins crbitrc:$CRA, crbitrc:$CRB),
2165 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2166 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2168 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
2169 (ins crbitrc:$CRA, crbitrc:$CRB),
2170 "cror $CRD, $CRA, $CRB", IIC_BrCR,
2171 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2173 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
2174 (ins crbitrc:$CRA, crbitrc:$CRB),
2175 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2176 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2178 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
2179 (ins crbitrc:$CRA, crbitrc:$CRB),
2180 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2181 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2183 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
2184 (ins crbitrc:$CRA, crbitrc:$CRB),
2185 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2186 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2189 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2190 (ins crbitrc:$CRA, crbitrc:$CRB),
2191 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2192 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2194 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
2195 (ins crbitrc:$CRA, crbitrc:$CRB),
2196 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2197 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2199 let isCodeGenOnly = 1 in {
2200 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2201 "creqv $dst, $dst, $dst", IIC_BrCR,
2202 [(set i1:$dst, 1)]>;
2204 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2205 "crxor $dst, $dst, $dst", IIC_BrCR,
2206 [(set i1:$dst, 0)]>;
2208 let Defs = [CR1EQ], CRD = 6 in {
2209 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2210 "creqv 6, 6, 6", IIC_BrCR,
2213 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2214 "crxor 6, 6, 6", IIC_BrCR,
2219 // XFX-Form instructions. Instructions that deal with SPRs.
2222 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2223 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2224 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2225 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2227 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2228 "mftb $RT, $SPR", IIC_SprMFTB>;
2230 // A pseudo-instruction used to implement the read of the 64-bit cycle counter
2231 // on a 32-bit target.
2232 let hasSideEffects = 1, usesCustomInserter = 1 in
2233 def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2236 let Uses = [CTR] in {
2237 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2238 "mfctr $rT", IIC_SprMFSPR>,
2239 PPC970_DGroup_First, PPC970_Unit_FXU;
2241 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2242 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2243 "mtctr $rS", IIC_SprMTSPR>,
2244 PPC970_DGroup_First, PPC970_Unit_FXU;
2246 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2247 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2248 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2249 "mtctr $rS", IIC_SprMTSPR>,
2250 PPC970_DGroup_First, PPC970_Unit_FXU;
2253 let Defs = [LR] in {
2254 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2255 "mtlr $rS", IIC_SprMTSPR>,
2256 PPC970_DGroup_First, PPC970_Unit_FXU;
2258 let Uses = [LR] in {
2259 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2260 "mflr $rT", IIC_SprMFSPR>,
2261 PPC970_DGroup_First, PPC970_Unit_FXU;
2264 let isCodeGenOnly = 1 in {
2265 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2266 // like a GPR on the PPC970. As such, copies in and out have the same
2267 // performance characteristics as an OR instruction.
2268 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2269 "mtspr 256, $rS", IIC_IntGeneral>,
2270 PPC970_DGroup_Single, PPC970_Unit_FXU;
2271 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2272 "mfspr $rT, 256", IIC_IntGeneral>,
2273 PPC970_DGroup_First, PPC970_Unit_FXU;
2275 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2276 (outs VRSAVERC:$reg), (ins gprc:$rS),
2277 "mtspr 256, $rS", IIC_IntGeneral>,
2278 PPC970_DGroup_Single, PPC970_Unit_FXU;
2279 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2280 (ins VRSAVERC:$reg),
2281 "mfspr $rT, 256", IIC_IntGeneral>,
2282 PPC970_DGroup_First, PPC970_Unit_FXU;
2285 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2286 // so we'll need to scavenge a register for it.
2288 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2289 "#SPILL_VRSAVE", []>;
2291 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2292 // spilled), so we'll need to scavenge a register for it.
2294 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2295 "#RESTORE_VRSAVE", []>;
2297 let hasSideEffects = 0 in {
2298 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2299 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2300 PPC970_DGroup_First, PPC970_Unit_CRU;
2302 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2303 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2304 PPC970_MicroCode, PPC970_Unit_CRU;
2306 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2307 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2308 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2309 PPC970_DGroup_First, PPC970_Unit_CRU;
2311 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2312 "mfcr $rT", IIC_SprMFCR>,
2313 PPC970_MicroCode, PPC970_Unit_CRU;
2314 } // hasSideEffects = 0
2316 // Pseudo instruction to perform FADD in round-to-zero mode.
2317 let usesCustomInserter = 1, Uses = [RM] in {
2318 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2319 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2322 // The above pseudo gets expanded to make use of the following instructions
2323 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2324 let Uses = [RM], Defs = [RM] in {
2325 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2326 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2327 PPC970_DGroup_Single, PPC970_Unit_FPU;
2328 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2329 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2330 PPC970_DGroup_Single, PPC970_Unit_FPU;
2331 let isCodeGenOnly = 1 in
2332 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2333 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2334 PPC970_DGroup_Single, PPC970_Unit_FPU;
2336 let Uses = [RM] in {
2337 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2338 "mffs $rT", IIC_IntMFFS,
2339 [(set f64:$rT, (PPCmffs))]>,
2340 PPC970_DGroup_Single, PPC970_Unit_FPU;
2343 def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2344 "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2348 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
2349 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2350 let isCommutable = 1 in
2351 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2352 "add", "$rT, $rA, $rB", IIC_IntSimple,
2353 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2354 let isCodeGenOnly = 1 in
2355 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2356 "add $rT, $rA, $rB", IIC_IntSimple,
2357 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2358 let isCommutable = 1 in
2359 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2360 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2361 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2362 PPC970_DGroup_Cracked;
2364 defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2365 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2366 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>;
2367 defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2368 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2369 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>;
2370 def DIVWE : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2371 "divwe $rT, $rA, $rB", IIC_IntDivW,
2372 [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>,
2373 Requires<[HasExtDiv]>;
2375 def DIVWEo : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2376 "divwe. $rT, $rA, $rB", IIC_IntDivW,
2377 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2378 Requires<[HasExtDiv]>;
2379 def DIVWEU : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2380 "divweu $rT, $rA, $rB", IIC_IntDivW,
2381 [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>,
2382 Requires<[HasExtDiv]>;
2384 def DIVWEUo : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2385 "divweu. $rT, $rA, $rB", IIC_IntDivW,
2386 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2387 Requires<[HasExtDiv]>;
2388 let isCommutable = 1 in {
2389 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2390 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2391 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2392 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2393 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2394 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2395 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2396 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2397 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2399 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2400 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2401 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2402 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2403 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2404 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2405 PPC970_DGroup_Cracked;
2406 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2407 "neg", "$rT, $rA", IIC_IntSimple,
2408 [(set i32:$rT, (ineg i32:$rA))]>;
2409 let Uses = [CARRY] in {
2410 let isCommutable = 1 in
2411 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2412 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2413 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2414 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2415 "addme", "$rT, $rA", IIC_IntGeneral,
2416 [(set i32:$rT, (adde i32:$rA, -1))]>;
2417 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2418 "addze", "$rT, $rA", IIC_IntGeneral,
2419 [(set i32:$rT, (adde i32:$rA, 0))]>;
2420 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2421 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2422 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2423 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2424 "subfme", "$rT, $rA", IIC_IntGeneral,
2425 [(set i32:$rT, (sube -1, i32:$rA))]>;
2426 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2427 "subfze", "$rT, $rA", IIC_IntGeneral,
2428 [(set i32:$rT, (sube 0, i32:$rA))]>;
2432 // A-Form instructions. Most of the instructions executed in the FPU are of
2435 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2436 let Uses = [RM] in {
2437 let isCommutable = 1 in {
2438 defm FMADD : AForm_1r<63, 29,
2439 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2440 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2441 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2442 defm FMADDS : AForm_1r<59, 29,
2443 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2444 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2445 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2446 defm FMSUB : AForm_1r<63, 28,
2447 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2448 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2450 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2451 defm FMSUBS : AForm_1r<59, 28,
2452 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2453 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2455 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2456 defm FNMADD : AForm_1r<63, 31,
2457 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2458 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2460 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2461 defm FNMADDS : AForm_1r<59, 31,
2462 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2463 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2465 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2466 defm FNMSUB : AForm_1r<63, 30,
2467 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2468 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2469 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2470 (fneg f64:$FRB))))]>;
2471 defm FNMSUBS : AForm_1r<59, 30,
2472 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2473 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2474 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2475 (fneg f32:$FRB))))]>;
2478 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2479 // having 4 of these, force the comparison to always be an 8-byte double (code
2480 // should use an FMRSD if the input comparison value really wants to be a float)
2481 // and 4/8 byte forms for the result and operand type..
2482 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2483 defm FSELD : AForm_1r<63, 23,
2484 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2485 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2486 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2487 defm FSELS : AForm_1r<63, 23,
2488 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2489 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2490 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2491 let Uses = [RM] in {
2492 let isCommutable = 1 in {
2493 defm FADD : AForm_2r<63, 21,
2494 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2495 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2496 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2497 defm FADDS : AForm_2r<59, 21,
2498 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2499 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2500 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2502 defm FDIV : AForm_2r<63, 18,
2503 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2504 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2505 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2506 defm FDIVS : AForm_2r<59, 18,
2507 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2508 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2509 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2510 let isCommutable = 1 in {
2511 defm FMUL : AForm_3r<63, 25,
2512 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2513 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2514 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2515 defm FMULS : AForm_3r<59, 25,
2516 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2517 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2518 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2520 defm FSUB : AForm_2r<63, 20,
2521 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2522 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2523 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2524 defm FSUBS : AForm_2r<59, 20,
2525 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2526 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2527 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2531 let hasSideEffects = 0 in {
2532 let PPC970_Unit = 1 in { // FXU Operations.
2534 def ISEL : AForm_4<31, 15,
2535 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2536 "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
2540 let PPC970_Unit = 1 in { // FXU Operations.
2541 // M-Form instructions. rotate and mask instructions.
2543 let isCommutable = 1 in {
2544 // RLWIMI can be commuted if the rotate amount is zero.
2545 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2546 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2547 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2548 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2549 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2551 let BaseName = "rlwinm" in {
2552 def RLWINM : MForm_2<21,
2553 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2554 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2557 def RLWINMo : MForm_2<21,
2558 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2559 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2560 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2562 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2563 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2564 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2567 } // hasSideEffects = 0
2569 //===----------------------------------------------------------------------===//
2570 // PowerPC Instruction Patterns
2573 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2574 def : Pat<(i32 imm:$imm),
2575 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2577 // Implement the 'not' operation with the NOR instruction.
2578 def i32not : OutPatFrag<(ops node:$in),
2580 def : Pat<(not i32:$in),
2583 // ADD an arbitrary immediate.
2584 def : Pat<(add i32:$in, imm:$imm),
2585 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2586 // OR an arbitrary immediate.
2587 def : Pat<(or i32:$in, imm:$imm),
2588 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2589 // XOR an arbitrary immediate.
2590 def : Pat<(xor i32:$in, imm:$imm),
2591 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2593 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2594 (SUBFIC $in, imm:$imm)>;
2597 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2598 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2599 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2600 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2603 def : Pat<(rotl i32:$in, i32:$sh),
2604 (RLWNM $in, $sh, 0, 31)>;
2605 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2606 (RLWINM $in, imm:$imm, 0, 31)>;
2609 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2610 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2613 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2614 (BL tglobaladdr:$dst)>;
2615 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2616 (BL texternalsym:$dst)>;
2618 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2619 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2621 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2622 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2624 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2625 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2629 // Hi and Lo for Darwin Global Addresses.
2630 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2631 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2632 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2633 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2634 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2635 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2636 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2637 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2638 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2639 (ADDIS $in, tglobaltlsaddr:$g)>;
2640 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2641 (ADDI $in, tglobaltlsaddr:$g)>;
2642 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2643 (ADDIS $in, tglobaladdr:$g)>;
2644 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2645 (ADDIS $in, tconstpool:$g)>;
2646 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2647 (ADDIS $in, tjumptable:$g)>;
2648 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2649 (ADDIS $in, tblockaddress:$g)>;
2651 // Support for thread-local storage.
2652 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2653 [(set i32:$rD, (PPCppc32GOT))]>;
2655 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2656 // This uses two output registers, the first as the real output, the second as a
2657 // temporary register, used internally in code generation.
2658 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2659 []>, NoEncode<"$rT">;
2661 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2664 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2665 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2666 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2668 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2671 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2672 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2673 // explicitly defined when this op is created, so not mentioned here.
2674 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2675 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2676 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2679 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2680 // Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR
2681 // are true defines while the rest of the Defs are clobbers.
2682 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2683 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2684 def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2685 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2686 "#ADDItlsgdLADDR32",
2688 (PPCaddiTlsgdLAddr i32:$reg,
2689 tglobaltlsaddr:$disp,
2690 tglobaltlsaddr:$sym))]>;
2691 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2694 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2695 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2696 // explicitly defined when this op is created, so not mentioned here.
2697 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2698 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2699 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2702 (PPCgetTlsldAddr i32:$reg,
2703 tglobaltlsaddr:$sym))]>;
2704 // Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR
2705 // are true defines while the rest of the Defs are clobbers.
2706 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2707 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2708 def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2709 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2710 "#ADDItlsldLADDR32",
2712 (PPCaddiTlsldLAddr i32:$reg,
2713 tglobaltlsaddr:$disp,
2714 tglobaltlsaddr:$sym))]>;
2715 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2718 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2719 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2722 (PPCaddisDtprelHA i32:$reg,
2723 tglobaltlsaddr:$disp))]>;
2725 // Support for Position-independent code
2726 def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2729 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2730 // Get Global (GOT) Base Register offset, from the word immediately preceding
2731 // the function label.
2732 def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2735 // Standard shifts. These are represented separately from the real shifts above
2736 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2738 def : Pat<(sra i32:$rS, i32:$rB),
2740 def : Pat<(srl i32:$rS, i32:$rB),
2742 def : Pat<(shl i32:$rS, i32:$rB),
2745 def : Pat<(zextloadi1 iaddr:$src),
2747 def : Pat<(zextloadi1 xaddr:$src),
2749 def : Pat<(extloadi1 iaddr:$src),
2751 def : Pat<(extloadi1 xaddr:$src),
2753 def : Pat<(extloadi8 iaddr:$src),
2755 def : Pat<(extloadi8 xaddr:$src),
2757 def : Pat<(extloadi16 iaddr:$src),
2759 def : Pat<(extloadi16 xaddr:$src),
2761 def : Pat<(f64 (extloadf32 iaddr:$src)),
2762 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2763 def : Pat<(f64 (extloadf32 xaddr:$src)),
2764 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2766 def : Pat<(f64 (fextend f32:$src)),
2767 (COPY_TO_REGCLASS $src, F8RC)>;
2769 // Only seq_cst fences require the heavyweight sync (SYNC 0).
2770 // All others can use the lightweight sync (SYNC 1).
2771 // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2772 // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2773 // versions of Power.
2774 def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2775 def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2776 def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2777 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2779 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2780 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2781 (FNMSUB $A, $C, $B)>;
2782 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2783 (FNMSUB $A, $C, $B)>;
2784 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2785 (FNMSUBS $A, $C, $B)>;
2786 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2787 (FNMSUBS $A, $C, $B)>;
2789 // FCOPYSIGN's operand types need not agree.
2790 def : Pat<(fcopysign f64:$frB, f32:$frA),
2791 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2792 def : Pat<(fcopysign f32:$frB, f64:$frA),
2793 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2795 include "PPCInstrAltivec.td"
2796 include "PPCInstrSPE.td"
2797 include "PPCInstr64Bit.td"
2798 include "PPCInstrVSX.td"
2799 include "PPCInstrQPX.td"
2800 include "PPCInstrHTM.td"
2802 def crnot : OutPatFrag<(ops node:$in),
2804 def : Pat<(not i1:$in),
2807 // Patterns for arithmetic i1 operations.
2808 def : Pat<(add i1:$a, i1:$b),
2810 def : Pat<(sub i1:$a, i1:$b),
2812 def : Pat<(mul i1:$a, i1:$b),
2815 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2816 // (-1 is used to mean all bits set).
2817 def : Pat<(i1 -1), (CRSET)>;
2819 // i1 extensions, implemented in terms of isel.
2820 def : Pat<(i32 (zext i1:$in)),
2821 (SELECT_I4 $in, (LI 1), (LI 0))>;
2822 def : Pat<(i32 (sext i1:$in)),
2823 (SELECT_I4 $in, (LI -1), (LI 0))>;
2825 def : Pat<(i64 (zext i1:$in)),
2826 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2827 def : Pat<(i64 (sext i1:$in)),
2828 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2830 // FIXME: We should choose either a zext or a sext based on other constants
2832 def : Pat<(i32 (anyext i1:$in)),
2833 (SELECT_I4 $in, (LI 1), (LI 0))>;
2834 def : Pat<(i64 (anyext i1:$in)),
2835 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2837 // match setcc on i1 variables.
2855 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2857 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2876 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2878 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2881 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2895 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2897 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2911 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2913 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2916 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2919 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2920 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2921 // floating-point types.
2923 multiclass CRNotPat<dag pattern, dag result> {
2924 def : Pat<pattern, (crnot result)>;
2925 def : Pat<(not pattern), result>;
2927 // We can also fold the crnot into an extension:
2928 def : Pat<(i32 (zext pattern)),
2929 (SELECT_I4 result, (LI 0), (LI 1))>;
2930 def : Pat<(i32 (sext pattern)),
2931 (SELECT_I4 result, (LI 0), (LI -1))>;
2933 // We can also fold the crnot into an extension:
2934 def : Pat<(i64 (zext pattern)),
2935 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2936 def : Pat<(i64 (sext pattern)),
2937 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2939 // FIXME: We should choose either a zext or a sext based on other constants
2941 def : Pat<(i32 (anyext pattern)),
2942 (SELECT_I4 result, (LI 0), (LI 1))>;
2944 def : Pat<(i64 (anyext pattern)),
2945 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2948 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2949 // we need to write imm:$imm in the output patterns below, not just $imm, or
2950 // else the resulting matcher will not correctly add the immediate operand
2951 // (making it a register operand instead).
2954 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2955 OutPatFrag rfrag, OutPatFrag rfrag8> {
2956 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2958 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2960 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2961 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2962 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2963 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2965 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2967 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2969 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2970 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2971 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2972 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2975 // Note that we do all inversions below with i(32|64)not, instead of using
2976 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2977 // has 2-cycle latency.
2979 defm : ExtSetCCPat<SETEQ,
2980 PatFrag<(ops node:$in, node:$cc),
2981 (setcc $in, 0, $cc)>,
2982 OutPatFrag<(ops node:$in),
2983 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2984 OutPatFrag<(ops node:$in),
2985 (RLDICL (CNTLZD $in), 58, 63)> >;
2987 defm : ExtSetCCPat<SETNE,
2988 PatFrag<(ops node:$in, node:$cc),
2989 (setcc $in, 0, $cc)>,
2990 OutPatFrag<(ops node:$in),
2991 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2992 OutPatFrag<(ops node:$in),
2993 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2995 defm : ExtSetCCPat<SETLT,
2996 PatFrag<(ops node:$in, node:$cc),
2997 (setcc $in, 0, $cc)>,
2998 OutPatFrag<(ops node:$in),
2999 (RLWINM $in, 1, 31, 31)>,
3000 OutPatFrag<(ops node:$in),
3001 (RLDICL $in, 1, 63)> >;
3003 defm : ExtSetCCPat<SETGE,
3004 PatFrag<(ops node:$in, node:$cc),
3005 (setcc $in, 0, $cc)>,
3006 OutPatFrag<(ops node:$in),
3007 (RLWINM (i32not $in), 1, 31, 31)>,
3008 OutPatFrag<(ops node:$in),
3009 (RLDICL (i64not $in), 1, 63)> >;
3011 defm : ExtSetCCPat<SETGT,
3012 PatFrag<(ops node:$in, node:$cc),
3013 (setcc $in, 0, $cc)>,
3014 OutPatFrag<(ops node:$in),
3015 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
3016 OutPatFrag<(ops node:$in),
3017 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
3019 defm : ExtSetCCPat<SETLE,
3020 PatFrag<(ops node:$in, node:$cc),
3021 (setcc $in, 0, $cc)>,
3022 OutPatFrag<(ops node:$in),
3023 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
3024 OutPatFrag<(ops node:$in),
3025 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
3027 defm : ExtSetCCPat<SETLT,
3028 PatFrag<(ops node:$in, node:$cc),
3029 (setcc $in, -1, $cc)>,
3030 OutPatFrag<(ops node:$in),
3031 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
3032 OutPatFrag<(ops node:$in),
3033 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3035 defm : ExtSetCCPat<SETGE,
3036 PatFrag<(ops node:$in, node:$cc),
3037 (setcc $in, -1, $cc)>,
3038 OutPatFrag<(ops node:$in),
3039 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
3040 OutPatFrag<(ops node:$in),
3041 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3043 defm : ExtSetCCPat<SETGT,
3044 PatFrag<(ops node:$in, node:$cc),
3045 (setcc $in, -1, $cc)>,
3046 OutPatFrag<(ops node:$in),
3047 (RLWINM (i32not $in), 1, 31, 31)>,
3048 OutPatFrag<(ops node:$in),
3049 (RLDICL (i64not $in), 1, 63)> >;
3051 defm : ExtSetCCPat<SETLE,
3052 PatFrag<(ops node:$in, node:$cc),
3053 (setcc $in, -1, $cc)>,
3054 OutPatFrag<(ops node:$in),
3055 (RLWINM $in, 1, 31, 31)>,
3056 OutPatFrag<(ops node:$in),
3057 (RLDICL $in, 1, 63)> >;
3060 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3061 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3062 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
3063 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3064 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3065 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3066 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
3067 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3068 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
3069 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3070 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
3071 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3073 // For non-equality comparisons, the default code would materialize the
3074 // constant, then compare against it, like this:
3076 // ori r2, r2, 22136
3079 // Since we are just comparing for equality, we can emit this instead:
3080 // xoris r0,r3,0x1234
3081 // cmplwi cr0,r0,0x5678
3084 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
3085 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3086 (LO16 imm:$imm)), sub_eq)>;
3088 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3089 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3090 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
3091 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3092 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
3093 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3094 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
3095 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3096 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
3097 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3098 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
3099 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3101 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
3102 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3103 (LO16 imm:$imm)), sub_eq)>;
3105 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3106 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3107 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3108 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3109 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3110 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3111 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
3112 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3113 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3114 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3116 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3117 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3118 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
3119 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3120 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
3121 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3122 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
3123 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3124 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
3125 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3128 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3129 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3130 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3131 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3132 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3133 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3134 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
3135 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3136 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3137 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3138 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3139 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3141 // For non-equality comparisons, the default code would materialize the
3142 // constant, then compare against it, like this:
3144 // ori r2, r2, 22136
3147 // Since we are just comparing for equality, we can emit this instead:
3148 // xoris r0,r3,0x1234
3149 // cmpldi cr0,r0,0x5678
3152 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
3153 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3154 (LO16 imm:$imm)), sub_eq)>;
3156 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3157 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3158 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
3159 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3160 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3161 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3162 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
3163 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3164 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
3165 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3166 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3167 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3169 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3170 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3171 (LO16 imm:$imm)), sub_eq)>;
3173 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3174 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3175 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3176 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3177 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3178 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3179 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3180 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3181 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3182 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3184 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3185 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3186 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3187 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3188 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3189 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3190 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
3191 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3192 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3193 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3196 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3197 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3198 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3199 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3200 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3201 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3202 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3203 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3204 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3205 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3206 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3207 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3208 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
3209 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3211 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3212 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3213 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3214 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3215 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3216 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3217 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3218 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3219 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3220 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3221 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3222 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3223 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3224 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3227 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3228 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3229 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3230 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3231 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3232 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3233 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3234 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3235 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3236 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3237 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3238 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3239 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3240 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3242 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3243 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3244 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3245 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3246 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3247 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3248 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3249 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3250 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3251 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3252 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3253 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3254 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3255 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3257 // match select on i1 variables:
3258 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3259 (CROR (CRAND $cond , $tval),
3260 (CRAND (crnot $cond), $fval))>;
3262 // match selectcc on i1 variables:
3263 // select (lhs == rhs), tval, fval is:
3264 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3265 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3266 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3267 (CRAND (CRORC $rhs, $lhs), $fval))>;
3268 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
3269 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3270 (CRAND (CRORC $lhs, $rhs), $fval))>;
3271 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3272 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
3273 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3274 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)),
3275 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
3276 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3277 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3278 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3279 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3280 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3281 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
3282 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3283 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
3284 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
3285 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3286 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3287 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3288 (CRAND (CRORC $lhs, $rhs), $fval))>;
3289 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
3290 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3291 (CRAND (CRORC $rhs, $lhs), $fval))>;
3292 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3293 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3294 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3296 // match selectcc on i1 variables with non-i1 output.
3297 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3298 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3299 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
3300 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3301 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3302 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3303 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)),
3304 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3305 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3306 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3307 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3308 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3309 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
3310 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3311 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3312 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3313 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
3314 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3315 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3316 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3318 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3319 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3320 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
3321 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3322 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3323 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3324 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)),
3325 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3326 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3327 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3328 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3329 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3330 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)),
3331 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3332 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3333 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3334 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
3335 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3336 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3337 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3339 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3340 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3341 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
3342 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3343 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3344 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3345 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
3346 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3347 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3348 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3349 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3350 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3351 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
3352 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3353 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3354 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3355 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
3356 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3357 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3358 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3360 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3361 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3362 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
3363 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3364 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3365 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3366 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
3367 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3368 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3369 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3370 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3371 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3372 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
3373 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3374 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3375 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3376 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
3377 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3378 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3379 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3381 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3382 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3383 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)),
3384 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3385 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3386 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3387 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)),
3388 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3389 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3390 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3391 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3392 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3393 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)),
3394 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3395 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3396 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3397 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)),
3398 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3399 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3400 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3402 let usesCustomInserter = 1 in {
3403 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3405 [(set i1:$dst, (trunc (not i32:$in)))]>;
3406 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3408 [(set i1:$dst, (trunc i32:$in))]>;
3410 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3412 [(set i1:$dst, (trunc (not i64:$in)))]>;
3413 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3415 [(set i1:$dst, (trunc i64:$in))]>;
3418 def : Pat<(i1 (not (trunc i32:$in))),
3419 (ANDIo_1_EQ_BIT $in)>;
3420 def : Pat<(i1 (not (trunc i64:$in))),
3421 (ANDIo_1_EQ_BIT8 $in)>;
3423 //===----------------------------------------------------------------------===//
3424 // PowerPC Instructions used for assembler/disassembler only
3427 // FIXME: For B=0 or B > 8, the registers following RT are used.
3428 // WARNING: Do not add patterns for this instruction without fixing this.
3429 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3430 "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3432 // FIXME: For B=0 or B > 8, the registers following RT are used.
3433 // WARNING: Do not add patterns for this instruction without fixing this.
3434 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3435 "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3437 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3438 "isync", IIC_SprISYNC, []>;
3440 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3441 "icbi $src", IIC_LdStICBI, []>;
3443 // We used to have EIEIO as value but E[0-9A-Z] is a reserved name
3444 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3445 "eieio", IIC_LdStLoad, []>;
3447 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3448 "wait $L", IIC_LdStLoad, []>;
3450 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3451 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3453 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3454 "mtsr $SR, $RS", IIC_SprMTSR>;
3456 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3457 "mfsr $RS, $SR", IIC_SprMFSR>;
3459 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3460 "mtsrin $RS, $RB", IIC_SprMTSR>;
3462 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3463 "mfsrin $RS, $RB", IIC_SprMFSR>;
3465 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3466 "mtmsr $RS, $L", IIC_SprMTMSR>;
3468 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3469 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3473 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3474 Requires<[IsBookE]> {
3478 let Inst{21-30} = 163;
3481 def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3482 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3483 def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3484 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3486 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3487 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3488 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3489 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3491 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3492 "mfmsr $RT", IIC_SprMFMSR, []>;
3494 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3495 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3497 def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
3498 "mcrfs $BF, $BFA", IIC_BrMCR>;
3500 def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3501 "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
3503 def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3504 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
3506 def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
3507 def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
3509 def MTFSF : XFLForm_1<63, 711, (outs),
3510 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3511 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
3512 def MTFSFo : XFLForm_1<63, 711, (outs),
3513 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3514 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
3516 def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3517 def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3519 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3520 "slbie $RB", IIC_SprSLBIE, []>;
3522 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3523 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3525 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3526 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3528 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3530 def TLBIA : XForm_0<31, 370, (outs), (ins),
3531 "tlbia", IIC_SprTLBIA, []>;
3533 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3534 "tlbsync", IIC_SprTLBSYNC, []>;
3536 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3537 "tlbiel $RB", IIC_SprTLBIEL, []>;
3539 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3540 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3541 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3542 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3544 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3545 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3547 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3548 IIC_LdStLoad>, Requires<[IsBookE]>;
3550 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3551 IIC_LdStLoad>, Requires<[IsBookE]>;
3553 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3554 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3556 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3557 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3559 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3560 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3562 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3563 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3565 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3566 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3567 Requires<[IsPPC4xx]>;
3568 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3569 (ins gprc:$RST, gprc:$A, gprc:$B),
3570 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3571 Requires<[IsPPC4xx]>, isDOT;
3573 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3575 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3576 Requires<[IsBookE]>;
3577 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3578 Requires<[IsBookE]>;
3580 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3582 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3585 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3586 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3587 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3588 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3590 def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3592 def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3593 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3594 def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3595 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3596 def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3597 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3598 def LDCIX : XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3599 "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3601 def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3602 "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3603 def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3604 "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3605 def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3606 "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3607 def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3608 "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3610 //===----------------------------------------------------------------------===//
3611 // PowerPC Assembler Instruction Aliases
3614 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3615 // These are aliases that require C++ handling to convert to the target
3616 // instruction, while InstAliases can be handled directly by tblgen.
3617 class PPCAsmPseudo<string asm, dag iops>
3619 let Namespace = "PPC";
3620 bit PPC64 = 0; // Default value, override with isPPC64
3622 let OutOperandList = (outs);
3623 let InOperandList = iops;
3625 let AsmString = asm;
3626 let isAsmParserOnly = 1;
3630 def : InstAlias<"sc", (SC 0)>;
3632 def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3633 def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>;
3634 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3635 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3637 def : InstAlias<"wait", (WAIT 0)>;
3638 def : InstAlias<"waitrsv", (WAIT 1)>;
3639 def : InstAlias<"waitimpl", (WAIT 2)>;
3641 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3643 def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>;
3644 def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>;
3646 def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3647 def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3648 def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>;
3650 def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3651 def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3652 def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>;
3654 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3655 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3656 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3657 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3659 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3660 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3662 def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3663 def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3665 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3666 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3668 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3669 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3671 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3672 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3674 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3675 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3677 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3678 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3680 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3681 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3683 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3684 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3686 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3687 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3689 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3690 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3692 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3693 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3695 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3696 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3698 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3699 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3701 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3702 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3703 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3705 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3706 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3708 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3709 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3710 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3711 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3713 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3715 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3716 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3718 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3719 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3721 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3723 foreach BATR = 0-3 in {
3724 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3725 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3726 Requires<[IsPPC6xx]>;
3727 def : InstAlias<"mfdbatu $Rx, "#BATR,
3728 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3729 Requires<[IsPPC6xx]>;
3730 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3731 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3732 Requires<[IsPPC6xx]>;
3733 def : InstAlias<"mfdbatl $Rx, "#BATR,
3734 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3735 Requires<[IsPPC6xx]>;
3736 def : InstAlias<"mtibatu "#BATR#", $Rx",
3737 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3738 Requires<[IsPPC6xx]>;
3739 def : InstAlias<"mfibatu $Rx, "#BATR,
3740 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3741 Requires<[IsPPC6xx]>;
3742 def : InstAlias<"mtibatl "#BATR#", $Rx",
3743 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3744 Requires<[IsPPC6xx]>;
3745 def : InstAlias<"mfibatl $Rx, "#BATR,
3746 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3747 Requires<[IsPPC6xx]>;
3750 foreach BR = 0-7 in {
3751 def : InstAlias<"mfbr"#BR#" $Rx",
3752 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3753 Requires<[IsPPC4xx]>;
3754 def : InstAlias<"mtbr"#BR#" $Rx",
3755 (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3756 Requires<[IsPPC4xx]>;
3759 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3760 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3762 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3763 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3765 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3766 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3768 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3769 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3771 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3772 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3774 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3775 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3777 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3779 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3780 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3781 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3782 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3783 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3784 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3785 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3786 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3788 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3789 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3790 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3791 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3793 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3794 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3796 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3797 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3799 foreach SPRG = 0-3 in {
3800 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3801 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3802 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3803 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3805 foreach SPRG = 4-7 in {
3806 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3807 Requires<[IsBookE]>;
3808 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3809 Requires<[IsBookE]>;
3810 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3811 Requires<[IsBookE]>;
3812 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3813 Requires<[IsBookE]>;
3816 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3818 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3819 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3821 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3823 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3824 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3826 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3827 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3828 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3829 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3831 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3833 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3834 Requires<[IsPPC4xx]>;
3835 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3836 Requires<[IsPPC4xx]>;
3837 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3838 Requires<[IsPPC4xx]>;
3839 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3840 Requires<[IsPPC4xx]>;
3842 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3843 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3844 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3845 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3846 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3847 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3848 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3849 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3850 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3851 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3852 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3853 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3854 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3855 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3856 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3857 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3858 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3859 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3860 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3861 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3862 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3863 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3864 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3865 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3866 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3867 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3868 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3869 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3870 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3871 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3872 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3873 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3874 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3875 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3876 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3877 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3879 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3880 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3881 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3882 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3883 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3884 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3886 def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
3887 def : InstAlias<"cntlzw. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
3888 // The POWER variant
3889 def : MnemonicAlias<"cntlz", "cntlzw">;
3890 def : MnemonicAlias<"cntlz.", "cntlzw.">;
3892 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3893 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3894 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3895 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3896 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3897 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3898 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3899 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3900 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3901 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3902 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3903 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3904 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3905 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3906 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3907 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3908 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3909 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3910 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3911 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3912 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3913 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3914 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3915 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3916 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3917 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3918 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3919 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3920 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3921 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3922 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3923 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3925 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3926 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3927 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3928 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3929 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3930 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3932 def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",
3933 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3934 def RLWINMobm : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b",
3935 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3936 def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b",
3937 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3938 def RLWIMIobm : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",
3939 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3940 def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b",
3941 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3942 def RLWNMobm : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
3943 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3945 // These generic branch instruction forms are used for the assembler parser only.
3946 // Defs and Uses are conservative, since we don't know the BO value.
3947 let PPC970_Unit = 7 in {
3948 let Defs = [CTR], Uses = [CTR, RM] in {
3949 def gBC : BForm_3<16, 0, 0, (outs),
3950 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3951 "bc $bo, $bi, $dst">;
3952 def gBCA : BForm_3<16, 1, 0, (outs),
3953 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3954 "bca $bo, $bi, $dst">;
3956 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3957 def gBCL : BForm_3<16, 0, 1, (outs),
3958 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3959 "bcl $bo, $bi, $dst">;
3960 def gBCLA : BForm_3<16, 1, 1, (outs),
3961 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3962 "bcla $bo, $bi, $dst">;
3964 let Defs = [CTR], Uses = [CTR, LR, RM] in
3965 def gBCLR : XLForm_2<19, 16, 0, (outs),
3966 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3967 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3968 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3969 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3970 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3971 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3972 let Defs = [CTR], Uses = [CTR, LR, RM] in
3973 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3974 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3975 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3976 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3977 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3978 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3979 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3981 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3982 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3983 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3984 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3986 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3987 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3988 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3989 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3990 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3991 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3992 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3994 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3995 : BranchSimpleMnemonic1<name, pm, bo> {
3996 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3997 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3999 defm : BranchSimpleMnemonic2<"t", "", 12>;
4000 defm : BranchSimpleMnemonic2<"f", "", 4>;
4001 defm : BranchSimpleMnemonic2<"t", "-", 14>;
4002 defm : BranchSimpleMnemonic2<"f", "-", 6>;
4003 defm : BranchSimpleMnemonic2<"t", "+", 15>;
4004 defm : BranchSimpleMnemonic2<"f", "+", 7>;
4005 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
4006 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
4007 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
4008 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
4010 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
4011 def : InstAlias<"b"#name#pm#" $cc, $dst",
4012 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
4013 def : InstAlias<"b"#name#pm#" $dst",
4014 (BCC bibo, CR0, condbrtarget:$dst)>;
4016 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
4017 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4018 def : InstAlias<"b"#name#"a"#pm#" $dst",
4019 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
4021 def : InstAlias<"b"#name#"lr"#pm#" $cc",
4022 (BCCLR bibo, crrc:$cc)>;
4023 def : InstAlias<"b"#name#"lr"#pm,
4026 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
4027 (BCCCTR bibo, crrc:$cc)>;
4028 def : InstAlias<"b"#name#"ctr"#pm,
4029 (BCCCTR bibo, CR0)>;
4031 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
4032 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
4033 def : InstAlias<"b"#name#"l"#pm#" $dst",
4034 (BCCL bibo, CR0, condbrtarget:$dst)>;
4036 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
4037 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4038 def : InstAlias<"b"#name#"la"#pm#" $dst",
4039 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
4041 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
4042 (BCCLRL bibo, crrc:$cc)>;
4043 def : InstAlias<"b"#name#"lrl"#pm,
4044 (BCCLRL bibo, CR0)>;
4046 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
4047 (BCCCTRL bibo, crrc:$cc)>;
4048 def : InstAlias<"b"#name#"ctrl"#pm,
4049 (BCCCTRL bibo, CR0)>;
4051 multiclass BranchExtendedMnemonic<string name, int bibo> {
4052 defm : BranchExtendedMnemonicPM<name, "", bibo>;
4053 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
4054 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
4056 defm : BranchExtendedMnemonic<"lt", 12>;
4057 defm : BranchExtendedMnemonic<"gt", 44>;
4058 defm : BranchExtendedMnemonic<"eq", 76>;
4059 defm : BranchExtendedMnemonic<"un", 108>;
4060 defm : BranchExtendedMnemonic<"so", 108>;
4061 defm : BranchExtendedMnemonic<"ge", 4>;
4062 defm : BranchExtendedMnemonic<"nl", 4>;
4063 defm : BranchExtendedMnemonic<"le", 36>;
4064 defm : BranchExtendedMnemonic<"ng", 36>;
4065 defm : BranchExtendedMnemonic<"ne", 68>;
4066 defm : BranchExtendedMnemonic<"nu", 100>;
4067 defm : BranchExtendedMnemonic<"ns", 100>;
4069 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
4070 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
4071 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
4072 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
4073 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
4074 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
4075 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
4076 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
4078 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
4079 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
4080 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
4081 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
4082 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
4083 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4084 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
4085 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4087 multiclass TrapExtendedMnemonic<string name, int to> {
4088 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
4089 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
4090 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
4091 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
4093 defm : TrapExtendedMnemonic<"lt", 16>;
4094 defm : TrapExtendedMnemonic<"le", 20>;
4095 defm : TrapExtendedMnemonic<"eq", 4>;
4096 defm : TrapExtendedMnemonic<"ge", 12>;
4097 defm : TrapExtendedMnemonic<"gt", 8>;
4098 defm : TrapExtendedMnemonic<"nl", 12>;
4099 defm : TrapExtendedMnemonic<"ne", 24>;
4100 defm : TrapExtendedMnemonic<"ng", 20>;
4101 defm : TrapExtendedMnemonic<"llt", 2>;
4102 defm : TrapExtendedMnemonic<"lle", 6>;
4103 defm : TrapExtendedMnemonic<"lge", 5>;
4104 defm : TrapExtendedMnemonic<"lgt", 1>;
4105 defm : TrapExtendedMnemonic<"lnl", 5>;
4106 defm : TrapExtendedMnemonic<"lng", 6>;
4107 defm : TrapExtendedMnemonic<"u", 31>;
4110 def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>;
4111 def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>;
4112 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>;
4113 def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>;
4114 def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
4115 def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
4118 def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>;
4119 def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>;
4120 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>;
4121 def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
4122 def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
4123 def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;