1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 2, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
56 def SDT_PPCnop : SDTypeProfile<0, 0, []>;
58 //===----------------------------------------------------------------------===//
59 // PowerPC specific DAG Nodes.
62 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
63 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
64 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
65 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
66 [SDNPHasChain, SDNPMayStore]>;
68 // This sequence is used for long double->int conversions. It changes the
69 // bits in the FPSCR which is not modelled.
70 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
72 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
73 [SDNPInGlue, SDNPOutGlue]>;
74 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
75 [SDNPInGlue, SDNPOutGlue]>;
76 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
77 [SDNPInGlue, SDNPOutGlue]>;
78 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
83 def PPCfsel : SDNode<"PPCISD::FSEL",
84 // Type constraint for fsel.
85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
88 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
89 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
90 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
91 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
92 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
94 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
96 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
97 // amounts. These nodes are generated by the multi-precision shift code.
98 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
99 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
100 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
102 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
103 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
104 [SDNPHasChain, SDNPMayStore]>;
106 // These are target-independent nodes, but have target-specific formats.
107 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
108 [SDNPHasChain, SDNPOutGlue]>;
109 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
112 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
113 def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall,
114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
116 def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall,
117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInGlue, SDNPOutGlue]>;
120 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
121 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
122 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
123 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
124 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
125 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
126 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
127 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
128 def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone,
129 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
132 def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone,
133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
136 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
137 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
139 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
140 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
143 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
145 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
146 [SDNPHasChain, SDNPOptInGlue]>;
148 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
149 [SDNPHasChain, SDNPMayLoad]>;
150 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
151 [SDNPHasChain, SDNPMayStore]>;
153 // Instructions to support atomic operations
154 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
155 [SDNPHasChain, SDNPMayLoad]>;
156 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
157 [SDNPHasChain, SDNPMayStore]>;
159 // Instructions to support dynamic alloca.
160 def SDTDynOp : SDTypeProfile<1, 2, []>;
161 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
163 //===----------------------------------------------------------------------===//
164 // PowerPC specific transformation functions and pattern fragments.
167 def SHL32 : SDNodeXForm<imm, [{
168 // Transformation function: 31 - imm
169 return getI32Imm(31 - N->getZExtValue());
172 def SRL32 : SDNodeXForm<imm, [{
173 // Transformation function: 32 - imm
174 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
177 def LO16 : SDNodeXForm<imm, [{
178 // Transformation function: get the low 16 bits.
179 return getI32Imm((unsigned short)N->getZExtValue());
182 def HI16 : SDNodeXForm<imm, [{
183 // Transformation function: shift the immediate value down into the low bits.
184 return getI32Imm((unsigned)N->getZExtValue() >> 16);
187 def HA16 : SDNodeXForm<imm, [{
188 // Transformation function: shift the immediate value down into the low bits.
189 signed int Val = N->getZExtValue();
190 return getI32Imm((Val - (signed short)Val) >> 16);
192 def MB : SDNodeXForm<imm, [{
193 // Transformation function: get the start bit of a mask
195 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
196 return getI32Imm(mb);
199 def ME : SDNodeXForm<imm, [{
200 // Transformation function: get the end bit of a mask
202 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
203 return getI32Imm(me);
205 def maskimm32 : PatLeaf<(imm), [{
206 // maskImm predicate - True if immediate is a run of ones.
208 if (N->getValueType(0) == MVT::i32)
209 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
214 def immSExt16 : PatLeaf<(imm), [{
215 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
216 // field. Used by instructions like 'addi'.
217 if (N->getValueType(0) == MVT::i32)
218 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
220 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
222 def immZExt16 : PatLeaf<(imm), [{
223 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
224 // field. Used by instructions like 'ori'.
225 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
228 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
229 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
230 // identical in 32-bit mode, but in 64-bit mode, they return true if the
231 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
233 def imm16ShiftedZExt : PatLeaf<(imm), [{
234 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
235 // immediate are set. Used by instructions like 'xoris'.
236 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
239 def imm16ShiftedSExt : PatLeaf<(imm), [{
240 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
241 // immediate are set. Used by instructions like 'addis'. Identical to
242 // imm16ShiftedZExt in 32-bit mode.
243 if (N->getZExtValue() & 0xFFFF) return false;
244 if (N->getValueType(0) == MVT::i32)
246 // For 64-bit, make sure it is sext right.
247 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
251 //===----------------------------------------------------------------------===//
252 // PowerPC Flag Definitions.
254 class isPPC64 { bit PPC64 = 1; }
256 list<Register> Defs = [CR0];
260 class RegConstraint<string C> {
261 string Constraints = C;
263 class NoEncode<string E> {
264 string DisableEncoding = E;
268 //===----------------------------------------------------------------------===//
269 // PowerPC Operand Definitions.
271 def s5imm : Operand<i32> {
272 let PrintMethod = "printS5ImmOperand";
274 def u5imm : Operand<i32> {
275 let PrintMethod = "printU5ImmOperand";
277 def u6imm : Operand<i32> {
278 let PrintMethod = "printU6ImmOperand";
280 def s16imm : Operand<i32> {
281 let PrintMethod = "printS16ImmOperand";
283 def u16imm : Operand<i32> {
284 let PrintMethod = "printU16ImmOperand";
286 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
287 let PrintMethod = "printS16X4ImmOperand";
289 def directbrtarget : Operand<OtherVT> {
290 let PrintMethod = "printBranchOperand";
291 let EncoderMethod = "getDirectBrEncoding";
293 def condbrtarget : Operand<OtherVT> {
294 let PrintMethod = "printBranchOperand";
295 let EncoderMethod = "getCondBrEncoding";
297 def calltarget : Operand<iPTR> {
298 let EncoderMethod = "getDirectBrEncoding";
300 def aaddr : Operand<iPTR> {
301 let PrintMethod = "printAbsAddrOperand";
303 def symbolHi: Operand<i32> {
304 let PrintMethod = "printSymbolHi";
305 let EncoderMethod = "getHA16Encoding";
307 def symbolLo: Operand<i32> {
308 let PrintMethod = "printSymbolLo";
309 let EncoderMethod = "getLO16Encoding";
311 def crbitm: Operand<i8> {
312 let PrintMethod = "printcrbitm";
313 let EncoderMethod = "get_crbitm_encoding";
316 def memri : Operand<iPTR> {
317 let PrintMethod = "printMemRegImm";
318 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
319 let EncoderMethod = "getMemRIEncoding";
321 def memrr : Operand<iPTR> {
322 let PrintMethod = "printMemRegReg";
323 let MIOperandInfo = (ops ptr_rc, ptr_rc);
325 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
326 let PrintMethod = "printMemRegImmShifted";
327 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
328 let EncoderMethod = "getMemRIXEncoding";
330 def tocentry : Operand<iPTR> {
331 let MIOperandInfo = (ops i32imm:$imm);
334 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
335 // that doesn't matter.
336 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
337 (ops (i32 20), (i32 zero_reg))> {
338 let PrintMethod = "printPredicateOperand";
341 // Define PowerPC specific addressing mode.
342 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
343 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
344 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
345 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
347 /// This is just the offset part of iaddr, used for preinc.
348 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
350 //===----------------------------------------------------------------------===//
351 // PowerPC Instruction Predicate Definitions.
352 def FPContractions : Predicate<"!TM.Options.NoExcessFPPrecision">;
353 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
354 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
355 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
357 //===----------------------------------------------------------------------===//
358 // PowerPC Instruction Definitions.
360 // Pseudo-instructions:
362 let hasCtrlDep = 1 in {
363 let Defs = [R1], Uses = [R1] in {
364 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "",
365 [(callseq_start timm:$amt)]>;
366 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "",
367 [(callseq_end timm:$amt1, timm:$amt2)]>;
370 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
371 "UPDATE_VRSAVE $rD, $rS", []>;
374 let Defs = [R1], Uses = [R1] in
375 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "",
377 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
379 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
380 // instruction selection into a branch sequence.
381 let usesCustomInserter = 1, // Expanded after instruction selection.
382 PPC970_Single = 1 in {
383 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
386 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
389 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
392 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
395 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
400 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
401 // scavenge a register for it.
403 def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
406 // RESTORE_CR - Indicate that we're restoring the CR register (previously
407 // spilled), so we'll need to scavenge a register for it.
409 def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
412 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
413 let isReturn = 1, Uses = [LR, RM] in
414 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
415 "b${p:cc}lr ${p:reg}", BrB,
417 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
418 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
422 def MovePCtoLR : Pseudo<(outs), (ins), "", []>,
425 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
426 let isBarrier = 1 in {
427 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
432 // BCC represents an arbitrary conditional branch on a predicate.
433 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
434 // a two-value operand where a dag node expects two operands. :(
435 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
436 "b${cond:cc} ${cond:reg}, $dst"
437 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
441 let isCall = 1, PPC970_Unit = 7,
442 // All calls clobber the non-callee saved registers...
443 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
444 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
445 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
447 CR0,CR1,CR5,CR6,CR7,CARRY] in {
448 // Convenient aliases for call instructions
450 def BL_Darwin : IForm<18, 0, 1,
451 (outs), (ins calltarget:$func, variable_ops),
452 "bl $func", BrB, []>; // See Pat patterns below.
453 def BLA_Darwin : IForm<18, 1, 1,
454 (outs), (ins aaddr:$func, variable_ops),
455 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>;
457 let Uses = [CTR, RM] in {
458 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
459 (outs), (ins variable_ops),
461 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>;
466 let isCall = 1, PPC970_Unit = 7,
467 // All calls clobber the non-callee saved registers...
468 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
469 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
470 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
472 CR0,CR1,CR5,CR6,CR7,CARRY] in {
473 // Convenient aliases for call instructions
475 def BL_SVR4 : IForm<18, 0, 1,
476 (outs), (ins calltarget:$func, variable_ops),
477 "bl $func", BrB, []>; // See Pat patterns below.
478 def BLA_SVR4 : IForm<18, 1, 1,
479 (outs), (ins aaddr:$func, variable_ops),
481 [(PPCcall_SVR4 (i32 imm:$func))]>;
483 let Uses = [CTR, RM] in {
484 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1,
485 (outs), (ins variable_ops),
487 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>;
492 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
493 def TCRETURNdi :Pseudo< (outs),
494 (ins calltarget:$dst, i32imm:$offset, variable_ops),
495 "#TC_RETURNd $dst $offset",
499 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
500 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
501 "#TC_RETURNa $func $offset",
502 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
504 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
505 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops),
506 "#TC_RETURNr $dst $offset",
510 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
511 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
512 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
513 Requires<[In32BitMode]>;
517 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
518 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
519 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
524 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
525 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
526 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
531 // DCB* instructions.
532 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
533 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
534 PPC970_DGroup_Single;
535 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
536 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
537 PPC970_DGroup_Single;
538 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
539 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
540 PPC970_DGroup_Single;
541 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
542 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
543 PPC970_DGroup_Single;
544 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
545 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
546 PPC970_DGroup_Single;
547 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
548 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
549 PPC970_DGroup_Single;
550 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
551 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
552 PPC970_DGroup_Single;
553 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
554 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
555 PPC970_DGroup_Single;
558 let usesCustomInserter = 1 in {
559 let Defs = [CR0] in {
560 def ATOMIC_LOAD_ADD_I8 : Pseudo<
561 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
562 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
563 def ATOMIC_LOAD_SUB_I8 : Pseudo<
564 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
565 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
566 def ATOMIC_LOAD_AND_I8 : Pseudo<
567 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
568 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
569 def ATOMIC_LOAD_OR_I8 : Pseudo<
570 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
571 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
572 def ATOMIC_LOAD_XOR_I8 : Pseudo<
573 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
574 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
575 def ATOMIC_LOAD_NAND_I8 : Pseudo<
576 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
577 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
578 def ATOMIC_LOAD_ADD_I16 : Pseudo<
579 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
580 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
581 def ATOMIC_LOAD_SUB_I16 : Pseudo<
582 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
583 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
584 def ATOMIC_LOAD_AND_I16 : Pseudo<
585 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
586 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
587 def ATOMIC_LOAD_OR_I16 : Pseudo<
588 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
589 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
590 def ATOMIC_LOAD_XOR_I16 : Pseudo<
591 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
592 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
593 def ATOMIC_LOAD_NAND_I16 : Pseudo<
594 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
595 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
596 def ATOMIC_LOAD_ADD_I32 : Pseudo<
597 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
598 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
599 def ATOMIC_LOAD_SUB_I32 : Pseudo<
600 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
601 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
602 def ATOMIC_LOAD_AND_I32 : Pseudo<
603 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
604 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
605 def ATOMIC_LOAD_OR_I32 : Pseudo<
606 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
607 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
608 def ATOMIC_LOAD_XOR_I32 : Pseudo<
609 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
610 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
611 def ATOMIC_LOAD_NAND_I32 : Pseudo<
612 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
613 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
615 def ATOMIC_CMP_SWAP_I8 : Pseudo<
616 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
618 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
619 def ATOMIC_CMP_SWAP_I16 : Pseudo<
620 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
622 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
623 def ATOMIC_CMP_SWAP_I32 : Pseudo<
624 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
626 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
628 def ATOMIC_SWAP_I8 : Pseudo<
629 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
630 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
631 def ATOMIC_SWAP_I16 : Pseudo<
632 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
633 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
634 def ATOMIC_SWAP_I32 : Pseudo<
635 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
636 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
640 // Instructions to support atomic operations
641 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
642 "lwarx $rD, $src", LdStLWARX,
643 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
646 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
647 "stwcx. $rS, $dst", LdStSTWCX,
648 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
651 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
652 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>;
654 //===----------------------------------------------------------------------===//
655 // PPC32 Load Instructions.
658 // Unindexed (r+i) Loads.
659 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
660 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
661 "lbz $rD, $src", LdStGeneral,
662 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
663 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
664 "lha $rD, $src", LdStLHA,
665 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
666 PPC970_DGroup_Cracked;
667 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
668 "lhz $rD, $src", LdStGeneral,
669 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
670 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
671 "lwz $rD, $src", LdStGeneral,
672 [(set GPRC:$rD, (load iaddr:$src))]>;
674 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
675 "lfs $rD, $src", LdStLFDU,
676 [(set F4RC:$rD, (load iaddr:$src))]>;
677 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
678 "lfd $rD, $src", LdStLFD,
679 [(set F8RC:$rD, (load iaddr:$src))]>;
682 // Unindexed (r+i) Loads with Update (preinc).
684 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
685 "lbzu $rD, $addr", LdStGeneral,
686 []>, RegConstraint<"$addr.reg = $ea_result">,
687 NoEncode<"$ea_result">;
689 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
690 "lhau $rD, $addr", LdStGeneral,
691 []>, RegConstraint<"$addr.reg = $ea_result">,
692 NoEncode<"$ea_result">;
694 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
695 "lhzu $rD, $addr", LdStGeneral,
696 []>, RegConstraint<"$addr.reg = $ea_result">,
697 NoEncode<"$ea_result">;
699 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
700 "lwzu $rD, $addr", LdStGeneral,
701 []>, RegConstraint<"$addr.reg = $ea_result">,
702 NoEncode<"$ea_result">;
704 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
705 "lfs $rD, $addr", LdStLFDU,
706 []>, RegConstraint<"$addr.reg = $ea_result">,
707 NoEncode<"$ea_result">;
709 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
710 "lfd $rD, $addr", LdStLFD,
711 []>, RegConstraint<"$addr.reg = $ea_result">,
712 NoEncode<"$ea_result">;
716 // Indexed (r+r) Loads.
718 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
719 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
720 "lbzx $rD, $src", LdStGeneral,
721 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
722 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
723 "lhax $rD, $src", LdStLHA,
724 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
725 PPC970_DGroup_Cracked;
726 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
727 "lhzx $rD, $src", LdStGeneral,
728 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
729 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
730 "lwzx $rD, $src", LdStGeneral,
731 [(set GPRC:$rD, (load xaddr:$src))]>;
734 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
735 "lhbrx $rD, $src", LdStGeneral,
736 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>;
737 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
738 "lwbrx $rD, $src", LdStGeneral,
739 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>;
741 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
742 "lfsx $frD, $src", LdStLFDU,
743 [(set F4RC:$frD, (load xaddr:$src))]>;
744 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
745 "lfdx $frD, $src", LdStLFDU,
746 [(set F8RC:$frD, (load xaddr:$src))]>;
749 //===----------------------------------------------------------------------===//
750 // PPC32 Store Instructions.
753 // Unindexed (r+i) Stores.
754 let PPC970_Unit = 2 in {
755 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
756 "stb $rS, $src", LdStGeneral,
757 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
758 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
759 "sth $rS, $src", LdStGeneral,
760 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
761 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
762 "stw $rS, $src", LdStGeneral,
763 [(store GPRC:$rS, iaddr:$src)]>;
764 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
765 "stfs $rS, $dst", LdStUX,
766 [(store F4RC:$rS, iaddr:$dst)]>;
767 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
768 "stfd $rS, $dst", LdStUX,
769 [(store F8RC:$rS, iaddr:$dst)]>;
772 // Unindexed (r+i) Stores with Update (preinc).
773 let PPC970_Unit = 2 in {
774 def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
775 symbolLo:$ptroff, ptr_rc:$ptrreg),
776 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
777 [(set ptr_rc:$ea_res,
778 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
779 iaddroff:$ptroff))]>,
780 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
781 def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
782 symbolLo:$ptroff, ptr_rc:$ptrreg),
783 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
784 [(set ptr_rc:$ea_res,
785 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
786 iaddroff:$ptroff))]>,
787 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
788 def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
789 symbolLo:$ptroff, ptr_rc:$ptrreg),
790 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
791 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
792 iaddroff:$ptroff))]>,
793 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
794 def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
795 symbolLo:$ptroff, ptr_rc:$ptrreg),
796 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
797 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
798 iaddroff:$ptroff))]>,
799 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
800 def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
801 symbolLo:$ptroff, ptr_rc:$ptrreg),
802 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
803 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
804 iaddroff:$ptroff))]>,
805 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
809 // Indexed (r+r) Stores.
811 let PPC970_Unit = 2 in {
812 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
813 "stbx $rS, $dst", LdStGeneral,
814 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
815 PPC970_DGroup_Cracked;
816 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
817 "sthx $rS, $dst", LdStGeneral,
818 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
819 PPC970_DGroup_Cracked;
820 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
821 "stwx $rS, $dst", LdStGeneral,
822 [(store GPRC:$rS, xaddr:$dst)]>,
823 PPC970_DGroup_Cracked;
825 let mayStore = 1 in {
826 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
827 "stwux $rS, $rA, $rB", LdStGeneral,
830 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
831 "sthbrx $rS, $dst", LdStGeneral,
832 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>,
833 PPC970_DGroup_Cracked;
834 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
835 "stwbrx $rS, $dst", LdStGeneral,
836 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>,
837 PPC970_DGroup_Cracked;
839 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
840 "stfiwx $frS, $dst", LdStUX,
841 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
843 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
844 "stfsx $frS, $dst", LdStUX,
845 [(store F4RC:$frS, xaddr:$dst)]>;
846 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
847 "stfdx $frS, $dst", LdStUX,
848 [(store F8RC:$frS, xaddr:$dst)]>;
851 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
855 //===----------------------------------------------------------------------===//
856 // PPC32 Arithmetic Instructions.
859 let PPC970_Unit = 1 in { // FXU Operations.
860 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
861 "addi $rD, $rA, $imm", IntGeneral,
862 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
863 let Defs = [CARRY] in {
864 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
865 "addic $rD, $rA, $imm", IntGeneral,
866 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
867 PPC970_DGroup_Cracked;
868 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
869 "addic. $rD, $rA, $imm", IntGeneral,
872 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
873 "addis $rD, $rA, $imm", IntGeneral,
874 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
875 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
876 "la $rD, $sym($rA)", IntGeneral,
877 [(set GPRC:$rD, (add GPRC:$rA,
878 (PPClo tglobaladdr:$sym, 0)))]>;
879 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
880 "mulli $rD, $rA, $imm", IntMulLI,
881 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
882 let Defs = [CARRY] in {
883 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
884 "subfic $rD, $rA, $imm", IntGeneral,
885 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
888 let isReMaterializable = 1 in {
889 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
890 "li $rD, $imm", IntGeneral,
891 [(set GPRC:$rD, immSExt16:$imm)]>;
892 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
893 "lis $rD, $imm", IntGeneral,
894 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
898 let PPC970_Unit = 1 in { // FXU Operations.
899 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
900 "andi. $dst, $src1, $src2", IntGeneral,
901 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
903 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
904 "andis. $dst, $src1, $src2", IntGeneral,
905 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
907 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
908 "ori $dst, $src1, $src2", IntGeneral,
909 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
910 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
911 "oris $dst, $src1, $src2", IntGeneral,
912 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
913 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
914 "xori $dst, $src1, $src2", IntGeneral,
915 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
916 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
917 "xoris $dst, $src1, $src2", IntGeneral,
918 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
919 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
921 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
922 "cmpwi $crD, $rA, $imm", IntCompare>;
923 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
924 "cmplwi $dst, $src1, $src2", IntCompare>;
928 let PPC970_Unit = 1 in { // FXU Operations.
929 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
930 "nand $rA, $rS, $rB", IntGeneral,
931 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
932 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
933 "and $rA, $rS, $rB", IntGeneral,
934 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
935 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
936 "andc $rA, $rS, $rB", IntGeneral,
937 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
938 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
939 "or $rA, $rS, $rB", IntGeneral,
940 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
941 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
942 "nor $rA, $rS, $rB", IntGeneral,
943 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
944 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
945 "orc $rA, $rS, $rB", IntGeneral,
946 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
947 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
948 "eqv $rA, $rS, $rB", IntGeneral,
949 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
950 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
951 "xor $rA, $rS, $rB", IntGeneral,
952 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
953 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
954 "slw $rA, $rS, $rB", IntGeneral,
955 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
956 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
957 "srw $rA, $rS, $rB", IntGeneral,
958 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
959 let Defs = [CARRY] in {
960 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
961 "sraw $rA, $rS, $rB", IntShift,
962 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
966 let PPC970_Unit = 1 in { // FXU Operations.
967 let Defs = [CARRY] in {
968 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
969 "srawi $rA, $rS, $SH", IntShift,
970 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
972 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
973 "cntlzw $rA, $rS", IntGeneral,
974 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
975 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
976 "extsb $rA, $rS", IntGeneral,
977 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
978 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
979 "extsh $rA, $rS", IntGeneral,
980 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
982 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
983 "cmpw $crD, $rA, $rB", IntCompare>;
984 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
985 "cmplw $crD, $rA, $rB", IntCompare>;
987 let PPC970_Unit = 3 in { // FPU Operations.
988 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
989 // "fcmpo $crD, $fA, $fB", FPCompare>;
990 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
991 "fcmpu $crD, $fA, $fB", FPCompare>;
992 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
993 "fcmpu $crD, $fA, $fB", FPCompare>;
996 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
997 "fctiwz $frD, $frB", FPGeneral,
998 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
999 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
1000 "frsp $frD, $frB", FPGeneral,
1001 [(set F4RC:$frD, (fround F8RC:$frB))]>;
1002 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1003 "fsqrt $frD, $frB", FPSqrt,
1004 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
1005 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1006 "fsqrts $frD, $frB", FPSqrt,
1007 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
1011 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1012 /// often coalesced away and we don't want the dispatch group builder to think
1013 /// that they will fill slots (which could cause the load of a LSU reject to
1014 /// sneak into a d-group with a store).
1015 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1016 "fmr $frD, $frB", FPGeneral,
1017 []>, // (set F4RC:$frD, F4RC:$frB)
1020 let PPC970_Unit = 3 in { // FPU Operations.
1021 // These are artificially split into two different forms, for 4/8 byte FP.
1022 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1023 "fabs $frD, $frB", FPGeneral,
1024 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
1025 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1026 "fabs $frD, $frB", FPGeneral,
1027 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
1028 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1029 "fnabs $frD, $frB", FPGeneral,
1030 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
1031 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1032 "fnabs $frD, $frB", FPGeneral,
1033 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
1034 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1035 "fneg $frD, $frB", FPGeneral,
1036 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
1037 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1038 "fneg $frD, $frB", FPGeneral,
1039 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
1043 // XL-Form instructions. condition register logical ops.
1045 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1046 "mcrf $BF, $BFA", BrMCR>,
1047 PPC970_DGroup_First, PPC970_Unit_CRU;
1049 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1050 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1051 "creqv $CRD, $CRA, $CRB", BrCR,
1054 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1055 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1056 "cror $CRD, $CRA, $CRB", BrCR,
1059 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1060 "creqv $dst, $dst, $dst", BrCR,
1063 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins),
1064 "crxor $dst, $dst, $dst", BrCR,
1067 // XFX-Form instructions. Instructions that deal with SPRs.
1069 let Uses = [CTR] in {
1070 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1071 "mfctr $rT", SprMFSPR>,
1072 PPC970_DGroup_First, PPC970_Unit_FXU;
1074 let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in {
1075 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1076 "mtctr $rS", SprMTSPR>,
1077 PPC970_DGroup_First, PPC970_Unit_FXU;
1080 let Defs = [LR] in {
1081 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1082 "mtlr $rS", SprMTSPR>,
1083 PPC970_DGroup_First, PPC970_Unit_FXU;
1085 let Uses = [LR] in {
1086 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1087 "mflr $rT", SprMFSPR>,
1088 PPC970_DGroup_First, PPC970_Unit_FXU;
1091 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1092 // a GPR on the PPC970. As such, copies in and out have the same performance
1093 // characteristics as an OR instruction.
1094 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1095 "mtspr 256, $rS", IntGeneral>,
1096 PPC970_DGroup_Single, PPC970_Unit_FXU;
1097 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1098 "mfspr $rT, 256", IntGeneral>,
1099 PPC970_DGroup_First, PPC970_Unit_FXU;
1101 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
1102 "mtcrf $FXM, $rS", BrMCRX>,
1103 PPC970_MicroCode, PPC970_Unit_CRU;
1105 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1106 // declaring that here gives the local register allocator problems with this:
1108 // MFCR <kill of whatever preg got assigned to vreg>
1109 // while not declaring it breaks DeadMachineInstructionElimination.
1110 // As it turns out, in all cases where we currently use this,
1111 // we're only interested in one subregister of it. Represent this in the
1112 // instruction to keep the register allocator from becoming confused.
1114 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1115 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1117 PPC970_MicroCode, PPC970_Unit_CRU;
1119 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1120 "mfcr $rT", SprMFCR>,
1121 PPC970_MicroCode, PPC970_Unit_CRU;
1123 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1124 "mfcr $rT, $FXM", SprMFCR>,
1125 PPC970_DGroup_First, PPC970_Unit_CRU;
1127 // Instructions to manipulate FPSCR. Only long double handling uses these.
1128 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1130 let Uses = [RM], Defs = [RM] in {
1131 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1132 "mtfsb0 $FM", IntMTFSB0,
1133 [(PPCmtfsb0 (i32 imm:$FM))]>,
1134 PPC970_DGroup_Single, PPC970_Unit_FPU;
1135 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1136 "mtfsb1 $FM", IntMTFSB0,
1137 [(PPCmtfsb1 (i32 imm:$FM))]>,
1138 PPC970_DGroup_Single, PPC970_Unit_FPU;
1139 // MTFSF does not actually produce an FP result. We pretend it copies
1140 // input reg B to the output. If we didn't do this it would look like the
1141 // instruction had no outputs (because we aren't modelling the FPSCR) and
1142 // it would be deleted.
1143 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1144 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1145 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1146 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1147 F8RC:$rT, F8RC:$FRB))]>,
1148 PPC970_DGroup_Single, PPC970_Unit_FPU;
1150 let Uses = [RM] in {
1151 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1152 "mffs $rT", IntMFFS,
1153 [(set F8RC:$rT, (PPCmffs))]>,
1154 PPC970_DGroup_Single, PPC970_Unit_FPU;
1155 def FADDrtz: AForm_2<63, 21,
1156 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1157 "fadd $FRT, $FRA, $FRB", FPGeneral,
1158 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1159 PPC970_DGroup_Single, PPC970_Unit_FPU;
1163 let PPC970_Unit = 1 in { // FXU Operations.
1165 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1167 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1168 "add $rT, $rA, $rB", IntGeneral,
1169 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1170 let Defs = [CARRY] in {
1171 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1172 "addc $rT, $rA, $rB", IntGeneral,
1173 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1174 PPC970_DGroup_Cracked;
1176 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1177 "divw $rT, $rA, $rB", IntDivW,
1178 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1179 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1180 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1181 "divwu $rT, $rA, $rB", IntDivW,
1182 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1183 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1184 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1185 "mulhw $rT, $rA, $rB", IntMulHW,
1186 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1187 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1188 "mulhwu $rT, $rA, $rB", IntMulHWU,
1189 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1190 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1191 "mullw $rT, $rA, $rB", IntMulHW,
1192 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1193 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1194 "subf $rT, $rA, $rB", IntGeneral,
1195 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1196 let Defs = [CARRY] in {
1197 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1198 "subfc $rT, $rA, $rB", IntGeneral,
1199 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1200 PPC970_DGroup_Cracked;
1202 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1203 "neg $rT, $rA", IntGeneral,
1204 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1205 let Uses = [CARRY], Defs = [CARRY] in {
1206 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1207 "adde $rT, $rA, $rB", IntGeneral,
1208 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1209 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1210 "addme $rT, $rA", IntGeneral,
1211 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>;
1212 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1213 "addze $rT, $rA", IntGeneral,
1214 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1215 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1216 "subfe $rT, $rA, $rB", IntGeneral,
1217 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1218 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1219 "subfme $rT, $rA", IntGeneral,
1220 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>;
1221 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1222 "subfze $rT, $rA", IntGeneral,
1223 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1227 // A-Form instructions. Most of the instructions executed in the FPU are of
1230 let PPC970_Unit = 3 in { // FPU Operations.
1231 let Uses = [RM] in {
1232 def FMADD : AForm_1<63, 29,
1233 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1234 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1235 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1237 Requires<[FPContractions]>;
1238 def FMADDS : AForm_1<59, 29,
1239 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1240 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1241 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1243 Requires<[FPContractions]>;
1244 def FMSUB : AForm_1<63, 28,
1245 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1246 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1247 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1249 Requires<[FPContractions]>;
1250 def FMSUBS : AForm_1<59, 28,
1251 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1252 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1253 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1255 Requires<[FPContractions]>;
1256 def FNMADD : AForm_1<63, 31,
1257 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1258 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1259 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1261 Requires<[FPContractions]>;
1262 def FNMADDS : AForm_1<59, 31,
1263 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1264 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1265 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1267 Requires<[FPContractions]>;
1268 def FNMSUB : AForm_1<63, 30,
1269 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1270 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1271 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1273 Requires<[FPContractions]>;
1274 def FNMSUBS : AForm_1<59, 30,
1275 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1276 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1277 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1279 Requires<[FPContractions]>;
1281 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1282 // having 4 of these, force the comparison to always be an 8-byte double (code
1283 // should use an FMRSD if the input comparison value really wants to be a float)
1284 // and 4/8 byte forms for the result and operand type..
1285 def FSELD : AForm_1<63, 23,
1286 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1287 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1288 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1289 def FSELS : AForm_1<63, 23,
1290 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1291 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1292 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1293 let Uses = [RM] in {
1294 def FADD : AForm_2<63, 21,
1295 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1296 "fadd $FRT, $FRA, $FRB", FPGeneral,
1297 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1298 def FADDS : AForm_2<59, 21,
1299 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1300 "fadds $FRT, $FRA, $FRB", FPGeneral,
1301 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1302 def FDIV : AForm_2<63, 18,
1303 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1304 "fdiv $FRT, $FRA, $FRB", FPDivD,
1305 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1306 def FDIVS : AForm_2<59, 18,
1307 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1308 "fdivs $FRT, $FRA, $FRB", FPDivS,
1309 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1310 def FMUL : AForm_3<63, 25,
1311 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1312 "fmul $FRT, $FRA, $FRB", FPFused,
1313 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1314 def FMULS : AForm_3<59, 25,
1315 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1316 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1317 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1318 def FSUB : AForm_2<63, 20,
1319 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1320 "fsub $FRT, $FRA, $FRB", FPGeneral,
1321 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1322 def FSUBS : AForm_2<59, 20,
1323 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1324 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1325 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1329 let PPC970_Unit = 1 in { // FXU Operations.
1330 // M-Form instructions. rotate and mask instructions.
1332 let isCommutable = 1 in {
1333 // RLWIMI can be commuted if the rotate amount is zero.
1334 def RLWIMI : MForm_2<20,
1335 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1336 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1337 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1340 def RLWINM : MForm_2<21,
1341 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1342 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1344 def RLWINMo : MForm_2<21,
1345 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1346 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1347 []>, isDOT, PPC970_DGroup_Cracked;
1348 def RLWNM : MForm_2<23,
1349 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1350 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1355 //===----------------------------------------------------------------------===//
1356 // PowerPC Instruction Patterns
1359 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1360 def : Pat<(i32 imm:$imm),
1361 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1363 // Implement the 'not' operation with the NOR instruction.
1364 def NOT : Pat<(not GPRC:$in),
1365 (NOR GPRC:$in, GPRC:$in)>;
1367 // ADD an arbitrary immediate.
1368 def : Pat<(add GPRC:$in, imm:$imm),
1369 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1370 // OR an arbitrary immediate.
1371 def : Pat<(or GPRC:$in, imm:$imm),
1372 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1373 // XOR an arbitrary immediate.
1374 def : Pat<(xor GPRC:$in, imm:$imm),
1375 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1377 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1378 (SUBFIC GPRC:$in, imm:$imm)>;
1381 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1382 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1383 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1384 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1387 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1388 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1389 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1390 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1393 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1394 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1397 def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)),
1398 (BL_Darwin tglobaladdr:$dst)>;
1399 def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)),
1400 (BL_Darwin texternalsym:$dst)>;
1401 def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)),
1402 (BL_SVR4 tglobaladdr:$dst)>;
1403 def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)),
1404 (BL_SVR4 texternalsym:$dst)>;
1407 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1408 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1410 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1411 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1413 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1414 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1418 // Hi and Lo for Darwin Global Addresses.
1419 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1420 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1421 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1422 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1423 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1424 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1425 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1426 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1427 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1428 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1429 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1430 (ADDIS GPRC:$in, tconstpool:$g)>;
1431 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1432 (ADDIS GPRC:$in, tjumptable:$g)>;
1433 def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)),
1434 (ADDIS GPRC:$in, tblockaddress:$g)>;
1436 // Fused negative multiply subtract, alternate pattern
1437 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1438 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1439 Requires<[FPContractions]>;
1440 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1441 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1442 Requires<[FPContractions]>;
1444 // Standard shifts. These are represented separately from the real shifts above
1445 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1447 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1448 (SRAW GPRC:$rS, GPRC:$rB)>;
1449 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1450 (SRW GPRC:$rS, GPRC:$rB)>;
1451 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1452 (SLW GPRC:$rS, GPRC:$rB)>;
1454 def : Pat<(zextloadi1 iaddr:$src),
1456 def : Pat<(zextloadi1 xaddr:$src),
1458 def : Pat<(extloadi1 iaddr:$src),
1460 def : Pat<(extloadi1 xaddr:$src),
1462 def : Pat<(extloadi8 iaddr:$src),
1464 def : Pat<(extloadi8 xaddr:$src),
1466 def : Pat<(extloadi16 iaddr:$src),
1468 def : Pat<(extloadi16 xaddr:$src),
1470 def : Pat<(f64 (extloadf32 iaddr:$src)),
1471 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1472 def : Pat<(f64 (extloadf32 xaddr:$src)),
1473 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1475 def : Pat<(f64 (fextend F4RC:$src)),
1476 (COPY_TO_REGCLASS F4RC:$src, F8RC)>;
1479 def : Pat<(membarrier (i32 imm /*ll*/),
1483 (i32 imm /*device*/)),
1486 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
1488 include "PPCInstrAltivec.td"
1489 include "PPCInstr64Bit.td"