1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC specific transformation functions and pattern fragments.
21 def LO16 : SDNodeXForm<imm, [{
22 // Transformation function: get the low 16 bits.
23 return getI32Imm((unsigned short)N->getValue());
26 def HI16 : SDNodeXForm<imm, [{
27 // Transformation function: shift the immediate value down into the low bits.
28 return getI32Imm((unsigned)N->getValue() >> 16);
31 def HA16 : SDNodeXForm<imm, [{
32 // Transformation function: shift the immediate value down into the low bits.
33 signed int Val = N->getValue();
34 return getI32Imm((Val - (signed short)Val) >> 16);
38 def immSExt16 : PatLeaf<(imm), [{
39 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
40 // field. Used by instructions like 'addi'.
41 return (int)N->getValue() == (short)N->getValue();
43 def immZExt16 : PatLeaf<(imm), [{
44 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
45 // field. Used by instructions like 'ori'.
46 return (unsigned)N->getValue() == (unsigned short)N->getValue();
49 def imm16Shifted : PatLeaf<(imm), [{
50 // imm16Shifted predicate - True if only bits in the top 16-bits of the
51 // immediate are set. Used by instructions like 'addis'.
52 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
56 // Example of a legalize expander: Only for PPC64.
57 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
58 [(set f64:$tmp , (FCTIDZ f64:$src)),
59 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
60 (store f64:$tmp, i32:$tmpFI),
61 (set i64:$dst, (load i32:$tmpFI))],
65 //===----------------------------------------------------------------------===//
66 // PowerPC Flag Definitions.
68 class isPPC64 { bit PPC64 = 1; }
69 class isVMX { bit VMX = 1; }
71 list<Register> Defs = [CR0];
77 //===----------------------------------------------------------------------===//
78 // PowerPC Operand Definitions.
80 def u5imm : Operand<i32> {
81 let PrintMethod = "printU5ImmOperand";
83 def u6imm : Operand<i32> {
84 let PrintMethod = "printU6ImmOperand";
86 def s16imm : Operand<i32> {
87 let PrintMethod = "printS16ImmOperand";
89 def u16imm : Operand<i32> {
90 let PrintMethod = "printU16ImmOperand";
92 def target : Operand<i32> {
93 let PrintMethod = "printBranchOperand";
95 def piclabel: Operand<i32> {
96 let PrintMethod = "printPICLabel";
98 def symbolHi: Operand<i32> {
99 let PrintMethod = "printSymbolHi";
101 def symbolLo: Operand<i32> {
102 let PrintMethod = "printSymbolLo";
104 def crbitm: Operand<i8> {
105 let PrintMethod = "printcrbitm";
110 //===----------------------------------------------------------------------===//
111 // PowerPC Instruction Definitions.
113 // Pseudo-instructions:
114 def PHI : Pseudo<(ops variable_ops), "; PHI">;
117 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN">;
118 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP">;
120 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
121 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8">;
122 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4">;
124 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
125 // scheduler into a branch sequence.
126 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
127 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
128 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
129 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
130 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
131 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
132 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
136 let isTerminator = 1 in {
138 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
139 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
143 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
145 let isBranch = 1, isTerminator = 1 in {
146 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
147 target:$true, target:$false),
149 def B : IForm<18, 0, 0, (ops target:$func), "b $func">;
150 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">;
151 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">;
152 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">;
154 // FIXME: 4*CR# needs to be added to the BI field!
155 // This will only work for CR0 as it stands now
156 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
158 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
160 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
162 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
164 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
166 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
171 // All calls clobber the non-callee saved registers...
172 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
173 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
175 CR0,CR1,CR5,CR6,CR7] in {
176 // Convenient aliases for call instructions
177 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">;
178 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
179 (ops variable_ops), "bctrl">;
182 // D-Form instructions. Most instructions that perform an operation on a
183 // register and an immediate are of this type.
186 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
187 "lbz $rD, $disp($rA)">;
188 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
189 "lha $rD, $disp($rA)">;
190 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
191 "lhz $rD, $disp($rA)">;
192 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
193 "lmw $rD, $disp($rA)">;
194 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
195 "lwz $rD, $disp($rA)">;
196 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
197 "lwzu $rD, $disp($rA)">;
199 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
200 "addi $rD, $rA, $imm",
201 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
202 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
203 "addic $rD, $rA, $imm",
205 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
206 "addic. $rD, $rA, $imm",
208 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
209 "addis $rD, $rA, $imm",
210 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
211 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
214 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
215 "mulli $rD, $rA, $imm",
216 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
217 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
218 "subfic $rD, $rA, $imm",
219 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
220 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
222 [(set GPRC:$rD, immSExt16:$imm)]>;
223 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
225 [(set GPRC:$rD, imm16Shifted:$imm)]>;
227 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
228 "stmw $rS, $disp($rA)">;
229 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
230 "stb $rS, $disp($rA)">;
231 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
232 "sth $rS, $disp($rA)">;
233 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
234 "stw $rS, $disp($rA)">;
235 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
236 "stwu $rS, $disp($rA)">;
238 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
239 "andi. $dst, $src1, $src2",
241 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
242 "andis. $dst, $src1, $src2",
244 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
245 "ori $dst, $src1, $src2",
246 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
247 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
248 "oris $dst, $src1, $src2",
249 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
250 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
251 "xori $dst, $src1, $src2",
252 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
253 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
254 "xoris $dst, $src1, $src2",
255 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
256 def NOP : DForm_4_zero<24, (ops), "nop">;
257 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
258 "cmpi $crD, $L, $rA, $imm">;
259 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
260 "cmpwi $crD, $rA, $imm">;
261 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
262 "cmpdi $crD, $rA, $imm">, isPPC64;
263 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
264 "cmpli $dst, $size, $src1, $src2">;
265 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
266 "cmplwi $dst, $src1, $src2">;
267 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
268 "cmpldi $dst, $src1, $src2">, isPPC64;
270 def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
271 "lfs $rD, $disp($rA)">;
272 def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
273 "lfd $rD, $disp($rA)">;
276 def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
277 "stfs $rS, $disp($rA)">;
278 def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
279 "stfd $rS, $disp($rA)">;
282 // DS-Form instructions. Load/Store instructions available in PPC-64
285 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
286 "lwa $rT, $DS($rA)">, isPPC64;
287 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
288 "ld $rT, $DS($rA)">, isPPC64;
291 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
292 "std $rT, $DS($rA)">, isPPC64;
293 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
294 "stdu $rT, $DS($rA)">, isPPC64;
297 // X-Form instructions. Most instructions that perform an operation on a
298 // register and another register are of this type.
301 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
302 "lbzx $dst, $base, $index">;
303 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
304 "lhax $dst, $base, $index">;
305 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
306 "lhzx $dst, $base, $index">;
307 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
308 "lwax $dst, $base, $index">, isPPC64;
309 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
310 "lwzx $dst, $base, $index">;
311 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
312 "ldx $dst, $base, $index">, isPPC64;
314 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
315 "nand $rA, $rS, $rB",
316 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
317 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
319 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
320 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
321 "and. $rA, $rS, $rB",
323 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
324 "andc $rA, $rS, $rB",
325 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
326 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
328 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
329 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
331 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
332 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
335 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
337 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
338 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
340 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
341 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
343 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
344 def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
347 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
349 [(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>;
350 def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
353 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
355 [(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>;
356 def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
357 "srad $rA, $rS, $rB",
359 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
360 "sraw $rA, $rS, $rB",
361 [(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>;
363 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
364 "stbx $rS, $rA, $rB">;
365 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
366 "sthx $rS, $rA, $rB">;
367 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
368 "stwx $rS, $rA, $rB">;
369 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
370 "stwux $rS, $rA, $rB">;
371 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
372 "stdx $rS, $rA, $rB">, isPPC64;
373 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
374 "stdux $rS, $rA, $rB">, isPPC64;
376 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
377 "srawi $rA, $rS, $SH",
378 [(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
379 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
381 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
382 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
384 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
385 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
387 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
388 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
391 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
392 "cmp $crD, $long, $rA, $rB">;
393 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
394 "cmpl $crD, $long, $rA, $rB">;
395 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
396 "cmpw $crD, $rA, $rB">;
397 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
398 "cmpd $crD, $rA, $rB">, isPPC64;
399 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
400 "cmplw $crD, $rA, $rB">;
401 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
402 "cmpld $crD, $rA, $rB">, isPPC64;
403 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
404 // "fcmpo $crD, $fA, $fB">;
405 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
406 "fcmpu $crD, $fA, $fB">;
407 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
408 "fcmpu $crD, $fA, $fB">;
411 def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
412 "lfsx $dst, $base, $index">;
413 def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
414 "lfdx $dst, $base, $index">;
416 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
419 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
422 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
425 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
427 [(set F4RC:$frD, (fround F8RC:$frB))]>;
428 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
430 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
431 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
435 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
436 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
438 []>; // (set F4RC:$frD, F4RC:$frB)
439 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
441 []>; // (set F8RC:$frD, F8RC:$frB)
442 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
444 [(set F8RC:$frD, (fextend F4RC:$frB))]>;
446 // These are artificially split into two different forms, for 4/8 byte FP.
447 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
449 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
450 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
452 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
453 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
455 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
456 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
458 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
459 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
461 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
462 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
464 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
468 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
469 "stfsx $frS, $rA, $rB">;
470 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
471 "stfdx $frS, $rA, $rB">;
474 // XL-Form instructions. condition register logical ops.
476 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
479 // XFX-Form instructions. Instructions that deal with SPRs
481 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
482 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
483 // which means the SPR value needs to be multiplied by a factor of 32.
484 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
485 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
486 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
487 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
489 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
491 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
492 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
494 // XS-Form instructions. Just 'sradi'
496 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
497 "sradi $rA, $rS, $SH">, isPPC64;
499 // XO-Form instructions. Arithmetic instructions that can set overflow bit
501 def ADD : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
503 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
504 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
505 "addc $rT, $rA, $rB",
507 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
508 "adde $rT, $rA, $rB",
510 def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
511 "divd $rT, $rA, $rB",
513 def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
514 "divdu $rT, $rA, $rB",
516 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
517 "divw $rT, $rA, $rB",
518 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
519 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
520 "divwu $rT, $rA, $rB",
521 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
522 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
523 "mulhw $rT, $rA, $rB",
524 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
525 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
526 "mulhwu $rT, $rA, $rB",
527 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
528 def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
529 "mulld $rT, $rA, $rB",
531 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
532 "mullw $rT, $rA, $rB",
533 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
534 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
535 "subf $rT, $rA, $rB",
536 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
537 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
538 "subfc $rT, $rA, $rB",
540 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
541 "subfe $rT, $rA, $rB",
543 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
546 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
549 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
551 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
552 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
556 // A-Form instructions. Most of the instructions executed in the FPU are of
559 def FMADD : AForm_1<63, 29,
560 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
561 "fmadd $FRT, $FRA, $FRC, $FRB",
562 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
564 def FMADDS : AForm_1<59, 29,
565 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
566 "fmadds $FRT, $FRA, $FRC, $FRB",
567 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
569 def FMSUB : AForm_1<63, 28,
570 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
571 "fmsub $FRT, $FRA, $FRC, $FRB",
572 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
574 def FMSUBS : AForm_1<59, 28,
575 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
576 "fmsubs $FRT, $FRA, $FRC, $FRB",
577 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
579 def FNMADD : AForm_1<63, 31,
580 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
581 "fnmadd $FRT, $FRA, $FRC, $FRB",
582 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
584 def FNMADDS : AForm_1<59, 31,
585 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
586 "fnmadds $FRT, $FRA, $FRC, $FRB",
587 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
589 def FNMSUB : AForm_1<63, 30,
590 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
591 "fnmsub $FRT, $FRA, $FRC, $FRB",
592 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
594 def FNMSUBS : AForm_1<59, 30,
595 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
596 "fnmsubs $FRT, $FRA, $FRC, $FRB",
597 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
599 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
600 // having 4 of these, force the comparison to always be an 8-byte double (code
601 // should use an FMRSD if the input comparison value really wants to be a float)
602 // and 4/8 byte forms for the result and operand type..
603 def FSELD : AForm_1<63, 23,
604 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
605 "fsel $FRT, $FRA, $FRC, $FRB",
607 def FSELS : AForm_1<63, 23,
608 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
609 "fsel $FRT, $FRA, $FRC, $FRB",
611 def FADD : AForm_2<63, 21,
612 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
613 "fadd $FRT, $FRA, $FRB",
614 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
615 def FADDS : AForm_2<59, 21,
616 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
617 "fadds $FRT, $FRA, $FRB",
618 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
619 def FDIV : AForm_2<63, 18,
620 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
621 "fdiv $FRT, $FRA, $FRB",
622 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
623 def FDIVS : AForm_2<59, 18,
624 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
625 "fdivs $FRT, $FRA, $FRB",
626 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
627 def FMUL : AForm_3<63, 25,
628 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
629 "fmul $FRT, $FRA, $FRB",
630 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
631 def FMULS : AForm_3<59, 25,
632 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
633 "fmuls $FRT, $FRA, $FRB",
634 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
635 def FSUB : AForm_2<63, 20,
636 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
637 "fsub $FRT, $FRA, $FRB",
638 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
639 def FSUBS : AForm_2<59, 20,
640 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
641 "fsubs $FRT, $FRA, $FRB",
642 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
644 // M-Form instructions. rotate and mask instructions.
646 let isTwoAddress = 1, isCommutable = 1 in {
647 // RLWIMI can be commuted if the rotate amount is zero.
648 def RLWIMI : MForm_2<20,
649 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
650 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
652 def RLWINM : MForm_2<21,
653 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
654 "rlwinm $rA, $rS, $SH, $MB, $ME">;
655 def RLWINMo : MForm_2<21,
656 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
657 "rlwinm. $rA, $rS, $SH, $MB, $ME">, isDOT;
658 def RLWNM : MForm_2<23,
659 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
660 "rlwnm $rA, $rS, $rB, $MB, $ME">;
662 // MD-Form instructions. 64 bit rotate instructions.
664 def RLDICL : MDForm_1<30, 0,
665 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
666 "rldicl $rA, $rS, $SH, $MB">, isPPC64;
667 def RLDICR : MDForm_1<30, 1,
668 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
669 "rldicr $rA, $rS, $SH, $ME">, isPPC64;
671 //===----------------------------------------------------------------------===//
672 // PowerPC Instruction Patterns
675 // Arbitrary immediate support. Implement in terms of LIS/ORI.
676 def : Pat<(i32 imm:$imm),
677 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
679 // Implement the 'not' operation with the NOR instruction.
680 def NOT : Pat<(not GPRC:$in),
681 (NOR GPRC:$in, GPRC:$in)>;
683 // ADD an arbitrary immediate.
684 def : Pat<(add GPRC:$in, imm:$imm),
685 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
686 // OR an arbitrary immediate.
687 def : Pat<(or GPRC:$in, imm:$imm),
688 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
689 // XOR an arbitrary immediate.
690 def : Pat<(xor GPRC:$in, imm:$imm),
691 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
695 // Same as above, but using a temporary. FIXME: implement temporaries :)
697 def : Pattern<(xor GPRC:$in, imm:$imm),
698 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
699 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
703 //===----------------------------------------------------------------------===//
704 // PowerPCInstrInfo Definition
706 def PowerPCInstrInfo : InstrInfo {
709 let TSFlagsFields = [ "VMX", "PPC64" ];
710 let TSFlagsShifts = [ 0, 1 ];
712 let isLittleEndianEncoding = 1;