1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
60 def tocentry32 : Operand<iPTR> {
61 let MIOperandInfo = (ops i32imm:$imm);
64 //===----------------------------------------------------------------------===//
65 // PowerPC specific DAG Nodes.
68 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
69 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
71 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
72 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
73 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
74 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
75 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
76 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
77 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
78 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
79 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
80 [SDNPHasChain, SDNPMayStore]>;
81 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
82 [SDNPHasChain, SDNPMayLoad]>;
83 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
84 [SDNPHasChain, SDNPMayLoad]>;
86 // Extract FPSCR (not modeled at the DAG level).
87 def PPCmffs : SDNode<"PPCISD::MFFS",
88 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
90 // Perform FADD in round-to-zero mode.
91 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
94 def PPCfsel : SDNode<"PPCISD::FSEL",
95 // Type constraint for fsel.
96 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
97 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
99 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
100 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
101 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
102 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
103 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
105 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
107 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
108 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
110 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
111 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
112 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
113 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
114 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
115 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
117 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
119 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
121 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
122 // amounts. These nodes are generated by the multi-precision shift code.
123 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
124 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
125 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
127 // These are target-independent nodes, but have target-specific formats.
128 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
129 [SDNPHasChain, SDNPOutGlue]>;
130 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
131 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
133 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
134 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
137 def PPCcall_tls : SDNode<"PPCISD::CALL_TLS", SDT_PPCCall,
138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
140 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
141 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
143 def PPCcall_nop_tls : SDNode<"PPCISD::CALL_NOP_TLS", SDT_PPCCall,
144 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
146 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
147 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
148 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
149 [SDNPHasChain, SDNPSideEffect,
150 SDNPInGlue, SDNPOutGlue]>;
151 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
152 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
153 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
154 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
157 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
158 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
160 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
161 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
163 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
164 SDTypeProfile<1, 1, [SDTCisInt<0>,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
168 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
169 [SDNPHasChain, SDNPSideEffect]>;
171 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
172 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
173 [SDNPHasChain, SDNPSideEffect]>;
175 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
176 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
178 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
179 [SDNPHasChain, SDNPOptInGlue]>;
181 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
182 [SDNPHasChain, SDNPMayLoad]>;
183 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
184 [SDNPHasChain, SDNPMayStore]>;
186 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
187 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
188 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
189 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
190 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
192 // Instructions to support atomic operations
193 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
194 [SDNPHasChain, SDNPMayLoad]>;
195 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
196 [SDNPHasChain, SDNPMayStore]>;
198 // Instructions to support medium and large code model
199 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
200 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
201 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
204 // Instructions to support dynamic alloca.
205 def SDTDynOp : SDTypeProfile<1, 2, []>;
206 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
208 //===----------------------------------------------------------------------===//
209 // PowerPC specific transformation functions and pattern fragments.
212 def SHL32 : SDNodeXForm<imm, [{
213 // Transformation function: 31 - imm
214 return getI32Imm(31 - N->getZExtValue());
217 def SRL32 : SDNodeXForm<imm, [{
218 // Transformation function: 32 - imm
219 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
222 def LO16 : SDNodeXForm<imm, [{
223 // Transformation function: get the low 16 bits.
224 return getI32Imm((unsigned short)N->getZExtValue());
227 def HI16 : SDNodeXForm<imm, [{
228 // Transformation function: shift the immediate value down into the low bits.
229 return getI32Imm((unsigned)N->getZExtValue() >> 16);
232 def HA16 : SDNodeXForm<imm, [{
233 // Transformation function: shift the immediate value down into the low bits.
234 signed int Val = N->getZExtValue();
235 return getI32Imm((Val - (signed short)Val) >> 16);
237 def MB : SDNodeXForm<imm, [{
238 // Transformation function: get the start bit of a mask
240 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
241 return getI32Imm(mb);
244 def ME : SDNodeXForm<imm, [{
245 // Transformation function: get the end bit of a mask
247 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
248 return getI32Imm(me);
250 def maskimm32 : PatLeaf<(imm), [{
251 // maskImm predicate - True if immediate is a run of ones.
253 if (N->getValueType(0) == MVT::i32)
254 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
259 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
260 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
261 // sign extended field. Used by instructions like 'addi'.
262 return (int32_t)Imm == (short)Imm;
264 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
265 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
266 // sign extended field. Used by instructions like 'addi'.
267 return (int64_t)Imm == (short)Imm;
269 def immZExt16 : PatLeaf<(imm), [{
270 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
271 // field. Used by instructions like 'ori'.
272 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
275 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
276 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
277 // identical in 32-bit mode, but in 64-bit mode, they return true if the
278 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
280 def imm16ShiftedZExt : PatLeaf<(imm), [{
281 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
282 // immediate are set. Used by instructions like 'xoris'.
283 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
286 def imm16ShiftedSExt : PatLeaf<(imm), [{
287 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
288 // immediate are set. Used by instructions like 'addis'. Identical to
289 // imm16ShiftedZExt in 32-bit mode.
290 if (N->getZExtValue() & 0xFFFF) return false;
291 if (N->getValueType(0) == MVT::i32)
293 // For 64-bit, make sure it is sext right.
294 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
297 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
298 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
299 // zero extended field.
300 return isUInt<32>(Imm);
303 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
304 // restricted memrix (4-aligned) constants are alignment sensitive. If these
305 // offsets are hidden behind TOC entries than the values of the lower-order
306 // bits cannot be checked directly. As a result, we need to also incorporate
307 // an alignment check into the relevant patterns.
309 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
310 return cast<LoadSDNode>(N)->getAlignment() >= 4;
312 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
313 (store node:$val, node:$ptr), [{
314 return cast<StoreSDNode>(N)->getAlignment() >= 4;
316 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
317 return cast<LoadSDNode>(N)->getAlignment() >= 4;
319 def aligned4pre_store : PatFrag<
320 (ops node:$val, node:$base, node:$offset),
321 (pre_store node:$val, node:$base, node:$offset), [{
322 return cast<StoreSDNode>(N)->getAlignment() >= 4;
325 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
326 return cast<LoadSDNode>(N)->getAlignment() < 4;
328 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
329 (store node:$val, node:$ptr), [{
330 return cast<StoreSDNode>(N)->getAlignment() < 4;
332 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
333 return cast<LoadSDNode>(N)->getAlignment() < 4;
336 //===----------------------------------------------------------------------===//
337 // PowerPC Flag Definitions.
339 class isPPC64 { bit PPC64 = 1; }
340 class isDOT { bit RC = 1; }
342 class RegConstraint<string C> {
343 string Constraints = C;
345 class NoEncode<string E> {
346 string DisableEncoding = E;
350 //===----------------------------------------------------------------------===//
351 // PowerPC Operand Definitions.
353 // In the default PowerPC assembler syntax, registers are specified simply
354 // by number, so they cannot be distinguished from immediate values (without
355 // looking at the opcode). This means that the default operand matching logic
356 // for the asm parser does not work, and we need to specify custom matchers.
357 // Since those can only be specified with RegisterOperand classes and not
358 // directly on the RegisterClass, all instructions patterns used by the asm
359 // parser need to use a RegisterOperand (instead of a RegisterClass) for
360 // all their register operands.
361 // For this purpose, we define one RegisterOperand for each RegisterClass,
362 // using the same name as the class, just in lower case.
364 def PPCRegGPRCAsmOperand : AsmOperandClass {
365 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
367 def gprc : RegisterOperand<GPRC> {
368 let ParserMatchClass = PPCRegGPRCAsmOperand;
370 def PPCRegG8RCAsmOperand : AsmOperandClass {
371 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
373 def g8rc : RegisterOperand<G8RC> {
374 let ParserMatchClass = PPCRegG8RCAsmOperand;
376 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
377 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
379 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
380 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
382 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
383 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
385 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
386 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
388 def PPCRegF8RCAsmOperand : AsmOperandClass {
389 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
391 def f8rc : RegisterOperand<F8RC> {
392 let ParserMatchClass = PPCRegF8RCAsmOperand;
394 def PPCRegF4RCAsmOperand : AsmOperandClass {
395 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
397 def f4rc : RegisterOperand<F4RC> {
398 let ParserMatchClass = PPCRegF4RCAsmOperand;
400 def PPCRegVRRCAsmOperand : AsmOperandClass {
401 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
403 def vrrc : RegisterOperand<VRRC> {
404 let ParserMatchClass = PPCRegVRRCAsmOperand;
406 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
407 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
409 def crbitrc : RegisterOperand<CRBITRC> {
410 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
412 def PPCRegCRRCAsmOperand : AsmOperandClass {
413 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
415 def crrc : RegisterOperand<CRRC> {
416 let ParserMatchClass = PPCRegCRRCAsmOperand;
419 def PPCU2ImmAsmOperand : AsmOperandClass {
420 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
421 let RenderMethod = "addImmOperands";
423 def u2imm : Operand<i32> {
424 let PrintMethod = "printU2ImmOperand";
425 let ParserMatchClass = PPCU2ImmAsmOperand;
428 def PPCU4ImmAsmOperand : AsmOperandClass {
429 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
430 let RenderMethod = "addImmOperands";
432 def u4imm : Operand<i32> {
433 let PrintMethod = "printU4ImmOperand";
434 let ParserMatchClass = PPCU4ImmAsmOperand;
436 def PPCS5ImmAsmOperand : AsmOperandClass {
437 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
438 let RenderMethod = "addImmOperands";
440 def s5imm : Operand<i32> {
441 let PrintMethod = "printS5ImmOperand";
442 let ParserMatchClass = PPCS5ImmAsmOperand;
443 let DecoderMethod = "decodeSImmOperand<5>";
445 def PPCU5ImmAsmOperand : AsmOperandClass {
446 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
447 let RenderMethod = "addImmOperands";
449 def u5imm : Operand<i32> {
450 let PrintMethod = "printU5ImmOperand";
451 let ParserMatchClass = PPCU5ImmAsmOperand;
452 let DecoderMethod = "decodeUImmOperand<5>";
454 def PPCU6ImmAsmOperand : AsmOperandClass {
455 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
456 let RenderMethod = "addImmOperands";
458 def u6imm : Operand<i32> {
459 let PrintMethod = "printU6ImmOperand";
460 let ParserMatchClass = PPCU6ImmAsmOperand;
461 let DecoderMethod = "decodeUImmOperand<6>";
463 def PPCS16ImmAsmOperand : AsmOperandClass {
464 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
465 let RenderMethod = "addS16ImmOperands";
467 def s16imm : Operand<i32> {
468 let PrintMethod = "printS16ImmOperand";
469 let EncoderMethod = "getImm16Encoding";
470 let ParserMatchClass = PPCS16ImmAsmOperand;
471 let DecoderMethod = "decodeSImmOperand<16>";
473 def PPCU16ImmAsmOperand : AsmOperandClass {
474 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
475 let RenderMethod = "addU16ImmOperands";
477 def u16imm : Operand<i32> {
478 let PrintMethod = "printU16ImmOperand";
479 let EncoderMethod = "getImm16Encoding";
480 let ParserMatchClass = PPCU16ImmAsmOperand;
481 let DecoderMethod = "decodeUImmOperand<16>";
483 def PPCS17ImmAsmOperand : AsmOperandClass {
484 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
485 let RenderMethod = "addS16ImmOperands";
487 def s17imm : Operand<i32> {
488 // This operand type is used for addis/lis to allow the assembler parser
489 // to accept immediates in the range -65536..65535 for compatibility with
490 // the GNU assembler. The operand is treated as 16-bit otherwise.
491 let PrintMethod = "printS16ImmOperand";
492 let EncoderMethod = "getImm16Encoding";
493 let ParserMatchClass = PPCS17ImmAsmOperand;
494 let DecoderMethod = "decodeSImmOperand<16>";
496 def PPCDirectBrAsmOperand : AsmOperandClass {
497 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
498 let RenderMethod = "addBranchTargetOperands";
500 def directbrtarget : Operand<OtherVT> {
501 let PrintMethod = "printBranchOperand";
502 let EncoderMethod = "getDirectBrEncoding";
503 let ParserMatchClass = PPCDirectBrAsmOperand;
505 def absdirectbrtarget : Operand<OtherVT> {
506 let PrintMethod = "printAbsBranchOperand";
507 let EncoderMethod = "getAbsDirectBrEncoding";
508 let ParserMatchClass = PPCDirectBrAsmOperand;
510 def PPCCondBrAsmOperand : AsmOperandClass {
511 let Name = "CondBr"; let PredicateMethod = "isCondBr";
512 let RenderMethod = "addBranchTargetOperands";
514 def condbrtarget : Operand<OtherVT> {
515 let PrintMethod = "printBranchOperand";
516 let EncoderMethod = "getCondBrEncoding";
517 let ParserMatchClass = PPCCondBrAsmOperand;
519 def abscondbrtarget : Operand<OtherVT> {
520 let PrintMethod = "printAbsBranchOperand";
521 let EncoderMethod = "getAbsCondBrEncoding";
522 let ParserMatchClass = PPCCondBrAsmOperand;
524 def calltarget : Operand<iPTR> {
525 let PrintMethod = "printBranchOperand";
526 let EncoderMethod = "getDirectBrEncoding";
527 let ParserMatchClass = PPCDirectBrAsmOperand;
529 def abscalltarget : Operand<iPTR> {
530 let PrintMethod = "printAbsBranchOperand";
531 let EncoderMethod = "getAbsDirectBrEncoding";
532 let ParserMatchClass = PPCDirectBrAsmOperand;
534 def PPCCRBitMaskOperand : AsmOperandClass {
535 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
537 def crbitm: Operand<i8> {
538 let PrintMethod = "printcrbitm";
539 let EncoderMethod = "get_crbitm_encoding";
540 let DecoderMethod = "decodeCRBitMOperand";
541 let ParserMatchClass = PPCCRBitMaskOperand;
544 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
545 def PPCRegGxRCNoR0Operand : AsmOperandClass {
546 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
548 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
549 let ParserMatchClass = PPCRegGxRCNoR0Operand;
551 // A version of ptr_rc usable with the asm parser.
552 def PPCRegGxRCOperand : AsmOperandClass {
553 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
555 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
556 let ParserMatchClass = PPCRegGxRCOperand;
559 def PPCDispRIOperand : AsmOperandClass {
560 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
561 let RenderMethod = "addS16ImmOperands";
563 def dispRI : Operand<iPTR> {
564 let ParserMatchClass = PPCDispRIOperand;
566 def PPCDispRIXOperand : AsmOperandClass {
567 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
568 let RenderMethod = "addImmOperands";
570 def dispRIX : Operand<iPTR> {
571 let ParserMatchClass = PPCDispRIXOperand;
573 def PPCDispSPE8Operand : AsmOperandClass {
574 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
575 let RenderMethod = "addImmOperands";
577 def dispSPE8 : Operand<iPTR> {
578 let ParserMatchClass = PPCDispSPE8Operand;
580 def PPCDispSPE4Operand : AsmOperandClass {
581 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
582 let RenderMethod = "addImmOperands";
584 def dispSPE4 : Operand<iPTR> {
585 let ParserMatchClass = PPCDispSPE4Operand;
587 def PPCDispSPE2Operand : AsmOperandClass {
588 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
589 let RenderMethod = "addImmOperands";
591 def dispSPE2 : Operand<iPTR> {
592 let ParserMatchClass = PPCDispSPE2Operand;
595 def memri : Operand<iPTR> {
596 let PrintMethod = "printMemRegImm";
597 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
598 let EncoderMethod = "getMemRIEncoding";
599 let DecoderMethod = "decodeMemRIOperands";
601 def memrr : Operand<iPTR> {
602 let PrintMethod = "printMemRegReg";
603 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
605 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
606 let PrintMethod = "printMemRegImm";
607 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
608 let EncoderMethod = "getMemRIXEncoding";
609 let DecoderMethod = "decodeMemRIXOperands";
611 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
612 let PrintMethod = "printMemRegImm";
613 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
614 let EncoderMethod = "getSPE8DisEncoding";
616 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
617 let PrintMethod = "printMemRegImm";
618 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
619 let EncoderMethod = "getSPE4DisEncoding";
621 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
622 let PrintMethod = "printMemRegImm";
623 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
624 let EncoderMethod = "getSPE2DisEncoding";
627 // A single-register address. This is used with the SjLj
628 // pseudo-instructions.
629 def memr : Operand<iPTR> {
630 let MIOperandInfo = (ops ptr_rc:$ptrreg);
632 def PPCTLSRegOperand : AsmOperandClass {
633 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
634 let RenderMethod = "addTLSRegOperands";
636 def tlsreg32 : Operand<i32> {
637 let EncoderMethod = "getTLSRegEncoding";
638 let ParserMatchClass = PPCTLSRegOperand;
640 def tlsgd32 : Operand<i32> {}
641 def tlscall32 : Operand<i32> {
642 let PrintMethod = "printTLSCall";
643 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
644 let EncoderMethod = "getTLSCallEncoding";
647 // PowerPC Predicate operand.
648 def pred : Operand<OtherVT> {
649 let PrintMethod = "printPredicateOperand";
650 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
653 // Define PowerPC specific addressing mode.
654 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
655 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
656 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
657 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
659 // The address in a single register. This is used with the SjLj
660 // pseudo-instructions.
661 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
663 /// This is just the offset part of iaddr, used for preinc.
664 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
666 //===----------------------------------------------------------------------===//
667 // PowerPC Instruction Predicate Definitions.
668 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
669 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
670 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
671 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
672 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
673 def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
674 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
675 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
676 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
677 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
679 //===----------------------------------------------------------------------===//
680 // PowerPC Multiclass Definitions.
682 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
683 string asmbase, string asmstr, InstrItinClass itin,
685 let BaseName = asmbase in {
686 def NAME : XForm_6<opcode, xo, OOL, IOL,
687 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
688 pattern>, RecFormRel;
690 def o : XForm_6<opcode, xo, OOL, IOL,
691 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
692 []>, isDOT, RecFormRel;
696 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
697 string asmbase, string asmstr, InstrItinClass itin,
699 let BaseName = asmbase in {
700 let Defs = [CARRY] in
701 def NAME : XForm_6<opcode, xo, OOL, IOL,
702 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
703 pattern>, RecFormRel;
704 let Defs = [CARRY, CR0] in
705 def o : XForm_6<opcode, xo, OOL, IOL,
706 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
707 []>, isDOT, RecFormRel;
711 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
712 string asmbase, string asmstr, InstrItinClass itin,
714 let BaseName = asmbase in {
715 let Defs = [CARRY] in
716 def NAME : XForm_10<opcode, xo, OOL, IOL,
717 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
718 pattern>, RecFormRel;
719 let Defs = [CARRY, CR0] in
720 def o : XForm_10<opcode, xo, OOL, IOL,
721 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
722 []>, isDOT, RecFormRel;
726 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
727 string asmbase, string asmstr, InstrItinClass itin,
729 let BaseName = asmbase in {
730 def NAME : XForm_11<opcode, xo, OOL, IOL,
731 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
732 pattern>, RecFormRel;
734 def o : XForm_11<opcode, xo, OOL, IOL,
735 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
736 []>, isDOT, RecFormRel;
740 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
741 string asmbase, string asmstr, InstrItinClass itin,
743 let BaseName = asmbase in {
744 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
745 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
746 pattern>, RecFormRel;
748 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
749 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
750 []>, isDOT, RecFormRel;
754 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
755 string asmbase, string asmstr, InstrItinClass itin,
757 let BaseName = asmbase in {
758 let Defs = [CARRY] in
759 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
760 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
761 pattern>, RecFormRel;
762 let Defs = [CARRY, CR0] in
763 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
764 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
765 []>, isDOT, RecFormRel;
769 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
770 string asmbase, string asmstr, InstrItinClass itin,
772 let BaseName = asmbase in {
773 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
774 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
775 pattern>, RecFormRel;
777 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
778 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
779 []>, isDOT, RecFormRel;
783 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
784 string asmbase, string asmstr, InstrItinClass itin,
786 let BaseName = asmbase in {
787 let Defs = [CARRY] in
788 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
789 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
790 pattern>, RecFormRel;
791 let Defs = [CARRY, CR0] in
792 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
793 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
794 []>, isDOT, RecFormRel;
798 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
799 string asmbase, string asmstr, InstrItinClass itin,
801 let BaseName = asmbase in {
802 def NAME : MForm_2<opcode, OOL, IOL,
803 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
804 pattern>, RecFormRel;
806 def o : MForm_2<opcode, OOL, IOL,
807 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
808 []>, isDOT, RecFormRel;
812 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
813 string asmbase, string asmstr, InstrItinClass itin,
815 let BaseName = asmbase in {
816 def NAME : MDForm_1<opcode, xo, OOL, IOL,
817 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
818 pattern>, RecFormRel;
820 def o : MDForm_1<opcode, xo, OOL, IOL,
821 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
822 []>, isDOT, RecFormRel;
826 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
827 string asmbase, string asmstr, InstrItinClass itin,
829 let BaseName = asmbase in {
830 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
831 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
832 pattern>, RecFormRel;
834 def o : MDSForm_1<opcode, xo, OOL, IOL,
835 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
836 []>, isDOT, RecFormRel;
840 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
841 string asmbase, string asmstr, InstrItinClass itin,
843 let BaseName = asmbase in {
844 let Defs = [CARRY] in
845 def NAME : XSForm_1<opcode, xo, OOL, IOL,
846 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
847 pattern>, RecFormRel;
848 let Defs = [CARRY, CR0] in
849 def o : XSForm_1<opcode, xo, OOL, IOL,
850 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
851 []>, isDOT, RecFormRel;
855 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
856 string asmbase, string asmstr, InstrItinClass itin,
858 let BaseName = asmbase in {
859 def NAME : XForm_26<opcode, xo, OOL, IOL,
860 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
861 pattern>, RecFormRel;
863 def o : XForm_26<opcode, xo, OOL, IOL,
864 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
865 []>, isDOT, RecFormRel;
869 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
870 string asmbase, string asmstr, InstrItinClass itin,
872 let BaseName = asmbase in {
873 def NAME : XForm_28<opcode, xo, OOL, IOL,
874 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
875 pattern>, RecFormRel;
877 def o : XForm_28<opcode, xo, OOL, IOL,
878 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
879 []>, isDOT, RecFormRel;
883 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
884 string asmbase, string asmstr, InstrItinClass itin,
886 let BaseName = asmbase in {
887 def NAME : AForm_1<opcode, xo, OOL, IOL,
888 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
889 pattern>, RecFormRel;
891 def o : AForm_1<opcode, xo, OOL, IOL,
892 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
893 []>, isDOT, RecFormRel;
897 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
898 string asmbase, string asmstr, InstrItinClass itin,
900 let BaseName = asmbase in {
901 def NAME : AForm_2<opcode, xo, OOL, IOL,
902 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
903 pattern>, RecFormRel;
905 def o : AForm_2<opcode, xo, OOL, IOL,
906 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
907 []>, isDOT, RecFormRel;
911 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
912 string asmbase, string asmstr, InstrItinClass itin,
914 let BaseName = asmbase in {
915 def NAME : AForm_3<opcode, xo, OOL, IOL,
916 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
917 pattern>, RecFormRel;
919 def o : AForm_3<opcode, xo, OOL, IOL,
920 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
921 []>, isDOT, RecFormRel;
925 //===----------------------------------------------------------------------===//
926 // PowerPC Instruction Definitions.
928 // Pseudo-instructions:
930 let hasCtrlDep = 1 in {
931 let Defs = [R1], Uses = [R1] in {
932 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
933 [(callseq_start timm:$amt)]>;
934 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
935 [(callseq_end timm:$amt1, timm:$amt2)]>;
938 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
939 "UPDATE_VRSAVE $rD, $rS", []>;
942 let Defs = [R1], Uses = [R1] in
943 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
945 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
947 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
948 // instruction selection into a branch sequence.
949 let usesCustomInserter = 1, // Expanded after instruction selection.
950 PPC970_Single = 1 in {
951 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
952 // because either operand might become the first operand in an isel, and
953 // that operand cannot be r0.
954 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
955 gprc_nor0:$T, gprc_nor0:$F,
956 i32imm:$BROPC), "#SELECT_CC_I4",
958 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
959 g8rc_nox0:$T, g8rc_nox0:$F,
960 i32imm:$BROPC), "#SELECT_CC_I8",
962 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
963 i32imm:$BROPC), "#SELECT_CC_F4",
965 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
966 i32imm:$BROPC), "#SELECT_CC_F8",
968 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
969 i32imm:$BROPC), "#SELECT_CC_VRRC",
972 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
973 // register bit directly.
974 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
975 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
976 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
977 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
978 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
979 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
980 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
981 f4rc:$T, f4rc:$F), "#SELECT_F4",
982 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
983 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
984 f8rc:$T, f8rc:$F), "#SELECT_F8",
985 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
986 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
987 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
989 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
992 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
993 // scavenge a register for it.
994 let mayStore = 1 in {
995 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
997 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1001 // RESTORE_CR - Indicate that we're restoring the CR register (previously
1002 // spilled), so we'll need to scavenge a register for it.
1003 let mayLoad = 1 in {
1004 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1006 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1007 "#RESTORE_CRBIT", []>;
1010 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1011 let isReturn = 1, Uses = [LR, RM] in
1012 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1014 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1015 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1018 let isCodeGenOnly = 1 in {
1019 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1020 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1023 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1024 "bcctr 12, $bi, 0", IIC_BrB, []>;
1025 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1026 "bcctr 4, $bi, 0", IIC_BrB, []>;
1032 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1035 def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1038 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1039 let isBarrier = 1 in {
1040 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1043 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1044 "ba $dst", IIC_BrB, []>;
1047 // BCC represents an arbitrary conditional branch on a predicate.
1048 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1049 // a two-value operand where a dag node expects two operands. :(
1050 let isCodeGenOnly = 1 in {
1051 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1052 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1053 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1054 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1055 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1057 let isReturn = 1, Uses = [LR, RM] in
1058 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1059 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1062 let isCodeGenOnly = 1 in {
1063 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1064 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1065 "bc 12, $bi, $dst">;
1067 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1068 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1071 let isReturn = 1, Uses = [LR, RM] in
1072 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1073 "bclr 12, $bi, 0", IIC_BrB, []>;
1074 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1075 "bclr 4, $bi, 0", IIC_BrB, []>;
1078 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1079 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1080 "bdzlr", IIC_BrB, []>;
1081 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1082 "bdnzlr", IIC_BrB, []>;
1083 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1084 "bdzlr+", IIC_BrB, []>;
1085 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1086 "bdnzlr+", IIC_BrB, []>;
1087 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1088 "bdzlr-", IIC_BrB, []>;
1089 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1090 "bdnzlr-", IIC_BrB, []>;
1093 let Defs = [CTR], Uses = [CTR] in {
1094 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1096 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1098 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1100 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1102 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1104 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1106 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1108 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1110 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1112 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1114 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1116 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1121 // The unconditional BCL used by the SjLj setjmp code.
1122 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1123 let Defs = [LR], Uses = [RM] in {
1124 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1125 "bcl 20, 31, $dst">;
1129 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1130 // Convenient aliases for call instructions
1131 let Uses = [RM] in {
1132 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1133 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1134 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1135 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1137 let isCodeGenOnly = 1 in {
1138 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1139 "bl $func", IIC_BrB, []>;
1140 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1141 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1142 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1143 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1145 def BCL : BForm_4<16, 12, 0, 1, (outs),
1146 (ins crbitrc:$bi, condbrtarget:$dst),
1147 "bcl 12, $bi, $dst">;
1148 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1149 (ins crbitrc:$bi, condbrtarget:$dst),
1150 "bcl 4, $bi, $dst">;
1153 let Uses = [CTR, RM] in {
1154 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1155 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1156 Requires<[In32BitMode]>;
1158 let isCodeGenOnly = 1 in {
1159 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1160 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1163 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1164 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1165 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1166 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1169 let Uses = [LR, RM] in {
1170 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1171 "blrl", IIC_BrB, []>;
1173 let isCodeGenOnly = 1 in {
1174 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1175 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1178 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1179 "bclrl 12, $bi, 0", IIC_BrB, []>;
1180 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1181 "bclrl 4, $bi, 0", IIC_BrB, []>;
1184 let Defs = [CTR], Uses = [CTR, RM] in {
1185 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1187 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1189 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1191 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1193 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1195 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1197 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1199 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1201 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1203 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1205 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1207 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1210 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1211 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1212 "bdzlrl", IIC_BrB, []>;
1213 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1214 "bdnzlrl", IIC_BrB, []>;
1215 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1216 "bdzlrl+", IIC_BrB, []>;
1217 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1218 "bdnzlrl+", IIC_BrB, []>;
1219 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1220 "bdzlrl-", IIC_BrB, []>;
1221 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1222 "bdnzlrl-", IIC_BrB, []>;
1226 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1227 def TCRETURNdi :Pseudo< (outs),
1228 (ins calltarget:$dst, i32imm:$offset),
1229 "#TC_RETURNd $dst $offset",
1233 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1234 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1235 "#TC_RETURNa $func $offset",
1236 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1238 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1239 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1240 "#TC_RETURNr $dst $offset",
1244 let isCodeGenOnly = 1 in {
1246 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1247 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1248 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1249 []>, Requires<[In32BitMode]>;
1251 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1252 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1253 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1257 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1258 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1259 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1265 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1267 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1268 "#EH_SJLJ_SETJMP32",
1269 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1270 Requires<[In32BitMode]>;
1271 let isTerminator = 1 in
1272 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1273 "#EH_SJLJ_LONGJMP32",
1274 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1275 Requires<[In32BitMode]>;
1278 let isBranch = 1, isTerminator = 1 in {
1279 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1280 "#EH_SjLj_Setup\t$dst", []>;
1284 let PPC970_Unit = 7 in {
1285 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1286 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1289 // DCB* instructions.
1290 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1291 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1292 PPC970_DGroup_Single;
1293 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1294 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1295 PPC970_DGroup_Single;
1296 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1297 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1298 PPC970_DGroup_Single;
1299 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1300 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1301 PPC970_DGroup_Single;
1302 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1303 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1304 PPC970_DGroup_Single;
1305 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1306 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1307 PPC970_DGroup_Single;
1308 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1309 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1310 PPC970_DGroup_Single;
1311 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1312 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1313 PPC970_DGroup_Single;
1315 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1316 "icbt $CT, $src", IIC_LdStLoad>, Requires<[IsBookE]>;
1318 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1319 (DCBT xoaddr:$dst)>; // data prefetch for loads
1320 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1321 (DCBTST xoaddr:$dst)>; // data prefetch for stores
1322 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1323 (ICBT 0, xoaddr:$dst)>; // inst prefetch (for read)
1325 // Atomic operations
1326 let usesCustomInserter = 1 in {
1327 let Defs = [CR0] in {
1328 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1329 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1330 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1331 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1332 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1333 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1334 def ATOMIC_LOAD_AND_I8 : Pseudo<
1335 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1336 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1337 def ATOMIC_LOAD_OR_I8 : Pseudo<
1338 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1339 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1340 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1341 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1342 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1343 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1344 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1345 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1346 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1347 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1348 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1349 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1350 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1351 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1352 def ATOMIC_LOAD_AND_I16 : Pseudo<
1353 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1354 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1355 def ATOMIC_LOAD_OR_I16 : Pseudo<
1356 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1357 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1358 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1359 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1360 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1361 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1362 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1363 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1364 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1365 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1366 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1367 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1368 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1369 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1370 def ATOMIC_LOAD_AND_I32 : Pseudo<
1371 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1372 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1373 def ATOMIC_LOAD_OR_I32 : Pseudo<
1374 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1375 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1376 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1377 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1378 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1379 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1380 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1381 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1383 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1384 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1385 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1386 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1387 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1388 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1389 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1390 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1391 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1393 def ATOMIC_SWAP_I8 : Pseudo<
1394 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1395 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1396 def ATOMIC_SWAP_I16 : Pseudo<
1397 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1398 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1399 def ATOMIC_SWAP_I32 : Pseudo<
1400 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1401 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1405 // Instructions to support atomic operations
1406 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1407 "lwarx $rD, $src", IIC_LdStLWARX,
1408 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1411 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1412 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1413 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1416 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1417 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1419 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1420 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1421 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1422 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1423 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1424 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1425 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1426 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1428 //===----------------------------------------------------------------------===//
1429 // PPC32 Load Instructions.
1432 // Unindexed (r+i) Loads.
1433 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1434 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1435 "lbz $rD, $src", IIC_LdStLoad,
1436 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1437 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1438 "lha $rD, $src", IIC_LdStLHA,
1439 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1440 PPC970_DGroup_Cracked;
1441 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1442 "lhz $rD, $src", IIC_LdStLoad,
1443 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1444 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1445 "lwz $rD, $src", IIC_LdStLoad,
1446 [(set i32:$rD, (load iaddr:$src))]>;
1448 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1449 "lfs $rD, $src", IIC_LdStLFD,
1450 [(set f32:$rD, (load iaddr:$src))]>;
1451 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1452 "lfd $rD, $src", IIC_LdStLFD,
1453 [(set f64:$rD, (load iaddr:$src))]>;
1456 // Unindexed (r+i) Loads with Update (preinc).
1457 let mayLoad = 1, hasSideEffects = 0 in {
1458 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1459 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1460 []>, RegConstraint<"$addr.reg = $ea_result">,
1461 NoEncode<"$ea_result">;
1463 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1464 "lhau $rD, $addr", IIC_LdStLHAU,
1465 []>, RegConstraint<"$addr.reg = $ea_result">,
1466 NoEncode<"$ea_result">;
1468 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1469 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1470 []>, RegConstraint<"$addr.reg = $ea_result">,
1471 NoEncode<"$ea_result">;
1473 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1474 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1475 []>, RegConstraint<"$addr.reg = $ea_result">,
1476 NoEncode<"$ea_result">;
1478 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1479 "lfsu $rD, $addr", IIC_LdStLFDU,
1480 []>, RegConstraint<"$addr.reg = $ea_result">,
1481 NoEncode<"$ea_result">;
1483 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1484 "lfdu $rD, $addr", IIC_LdStLFDU,
1485 []>, RegConstraint<"$addr.reg = $ea_result">,
1486 NoEncode<"$ea_result">;
1489 // Indexed (r+r) Loads with Update (preinc).
1490 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1492 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1493 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1494 NoEncode<"$ea_result">;
1496 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1498 "lhaux $rD, $addr", IIC_LdStLHAUX,
1499 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1500 NoEncode<"$ea_result">;
1502 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1504 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1505 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1506 NoEncode<"$ea_result">;
1508 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1510 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1511 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1512 NoEncode<"$ea_result">;
1514 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1516 "lfsux $rD, $addr", IIC_LdStLFDUX,
1517 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1518 NoEncode<"$ea_result">;
1520 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1522 "lfdux $rD, $addr", IIC_LdStLFDUX,
1523 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1524 NoEncode<"$ea_result">;
1528 // Indexed (r+r) Loads.
1530 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1531 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1532 "lbzx $rD, $src", IIC_LdStLoad,
1533 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1534 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1535 "lhax $rD, $src", IIC_LdStLHA,
1536 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1537 PPC970_DGroup_Cracked;
1538 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1539 "lhzx $rD, $src", IIC_LdStLoad,
1540 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1541 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1542 "lwzx $rD, $src", IIC_LdStLoad,
1543 [(set i32:$rD, (load xaddr:$src))]>;
1546 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1547 "lhbrx $rD, $src", IIC_LdStLoad,
1548 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1549 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1550 "lwbrx $rD, $src", IIC_LdStLoad,
1551 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1553 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1554 "lfsx $frD, $src", IIC_LdStLFD,
1555 [(set f32:$frD, (load xaddr:$src))]>;
1556 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1557 "lfdx $frD, $src", IIC_LdStLFD,
1558 [(set f64:$frD, (load xaddr:$src))]>;
1560 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1561 "lfiwax $frD, $src", IIC_LdStLFD,
1562 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1563 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1564 "lfiwzx $frD, $src", IIC_LdStLFD,
1565 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1569 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1570 "lmw $rD, $src", IIC_LdStLMW, []>;
1572 //===----------------------------------------------------------------------===//
1573 // PPC32 Store Instructions.
1576 // Unindexed (r+i) Stores.
1577 let PPC970_Unit = 2 in {
1578 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1579 "stb $rS, $src", IIC_LdStStore,
1580 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1581 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1582 "sth $rS, $src", IIC_LdStStore,
1583 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1584 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1585 "stw $rS, $src", IIC_LdStStore,
1586 [(store i32:$rS, iaddr:$src)]>;
1587 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1588 "stfs $rS, $dst", IIC_LdStSTFD,
1589 [(store f32:$rS, iaddr:$dst)]>;
1590 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1591 "stfd $rS, $dst", IIC_LdStSTFD,
1592 [(store f64:$rS, iaddr:$dst)]>;
1595 // Unindexed (r+i) Stores with Update (preinc).
1596 let PPC970_Unit = 2, mayStore = 1 in {
1597 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1598 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1599 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1600 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1601 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1602 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1603 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1604 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1605 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1606 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1607 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1608 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1609 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1610 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1611 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1614 // Patterns to match the pre-inc stores. We can't put the patterns on
1615 // the instruction definitions directly as ISel wants the address base
1616 // and offset to be separate operands, not a single complex operand.
1617 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1618 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1619 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1620 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1621 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1622 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1623 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1624 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1625 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1626 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1628 // Indexed (r+r) Stores.
1629 let PPC970_Unit = 2 in {
1630 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1631 "stbx $rS, $dst", IIC_LdStStore,
1632 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1633 PPC970_DGroup_Cracked;
1634 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1635 "sthx $rS, $dst", IIC_LdStStore,
1636 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1637 PPC970_DGroup_Cracked;
1638 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1639 "stwx $rS, $dst", IIC_LdStStore,
1640 [(store i32:$rS, xaddr:$dst)]>,
1641 PPC970_DGroup_Cracked;
1643 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1644 "sthbrx $rS, $dst", IIC_LdStStore,
1645 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1646 PPC970_DGroup_Cracked;
1647 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1648 "stwbrx $rS, $dst", IIC_LdStStore,
1649 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1650 PPC970_DGroup_Cracked;
1652 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1653 "stfiwx $frS, $dst", IIC_LdStSTFD,
1654 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1656 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1657 "stfsx $frS, $dst", IIC_LdStSTFD,
1658 [(store f32:$frS, xaddr:$dst)]>;
1659 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1660 "stfdx $frS, $dst", IIC_LdStSTFD,
1661 [(store f64:$frS, xaddr:$dst)]>;
1664 // Indexed (r+r) Stores with Update (preinc).
1665 let PPC970_Unit = 2, mayStore = 1 in {
1666 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1667 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1668 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1669 PPC970_DGroup_Cracked;
1670 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1671 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1672 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1673 PPC970_DGroup_Cracked;
1674 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1675 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1676 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1677 PPC970_DGroup_Cracked;
1678 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1679 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1680 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1681 PPC970_DGroup_Cracked;
1682 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1683 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1684 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1685 PPC970_DGroup_Cracked;
1688 // Patterns to match the pre-inc stores. We can't put the patterns on
1689 // the instruction definitions directly as ISel wants the address base
1690 // and offset to be separate operands, not a single complex operand.
1691 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1692 (STBUX $rS, $ptrreg, $ptroff)>;
1693 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1694 (STHUX $rS, $ptrreg, $ptroff)>;
1695 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1696 (STWUX $rS, $ptrreg, $ptroff)>;
1697 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1698 (STFSUX $rS, $ptrreg, $ptroff)>;
1699 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1700 (STFDUX $rS, $ptrreg, $ptroff)>;
1703 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1704 "stmw $rS, $dst", IIC_LdStLMW, []>;
1706 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1707 "sync $L", IIC_LdStSync, []>;
1709 let isCodeGenOnly = 1 in {
1710 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1711 "msync", IIC_LdStSync, []> {
1716 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>;
1717 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1718 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1719 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1721 //===----------------------------------------------------------------------===//
1722 // PPC32 Arithmetic Instructions.
1725 let PPC970_Unit = 1 in { // FXU Operations.
1726 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1727 "addi $rD, $rA, $imm", IIC_IntSimple,
1728 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1729 let BaseName = "addic" in {
1730 let Defs = [CARRY] in
1731 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1732 "addic $rD, $rA, $imm", IIC_IntGeneral,
1733 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1734 RecFormRel, PPC970_DGroup_Cracked;
1735 let Defs = [CARRY, CR0] in
1736 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1737 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1738 []>, isDOT, RecFormRel;
1740 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1741 "addis $rD, $rA, $imm", IIC_IntSimple,
1742 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1743 let isCodeGenOnly = 1 in
1744 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1745 "la $rD, $sym($rA)", IIC_IntGeneral,
1746 [(set i32:$rD, (add i32:$rA,
1747 (PPClo tglobaladdr:$sym, 0)))]>;
1748 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1749 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1750 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1751 let Defs = [CARRY] in
1752 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1753 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1754 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1756 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1757 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1758 "li $rD, $imm", IIC_IntSimple,
1759 [(set i32:$rD, imm32SExt16:$imm)]>;
1760 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1761 "lis $rD, $imm", IIC_IntSimple,
1762 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1766 let PPC970_Unit = 1 in { // FXU Operations.
1767 let Defs = [CR0] in {
1768 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1769 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1770 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1772 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1773 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1774 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1777 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1778 "ori $dst, $src1, $src2", IIC_IntSimple,
1779 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1780 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1781 "oris $dst, $src1, $src2", IIC_IntSimple,
1782 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1783 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1784 "xori $dst, $src1, $src2", IIC_IntSimple,
1785 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1786 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1787 "xoris $dst, $src1, $src2", IIC_IntSimple,
1788 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1790 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1792 let isCodeGenOnly = 1 in {
1793 // The POWER6 and POWER7 have special group-terminating nops.
1794 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1795 "ori 1, 1, 0", IIC_IntSimple, []>;
1796 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1797 "ori 2, 2, 0", IIC_IntSimple, []>;
1800 let isCompare = 1, hasSideEffects = 0 in {
1801 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1802 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1803 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1804 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1808 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
1809 let isCommutable = 1 in {
1810 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1811 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1812 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1813 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1814 "and", "$rA, $rS, $rB", IIC_IntSimple,
1815 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1817 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1818 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1819 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1820 let isCommutable = 1 in {
1821 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1822 "or", "$rA, $rS, $rB", IIC_IntSimple,
1823 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1824 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1825 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1826 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1828 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1829 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1830 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1831 let isCommutable = 1 in {
1832 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1833 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1834 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1835 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1836 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1837 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1839 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1840 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1841 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1842 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1843 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1844 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1845 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1846 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1847 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1850 let PPC970_Unit = 1 in { // FXU Operations.
1851 let hasSideEffects = 0 in {
1852 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1853 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1854 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1855 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1856 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1857 [(set i32:$rA, (ctlz i32:$rS))]>;
1858 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1859 "extsb", "$rA, $rS", IIC_IntSimple,
1860 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1861 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1862 "extsh", "$rA, $rS", IIC_IntSimple,
1863 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1865 let isCompare = 1, hasSideEffects = 0 in {
1866 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1867 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1868 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1869 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1872 let PPC970_Unit = 3 in { // FPU Operations.
1873 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1874 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1875 let isCompare = 1, hasSideEffects = 0 in {
1876 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1877 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1878 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1879 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1880 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1883 let Uses = [RM] in {
1884 let hasSideEffects = 0 in {
1885 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1886 "fctiw", "$frD, $frB", IIC_FPGeneral,
1888 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1889 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1890 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1892 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1893 "frsp", "$frD, $frB", IIC_FPGeneral,
1894 [(set f32:$frD, (fround f64:$frB))]>;
1896 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1897 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1898 "frin", "$frD, $frB", IIC_FPGeneral,
1899 [(set f64:$frD, (frnd f64:$frB))]>;
1900 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1901 "frin", "$frD, $frB", IIC_FPGeneral,
1902 [(set f32:$frD, (frnd f32:$frB))]>;
1905 let hasSideEffects = 0 in {
1906 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1907 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1908 "frip", "$frD, $frB", IIC_FPGeneral,
1909 [(set f64:$frD, (fceil f64:$frB))]>;
1910 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1911 "frip", "$frD, $frB", IIC_FPGeneral,
1912 [(set f32:$frD, (fceil f32:$frB))]>;
1913 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1914 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1915 "friz", "$frD, $frB", IIC_FPGeneral,
1916 [(set f64:$frD, (ftrunc f64:$frB))]>;
1917 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1918 "friz", "$frD, $frB", IIC_FPGeneral,
1919 [(set f32:$frD, (ftrunc f32:$frB))]>;
1920 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1921 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1922 "frim", "$frD, $frB", IIC_FPGeneral,
1923 [(set f64:$frD, (ffloor f64:$frB))]>;
1924 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1925 "frim", "$frD, $frB", IIC_FPGeneral,
1926 [(set f32:$frD, (ffloor f32:$frB))]>;
1928 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1929 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1930 [(set f64:$frD, (fsqrt f64:$frB))]>;
1931 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1932 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1933 [(set f32:$frD, (fsqrt f32:$frB))]>;
1938 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1939 /// often coalesced away and we don't want the dispatch group builder to think
1940 /// that they will fill slots (which could cause the load of a LSU reject to
1941 /// sneak into a d-group with a store).
1942 let hasSideEffects = 0 in
1943 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1944 "fmr", "$frD, $frB", IIC_FPGeneral,
1945 []>, // (set f32:$frD, f32:$frB)
1948 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
1949 // These are artificially split into two different forms, for 4/8 byte FP.
1950 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1951 "fabs", "$frD, $frB", IIC_FPGeneral,
1952 [(set f32:$frD, (fabs f32:$frB))]>;
1953 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1954 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1955 "fabs", "$frD, $frB", IIC_FPGeneral,
1956 [(set f64:$frD, (fabs f64:$frB))]>;
1957 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1958 "fnabs", "$frD, $frB", IIC_FPGeneral,
1959 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1960 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1961 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1962 "fnabs", "$frD, $frB", IIC_FPGeneral,
1963 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1964 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1965 "fneg", "$frD, $frB", IIC_FPGeneral,
1966 [(set f32:$frD, (fneg f32:$frB))]>;
1967 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1968 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1969 "fneg", "$frD, $frB", IIC_FPGeneral,
1970 [(set f64:$frD, (fneg f64:$frB))]>;
1972 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1973 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1974 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1975 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1976 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1977 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1978 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1980 // Reciprocal estimates.
1981 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1982 "fre", "$frD, $frB", IIC_FPGeneral,
1983 [(set f64:$frD, (PPCfre f64:$frB))]>;
1984 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1985 "fres", "$frD, $frB", IIC_FPGeneral,
1986 [(set f32:$frD, (PPCfre f32:$frB))]>;
1987 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1988 "frsqrte", "$frD, $frB", IIC_FPGeneral,
1989 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1990 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1991 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
1992 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1995 // XL-Form instructions. condition register logical ops.
1997 let hasSideEffects = 0 in
1998 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1999 "mcrf $BF, $BFA", IIC_BrMCR>,
2000 PPC970_DGroup_First, PPC970_Unit_CRU;
2002 let isCommutable = 1 in {
2003 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
2004 (ins crbitrc:$CRA, crbitrc:$CRB),
2005 "crand $CRD, $CRA, $CRB", IIC_BrCR,
2006 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2008 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2009 (ins crbitrc:$CRA, crbitrc:$CRB),
2010 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2011 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2013 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
2014 (ins crbitrc:$CRA, crbitrc:$CRB),
2015 "cror $CRD, $CRA, $CRB", IIC_BrCR,
2016 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2018 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
2019 (ins crbitrc:$CRA, crbitrc:$CRB),
2020 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2021 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2023 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
2024 (ins crbitrc:$CRA, crbitrc:$CRB),
2025 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2026 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2028 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
2029 (ins crbitrc:$CRA, crbitrc:$CRB),
2030 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2031 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2034 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2035 (ins crbitrc:$CRA, crbitrc:$CRB),
2036 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2037 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2039 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
2040 (ins crbitrc:$CRA, crbitrc:$CRB),
2041 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2042 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2044 let isCodeGenOnly = 1 in {
2045 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2046 "creqv $dst, $dst, $dst", IIC_BrCR,
2047 [(set i1:$dst, 1)]>;
2049 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2050 "crxor $dst, $dst, $dst", IIC_BrCR,
2051 [(set i1:$dst, 0)]>;
2053 let Defs = [CR1EQ], CRD = 6 in {
2054 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2055 "creqv 6, 6, 6", IIC_BrCR,
2058 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2059 "crxor 6, 6, 6", IIC_BrCR,
2064 // XFX-Form instructions. Instructions that deal with SPRs.
2067 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2068 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2069 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2070 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2072 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2073 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2075 // A pseudo-instruction used to implement the read of the 64-bit cycle counter
2076 // on a 32-bit target.
2077 let hasSideEffects = 1, usesCustomInserter = 1 in
2078 def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2081 let Uses = [CTR] in {
2082 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2083 "mfctr $rT", IIC_SprMFSPR>,
2084 PPC970_DGroup_First, PPC970_Unit_FXU;
2086 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2087 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2088 "mtctr $rS", IIC_SprMTSPR>,
2089 PPC970_DGroup_First, PPC970_Unit_FXU;
2091 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2092 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2093 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2094 "mtctr $rS", IIC_SprMTSPR>,
2095 PPC970_DGroup_First, PPC970_Unit_FXU;
2098 let Defs = [LR] in {
2099 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2100 "mtlr $rS", IIC_SprMTSPR>,
2101 PPC970_DGroup_First, PPC970_Unit_FXU;
2103 let Uses = [LR] in {
2104 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2105 "mflr $rT", IIC_SprMFSPR>,
2106 PPC970_DGroup_First, PPC970_Unit_FXU;
2109 let isCodeGenOnly = 1 in {
2110 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2111 // like a GPR on the PPC970. As such, copies in and out have the same
2112 // performance characteristics as an OR instruction.
2113 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2114 "mtspr 256, $rS", IIC_IntGeneral>,
2115 PPC970_DGroup_Single, PPC970_Unit_FXU;
2116 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2117 "mfspr $rT, 256", IIC_IntGeneral>,
2118 PPC970_DGroup_First, PPC970_Unit_FXU;
2120 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2121 (outs VRSAVERC:$reg), (ins gprc:$rS),
2122 "mtspr 256, $rS", IIC_IntGeneral>,
2123 PPC970_DGroup_Single, PPC970_Unit_FXU;
2124 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2125 (ins VRSAVERC:$reg),
2126 "mfspr $rT, 256", IIC_IntGeneral>,
2127 PPC970_DGroup_First, PPC970_Unit_FXU;
2130 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2131 // so we'll need to scavenge a register for it.
2133 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2134 "#SPILL_VRSAVE", []>;
2136 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2137 // spilled), so we'll need to scavenge a register for it.
2139 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2140 "#RESTORE_VRSAVE", []>;
2142 let hasSideEffects = 0 in {
2143 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2144 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2145 PPC970_DGroup_First, PPC970_Unit_CRU;
2147 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2148 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2149 PPC970_MicroCode, PPC970_Unit_CRU;
2151 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2152 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2153 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2154 PPC970_DGroup_First, PPC970_Unit_CRU;
2156 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2157 "mfcr $rT", IIC_SprMFCR>,
2158 PPC970_MicroCode, PPC970_Unit_CRU;
2159 } // hasSideEffects = 0
2161 // Pseudo instruction to perform FADD in round-to-zero mode.
2162 let usesCustomInserter = 1, Uses = [RM] in {
2163 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2164 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2167 // The above pseudo gets expanded to make use of the following instructions
2168 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2169 let Uses = [RM], Defs = [RM] in {
2170 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2171 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2172 PPC970_DGroup_Single, PPC970_Unit_FPU;
2173 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2174 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2175 PPC970_DGroup_Single, PPC970_Unit_FPU;
2176 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2177 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2178 PPC970_DGroup_Single, PPC970_Unit_FPU;
2180 let Uses = [RM] in {
2181 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2182 "mffs $rT", IIC_IntMFFS,
2183 [(set f64:$rT, (PPCmffs))]>,
2184 PPC970_DGroup_Single, PPC970_Unit_FPU;
2188 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
2189 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2190 let isCommutable = 1 in
2191 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2192 "add", "$rT, $rA, $rB", IIC_IntSimple,
2193 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2194 let isCodeGenOnly = 1 in
2195 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2196 "add $rT, $rA, $rB", IIC_IntSimple,
2197 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2198 let isCommutable = 1 in
2199 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2200 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2201 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2202 PPC970_DGroup_Cracked;
2204 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2205 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2206 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2207 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2208 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2209 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2210 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2211 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2212 let isCommutable = 1 in {
2213 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2214 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2215 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2216 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2217 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2218 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2219 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2220 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2221 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2223 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2224 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2225 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2226 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2227 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2228 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2229 PPC970_DGroup_Cracked;
2230 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2231 "neg", "$rT, $rA", IIC_IntSimple,
2232 [(set i32:$rT, (ineg i32:$rA))]>;
2233 let Uses = [CARRY] in {
2234 let isCommutable = 1 in
2235 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2236 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2237 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2238 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2239 "addme", "$rT, $rA", IIC_IntGeneral,
2240 [(set i32:$rT, (adde i32:$rA, -1))]>;
2241 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2242 "addze", "$rT, $rA", IIC_IntGeneral,
2243 [(set i32:$rT, (adde i32:$rA, 0))]>;
2244 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2245 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2246 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2247 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2248 "subfme", "$rT, $rA", IIC_IntGeneral,
2249 [(set i32:$rT, (sube -1, i32:$rA))]>;
2250 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2251 "subfze", "$rT, $rA", IIC_IntGeneral,
2252 [(set i32:$rT, (sube 0, i32:$rA))]>;
2256 // A-Form instructions. Most of the instructions executed in the FPU are of
2259 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2260 let Uses = [RM] in {
2261 let isCommutable = 1 in {
2262 defm FMADD : AForm_1r<63, 29,
2263 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2264 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2265 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2266 defm FMADDS : AForm_1r<59, 29,
2267 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2268 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2269 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2270 defm FMSUB : AForm_1r<63, 28,
2271 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2272 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2274 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2275 defm FMSUBS : AForm_1r<59, 28,
2276 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2277 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2279 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2280 defm FNMADD : AForm_1r<63, 31,
2281 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2282 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2284 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2285 defm FNMADDS : AForm_1r<59, 31,
2286 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2287 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2289 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2290 defm FNMSUB : AForm_1r<63, 30,
2291 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2292 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2293 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2294 (fneg f64:$FRB))))]>;
2295 defm FNMSUBS : AForm_1r<59, 30,
2296 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2297 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2298 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2299 (fneg f32:$FRB))))]>;
2302 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2303 // having 4 of these, force the comparison to always be an 8-byte double (code
2304 // should use an FMRSD if the input comparison value really wants to be a float)
2305 // and 4/8 byte forms for the result and operand type..
2306 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2307 defm FSELD : AForm_1r<63, 23,
2308 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2309 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2310 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2311 defm FSELS : AForm_1r<63, 23,
2312 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2313 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2314 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2315 let Uses = [RM] in {
2316 let isCommutable = 1 in {
2317 defm FADD : AForm_2r<63, 21,
2318 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2319 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2320 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2321 defm FADDS : AForm_2r<59, 21,
2322 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2323 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2324 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2326 defm FDIV : AForm_2r<63, 18,
2327 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2328 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2329 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2330 defm FDIVS : AForm_2r<59, 18,
2331 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2332 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2333 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2334 let isCommutable = 1 in {
2335 defm FMUL : AForm_3r<63, 25,
2336 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2337 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2338 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2339 defm FMULS : AForm_3r<59, 25,
2340 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2341 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2342 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2344 defm FSUB : AForm_2r<63, 20,
2345 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2346 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2347 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2348 defm FSUBS : AForm_2r<59, 20,
2349 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2350 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2351 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2355 let hasSideEffects = 0 in {
2356 let PPC970_Unit = 1 in { // FXU Operations.
2358 def ISEL : AForm_4<31, 15,
2359 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2360 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
2364 let PPC970_Unit = 1 in { // FXU Operations.
2365 // M-Form instructions. rotate and mask instructions.
2367 let isCommutable = 1 in {
2368 // RLWIMI can be commuted if the rotate amount is zero.
2369 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2370 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2371 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2372 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2373 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2375 let BaseName = "rlwinm" in {
2376 def RLWINM : MForm_2<21,
2377 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2378 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2381 def RLWINMo : MForm_2<21,
2382 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2383 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2384 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2386 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2387 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2388 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2391 } // hasSideEffects = 0
2393 //===----------------------------------------------------------------------===//
2394 // PowerPC Instruction Patterns
2397 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2398 def : Pat<(i32 imm:$imm),
2399 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2401 // Implement the 'not' operation with the NOR instruction.
2402 def i32not : OutPatFrag<(ops node:$in),
2404 def : Pat<(not i32:$in),
2407 // ADD an arbitrary immediate.
2408 def : Pat<(add i32:$in, imm:$imm),
2409 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2410 // OR an arbitrary immediate.
2411 def : Pat<(or i32:$in, imm:$imm),
2412 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2413 // XOR an arbitrary immediate.
2414 def : Pat<(xor i32:$in, imm:$imm),
2415 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2417 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2418 (SUBFIC $in, imm:$imm)>;
2421 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2422 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2423 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2424 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2427 def : Pat<(rotl i32:$in, i32:$sh),
2428 (RLWNM $in, $sh, 0, 31)>;
2429 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2430 (RLWINM $in, imm:$imm, 0, 31)>;
2433 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2434 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2437 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2438 (BL tglobaladdr:$dst)>;
2439 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2440 (BL texternalsym:$dst)>;
2442 def : Pat<(PPCcall_tls texternalsym:$func, tglobaltlsaddr:$sym),
2443 (BL_TLS texternalsym:$func, tglobaltlsaddr:$sym)>;
2445 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2446 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2448 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2449 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2451 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2452 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2456 // Hi and Lo for Darwin Global Addresses.
2457 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2458 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2459 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2460 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2461 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2462 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2463 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2464 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2465 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2466 (ADDIS $in, tglobaltlsaddr:$g)>;
2467 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2468 (ADDI $in, tglobaltlsaddr:$g)>;
2469 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2470 (ADDIS $in, tglobaladdr:$g)>;
2471 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2472 (ADDIS $in, tconstpool:$g)>;
2473 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2474 (ADDIS $in, tjumptable:$g)>;
2475 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2476 (ADDIS $in, tblockaddress:$g)>;
2478 // Support for thread-local storage.
2479 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2480 [(set i32:$rD, (PPCppc32GOT))]>;
2482 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2483 // This uses two output registers, the first as the real output, the second as a
2484 // temporary register, used internally in code generation.
2485 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2486 []>, NoEncode<"$rT">;
2488 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2491 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2492 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2493 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2495 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2498 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2499 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2502 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2503 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2506 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2507 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2510 (PPCaddisDtprelHA i32:$reg,
2511 tglobaltlsaddr:$disp))]>;
2513 // Support for Position-independent code
2514 def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2517 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2518 // Get Global (GOT) Base Register offset, from the word immediately preceding
2519 // the function label.
2520 def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2523 // Standard shifts. These are represented separately from the real shifts above
2524 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2526 def : Pat<(sra i32:$rS, i32:$rB),
2528 def : Pat<(srl i32:$rS, i32:$rB),
2530 def : Pat<(shl i32:$rS, i32:$rB),
2533 def : Pat<(zextloadi1 iaddr:$src),
2535 def : Pat<(zextloadi1 xaddr:$src),
2537 def : Pat<(extloadi1 iaddr:$src),
2539 def : Pat<(extloadi1 xaddr:$src),
2541 def : Pat<(extloadi8 iaddr:$src),
2543 def : Pat<(extloadi8 xaddr:$src),
2545 def : Pat<(extloadi16 iaddr:$src),
2547 def : Pat<(extloadi16 xaddr:$src),
2549 def : Pat<(f64 (extloadf32 iaddr:$src)),
2550 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2551 def : Pat<(f64 (extloadf32 xaddr:$src)),
2552 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2554 def : Pat<(f64 (fextend f32:$src)),
2555 (COPY_TO_REGCLASS $src, F8RC)>;
2557 // Only seq_cst fences require the heavyweight sync (SYNC 0).
2558 // All others can use the lightweight sync (SYNC 1).
2559 // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2560 // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2561 // versions of Power.
2562 def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2563 def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2564 def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2565 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2567 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2568 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2569 (FNMSUB $A, $C, $B)>;
2570 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2571 (FNMSUB $A, $C, $B)>;
2572 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2573 (FNMSUBS $A, $C, $B)>;
2574 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2575 (FNMSUBS $A, $C, $B)>;
2577 // FCOPYSIGN's operand types need not agree.
2578 def : Pat<(fcopysign f64:$frB, f32:$frA),
2579 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2580 def : Pat<(fcopysign f32:$frB, f64:$frA),
2581 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2583 include "PPCInstrAltivec.td"
2584 include "PPCInstrSPE.td"
2585 include "PPCInstr64Bit.td"
2586 include "PPCInstrVSX.td"
2588 def crnot : OutPatFrag<(ops node:$in),
2590 def : Pat<(not i1:$in),
2593 // Patterns for arithmetic i1 operations.
2594 def : Pat<(add i1:$a, i1:$b),
2596 def : Pat<(sub i1:$a, i1:$b),
2598 def : Pat<(mul i1:$a, i1:$b),
2601 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2602 // (-1 is used to mean all bits set).
2603 def : Pat<(i1 -1), (CRSET)>;
2605 // i1 extensions, implemented in terms of isel.
2606 def : Pat<(i32 (zext i1:$in)),
2607 (SELECT_I4 $in, (LI 1), (LI 0))>;
2608 def : Pat<(i32 (sext i1:$in)),
2609 (SELECT_I4 $in, (LI -1), (LI 0))>;
2611 def : Pat<(i64 (zext i1:$in)),
2612 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2613 def : Pat<(i64 (sext i1:$in)),
2614 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2616 // FIXME: We should choose either a zext or a sext based on other constants
2618 def : Pat<(i32 (anyext i1:$in)),
2619 (SELECT_I4 $in, (LI 1), (LI 0))>;
2620 def : Pat<(i64 (anyext i1:$in)),
2621 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2623 // match setcc on i1 variables.
2624 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2626 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2628 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2630 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2632 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2634 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2636 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2638 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2640 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2642 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2645 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2646 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2647 // floating-point types.
2649 multiclass CRNotPat<dag pattern, dag result> {
2650 def : Pat<pattern, (crnot result)>;
2651 def : Pat<(not pattern), result>;
2653 // We can also fold the crnot into an extension:
2654 def : Pat<(i32 (zext pattern)),
2655 (SELECT_I4 result, (LI 0), (LI 1))>;
2656 def : Pat<(i32 (sext pattern)),
2657 (SELECT_I4 result, (LI 0), (LI -1))>;
2659 // We can also fold the crnot into an extension:
2660 def : Pat<(i64 (zext pattern)),
2661 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2662 def : Pat<(i64 (sext pattern)),
2663 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2665 // FIXME: We should choose either a zext or a sext based on other constants
2667 def : Pat<(i32 (anyext pattern)),
2668 (SELECT_I4 result, (LI 0), (LI 1))>;
2670 def : Pat<(i64 (anyext pattern)),
2671 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2674 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2675 // we need to write imm:$imm in the output patterns below, not just $imm, or
2676 // else the resulting matcher will not correctly add the immediate operand
2677 // (making it a register operand instead).
2680 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2681 OutPatFrag rfrag, OutPatFrag rfrag8> {
2682 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2684 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2686 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2687 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2688 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2689 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2691 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2693 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2695 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2696 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2697 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2698 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2701 // Note that we do all inversions below with i(32|64)not, instead of using
2702 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2703 // has 2-cycle latency.
2705 defm : ExtSetCCPat<SETEQ,
2706 PatFrag<(ops node:$in, node:$cc),
2707 (setcc $in, 0, $cc)>,
2708 OutPatFrag<(ops node:$in),
2709 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2710 OutPatFrag<(ops node:$in),
2711 (RLDICL (CNTLZD $in), 58, 63)> >;
2713 defm : ExtSetCCPat<SETNE,
2714 PatFrag<(ops node:$in, node:$cc),
2715 (setcc $in, 0, $cc)>,
2716 OutPatFrag<(ops node:$in),
2717 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2718 OutPatFrag<(ops node:$in),
2719 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2721 defm : ExtSetCCPat<SETLT,
2722 PatFrag<(ops node:$in, node:$cc),
2723 (setcc $in, 0, $cc)>,
2724 OutPatFrag<(ops node:$in),
2725 (RLWINM $in, 1, 31, 31)>,
2726 OutPatFrag<(ops node:$in),
2727 (RLDICL $in, 1, 63)> >;
2729 defm : ExtSetCCPat<SETGE,
2730 PatFrag<(ops node:$in, node:$cc),
2731 (setcc $in, 0, $cc)>,
2732 OutPatFrag<(ops node:$in),
2733 (RLWINM (i32not $in), 1, 31, 31)>,
2734 OutPatFrag<(ops node:$in),
2735 (RLDICL (i64not $in), 1, 63)> >;
2737 defm : ExtSetCCPat<SETGT,
2738 PatFrag<(ops node:$in, node:$cc),
2739 (setcc $in, 0, $cc)>,
2740 OutPatFrag<(ops node:$in),
2741 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2742 OutPatFrag<(ops node:$in),
2743 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2745 defm : ExtSetCCPat<SETLE,
2746 PatFrag<(ops node:$in, node:$cc),
2747 (setcc $in, 0, $cc)>,
2748 OutPatFrag<(ops node:$in),
2749 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2750 OutPatFrag<(ops node:$in),
2751 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2753 defm : ExtSetCCPat<SETLT,
2754 PatFrag<(ops node:$in, node:$cc),
2755 (setcc $in, -1, $cc)>,
2756 OutPatFrag<(ops node:$in),
2757 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2758 OutPatFrag<(ops node:$in),
2759 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2761 defm : ExtSetCCPat<SETGE,
2762 PatFrag<(ops node:$in, node:$cc),
2763 (setcc $in, -1, $cc)>,
2764 OutPatFrag<(ops node:$in),
2765 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2766 OutPatFrag<(ops node:$in),
2767 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2769 defm : ExtSetCCPat<SETGT,
2770 PatFrag<(ops node:$in, node:$cc),
2771 (setcc $in, -1, $cc)>,
2772 OutPatFrag<(ops node:$in),
2773 (RLWINM (i32not $in), 1, 31, 31)>,
2774 OutPatFrag<(ops node:$in),
2775 (RLDICL (i64not $in), 1, 63)> >;
2777 defm : ExtSetCCPat<SETLE,
2778 PatFrag<(ops node:$in, node:$cc),
2779 (setcc $in, -1, $cc)>,
2780 OutPatFrag<(ops node:$in),
2781 (RLWINM $in, 1, 31, 31)>,
2782 OutPatFrag<(ops node:$in),
2783 (RLDICL $in, 1, 63)> >;
2786 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2787 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2788 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2789 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2790 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2791 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2792 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2793 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2794 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2795 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2796 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2797 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2799 // For non-equality comparisons, the default code would materialize the
2800 // constant, then compare against it, like this:
2802 // ori r2, r2, 22136
2805 // Since we are just comparing for equality, we can emit this instead:
2806 // xoris r0,r3,0x1234
2807 // cmplwi cr0,r0,0x5678
2810 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2811 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2812 (LO16 imm:$imm)), sub_eq)>;
2814 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2815 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2816 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2817 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2818 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2819 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2820 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2821 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2822 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2823 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2824 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2825 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2827 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2828 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2829 (LO16 imm:$imm)), sub_eq)>;
2831 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
2832 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2833 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2834 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2835 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2836 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2837 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
2838 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2839 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2840 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2842 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2843 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2844 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
2845 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2846 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2847 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2848 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
2849 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2850 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2851 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2854 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
2855 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2856 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2857 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2858 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2859 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2860 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
2861 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2862 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
2863 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2864 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
2865 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2867 // For non-equality comparisons, the default code would materialize the
2868 // constant, then compare against it, like this:
2870 // ori r2, r2, 22136
2873 // Since we are just comparing for equality, we can emit this instead:
2874 // xoris r0,r3,0x1234
2875 // cmpldi cr0,r0,0x5678
2878 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
2879 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2880 (LO16 imm:$imm)), sub_eq)>;
2882 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
2883 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2884 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
2885 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2886 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
2887 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2888 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
2889 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2890 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
2891 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2892 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
2893 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2895 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
2896 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2897 (LO16 imm:$imm)), sub_eq)>;
2899 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
2900 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2901 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
2902 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2903 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
2904 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2905 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
2906 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2907 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
2908 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2910 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
2911 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2912 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
2913 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2914 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
2915 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2916 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
2917 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2918 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
2919 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2922 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
2923 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2924 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
2925 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2926 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
2927 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2928 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
2929 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2930 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
2931 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2932 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
2933 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2934 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
2935 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2937 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
2938 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2939 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
2940 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2941 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
2942 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2943 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
2944 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2945 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
2946 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2947 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
2948 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2949 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
2950 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2953 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
2954 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2955 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
2956 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2957 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
2958 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2959 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
2960 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2961 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
2962 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2963 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
2964 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2965 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
2966 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2968 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
2969 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2970 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
2971 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2972 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
2973 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2974 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
2975 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2976 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
2977 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2978 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
2979 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2980 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
2981 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2983 // match select on i1 variables:
2984 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
2985 (CROR (CRAND $cond , $tval),
2986 (CRAND (crnot $cond), $fval))>;
2988 // match selectcc on i1 variables:
2989 // select (lhs == rhs), tval, fval is:
2990 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
2991 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
2992 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
2993 (CRAND (CRORC $lhs, $rhs), $fval))>;
2994 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
2995 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
2996 (CRAND (CRANDC $lhs, $rhs), $fval))>;
2997 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
2998 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
2999 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3000 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3001 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
3002 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3003 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3004 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3005 (CRAND (CRORC $rhs, $lhs), $fval))>;
3006 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3007 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3008 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3010 // match selectcc on i1 variables with non-i1 output.
3011 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3012 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3013 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3014 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3015 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3016 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3017 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3018 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3019 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3020 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3021 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3022 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3024 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3025 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3026 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3027 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3028 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3029 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3030 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3031 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3032 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3033 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3034 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3035 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3037 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3038 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3039 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3040 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3041 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3042 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3043 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3044 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3045 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3046 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3047 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3048 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3050 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3051 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3052 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3053 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3054 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3055 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3056 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3057 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3058 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3059 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3060 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3061 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3063 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3064 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3065 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3066 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3067 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3068 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3069 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3070 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3071 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3072 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3073 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3074 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3076 let usesCustomInserter = 1 in {
3077 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3079 [(set i1:$dst, (trunc (not i32:$in)))]>;
3080 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3082 [(set i1:$dst, (trunc i32:$in))]>;
3084 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3086 [(set i1:$dst, (trunc (not i64:$in)))]>;
3087 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3089 [(set i1:$dst, (trunc i64:$in))]>;
3092 def : Pat<(i1 (not (trunc i32:$in))),
3093 (ANDIo_1_EQ_BIT $in)>;
3094 def : Pat<(i1 (not (trunc i64:$in))),
3095 (ANDIo_1_EQ_BIT8 $in)>;
3097 //===----------------------------------------------------------------------===//
3098 // PowerPC Instructions used for assembler/disassembler only
3101 // FIXME: For B=0 or B > 8, the registers following RT are used.
3102 // WARNING: Do not add patterns for this instruction without fixing this.
3103 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3104 "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3106 // FIXME: For B=0 or B > 8, the registers following RT are used.
3107 // WARNING: Do not add patterns for this instruction without fixing this.
3108 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3109 "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3111 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3112 "isync", IIC_SprISYNC, []>;
3114 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3115 "icbi $src", IIC_LdStICBI, []>;
3117 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3118 "eieio", IIC_LdStLoad, []>;
3120 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3121 "wait $L", IIC_LdStLoad, []>;
3123 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3124 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3126 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3127 "mtsr $SR, $RS", IIC_SprMTSR>;
3129 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3130 "mfsr $RS, $SR", IIC_SprMFSR>;
3132 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3133 "mtsrin $RS, $RB", IIC_SprMTSR>;
3135 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3136 "mfsrin $RS, $RB", IIC_SprMFSR>;
3138 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3139 "mtmsr $RS, $L", IIC_SprMTMSR>;
3141 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3142 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3146 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3147 Requires<[IsBookE]> {
3151 let Inst{21-30} = 163;
3154 def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3155 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3156 def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3157 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3159 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3160 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3161 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3162 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3164 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3165 "mfmsr $RT", IIC_SprMFMSR, []>;
3167 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3168 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3170 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3171 "slbie $RB", IIC_SprSLBIE, []>;
3173 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3174 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3176 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3177 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3179 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3181 def TLBIA : XForm_0<31, 370, (outs), (ins),
3182 "tlbia", IIC_SprTLBIA, []>;
3184 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3185 "tlbsync", IIC_SprTLBSYNC, []>;
3187 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3188 "tlbiel $RB", IIC_SprTLBIEL, []>;
3190 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3191 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3192 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3193 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3195 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3196 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3198 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3199 IIC_LdStLoad>, Requires<[IsBookE]>;
3201 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3202 IIC_LdStLoad>, Requires<[IsBookE]>;
3204 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3205 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3207 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3208 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3210 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3211 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3213 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3214 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3216 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3217 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3218 Requires<[IsPPC4xx]>;
3219 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3220 (ins gprc:$RST, gprc:$A, gprc:$B),
3221 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3222 Requires<[IsPPC4xx]>, isDOT;
3224 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3226 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3227 Requires<[IsBookE]>;
3228 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3229 Requires<[IsBookE]>;
3231 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3233 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3236 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3237 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3238 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3239 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3241 def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3243 def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3244 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3245 def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3246 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3247 def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3248 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3249 def LDCIX : XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3250 "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3252 def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3253 "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3254 def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3255 "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3256 def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3257 "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3258 def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3259 "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3261 //===----------------------------------------------------------------------===//
3262 // PowerPC Assembler Instruction Aliases
3265 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3266 // These are aliases that require C++ handling to convert to the target
3267 // instruction, while InstAliases can be handled directly by tblgen.
3268 class PPCAsmPseudo<string asm, dag iops>
3270 let Namespace = "PPC";
3271 bit PPC64 = 0; // Default value, override with isPPC64
3273 let OutOperandList = (outs);
3274 let InOperandList = iops;
3276 let AsmString = asm;
3277 let isAsmParserOnly = 1;
3281 def : InstAlias<"sc", (SC 0)>;
3283 def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3284 def : InstAlias<"msync", (SYNC 0)>, Requires<[HasSYNC]>;
3285 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3286 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3288 def : InstAlias<"wait", (WAIT 0)>;
3289 def : InstAlias<"waitrsv", (WAIT 1)>;
3290 def : InstAlias<"waitimpl", (WAIT 2)>;
3292 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3294 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3295 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3296 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3297 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3299 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3300 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3302 def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3303 def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3305 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3306 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3308 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3309 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3311 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3312 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3314 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3315 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3317 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3318 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3320 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3321 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3323 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3324 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3326 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3327 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3329 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3330 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3332 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3333 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3335 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3336 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3338 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3339 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3341 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3342 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3343 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3345 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3346 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3348 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3349 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3350 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3351 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3353 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3355 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3356 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3358 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3359 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3361 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3363 foreach BATR = 0-3 in {
3364 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3365 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3366 Requires<[IsPPC6xx]>;
3367 def : InstAlias<"mfdbatu $Rx, "#BATR,
3368 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3369 Requires<[IsPPC6xx]>;
3370 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3371 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3372 Requires<[IsPPC6xx]>;
3373 def : InstAlias<"mfdbatl $Rx, "#BATR,
3374 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3375 Requires<[IsPPC6xx]>;
3376 def : InstAlias<"mtibatu "#BATR#", $Rx",
3377 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3378 Requires<[IsPPC6xx]>;
3379 def : InstAlias<"mfibatu $Rx, "#BATR,
3380 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3381 Requires<[IsPPC6xx]>;
3382 def : InstAlias<"mtibatl "#BATR#", $Rx",
3383 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3384 Requires<[IsPPC6xx]>;
3385 def : InstAlias<"mfibatl $Rx, "#BATR,
3386 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3387 Requires<[IsPPC6xx]>;
3390 foreach BR = 0-7 in {
3391 def : InstAlias<"mfbr"#BR#" $Rx",
3392 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3393 Requires<[IsPPC4xx]>;
3394 def : InstAlias<"mtbr"#BR#" $Rx",
3395 (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3396 Requires<[IsPPC4xx]>;
3399 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3400 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3402 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3403 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3405 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3406 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3408 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3409 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3411 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3412 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3414 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3415 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3417 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3419 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3420 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3421 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3422 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3423 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3424 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3425 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3426 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3428 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3429 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3430 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3431 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3433 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3434 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3436 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3437 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3439 foreach SPRG = 0-3 in {
3440 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3441 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3442 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3443 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3445 foreach SPRG = 4-7 in {
3446 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3447 Requires<[IsBookE]>;
3448 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3449 Requires<[IsBookE]>;
3450 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3451 Requires<[IsBookE]>;
3452 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3453 Requires<[IsBookE]>;
3456 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3458 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3459 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3461 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3463 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3464 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3466 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3467 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3468 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3469 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3471 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3473 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3474 Requires<[IsPPC4xx]>;
3475 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3476 Requires<[IsPPC4xx]>;
3477 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3478 Requires<[IsPPC4xx]>;
3479 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3480 Requires<[IsPPC4xx]>;
3482 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3483 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3484 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3485 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3486 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3487 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3488 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3489 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3490 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3491 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3492 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3493 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3494 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3495 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3496 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3497 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3498 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3499 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3500 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3501 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3502 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3503 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3504 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3505 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3506 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3507 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3508 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3509 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3510 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3511 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3512 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3513 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3514 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3515 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3516 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3517 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3519 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3520 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3521 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3522 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3523 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3524 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3526 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3527 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3528 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3529 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3530 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3531 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3532 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3533 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3534 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3535 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3536 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3537 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3538 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3539 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3540 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3541 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3542 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3543 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3544 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3545 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3546 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3547 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3548 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3549 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3550 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3551 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3552 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3553 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3554 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3555 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3556 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3557 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3559 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3560 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3561 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3562 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3563 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3564 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3566 // These generic branch instruction forms are used for the assembler parser only.
3567 // Defs and Uses are conservative, since we don't know the BO value.
3568 let PPC970_Unit = 7 in {
3569 let Defs = [CTR], Uses = [CTR, RM] in {
3570 def gBC : BForm_3<16, 0, 0, (outs),
3571 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3572 "bc $bo, $bi, $dst">;
3573 def gBCA : BForm_3<16, 1, 0, (outs),
3574 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3575 "bca $bo, $bi, $dst">;
3577 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3578 def gBCL : BForm_3<16, 0, 1, (outs),
3579 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3580 "bcl $bo, $bi, $dst">;
3581 def gBCLA : BForm_3<16, 1, 1, (outs),
3582 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3583 "bcla $bo, $bi, $dst">;
3585 let Defs = [CTR], Uses = [CTR, LR, RM] in
3586 def gBCLR : XLForm_2<19, 16, 0, (outs),
3587 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3588 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3589 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3590 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3591 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3592 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3593 let Defs = [CTR], Uses = [CTR, LR, RM] in
3594 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3595 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3596 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3597 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3598 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3599 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3600 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3602 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3603 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3604 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3605 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3607 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3608 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3609 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3610 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3611 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3612 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3613 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3615 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3616 : BranchSimpleMnemonic1<name, pm, bo> {
3617 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3618 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3620 defm : BranchSimpleMnemonic2<"t", "", 12>;
3621 defm : BranchSimpleMnemonic2<"f", "", 4>;
3622 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3623 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3624 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3625 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3626 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3627 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3628 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3629 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3631 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3632 def : InstAlias<"b"#name#pm#" $cc, $dst",
3633 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3634 def : InstAlias<"b"#name#pm#" $dst",
3635 (BCC bibo, CR0, condbrtarget:$dst)>;
3637 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3638 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3639 def : InstAlias<"b"#name#"a"#pm#" $dst",
3640 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3642 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3643 (BCCLR bibo, crrc:$cc)>;
3644 def : InstAlias<"b"#name#"lr"#pm,
3647 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3648 (BCCCTR bibo, crrc:$cc)>;
3649 def : InstAlias<"b"#name#"ctr"#pm,
3650 (BCCCTR bibo, CR0)>;
3652 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3653 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3654 def : InstAlias<"b"#name#"l"#pm#" $dst",
3655 (BCCL bibo, CR0, condbrtarget:$dst)>;
3657 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3658 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3659 def : InstAlias<"b"#name#"la"#pm#" $dst",
3660 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3662 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3663 (BCCLRL bibo, crrc:$cc)>;
3664 def : InstAlias<"b"#name#"lrl"#pm,
3665 (BCCLRL bibo, CR0)>;
3667 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3668 (BCCCTRL bibo, crrc:$cc)>;
3669 def : InstAlias<"b"#name#"ctrl"#pm,
3670 (BCCCTRL bibo, CR0)>;
3672 multiclass BranchExtendedMnemonic<string name, int bibo> {
3673 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3674 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3675 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3677 defm : BranchExtendedMnemonic<"lt", 12>;
3678 defm : BranchExtendedMnemonic<"gt", 44>;
3679 defm : BranchExtendedMnemonic<"eq", 76>;
3680 defm : BranchExtendedMnemonic<"un", 108>;
3681 defm : BranchExtendedMnemonic<"so", 108>;
3682 defm : BranchExtendedMnemonic<"ge", 4>;
3683 defm : BranchExtendedMnemonic<"nl", 4>;
3684 defm : BranchExtendedMnemonic<"le", 36>;
3685 defm : BranchExtendedMnemonic<"ng", 36>;
3686 defm : BranchExtendedMnemonic<"ne", 68>;
3687 defm : BranchExtendedMnemonic<"nu", 100>;
3688 defm : BranchExtendedMnemonic<"ns", 100>;
3690 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3691 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3692 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3693 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3694 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3695 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3696 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3697 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3699 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3700 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3701 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3702 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3703 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3704 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3705 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3706 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3708 multiclass TrapExtendedMnemonic<string name, int to> {
3709 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3710 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3711 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3712 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3714 defm : TrapExtendedMnemonic<"lt", 16>;
3715 defm : TrapExtendedMnemonic<"le", 20>;
3716 defm : TrapExtendedMnemonic<"eq", 4>;
3717 defm : TrapExtendedMnemonic<"ge", 12>;
3718 defm : TrapExtendedMnemonic<"gt", 8>;
3719 defm : TrapExtendedMnemonic<"nl", 12>;
3720 defm : TrapExtendedMnemonic<"ne", 24>;
3721 defm : TrapExtendedMnemonic<"ng", 20>;
3722 defm : TrapExtendedMnemonic<"llt", 2>;
3723 defm : TrapExtendedMnemonic<"lle", 6>;
3724 defm : TrapExtendedMnemonic<"lge", 5>;
3725 defm : TrapExtendedMnemonic<"lgt", 1>;
3726 defm : TrapExtendedMnemonic<"lnl", 5>;
3727 defm : TrapExtendedMnemonic<"lng", 6>;
3728 defm : TrapExtendedMnemonic<"u", 31>;
3731 def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>;
3732 def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>;
3733 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>;
3734 def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>;
3735 def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
3736 def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
3739 def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>;
3740 def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>;
3741 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>;
3742 def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
3743 def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
3744 def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;