1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
28 def SDT_PPCvperm : SDTypeProfile<1, 3, [
29 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
32 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
33 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
36 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
37 SDTCisVT<1, i32>, SDTCisVT<2, OtherVT>
40 //===----------------------------------------------------------------------===//
41 // PowerPC specific DAG Nodes.
44 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
45 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
46 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
47 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
49 def PPCfsel : SDNode<"PPCISD::FSEL",
50 // Type constraint for fsel.
51 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
52 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
54 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
55 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
56 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
57 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
59 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
61 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
62 // amounts. These nodes are generated by the multi-precision shift code.
63 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
64 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
65 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
67 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
68 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
70 // These are target-independent nodes, but have target-specific formats.
71 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
72 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
74 def SDT_PPCCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
75 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
76 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
77 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
78 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTRet,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
82 def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet,
83 [SDNPHasChain, SDNPOptInFlag]>;
85 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
86 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
88 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
89 [SDNPHasChain, SDNPOptInFlag]>;
91 //===----------------------------------------------------------------------===//
92 // PowerPC specific transformation functions and pattern fragments.
95 def SHL32 : SDNodeXForm<imm, [{
96 // Transformation function: 31 - imm
97 return getI32Imm(31 - N->getValue());
100 def SHL64 : SDNodeXForm<imm, [{
101 // Transformation function: 63 - imm
102 return getI32Imm(63 - N->getValue());
105 def SRL32 : SDNodeXForm<imm, [{
106 // Transformation function: 32 - imm
107 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
110 def SRL64 : SDNodeXForm<imm, [{
111 // Transformation function: 64 - imm
112 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
115 def LO16 : SDNodeXForm<imm, [{
116 // Transformation function: get the low 16 bits.
117 return getI32Imm((unsigned short)N->getValue());
120 def HI16 : SDNodeXForm<imm, [{
121 // Transformation function: shift the immediate value down into the low bits.
122 return getI32Imm((unsigned)N->getValue() >> 16);
125 def HA16 : SDNodeXForm<imm, [{
126 // Transformation function: shift the immediate value down into the low bits.
127 signed int Val = N->getValue();
128 return getI32Imm((Val - (signed short)Val) >> 16);
132 def immSExt16 : PatLeaf<(imm), [{
133 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
134 // field. Used by instructions like 'addi'.
135 return (int)N->getValue() == (short)N->getValue();
137 def immZExt16 : PatLeaf<(imm), [{
138 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
139 // field. Used by instructions like 'ori'.
140 return (unsigned)N->getValue() == (unsigned short)N->getValue();
143 def imm16Shifted : PatLeaf<(imm), [{
144 // imm16Shifted predicate - True if only bits in the top 16-bits of the
145 // immediate are set. Used by instructions like 'addis'.
146 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
150 //===----------------------------------------------------------------------===//
151 // PowerPC Flag Definitions.
153 class isPPC64 { bit PPC64 = 1; }
154 class isVMX { bit VMX = 1; }
156 list<Register> Defs = [CR0];
162 //===----------------------------------------------------------------------===//
163 // PowerPC Operand Definitions.
165 def s5imm : Operand<i32> {
166 let PrintMethod = "printS5ImmOperand";
168 def u5imm : Operand<i32> {
169 let PrintMethod = "printU5ImmOperand";
171 def u6imm : Operand<i32> {
172 let PrintMethod = "printU6ImmOperand";
174 def s16imm : Operand<i32> {
175 let PrintMethod = "printS16ImmOperand";
177 def u16imm : Operand<i32> {
178 let PrintMethod = "printU16ImmOperand";
180 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
181 let PrintMethod = "printS16X4ImmOperand";
183 def target : Operand<OtherVT> {
184 let PrintMethod = "printBranchOperand";
186 def calltarget : Operand<i32> {
187 let PrintMethod = "printCallOperand";
189 def aaddr : Operand<i32> {
190 let PrintMethod = "printAbsAddrOperand";
192 def piclabel: Operand<i32> {
193 let PrintMethod = "printPICLabel";
195 def symbolHi: Operand<i32> {
196 let PrintMethod = "printSymbolHi";
198 def symbolLo: Operand<i32> {
199 let PrintMethod = "printSymbolLo";
201 def crbitm: Operand<i8> {
202 let PrintMethod = "printcrbitm";
205 def memri : Operand<i32> {
206 let PrintMethod = "printMemRegImm";
207 let NumMIOperands = 2;
208 let MIOperandInfo = (ops i32imm, GPRC);
210 def memrr : Operand<i32> {
211 let PrintMethod = "printMemRegReg";
212 let NumMIOperands = 2;
213 let MIOperandInfo = (ops GPRC, GPRC);
215 def memrix : Operand<i32> { // memri where the imm is shifted 2 bits.
216 let PrintMethod = "printMemRegImmShifted";
217 let NumMIOperands = 2;
218 let MIOperandInfo = (ops i32imm, GPRC);
221 // Define PowerPC specific addressing mode.
222 def iaddr : ComplexPattern<i32, 2, "SelectAddrImm", []>;
223 def xaddr : ComplexPattern<i32, 2, "SelectAddrIdx", []>;
224 def xoaddr : ComplexPattern<i32, 2, "SelectAddrIdxOnly",[]>;
225 def ixaddr : ComplexPattern<i32, 2, "SelectAddrImmShift", []>; // "std"
227 //===----------------------------------------------------------------------===//
228 // PowerPC Instruction Predicate Definitions.
229 def FPContractions : Predicate<"!NoExcessFPPrecision">;
231 //===----------------------------------------------------------------------===//
232 // PowerPC Instruction Definitions.
234 // Pseudo-instructions:
236 let hasCtrlDep = 1 in {
237 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
238 "; ADJCALLSTACKDOWN",
239 [(callseq_start imm:$amt)]>;
240 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
242 [(callseq_end imm:$amt)]>;
244 def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
245 "UPDATE_VRSAVE $rD, $rS", []>;
247 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
248 [(set GPRC:$rD, (undef))]>;
249 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8",
250 [(set F8RC:$rD, (undef))]>;
251 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; $rD = IMPLICIT_DEF_F4",
252 [(set F4RC:$rD, (undef))]>;
254 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
255 // scheduler into a branch sequence.
256 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
257 PPC970_Single = 1 in {
258 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
259 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
260 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
261 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
262 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
263 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
264 def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F,
265 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
268 let isTerminator = 1, noResults = 1, PPC970_Unit = 7 in {
270 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
271 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
275 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
278 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
279 noResults = 1, PPC970_Unit = 7 in {
280 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
281 "; COND_BRANCH $crS, $opc, $dst",
282 [(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
283 def B : IForm<18, 0, 0, (ops target:$dst),
287 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
288 "blt $crS, $block", BrB>;
289 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
290 "ble $crS, $block", BrB>;
291 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
292 "beq $crS, $block", BrB>;
293 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
294 "bge $crS, $block", BrB>;
295 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
296 "bgt $crS, $block", BrB>;
297 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
298 "bne $crS, $block", BrB>;
299 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
300 "bun $crS, $block", BrB>;
301 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
302 "bnu $crS, $block", BrB>;
305 let isCall = 1, noResults = 1, PPC970_Unit = 7,
306 // All calls clobber the non-callee saved registers...
307 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
308 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
309 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
311 CR0,CR1,CR5,CR6,CR7] in {
312 // Convenient aliases for call instructions
313 def BL : IForm<18, 0, 1, (ops calltarget:$func),
314 "bl $func", BrB, []>; // See Pat patterns below.
315 def BLA : IForm<18, 1, 1, (ops aaddr:$func),
316 "bla $func", BrB, [(PPCcall imm:$func)]>;
317 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops), "bctrl", BrB,
321 // DCB* instructions.
322 def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
323 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
324 PPC970_DGroup_Single;
325 def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
326 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
327 PPC970_DGroup_Single;
329 // D-Form instructions. Most instructions that perform an operation on a
330 // register and an immediate are of this type.
332 let isLoad = 1, PPC970_Unit = 2 in {
333 def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
334 "lbz $rD, $src", LdStGeneral,
335 [(set GPRC:$rD, (zextload iaddr:$src, i8))]>;
336 def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
337 "lha $rD, $src", LdStLHA,
338 [(set GPRC:$rD, (sextload iaddr:$src, i16))]>,
339 PPC970_DGroup_Cracked;
340 def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
341 "lhz $rD, $src", LdStGeneral,
342 [(set GPRC:$rD, (zextload iaddr:$src, i16))]>;
343 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
344 "lwz $rD, $src", LdStGeneral,
345 [(set GPRC:$rD, (load iaddr:$src))]>;
346 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
347 "lwzu $rD, $disp($rA)", LdStGeneral,
350 let PPC970_Unit = 1 in { // FXU Operations.
351 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
352 "addi $rD, $rA, $imm", IntGeneral,
353 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
354 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
355 "addic $rD, $rA, $imm", IntGeneral,
356 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
357 PPC970_DGroup_Cracked;
358 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
359 "addic. $rD, $rA, $imm", IntGeneral,
361 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
362 "addis $rD, $rA, $imm", IntGeneral,
363 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
364 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
365 "la $rD, $sym($rA)", IntGeneral,
366 [(set GPRC:$rD, (add GPRC:$rA,
367 (PPClo tglobaladdr:$sym, 0)))]>;
368 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
369 "mulli $rD, $rA, $imm", IntMulLI,
370 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
371 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
372 "subfic $rD, $rA, $imm", IntGeneral,
373 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
374 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
375 "li $rD, $imm", IntGeneral,
376 [(set GPRC:$rD, immSExt16:$imm)]>;
377 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
378 "lis $rD, $imm", IntGeneral,
379 [(set GPRC:$rD, imm16Shifted:$imm)]>;
381 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
382 def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
383 "stb $rS, $src", LdStGeneral,
384 [(truncstore GPRC:$rS, iaddr:$src, i8)]>;
385 def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
386 "sth $rS, $src", LdStGeneral,
387 [(truncstore GPRC:$rS, iaddr:$src, i16)]>;
388 def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
389 "stw $rS, $src", LdStGeneral,
390 [(store GPRC:$rS, iaddr:$src)]>;
391 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
392 "stwu $rS, $disp($rA)", LdStGeneral,
395 let PPC970_Unit = 1 in { // FXU Operations.
396 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
397 "andi. $dst, $src1, $src2", IntGeneral,
398 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
400 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
401 "andis. $dst, $src1, $src2", IntGeneral,
402 [(set GPRC:$dst, (and GPRC:$src1, imm16Shifted:$src2))]>,
404 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
405 "ori $dst, $src1, $src2", IntGeneral,
406 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
407 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
408 "oris $dst, $src1, $src2", IntGeneral,
409 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
410 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
411 "xori $dst, $src1, $src2", IntGeneral,
412 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
413 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
414 "xoris $dst, $src1, $src2", IntGeneral,
415 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
416 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
418 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
419 "cmpi $crD, $L, $rA, $imm", IntCompare>;
420 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
421 "cmpwi $crD, $rA, $imm", IntCompare>;
422 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
423 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
424 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
425 "cmpli $dst, $size, $src1, $src2", IntCompare>;
426 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
427 "cmplwi $dst, $src1, $src2", IntCompare>;
428 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
429 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
431 let isLoad = 1, PPC970_Unit = 2 in {
432 def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src),
433 "lfs $rD, $src", LdStLFDU,
434 [(set F4RC:$rD, (load iaddr:$src))]>;
435 def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src),
436 "lfd $rD, $src", LdStLFD,
437 [(set F8RC:$rD, (load iaddr:$src))]>;
439 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
440 def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst),
441 "stfs $rS, $dst", LdStUX,
442 [(store F4RC:$rS, iaddr:$dst)]>;
443 def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst),
444 "stfd $rS, $dst", LdStUX,
445 [(store F8RC:$rS, iaddr:$dst)]>;
448 // DS-Form instructions. Load/Store instructions available in PPC-64
450 let isLoad = 1, PPC970_Unit = 2 in {
451 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
452 "lwa $rT, $DS($rA)", LdStLWA,
453 []>, isPPC64, PPC970_DGroup_Cracked;
454 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
455 "ld $rT, $DS($rA)", LdStLD,
458 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
459 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
460 "std $rT, $DS($rA)", LdStSTD,
463 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
464 def STD_32 : DSForm_2<62, 0, (ops GPRC:$rT, memrix:$dst),
465 "std $rT, $dst", LdStSTD,
466 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
467 def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst),
468 "stdx $rT, $dst", LdStSTD,
469 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
470 PPC970_DGroup_Cracked;
473 // X-Form instructions. Most instructions that perform an operation on a
474 // register and another register are of this type.
476 let isLoad = 1, PPC970_Unit = 2 in {
477 def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
478 "lbzx $rD, $src", LdStGeneral,
479 [(set GPRC:$rD, (zextload xaddr:$src, i8))]>;
480 def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
481 "lhax $rD, $src", LdStLHA,
482 [(set GPRC:$rD, (sextload xaddr:$src, i16))]>,
483 PPC970_DGroup_Cracked;
484 def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
485 "lhzx $rD, $src", LdStGeneral,
486 [(set GPRC:$rD, (zextload xaddr:$src, i16))]>;
487 def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
488 "lwax $rD, $src", LdStLHA,
489 [(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64,
490 PPC970_DGroup_Cracked;
491 def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
492 "lwzx $rD, $src", LdStGeneral,
493 [(set GPRC:$rD, (load xaddr:$src))]>;
494 def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
495 "ldx $rD, $src", LdStLD,
496 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
499 let PPC970_Unit = 1 in { // FXU Operations.
500 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
501 "nand $rA, $rS, $rB", IntGeneral,
502 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
503 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
504 "and $rA, $rS, $rB", IntGeneral,
505 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
506 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
507 "and. $rA, $rS, $rB", IntGeneral,
509 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
510 "andc $rA, $rS, $rB", IntGeneral,
511 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
512 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
513 "or $rA, $rS, $rB", IntGeneral,
514 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
515 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
516 "or $rA, $rS, $rB", IntGeneral,
517 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
518 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
519 "or $rA, $rS, $rB", IntGeneral,
521 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
522 "or $rA, $rS, $rB", IntGeneral,
524 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
525 "nor $rA, $rS, $rB", IntGeneral,
526 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
527 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
528 "or. $rA, $rS, $rB", IntGeneral,
530 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
531 "orc $rA, $rS, $rB", IntGeneral,
532 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
533 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
534 "eqv $rA, $rS, $rB", IntGeneral,
535 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
536 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
537 "xor $rA, $rS, $rB", IntGeneral,
538 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
539 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
540 "sld $rA, $rS, $rB", IntRotateD,
541 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
542 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
543 "slw $rA, $rS, $rB", IntGeneral,
544 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
545 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
546 "srd $rA, $rS, $rB", IntRotateD,
547 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
548 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
549 "srw $rA, $rS, $rB", IntGeneral,
550 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
551 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
552 "srad $rA, $rS, $rB", IntRotateD,
553 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
554 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
555 "sraw $rA, $rS, $rB", IntShift,
556 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
558 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
559 def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
560 "stbx $rS, $dst", LdStGeneral,
561 [(truncstore GPRC:$rS, xaddr:$dst, i8)]>,
562 PPC970_DGroup_Cracked;
563 def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
564 "sthx $rS, $dst", LdStGeneral,
565 [(truncstore GPRC:$rS, xaddr:$dst, i16)]>,
566 PPC970_DGroup_Cracked;
567 def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
568 "stwx $rS, $dst", LdStGeneral,
569 [(store GPRC:$rS, xaddr:$dst)]>,
570 PPC970_DGroup_Cracked;
571 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
572 "stwux $rS, $rA, $rB", LdStGeneral,
574 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
575 "stdx $rS, $rA, $rB", LdStSTD,
576 []>, isPPC64, PPC970_DGroup_Cracked;
577 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
578 "stdux $rS, $rA, $rB", LdStSTD,
581 let PPC970_Unit = 1 in { // FXU Operations.
582 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
583 "srawi $rA, $rS, $SH", IntShift,
584 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
585 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
586 "cntlzw $rA, $rS", IntGeneral,
587 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
588 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
589 "extsb $rA, $rS", IntGeneral,
590 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
591 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
592 "extsh $rA, $rS", IntGeneral,
593 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
594 def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
595 "extsw $rA, $rS", IntGeneral,
596 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
597 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
598 def EXTSW_32 : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
599 "extsw $rA, $rS", IntGeneral,
600 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
602 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
603 "cmp $crD, $long, $rA, $rB", IntCompare>;
604 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
605 "cmpl $crD, $long, $rA, $rB", IntCompare>;
606 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
607 "cmpw $crD, $rA, $rB", IntCompare>;
608 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
609 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
610 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
611 "cmplw $crD, $rA, $rB", IntCompare>;
612 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
613 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
615 let PPC970_Unit = 3 in { // FPU Operations.
616 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
617 // "fcmpo $crD, $fA, $fB", FPCompare>;
618 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
619 "fcmpu $crD, $fA, $fB", FPCompare>;
620 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
621 "fcmpu $crD, $fA, $fB", FPCompare>;
623 let isLoad = 1, PPC970_Unit = 2 in {
624 def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
625 "lfsx $frD, $src", LdStLFDU,
626 [(set F4RC:$frD, (load xaddr:$src))]>;
627 def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
628 "lfdx $frD, $src", LdStLFDU,
629 [(set F8RC:$frD, (load xaddr:$src))]>;
631 let PPC970_Unit = 3 in { // FPU Operations.
632 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
633 "fcfid $frD, $frB", FPGeneral,
634 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
635 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
636 "fctidz $frD, $frB", FPGeneral,
637 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
638 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
639 "fctiwz $frD, $frB", FPGeneral,
640 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
641 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
642 "frsp $frD, $frB", FPGeneral,
643 [(set F4RC:$frD, (fround F8RC:$frB))]>;
644 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
645 "fsqrt $frD, $frB", FPSqrt,
646 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
647 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
648 "fsqrts $frD, $frB", FPSqrt,
649 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
652 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
654 /// Note that these are defined as pseudo-ops on the PPC970 because they are
655 /// often coalesced away and we don't want the dispatch group builder to think
656 /// that they will fill slots (which could cause the load of a LSU reject to
657 /// sneak into a d-group with a store).
658 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
659 "fmr $frD, $frB", FPGeneral,
660 []>, // (set F4RC:$frD, F4RC:$frB)
662 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
663 "fmr $frD, $frB", FPGeneral,
664 []>, // (set F8RC:$frD, F8RC:$frB)
666 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
667 "fmr $frD, $frB", FPGeneral,
668 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
671 let PPC970_Unit = 3 in { // FPU Operations.
672 // These are artificially split into two different forms, for 4/8 byte FP.
673 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
674 "fabs $frD, $frB", FPGeneral,
675 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
676 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
677 "fabs $frD, $frB", FPGeneral,
678 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
679 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
680 "fnabs $frD, $frB", FPGeneral,
681 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
682 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
683 "fnabs $frD, $frB", FPGeneral,
684 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
685 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
686 "fneg $frD, $frB", FPGeneral,
687 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
688 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
689 "fneg $frD, $frB", FPGeneral,
690 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
693 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
694 def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst),
695 "stfiwx $frS, $dst", LdStUX,
696 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
697 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
698 "stfsx $frS, $dst", LdStUX,
699 [(store F4RC:$frS, xaddr:$dst)]>;
700 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
701 "stfdx $frS, $dst", LdStUX,
702 [(store F8RC:$frS, xaddr:$dst)]>;
705 // XL-Form instructions. condition register logical ops.
707 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
708 "mcrf $BF, $BFA", BrMCR>,
709 PPC970_DGroup_First, PPC970_Unit_CRU;
711 // XFX-Form instructions. Instructions that deal with SPRs.
713 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>,
714 PPC970_DGroup_First, PPC970_Unit_FXU;
715 let Pattern = [(PPCmtctr GPRC:$rS)] in {
716 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>,
717 PPC970_DGroup_First, PPC970_Unit_FXU;
720 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>,
721 PPC970_DGroup_First, PPC970_Unit_FXU;
722 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>,
723 PPC970_DGroup_First, PPC970_Unit_FXU;
725 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
726 // a GPR on the PPC970. As such, copies in and out have the same performance
727 // characteristics as an OR instruction.
728 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS),
729 "mtspr 256, $rS", IntGeneral>,
730 PPC970_DGroup_Single, PPC970_Unit_FXU;
731 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT),
732 "mfspr $rT, 256", IntGeneral>,
733 PPC970_DGroup_First, PPC970_Unit_FXU;
735 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
736 "mtcrf $FXM, $rS", BrMCRX>,
737 PPC970_MicroCode, PPC970_Unit_CRU;
738 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>,
739 PPC970_MicroCode, PPC970_Unit_CRU;
740 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
741 "mfcr $rT, $FXM", SprMFCR>,
742 PPC970_DGroup_First, PPC970_Unit_CRU;
744 // XS-Form instructions. Just 'sradi'
746 let PPC970_Unit = 1 in { // FXU Operations.
747 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
748 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
750 // XO-Form instructions. Arithmetic instructions that can set overflow bit
752 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
753 "add $rT, $rA, $rB", IntGeneral,
754 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
755 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
756 "add $rT, $rA, $rB", IntGeneral,
757 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
758 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
759 "addc $rT, $rA, $rB", IntGeneral,
760 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
761 PPC970_DGroup_Cracked;
762 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
763 "adde $rT, $rA, $rB", IntGeneral,
764 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
765 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
766 "divd $rT, $rA, $rB", IntDivD,
767 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
768 PPC970_DGroup_First, PPC970_DGroup_Cracked;
769 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
770 "divdu $rT, $rA, $rB", IntDivD,
771 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
772 PPC970_DGroup_First, PPC970_DGroup_Cracked;
773 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
774 "divw $rT, $rA, $rB", IntDivW,
775 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
776 PPC970_DGroup_First, PPC970_DGroup_Cracked;
777 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
778 "divwu $rT, $rA, $rB", IntDivW,
779 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
780 PPC970_DGroup_First, PPC970_DGroup_Cracked;
781 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
782 "mulhd $rT, $rA, $rB", IntMulHW,
783 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
784 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
785 "mulhdu $rT, $rA, $rB", IntMulHWU,
786 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
787 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
788 "mulhw $rT, $rA, $rB", IntMulHW,
789 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
790 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
791 "mulhwu $rT, $rA, $rB", IntMulHWU,
792 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
793 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
794 "mulld $rT, $rA, $rB", IntMulHD,
795 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
796 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
797 "mullw $rT, $rA, $rB", IntMulHW,
798 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
799 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
800 "subf $rT, $rA, $rB", IntGeneral,
801 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
802 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
803 "subfc $rT, $rA, $rB", IntGeneral,
804 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
805 PPC970_DGroup_Cracked;
806 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
807 "subfe $rT, $rA, $rB", IntGeneral,
808 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
809 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
810 "addme $rT, $rA", IntGeneral,
811 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
812 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
813 "addze $rT, $rA", IntGeneral,
814 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
815 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
816 "neg $rT, $rA", IntGeneral,
817 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
818 def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA),
819 "subfme $rT, $rA", IntGeneral,
820 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
821 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
822 "subfze $rT, $rA", IntGeneral,
823 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
826 // A-Form instructions. Most of the instructions executed in the FPU are of
829 let PPC970_Unit = 3 in { // FPU Operations.
830 def FMADD : AForm_1<63, 29,
831 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
832 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
833 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
835 Requires<[FPContractions]>;
836 def FMADDS : AForm_1<59, 29,
837 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
838 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
839 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
841 Requires<[FPContractions]>;
842 def FMSUB : AForm_1<63, 28,
843 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
844 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
845 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
847 Requires<[FPContractions]>;
848 def FMSUBS : AForm_1<59, 28,
849 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
850 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
851 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
853 Requires<[FPContractions]>;
854 def FNMADD : AForm_1<63, 31,
855 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
856 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
857 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
859 Requires<[FPContractions]>;
860 def FNMADDS : AForm_1<59, 31,
861 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
862 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
863 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
865 Requires<[FPContractions]>;
866 def FNMSUB : AForm_1<63, 30,
867 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
868 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
869 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
871 Requires<[FPContractions]>;
872 def FNMSUBS : AForm_1<59, 30,
873 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
874 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
875 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
877 Requires<[FPContractions]>;
878 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
879 // having 4 of these, force the comparison to always be an 8-byte double (code
880 // should use an FMRSD if the input comparison value really wants to be a float)
881 // and 4/8 byte forms for the result and operand type..
882 def FSELD : AForm_1<63, 23,
883 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
884 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
885 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
886 def FSELS : AForm_1<63, 23,
887 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
888 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
889 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
890 def FADD : AForm_2<63, 21,
891 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
892 "fadd $FRT, $FRA, $FRB", FPGeneral,
893 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
894 def FADDS : AForm_2<59, 21,
895 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
896 "fadds $FRT, $FRA, $FRB", FPGeneral,
897 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
898 def FDIV : AForm_2<63, 18,
899 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
900 "fdiv $FRT, $FRA, $FRB", FPDivD,
901 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
902 def FDIVS : AForm_2<59, 18,
903 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
904 "fdivs $FRT, $FRA, $FRB", FPDivS,
905 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
906 def FMUL : AForm_3<63, 25,
907 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
908 "fmul $FRT, $FRA, $FRB", FPFused,
909 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
910 def FMULS : AForm_3<59, 25,
911 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
912 "fmuls $FRT, $FRA, $FRB", FPGeneral,
913 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
914 def FSUB : AForm_2<63, 20,
915 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
916 "fsub $FRT, $FRA, $FRB", FPGeneral,
917 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
918 def FSUBS : AForm_2<59, 20,
919 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
920 "fsubs $FRT, $FRA, $FRB", FPGeneral,
921 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
924 let PPC970_Unit = 1 in { // FXU Operations.
925 // M-Form instructions. rotate and mask instructions.
927 let isTwoAddress = 1, isCommutable = 1 in {
928 // RLWIMI can be commuted if the rotate amount is zero.
929 def RLWIMI : MForm_2<20,
930 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
931 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
932 []>, PPC970_DGroup_Cracked;
933 def RLDIMI : MDForm_1<30, 3,
934 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
935 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
938 def RLWINM : MForm_2<21,
939 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
940 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
942 def RLWINMo : MForm_2<21,
943 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
944 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
945 []>, isDOT, PPC970_DGroup_Cracked;
946 def RLWNM : MForm_2<23,
947 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
948 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
951 // MD-Form instructions. 64 bit rotate instructions.
953 def RLDICL : MDForm_1<30, 0,
954 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
955 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
957 def RLDICR : MDForm_1<30, 1,
958 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
959 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
964 //===----------------------------------------------------------------------===//
965 // DWARF Pseudo Instructions
968 def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
969 "; .loc $file, $line, $col",
970 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
973 def DWARF_LABEL : Pseudo<(ops i32imm:$id),
975 [(dwarf_label (i32 imm:$id))]>;
977 //===----------------------------------------------------------------------===//
978 // PowerPC Instruction Patterns
981 // Arbitrary immediate support. Implement in terms of LIS/ORI.
982 def : Pat<(i32 imm:$imm),
983 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
985 // Implement the 'not' operation with the NOR instruction.
986 def NOT : Pat<(not GPRC:$in),
987 (NOR GPRC:$in, GPRC:$in)>;
989 // ADD an arbitrary immediate.
990 def : Pat<(add GPRC:$in, imm:$imm),
991 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
992 // OR an arbitrary immediate.
993 def : Pat<(or GPRC:$in, imm:$imm),
994 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
995 // XOR an arbitrary immediate.
996 def : Pat<(xor GPRC:$in, imm:$imm),
997 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
999 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1000 (SUBFIC GPRC:$in, imm:$imm)>;
1002 // Return void support.
1003 def : Pat<(ret), (BLR)>;
1006 def : Pat<(i64 (zext GPRC:$in)),
1007 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
1008 def : Pat<(i64 (anyext GPRC:$in)),
1009 (OR4To8 GPRC:$in, GPRC:$in)>;
1010 def : Pat<(i32 (trunc G8RC:$in)),
1011 (OR8To4 G8RC:$in, G8RC:$in)>;
1014 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1015 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1016 def : Pat<(shl G8RC:$in, (i64 imm:$imm)),
1017 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
1019 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1020 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1021 def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
1022 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
1025 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1026 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1027 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1028 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1031 def : Pat<(PPCcall tglobaladdr:$dst),
1032 (BL tglobaladdr:$dst)>;
1033 def : Pat<(PPCcall texternalsym:$dst),
1034 (BL texternalsym:$dst)>;
1036 // Hi and Lo for Darwin Global Addresses.
1037 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1038 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1039 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1040 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1041 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1042 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1043 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1044 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1045 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1046 (ADDIS GPRC:$in, tconstpool:$g)>;
1047 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1048 (ADDIS GPRC:$in, tjumptable:$g)>;
1050 // Fused negative multiply subtract, alternate pattern
1051 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1052 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1053 Requires<[FPContractions]>;
1054 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1055 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1056 Requires<[FPContractions]>;
1058 // Standard shifts. These are represented separately from the real shifts above
1059 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1061 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1062 (SRAW GPRC:$rS, GPRC:$rB)>;
1063 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1064 (SRW GPRC:$rS, GPRC:$rB)>;
1065 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1066 (SLW GPRC:$rS, GPRC:$rB)>;
1068 def : Pat<(i32 (zextload iaddr:$src, i1)),
1070 def : Pat<(i32 (zextload xaddr:$src, i1)),
1072 def : Pat<(i32 (extload iaddr:$src, i1)),
1074 def : Pat<(i32 (extload xaddr:$src, i1)),
1076 def : Pat<(i32 (extload iaddr:$src, i8)),
1078 def : Pat<(i32 (extload xaddr:$src, i8)),
1080 def : Pat<(i32 (extload iaddr:$src, i16)),
1082 def : Pat<(i32 (extload xaddr:$src, i16)),
1084 def : Pat<(f64 (extload iaddr:$src, f32)),
1085 (FMRSD (LFS iaddr:$src))>;
1086 def : Pat<(f64 (extload xaddr:$src, f32)),
1087 (FMRSD (LFSX xaddr:$src))>;
1090 include "PPCInstrAltivec.td"