1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific DAG Nodes.
21 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
22 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
23 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
25 def PPCfsel : SDNode<"PPCISD::FSEL",
26 // Type constraint for fsel.
27 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
28 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
30 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
31 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
33 //===----------------------------------------------------------------------===//
34 // PowerPC specific transformation functions and pattern fragments.
37 def SHL32 : SDNodeXForm<imm, [{
38 // Transformation function: 31 - imm
39 return getI32Imm(31 - N->getValue());
42 def SHL64 : SDNodeXForm<imm, [{
43 // Transformation function: 63 - imm
44 return getI32Imm(63 - N->getValue());
47 def SRL32 : SDNodeXForm<imm, [{
48 // Transformation function: 32 - imm
49 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
52 def SRL64 : SDNodeXForm<imm, [{
53 // Transformation function: 64 - imm
54 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
57 def LO16 : SDNodeXForm<imm, [{
58 // Transformation function: get the low 16 bits.
59 return getI32Imm((unsigned short)N->getValue());
62 def HI16 : SDNodeXForm<imm, [{
63 // Transformation function: shift the immediate value down into the low bits.
64 return getI32Imm((unsigned)N->getValue() >> 16);
67 def HA16 : SDNodeXForm<imm, [{
68 // Transformation function: shift the immediate value down into the low bits.
69 signed int Val = N->getValue();
70 return getI32Imm((Val - (signed short)Val) >> 16);
74 def immSExt16 : PatLeaf<(imm), [{
75 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
76 // field. Used by instructions like 'addi'.
77 return (int)N->getValue() == (short)N->getValue();
79 def immZExt16 : PatLeaf<(imm), [{
80 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
81 // field. Used by instructions like 'ori'.
82 return (unsigned)N->getValue() == (unsigned short)N->getValue();
85 def imm16Shifted : PatLeaf<(imm), [{
86 // imm16Shifted predicate - True if only bits in the top 16-bits of the
87 // immediate are set. Used by instructions like 'addis'.
88 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
92 // Example of a legalize expander: Only for PPC64.
93 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
94 [(set f64:$tmp , (FCTIDZ f64:$src)),
95 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
96 (store f64:$tmp, i32:$tmpFI),
97 (set i64:$dst, (load i32:$tmpFI))],
101 //===----------------------------------------------------------------------===//
102 // PowerPC Flag Definitions.
104 class isPPC64 { bit PPC64 = 1; }
105 class isVMX { bit VMX = 1; }
107 list<Register> Defs = [CR0];
113 //===----------------------------------------------------------------------===//
114 // PowerPC Operand Definitions.
116 def u5imm : Operand<i32> {
117 let PrintMethod = "printU5ImmOperand";
119 def u6imm : Operand<i32> {
120 let PrintMethod = "printU6ImmOperand";
122 def s16imm : Operand<i32> {
123 let PrintMethod = "printS16ImmOperand";
125 def u16imm : Operand<i32> {
126 let PrintMethod = "printU16ImmOperand";
128 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
129 let PrintMethod = "printS16X4ImmOperand";
131 def target : Operand<i32> {
132 let PrintMethod = "printBranchOperand";
134 def calltarget : Operand<i32> {
135 let PrintMethod = "printCallOperand";
137 def aaddr : Operand<i32> {
138 let PrintMethod = "printAbsAddrOperand";
140 def piclabel: Operand<i32> {
141 let PrintMethod = "printPICLabel";
143 def symbolHi: Operand<i32> {
144 let PrintMethod = "printSymbolHi";
146 def symbolLo: Operand<i32> {
147 let PrintMethod = "printSymbolLo";
149 def crbitm: Operand<i8> {
150 let PrintMethod = "printcrbitm";
155 //===----------------------------------------------------------------------===//
156 // PowerPC Instruction Definitions.
158 // Pseudo-instructions:
159 def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
162 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN", []>;
163 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP", []>;
165 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
166 [(set GPRC:$rD, (undef))]>;
167 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8",
168 [(set F8RC:$rD, (undef))]>;
169 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4",
170 [(set F4RC:$rD, (undef))]>;
172 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
173 // scheduler into a branch sequence.
174 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
175 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
176 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
177 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
178 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
179 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
180 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
184 let isTerminator = 1 in {
186 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB>;
187 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB>;
191 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>;
193 let isBranch = 1, isTerminator = 1 in {
194 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
195 target:$true, target:$false),
196 "; COND_BRANCH", []>;
197 def B : IForm<18, 0, 0, (ops target:$func), "b $func", BrB>;
199 // FIXME: 4*CR# needs to be added to the BI field!
200 // This will only work for CR0 as it stands now
201 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
202 "blt $crS, $block", BrB>;
203 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
204 "ble $crS, $block", BrB>;
205 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
206 "beq $crS, $block", BrB>;
207 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
208 "bge $crS, $block", BrB>;
209 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
210 "bgt $crS, $block", BrB>;
211 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
212 "bne $crS, $block", BrB>;
213 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
214 "bun $crS, $block", BrB>;
215 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
216 "bnu $crS, $block", BrB>;
220 // All calls clobber the non-callee saved registers...
221 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
222 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
224 CR0,CR1,CR5,CR6,CR7] in {
225 // Convenient aliases for call instructions
226 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops), "bl $func", BrB>;
227 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops), "bla $func", BrB>;
228 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB>;
231 // D-Form instructions. Most instructions that perform an operation on a
232 // register and an immediate are of this type.
235 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
236 "lbz $rD, $disp($rA)", LdStGeneral>;
237 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
238 "lha $rD, $disp($rA)", LdStLHA>;
239 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
240 "lhz $rD, $disp($rA)", LdStGeneral>;
241 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
242 "lmw $rD, $disp($rA)", LdStLMW>;
243 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
244 "lwz $rD, $disp($rA)", LdStGeneral>;
245 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
246 "lwzu $rD, $disp($rA)", LdStGeneral>;
248 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
249 "addi $rD, $rA, $imm", IntGeneral,
250 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
251 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
252 "addic $rD, $rA, $imm", IntGeneral,
254 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
255 "addic. $rD, $rA, $imm", IntGeneral,
257 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
258 "addis $rD, $rA, $imm", IntGeneral,
259 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
260 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
261 "la $rD, $sym($rA)", IntGeneral,
262 [(set GPRC:$rD, (add GPRC:$rA,
263 (PPClo tglobaladdr:$sym, 0)))]>;
264 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
265 "mulli $rD, $rA, $imm", IntMulLI,
266 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
267 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
268 "subfic $rD, $rA, $imm", IntGeneral,
269 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
270 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
271 "li $rD, $imm", IntGeneral,
272 [(set GPRC:$rD, immSExt16:$imm)]>;
273 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
274 "lis $rD, $imm", IntGeneral,
275 [(set GPRC:$rD, imm16Shifted:$imm)]>;
277 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
278 "stmw $rS, $disp($rA)", LdStLMW>;
279 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
280 "stb $rS, $disp($rA)", LdStGeneral>;
281 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
282 "sth $rS, $disp($rA)", LdStGeneral>;
283 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
284 "stw $rS, $disp($rA)", LdStGeneral>;
285 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
286 "stwu $rS, $disp($rA)", LdStGeneral>;
288 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
289 "andi. $dst, $src1, $src2", IntGeneral,
291 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
292 "andis. $dst, $src1, $src2", IntGeneral,
294 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
295 "ori $dst, $src1, $src2", IntGeneral,
296 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
297 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
298 "oris $dst, $src1, $src2", IntGeneral,
299 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
300 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
301 "xori $dst, $src1, $src2", IntGeneral,
302 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
303 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
304 "xoris $dst, $src1, $src2", IntGeneral,
305 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
306 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral>;
307 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
308 "cmpi $crD, $L, $rA, $imm", IntCompare>;
309 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
310 "cmpwi $crD, $rA, $imm", IntCompare>;
311 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
312 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
313 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
314 "cmpli $dst, $size, $src1, $src2", IntCompare>;
315 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
316 "cmplwi $dst, $src1, $src2", IntCompare>;
317 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
318 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
320 def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
321 "lfs $rD, $disp($rA)", LdStLFDU>;
322 def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
323 "lfd $rD, $disp($rA)", LdStLFD>;
326 def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
327 "stfs $rS, $disp($rA)", LdStUX>;
328 def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
329 "stfd $rS, $disp($rA)", LdStUX>;
332 // DS-Form instructions. Load/Store instructions available in PPC-64
335 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
336 "lwa $rT, $DS($rA)", LdStLWA>, isPPC64;
337 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
338 "ld $rT, $DS($rA)", LdStLD>, isPPC64;
341 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
342 "std $rT, $DS($rA)", LdStSTD>, isPPC64;
343 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
344 "stdu $rT, $DS($rA)", LdStSTD>, isPPC64;
347 // X-Form instructions. Most instructions that perform an operation on a
348 // register and another register are of this type.
351 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
352 "lbzx $dst, $base, $index", LdStGeneral>;
353 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
354 "lhax $dst, $base, $index", LdStLHA>;
355 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
356 "lhzx $dst, $base, $index", LdStGeneral>;
357 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
358 "lwax $dst, $base, $index", LdStLHA>, isPPC64;
359 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
360 "lwzx $dst, $base, $index", LdStGeneral>;
361 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
362 "ldx $dst, $base, $index", LdStLD>, isPPC64;
363 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
364 "lvebx $vD, $base, $rA", LdStGeneral>;
365 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
366 "lvehx $vD, $base, $rA", LdStGeneral>;
367 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
368 "lvewx $vD, $base, $rA", LdStGeneral>;
369 def LVX : XForm_1<31, 103, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
370 "lvx $vD, $base, $rA", LdStGeneral>;
371 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
372 "lvsl $vD, $base, $rA", LdStGeneral>;
373 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
374 "lvsl $vD, $base, $rA", LdStGeneral>;
376 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
377 "nand $rA, $rS, $rB", IntGeneral,
378 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
379 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
380 "and $rA, $rS, $rB", IntGeneral,
381 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
382 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
383 "and. $rA, $rS, $rB", IntGeneral,
385 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
386 "andc $rA, $rS, $rB", IntGeneral,
387 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
388 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
389 "or $rA, $rS, $rB", IntGeneral,
390 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
391 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
392 "or $rA, $rS, $rB", IntGeneral,
393 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
394 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
395 "or $rA, $rS, $rB", IntGeneral,
397 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
398 "or $rA, $rS, $rB", IntGeneral,
400 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
401 "nor $rA, $rS, $rB", IntGeneral,
402 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
403 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
404 "or. $rA, $rS, $rB", IntGeneral,
406 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
407 "orc $rA, $rS, $rB", IntGeneral,
408 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
409 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
410 "eqv $rA, $rS, $rB", IntGeneral,
411 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
412 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
413 "xor $rA, $rS, $rB", IntGeneral,
414 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
415 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
416 "sld $rA, $rS, $rB", IntRotateD,
417 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
418 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
419 "slw $rA, $rS, $rB", IntGeneral,
420 [(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>;
421 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
422 "srd $rA, $rS, $rB", IntRotateD,
423 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
424 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
425 "srw $rA, $rS, $rB", IntGeneral,
426 [(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>;
427 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
428 "srad $rA, $rS, $rB", IntRotateD,
429 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
430 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
431 "sraw $rA, $rS, $rB", IntShift,
432 [(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>;
434 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
435 "stbx $rS, $rA, $rB", LdStGeneral>;
436 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
437 "sthx $rS, $rA, $rB", LdStGeneral>;
438 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
439 "stwx $rS, $rA, $rB", LdStGeneral>;
440 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
441 "stwux $rS, $rA, $rB", LdStGeneral>;
442 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
443 "stdx $rS, $rA, $rB", LdStSTD>, isPPC64;
444 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
445 "stdux $rS, $rA, $rB", LdStSTD>, isPPC64;
446 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
447 "stvebx $rS, $rA, $rB", LdStGeneral>;
448 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
449 "stvehx $rS, $rA, $rB", LdStGeneral>;
450 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
451 "stvewx $rS, $rA, $rB", LdStGeneral>;
452 def STVX : XForm_8<31, 231, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
453 "stvx $rS, $rA, $rB", LdStGeneral>;
455 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
456 "srawi $rA, $rS, $SH", IntShift,
457 [(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
458 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
459 "cntlzw $rA, $rS", IntGeneral,
460 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
461 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
462 "extsb $rA, $rS", IntGeneral,
463 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
464 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
465 "extsh $rA, $rS", IntGeneral,
466 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
467 def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
468 "extsw $rA, $rS", IntGeneral,
469 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
470 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
471 "cmp $crD, $long, $rA, $rB", IntCompare>;
472 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
473 "cmpl $crD, $long, $rA, $rB", IntCompare>;
474 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
475 "cmpw $crD, $rA, $rB", IntCompare>;
476 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
477 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
478 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
479 "cmplw $crD, $rA, $rB", IntCompare>;
480 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
481 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
482 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
483 // "fcmpo $crD, $fA, $fB", FPCompare>;
484 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
485 "fcmpu $crD, $fA, $fB", FPCompare>;
486 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
487 "fcmpu $crD, $fA, $fB", FPCompare>;
490 def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
491 "lfsx $dst, $base, $index", LdStLFDU>;
492 def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
493 "lfdx $dst, $base, $index", LdStLFDU>;
495 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
496 "fcfid $frD, $frB", FPGeneral,
497 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
498 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
499 "fctidz $frD, $frB", FPGeneral,
500 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
501 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
502 "fctiwz $frD, $frB", FPGeneral,
503 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
504 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
505 "frsp $frD, $frB", FPGeneral,
506 [(set F4RC:$frD, (fround F8RC:$frB))]>;
507 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
508 "fsqrt $frD, $frB", FPSqrt,
509 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
510 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
511 "fsqrts $frD, $frB", FPSqrt,
512 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
514 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
515 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
516 "fmr $frD, $frB", FPGeneral,
517 []>; // (set F4RC:$frD, F4RC:$frB)
518 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
519 "fmr $frD, $frB", FPGeneral,
520 []>; // (set F8RC:$frD, F8RC:$frB)
521 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
522 "fmr $frD, $frB", FPGeneral,
523 [(set F8RC:$frD, (fextend F4RC:$frB))]>;
525 // These are artificially split into two different forms, for 4/8 byte FP.
526 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
527 "fabs $frD, $frB", FPGeneral,
528 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
529 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
530 "fabs $frD, $frB", FPGeneral,
531 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
532 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
533 "fnabs $frD, $frB", FPGeneral,
534 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
535 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
536 "fnabs $frD, $frB", FPGeneral,
537 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
538 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
539 "fneg $frD, $frB", FPGeneral,
540 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
541 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
542 "fneg $frD, $frB", FPGeneral,
543 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
547 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
548 "stfsx $frS, $rA, $rB", LdStUX>;
549 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
550 "stfdx $frS, $rA, $rB", LdStUX>;
553 // XL-Form instructions. condition register logical ops.
555 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
556 "mcrf $BF, $BFA", BrMCR>;
558 // XFX-Form instructions. Instructions that deal with SPRs
560 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
561 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
562 // which means the SPR value needs to be multiplied by a factor of 32.
563 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
564 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
565 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
566 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
567 "mtcrf $FXM, $rS", BrMCRX>;
568 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
569 "mfcr $rT, $FXM", SprMFCR>;
570 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
571 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
573 // XS-Form instructions. Just 'sradi'
575 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
576 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
578 // XO-Form instructions. Arithmetic instructions that can set overflow bit
580 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
581 "add $rT, $rA, $rB", IntGeneral,
582 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
583 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
584 "add $rT, $rA, $rB", IntGeneral,
585 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
586 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
587 "addc $rT, $rA, $rB", IntGeneral,
589 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
590 "adde $rT, $rA, $rB", IntGeneral,
592 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
593 "divd $rT, $rA, $rB", IntDivD,
594 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
595 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
596 "divdu $rT, $rA, $rB", IntDivD,
597 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
598 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
599 "divw $rT, $rA, $rB", IntDivW,
600 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
601 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
602 "divwu $rT, $rA, $rB", IntDivW,
603 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
604 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
605 "mulhd $rT, $rA, $rB", IntMulHW,
606 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
607 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
608 "mulhdu $rT, $rA, $rB", IntMulHWU,
609 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
610 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
611 "mulhw $rT, $rA, $rB", IntMulHW,
612 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
613 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
614 "mulhwu $rT, $rA, $rB", IntMulHWU,
615 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
616 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
617 "mulld $rT, $rA, $rB", IntMulHD,
618 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
619 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
620 "mullw $rT, $rA, $rB", IntMulHW,
621 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
622 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
623 "subf $rT, $rA, $rB", IntGeneral,
624 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
625 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
626 "subfc $rT, $rA, $rB", IntGeneral,
628 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
629 "subfe $rT, $rA, $rB", IntGeneral,
631 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
632 "addme $rT, $rA", IntGeneral,
634 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
635 "addze $rT, $rA", IntGeneral,
637 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
638 "neg $rT, $rA", IntGeneral,
639 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
640 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
641 "subfze $rT, $rA", IntGeneral,
644 // A-Form instructions. Most of the instructions executed in the FPU are of
647 def FMADD : AForm_1<63, 29,
648 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
649 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
650 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
652 def FMADDS : AForm_1<59, 29,
653 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
654 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
655 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
657 def FMSUB : AForm_1<63, 28,
658 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
659 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
660 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
662 def FMSUBS : AForm_1<59, 28,
663 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
664 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
665 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
667 def FNMADD : AForm_1<63, 31,
668 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
669 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
670 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
672 def FNMADDS : AForm_1<59, 31,
673 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
674 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
675 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
677 def FNMSUB : AForm_1<63, 30,
678 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
679 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
680 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
682 def FNMSUBS : AForm_1<59, 30,
683 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
684 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
685 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
687 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
688 // having 4 of these, force the comparison to always be an 8-byte double (code
689 // should use an FMRSD if the input comparison value really wants to be a float)
690 // and 4/8 byte forms for the result and operand type..
691 def FSELD : AForm_1<63, 23,
692 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
693 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
694 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
695 def FSELS : AForm_1<63, 23,
696 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
697 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
698 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
699 def FADD : AForm_2<63, 21,
700 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
701 "fadd $FRT, $FRA, $FRB", FPGeneral,
702 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
703 def FADDS : AForm_2<59, 21,
704 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
705 "fadds $FRT, $FRA, $FRB", FPGeneral,
706 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
707 def FDIV : AForm_2<63, 18,
708 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
709 "fdiv $FRT, $FRA, $FRB", FPDivD,
710 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
711 def FDIVS : AForm_2<59, 18,
712 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
713 "fdivs $FRT, $FRA, $FRB", FPDivS,
714 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
715 def FMUL : AForm_3<63, 25,
716 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
717 "fmul $FRT, $FRA, $FRB", FPFused,
718 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
719 def FMULS : AForm_3<59, 25,
720 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
721 "fmuls $FRT, $FRA, $FRB", FPGeneral,
722 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
723 def FSUB : AForm_2<63, 20,
724 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
725 "fsub $FRT, $FRA, $FRB", FPGeneral,
726 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
727 def FSUBS : AForm_2<59, 20,
728 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
729 "fsubs $FRT, $FRA, $FRB", FPGeneral,
730 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
732 // M-Form instructions. rotate and mask instructions.
734 let isTwoAddress = 1, isCommutable = 1 in {
735 // RLWIMI can be commuted if the rotate amount is zero.
736 def RLWIMI : MForm_2<20,
737 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
738 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
740 def RLDIMI : MDForm_1<30, 3,
741 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
742 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
745 def RLWINM : MForm_2<21,
746 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
747 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
749 def RLWINMo : MForm_2<21,
750 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
751 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
753 def RLWNM : MForm_2<23,
754 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
755 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
758 // MD-Form instructions. 64 bit rotate instructions.
760 def RLDICL : MDForm_1<30, 0,
761 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
762 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
764 def RLDICR : MDForm_1<30, 1,
765 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
766 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
769 // VA-Form instructions. 3-input AltiVec ops.
770 def VMADDFP: VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
771 "vmaddfp $vD, $vA, $vB, $vC", VecFP,
774 // VX-Form instructions. AltiVec arithmetic ops.
775 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
776 "vaddfp $vD, $vA, $vB", VecFP,
778 def VADDUWM: VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
779 "vadduwm $vD, $vA, $vB", VecGeneral,
781 def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
782 "vand $vD, $vA, $vB", VecGeneral,
784 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
785 "vcfsx $vD, $vB, $UIMM", VecFP,
787 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
788 "vcfux $vD, $vB, $UIMM", VecFP,
790 def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
791 "vor $vD, $vA, $vB", VecGeneral,
793 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
794 "vxor $vD, $vA, $vB", VecGeneral,
797 //===----------------------------------------------------------------------===//
798 // PowerPC Instruction Patterns
801 // Arbitrary immediate support. Implement in terms of LIS/ORI.
802 def : Pat<(i32 imm:$imm),
803 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
805 // Implement the 'not' operation with the NOR instruction.
806 def NOT : Pat<(not GPRC:$in),
807 (NOR GPRC:$in, GPRC:$in)>;
809 // ADD an arbitrary immediate.
810 def : Pat<(add GPRC:$in, imm:$imm),
811 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
812 // OR an arbitrary immediate.
813 def : Pat<(or GPRC:$in, imm:$imm),
814 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
815 // XOR an arbitrary immediate.
816 def : Pat<(xor GPRC:$in, imm:$imm),
817 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
818 def : Pat<(or (shl GPRC:$rS, GPRC:$rB),
819 (srl GPRC:$rS, (sub 32, GPRC:$rB))),
820 (RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
822 def : Pat<(zext GPRC:$in),
823 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
824 def : Pat<(anyext GPRC:$in),
825 (OR4To8 GPRC:$in, GPRC:$in)>;
826 def : Pat<(trunc G8RC:$in),
827 (OR8To4 G8RC:$in, G8RC:$in)>;
830 def : Pat<(shl GPRC:$in, imm:$imm),
831 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
832 def : Pat<(shl G8RC:$in, imm:$imm),
833 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
835 def : Pat<(srl GPRC:$in, imm:$imm),
836 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
837 def : Pat<(srl G8RC:$in, imm:$imm),
838 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
840 // Hi and Lo for Darwin Global Addresses.
841 def : Pat<(PPChi tglobaladdr:$in, (i32 0)), (LIS tglobaladdr:$in)>;
842 def : Pat<(PPClo tglobaladdr:$in, (i32 0)), (LI tglobaladdr:$in)>;
843 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
844 (ADDIS GPRC:$in, tglobaladdr:$g)>;
846 // Same as above, but using a temporary. FIXME: implement temporaries :)
848 def : Pattern<(xor GPRC:$in, imm:$imm),
849 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
850 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
853 //===----------------------------------------------------------------------===//
854 // PowerPCInstrInfo Definition
856 def PowerPCInstrInfo : InstrInfo {
859 let TSFlagsFields = [ "VMX", "PPC64" ];
860 let TSFlagsShifts = [ 0, 1 ];
862 let isLittleEndianEncoding = 1;