1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
28 def SDT_PPCvperm : SDTypeProfile<1, 3, [
29 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
32 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
33 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
36 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
37 SDTCisVT<1, i32>, SDTCisVT<2, OtherVT>
40 //===----------------------------------------------------------------------===//
41 // PowerPC specific DAG Nodes.
44 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
45 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
46 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
47 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
49 def PPCfsel : SDNode<"PPCISD::FSEL",
50 // Type constraint for fsel.
51 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
52 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
54 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
55 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
56 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
57 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
59 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
61 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
62 // amounts. These nodes are generated by the multi-precision shift code.
63 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
64 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
65 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
67 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
68 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
70 // These are target-independent nodes, but have target-specific formats.
71 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
72 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
74 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
75 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
76 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
77 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
78 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTRet,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
82 def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet,
83 [SDNPHasChain, SDNPOptInFlag]>;
85 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
86 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
88 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
89 [SDNPHasChain, SDNPOptInFlag]>;
91 //===----------------------------------------------------------------------===//
92 // PowerPC specific transformation functions and pattern fragments.
95 def SHL32 : SDNodeXForm<imm, [{
96 // Transformation function: 31 - imm
97 return getI32Imm(31 - N->getValue());
100 def SHL64 : SDNodeXForm<imm, [{
101 // Transformation function: 63 - imm
102 return getI32Imm(63 - N->getValue());
105 def SRL32 : SDNodeXForm<imm, [{
106 // Transformation function: 32 - imm
107 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
110 def SRL64 : SDNodeXForm<imm, [{
111 // Transformation function: 64 - imm
112 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
115 def LO16 : SDNodeXForm<imm, [{
116 // Transformation function: get the low 16 bits.
117 return getI32Imm((unsigned short)N->getValue());
120 def HI16 : SDNodeXForm<imm, [{
121 // Transformation function: shift the immediate value down into the low bits.
122 return getI32Imm((unsigned)N->getValue() >> 16);
125 def HA16 : SDNodeXForm<imm, [{
126 // Transformation function: shift the immediate value down into the low bits.
127 signed int Val = N->getValue();
128 return getI32Imm((Val - (signed short)Val) >> 16);
132 def immSExt16 : PatLeaf<(imm), [{
133 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
134 // field. Used by instructions like 'addi'.
135 return (int)N->getValue() == (short)N->getValue();
137 def immZExt16 : PatLeaf<(imm), [{
138 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
139 // field. Used by instructions like 'ori'.
140 return (unsigned)N->getValue() == (unsigned short)N->getValue();
143 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
144 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
145 // identical in 32-bit mode, but in 64-bit mode, they return true if the
146 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
148 def imm16ShiftedZExt : PatLeaf<(imm), [{
149 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
150 // immediate are set. Used by instructions like 'xoris'.
151 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
154 def imm16ShiftedSExt : PatLeaf<(imm), [{
155 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
156 // immediate are set. Used by instructions like 'addis'. Identical to
157 // imm16ShiftedZExt in 32-bit mode.
158 if (N->getValue() & 0xFFFF) return false;
159 if (N->getValueType(0) == MVT::i32)
161 // For 64-bit, make sure it is sext right.
162 return N->getValue() == (uint64_t)(int)N->getValue();
166 //===----------------------------------------------------------------------===//
167 // PowerPC Flag Definitions.
169 class isPPC64 { bit PPC64 = 1; }
170 class isVMX { bit VMX = 1; }
172 list<Register> Defs = [CR0];
178 //===----------------------------------------------------------------------===//
179 // PowerPC Operand Definitions.
181 def s5imm : Operand<i32> {
182 let PrintMethod = "printS5ImmOperand";
184 def u5imm : Operand<i32> {
185 let PrintMethod = "printU5ImmOperand";
187 def u6imm : Operand<i32> {
188 let PrintMethod = "printU6ImmOperand";
190 def s16imm : Operand<i32> {
191 let PrintMethod = "printS16ImmOperand";
193 def u16imm : Operand<i32> {
194 let PrintMethod = "printU16ImmOperand";
196 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
197 let PrintMethod = "printS16X4ImmOperand";
199 def target : Operand<OtherVT> {
200 let PrintMethod = "printBranchOperand";
202 def calltarget : Operand<iPTR> {
203 let PrintMethod = "printCallOperand";
205 def aaddr : Operand<iPTR> {
206 let PrintMethod = "printAbsAddrOperand";
208 def piclabel: Operand<iPTR> {
209 let PrintMethod = "printPICLabel";
211 def symbolHi: Operand<i32> {
212 let PrintMethod = "printSymbolHi";
214 def symbolLo: Operand<i32> {
215 let PrintMethod = "printSymbolLo";
217 def crbitm: Operand<i8> {
218 let PrintMethod = "printcrbitm";
221 def memri : Operand<iPTR> {
222 let PrintMethod = "printMemRegImm";
223 let NumMIOperands = 2;
224 let MIOperandInfo = (ops i32imm, ptr_rc);
226 def memrr : Operand<iPTR> {
227 let PrintMethod = "printMemRegReg";
228 let NumMIOperands = 2;
229 let MIOperandInfo = (ops ptr_rc, ptr_rc);
231 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
232 let PrintMethod = "printMemRegImmShifted";
233 let NumMIOperands = 2;
234 let MIOperandInfo = (ops i32imm, ptr_rc);
237 // Define PowerPC specific addressing mode.
238 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", []>;
239 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", []>;
240 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[]>;
241 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", []>; // "std"
243 //===----------------------------------------------------------------------===//
244 // PowerPC Instruction Predicate Definitions.
245 def FPContractions : Predicate<"!NoExcessFPPrecision">;
247 //===----------------------------------------------------------------------===//
248 // PowerPC Instruction Definitions.
250 // Pseudo-instructions:
252 let hasCtrlDep = 1 in {
253 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
254 "; ADJCALLSTACKDOWN",
255 [(callseq_start imm:$amt)]>;
256 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
258 [(callseq_end imm:$amt)]>;
260 def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
261 "UPDATE_VRSAVE $rD, $rS", []>;
263 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
264 [(set GPRC:$rD, (undef))]>;
265 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8",
266 [(set F8RC:$rD, (undef))]>;
267 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; $rD = IMPLICIT_DEF_F4",
268 [(set F4RC:$rD, (undef))]>;
270 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
271 // scheduler into a branch sequence.
272 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
273 PPC970_Single = 1 in {
274 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
275 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
276 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
277 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
278 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
279 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
280 def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F,
281 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
284 let isTerminator = 1, noResults = 1, PPC970_Unit = 7 in {
286 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
287 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
291 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
294 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
295 noResults = 1, PPC970_Unit = 7 in {
296 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
297 "; COND_BRANCH $crS, $opc, $dst",
298 [(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
299 def B : IForm<18, 0, 0, (ops target:$dst),
303 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
304 "blt $crS, $block", BrB>;
305 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
306 "ble $crS, $block", BrB>;
307 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
308 "beq $crS, $block", BrB>;
309 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
310 "bge $crS, $block", BrB>;
311 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
312 "bgt $crS, $block", BrB>;
313 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
314 "bne $crS, $block", BrB>;
315 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
316 "bun $crS, $block", BrB>;
317 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
318 "bnu $crS, $block", BrB>;
321 let isCall = 1, noResults = 1, PPC970_Unit = 7,
322 // All calls clobber the non-callee saved registers...
323 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
324 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
325 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
327 CR0,CR1,CR5,CR6,CR7] in {
328 // Convenient aliases for call instructions
329 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
330 "bl $func", BrB, []>; // See Pat patterns below.
331 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
332 "bla $func", BrB, [(PPCcall imm:$func)]>;
333 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB,
337 // DCB* instructions.
338 def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
339 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
340 PPC970_DGroup_Single;
341 def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
342 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
343 PPC970_DGroup_Single;
345 // D-Form instructions. Most instructions that perform an operation on a
346 // register and an immediate are of this type.
348 let isLoad = 1, PPC970_Unit = 2 in {
349 def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
350 "lbz $rD, $src", LdStGeneral,
351 [(set GPRC:$rD, (zextload iaddr:$src, i8))]>;
352 def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
353 "lha $rD, $src", LdStLHA,
354 [(set GPRC:$rD, (sextload iaddr:$src, i16))]>,
355 PPC970_DGroup_Cracked;
356 def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
357 "lhz $rD, $src", LdStGeneral,
358 [(set GPRC:$rD, (zextload iaddr:$src, i16))]>;
359 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
360 "lwz $rD, $src", LdStGeneral,
361 [(set GPRC:$rD, (load iaddr:$src))]>;
362 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
363 "lwzu $rD, $disp($rA)", LdStGeneral,
366 let PPC970_Unit = 1 in { // FXU Operations.
367 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
368 "addi $rD, $rA, $imm", IntGeneral,
369 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
370 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
371 "addic $rD, $rA, $imm", IntGeneral,
372 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
373 PPC970_DGroup_Cracked;
374 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
375 "addic. $rD, $rA, $imm", IntGeneral,
377 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
378 "addis $rD, $rA, $imm", IntGeneral,
379 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
380 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
381 "la $rD, $sym($rA)", IntGeneral,
382 [(set GPRC:$rD, (add GPRC:$rA,
383 (PPClo tglobaladdr:$sym, 0)))]>;
384 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
385 "mulli $rD, $rA, $imm", IntMulLI,
386 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
387 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
388 "subfic $rD, $rA, $imm", IntGeneral,
389 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
390 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
391 "li $rD, $imm", IntGeneral,
392 [(set GPRC:$rD, immSExt16:$imm)]>;
393 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
394 "lis $rD, $imm", IntGeneral,
395 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
397 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
398 def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
399 "stb $rS, $src", LdStGeneral,
400 [(truncstore GPRC:$rS, iaddr:$src, i8)]>;
401 def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
402 "sth $rS, $src", LdStGeneral,
403 [(truncstore GPRC:$rS, iaddr:$src, i16)]>;
404 def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
405 "stw $rS, $src", LdStGeneral,
406 [(store GPRC:$rS, iaddr:$src)]>;
407 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
408 "stwu $rS, $disp($rA)", LdStGeneral,
411 let PPC970_Unit = 1 in { // FXU Operations.
412 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
413 "andi. $dst, $src1, $src2", IntGeneral,
414 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
416 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
417 "andis. $dst, $src1, $src2", IntGeneral,
418 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
420 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
421 "ori $dst, $src1, $src2", IntGeneral,
422 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
423 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
424 "oris $dst, $src1, $src2", IntGeneral,
425 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
426 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
427 "xori $dst, $src1, $src2", IntGeneral,
428 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
429 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
430 "xoris $dst, $src1, $src2", IntGeneral,
431 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
432 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
434 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
435 "cmpi $crD, $L, $rA, $imm", IntCompare>;
436 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
437 "cmpwi $crD, $rA, $imm", IntCompare>;
438 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
439 "cmpli $dst, $size, $src1, $src2", IntCompare>;
440 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
441 "cmplwi $dst, $src1, $src2", IntCompare>;
443 let isLoad = 1, PPC970_Unit = 2 in {
444 def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src),
445 "lfs $rD, $src", LdStLFDU,
446 [(set F4RC:$rD, (load iaddr:$src))]>;
447 def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src),
448 "lfd $rD, $src", LdStLFD,
449 [(set F8RC:$rD, (load iaddr:$src))]>;
451 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
452 def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst),
453 "stfs $rS, $dst", LdStUX,
454 [(store F4RC:$rS, iaddr:$dst)]>;
455 def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst),
456 "stfd $rS, $dst", LdStUX,
457 [(store F8RC:$rS, iaddr:$dst)]>;
460 // X-Form instructions. Most instructions that perform an operation on a
461 // register and another register are of this type.
463 let isLoad = 1, PPC970_Unit = 2 in {
464 def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
465 "lbzx $rD, $src", LdStGeneral,
466 [(set GPRC:$rD, (zextload xaddr:$src, i8))]>;
467 def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
468 "lhax $rD, $src", LdStLHA,
469 [(set GPRC:$rD, (sextload xaddr:$src, i16))]>,
470 PPC970_DGroup_Cracked;
471 def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
472 "lhzx $rD, $src", LdStGeneral,
473 [(set GPRC:$rD, (zextload xaddr:$src, i16))]>;
474 def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
475 "lwzx $rD, $src", LdStGeneral,
476 [(set GPRC:$rD, (load xaddr:$src))]>;
479 let PPC970_Unit = 1 in { // FXU Operations.
480 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
481 "nand $rA, $rS, $rB", IntGeneral,
482 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
483 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
484 "and $rA, $rS, $rB", IntGeneral,
485 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
486 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
487 "and. $rA, $rS, $rB", IntGeneral,
489 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
490 "andc $rA, $rS, $rB", IntGeneral,
491 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
492 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
493 "or $rA, $rS, $rB", IntGeneral,
494 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
495 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
496 "nor $rA, $rS, $rB", IntGeneral,
497 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
498 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
499 "or. $rA, $rS, $rB", IntGeneral,
501 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
502 "orc $rA, $rS, $rB", IntGeneral,
503 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
504 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
505 "eqv $rA, $rS, $rB", IntGeneral,
506 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
507 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
508 "xor $rA, $rS, $rB", IntGeneral,
509 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
510 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
511 "slw $rA, $rS, $rB", IntGeneral,
512 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
513 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
514 "srw $rA, $rS, $rB", IntGeneral,
515 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
516 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
517 "sraw $rA, $rS, $rB", IntShift,
518 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
520 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
521 def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
522 "stbx $rS, $dst", LdStGeneral,
523 [(truncstore GPRC:$rS, xaddr:$dst, i8)]>,
524 PPC970_DGroup_Cracked;
525 def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
526 "sthx $rS, $dst", LdStGeneral,
527 [(truncstore GPRC:$rS, xaddr:$dst, i16)]>,
528 PPC970_DGroup_Cracked;
529 def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
530 "stwx $rS, $dst", LdStGeneral,
531 [(store GPRC:$rS, xaddr:$dst)]>,
532 PPC970_DGroup_Cracked;
533 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
534 "stwux $rS, $rA, $rB", LdStGeneral,
537 let PPC970_Unit = 1 in { // FXU Operations.
538 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
539 "srawi $rA, $rS, $SH", IntShift,
540 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
541 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
542 "cntlzw $rA, $rS", IntGeneral,
543 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
544 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
545 "extsb $rA, $rS", IntGeneral,
546 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
547 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
548 "extsh $rA, $rS", IntGeneral,
549 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
551 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
552 "cmp $crD, $long, $rA, $rB", IntCompare>;
553 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
554 "cmpl $crD, $long, $rA, $rB", IntCompare>;
555 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
556 "cmpw $crD, $rA, $rB", IntCompare>;
557 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
558 "cmplw $crD, $rA, $rB", IntCompare>;
560 let PPC970_Unit = 3 in { // FPU Operations.
561 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
562 // "fcmpo $crD, $fA, $fB", FPCompare>;
563 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
564 "fcmpu $crD, $fA, $fB", FPCompare>;
565 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
566 "fcmpu $crD, $fA, $fB", FPCompare>;
568 let isLoad = 1, PPC970_Unit = 2 in {
569 def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
570 "lfsx $frD, $src", LdStLFDU,
571 [(set F4RC:$frD, (load xaddr:$src))]>;
572 def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
573 "lfdx $frD, $src", LdStLFDU,
574 [(set F8RC:$frD, (load xaddr:$src))]>;
576 let PPC970_Unit = 3 in { // FPU Operations.
577 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
578 "fctiwz $frD, $frB", FPGeneral,
579 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
580 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
581 "frsp $frD, $frB", FPGeneral,
582 [(set F4RC:$frD, (fround F8RC:$frB))]>;
583 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
584 "fsqrt $frD, $frB", FPSqrt,
585 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
586 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
587 "fsqrts $frD, $frB", FPSqrt,
588 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
591 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
593 /// Note that these are defined as pseudo-ops on the PPC970 because they are
594 /// often coalesced away and we don't want the dispatch group builder to think
595 /// that they will fill slots (which could cause the load of a LSU reject to
596 /// sneak into a d-group with a store).
597 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
598 "fmr $frD, $frB", FPGeneral,
599 []>, // (set F4RC:$frD, F4RC:$frB)
601 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
602 "fmr $frD, $frB", FPGeneral,
603 []>, // (set F8RC:$frD, F8RC:$frB)
605 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
606 "fmr $frD, $frB", FPGeneral,
607 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
610 let PPC970_Unit = 3 in { // FPU Operations.
611 // These are artificially split into two different forms, for 4/8 byte FP.
612 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
613 "fabs $frD, $frB", FPGeneral,
614 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
615 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
616 "fabs $frD, $frB", FPGeneral,
617 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
618 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
619 "fnabs $frD, $frB", FPGeneral,
620 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
621 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
622 "fnabs $frD, $frB", FPGeneral,
623 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
624 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
625 "fneg $frD, $frB", FPGeneral,
626 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
627 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
628 "fneg $frD, $frB", FPGeneral,
629 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
632 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
633 def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst),
634 "stfiwx $frS, $dst", LdStUX,
635 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
636 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
637 "stfsx $frS, $dst", LdStUX,
638 [(store F4RC:$frS, xaddr:$dst)]>;
639 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
640 "stfdx $frS, $dst", LdStUX,
641 [(store F8RC:$frS, xaddr:$dst)]>;
644 // XL-Form instructions. condition register logical ops.
646 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
647 "mcrf $BF, $BFA", BrMCR>,
648 PPC970_DGroup_First, PPC970_Unit_CRU;
650 // XFX-Form instructions. Instructions that deal with SPRs.
652 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>,
653 PPC970_DGroup_First, PPC970_Unit_FXU;
654 let Pattern = [(PPCmtctr GPRC:$rS)] in {
655 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>,
656 PPC970_DGroup_First, PPC970_Unit_FXU;
659 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>,
660 PPC970_DGroup_First, PPC970_Unit_FXU;
661 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>,
662 PPC970_DGroup_First, PPC970_Unit_FXU;
664 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
665 // a GPR on the PPC970. As such, copies in and out have the same performance
666 // characteristics as an OR instruction.
667 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS),
668 "mtspr 256, $rS", IntGeneral>,
669 PPC970_DGroup_Single, PPC970_Unit_FXU;
670 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT),
671 "mfspr $rT, 256", IntGeneral>,
672 PPC970_DGroup_First, PPC970_Unit_FXU;
674 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
675 "mtcrf $FXM, $rS", BrMCRX>,
676 PPC970_MicroCode, PPC970_Unit_CRU;
677 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>,
678 PPC970_MicroCode, PPC970_Unit_CRU;
679 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
680 "mfcr $rT, $FXM", SprMFCR>,
681 PPC970_DGroup_First, PPC970_Unit_CRU;
683 let PPC970_Unit = 1 in { // FXU Operations.
685 // XO-Form instructions. Arithmetic instructions that can set overflow bit
687 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
688 "add $rT, $rA, $rB", IntGeneral,
689 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
690 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
691 "addc $rT, $rA, $rB", IntGeneral,
692 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
693 PPC970_DGroup_Cracked;
694 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
695 "adde $rT, $rA, $rB", IntGeneral,
696 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
697 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
698 "divw $rT, $rA, $rB", IntDivW,
699 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
700 PPC970_DGroup_First, PPC970_DGroup_Cracked;
701 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
702 "divwu $rT, $rA, $rB", IntDivW,
703 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
704 PPC970_DGroup_First, PPC970_DGroup_Cracked;
705 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
706 "mulhw $rT, $rA, $rB", IntMulHW,
707 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
708 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
709 "mulhwu $rT, $rA, $rB", IntMulHWU,
710 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
711 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
712 "mullw $rT, $rA, $rB", IntMulHW,
713 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
714 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
715 "subf $rT, $rA, $rB", IntGeneral,
716 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
717 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
718 "subfc $rT, $rA, $rB", IntGeneral,
719 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
720 PPC970_DGroup_Cracked;
721 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
722 "subfe $rT, $rA, $rB", IntGeneral,
723 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
724 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
725 "addme $rT, $rA", IntGeneral,
726 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
727 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
728 "addze $rT, $rA", IntGeneral,
729 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
730 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
731 "neg $rT, $rA", IntGeneral,
732 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
733 def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA),
734 "subfme $rT, $rA", IntGeneral,
735 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
736 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
737 "subfze $rT, $rA", IntGeneral,
738 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
741 // A-Form instructions. Most of the instructions executed in the FPU are of
744 let PPC970_Unit = 3 in { // FPU Operations.
745 def FMADD : AForm_1<63, 29,
746 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
747 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
748 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
750 Requires<[FPContractions]>;
751 def FMADDS : AForm_1<59, 29,
752 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
753 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
754 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
756 Requires<[FPContractions]>;
757 def FMSUB : AForm_1<63, 28,
758 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
759 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
760 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
762 Requires<[FPContractions]>;
763 def FMSUBS : AForm_1<59, 28,
764 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
765 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
766 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
768 Requires<[FPContractions]>;
769 def FNMADD : AForm_1<63, 31,
770 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
771 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
772 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
774 Requires<[FPContractions]>;
775 def FNMADDS : AForm_1<59, 31,
776 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
777 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
778 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
780 Requires<[FPContractions]>;
781 def FNMSUB : AForm_1<63, 30,
782 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
783 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
784 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
786 Requires<[FPContractions]>;
787 def FNMSUBS : AForm_1<59, 30,
788 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
789 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
790 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
792 Requires<[FPContractions]>;
793 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
794 // having 4 of these, force the comparison to always be an 8-byte double (code
795 // should use an FMRSD if the input comparison value really wants to be a float)
796 // and 4/8 byte forms for the result and operand type..
797 def FSELD : AForm_1<63, 23,
798 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
799 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
800 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
801 def FSELS : AForm_1<63, 23,
802 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
803 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
804 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
805 def FADD : AForm_2<63, 21,
806 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
807 "fadd $FRT, $FRA, $FRB", FPGeneral,
808 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
809 def FADDS : AForm_2<59, 21,
810 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
811 "fadds $FRT, $FRA, $FRB", FPGeneral,
812 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
813 def FDIV : AForm_2<63, 18,
814 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
815 "fdiv $FRT, $FRA, $FRB", FPDivD,
816 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
817 def FDIVS : AForm_2<59, 18,
818 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
819 "fdivs $FRT, $FRA, $FRB", FPDivS,
820 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
821 def FMUL : AForm_3<63, 25,
822 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
823 "fmul $FRT, $FRA, $FRB", FPFused,
824 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
825 def FMULS : AForm_3<59, 25,
826 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
827 "fmuls $FRT, $FRA, $FRB", FPGeneral,
828 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
829 def FSUB : AForm_2<63, 20,
830 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
831 "fsub $FRT, $FRA, $FRB", FPGeneral,
832 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
833 def FSUBS : AForm_2<59, 20,
834 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
835 "fsubs $FRT, $FRA, $FRB", FPGeneral,
836 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
839 let PPC970_Unit = 1 in { // FXU Operations.
840 // M-Form instructions. rotate and mask instructions.
842 let isTwoAddress = 1, isCommutable = 1 in {
843 // RLWIMI can be commuted if the rotate amount is zero.
844 def RLWIMI : MForm_2<20,
845 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
846 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
847 []>, PPC970_DGroup_Cracked;
849 def RLWINM : MForm_2<21,
850 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
851 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
853 def RLWINMo : MForm_2<21,
854 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
855 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
856 []>, isDOT, PPC970_DGroup_Cracked;
857 def RLWNM : MForm_2<23,
858 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
859 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
864 //===----------------------------------------------------------------------===//
865 // DWARF Pseudo Instructions
868 def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
869 "; .loc $file, $line, $col",
870 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
873 def DWARF_LABEL : Pseudo<(ops i32imm:$id),
875 [(dwarf_label (i32 imm:$id))]>;
877 //===----------------------------------------------------------------------===//
878 // PowerPC Instruction Patterns
881 // Arbitrary immediate support. Implement in terms of LIS/ORI.
882 def : Pat<(i32 imm:$imm),
883 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
885 // Implement the 'not' operation with the NOR instruction.
886 def NOT : Pat<(not GPRC:$in),
887 (NOR GPRC:$in, GPRC:$in)>;
889 // ADD an arbitrary immediate.
890 def : Pat<(add GPRC:$in, imm:$imm),
891 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
892 // OR an arbitrary immediate.
893 def : Pat<(or GPRC:$in, imm:$imm),
894 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
895 // XOR an arbitrary immediate.
896 def : Pat<(xor GPRC:$in, imm:$imm),
897 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
899 def : Pat<(sub immSExt16:$imm, GPRC:$in),
900 (SUBFIC GPRC:$in, imm:$imm)>;
902 // Return void support.
903 def : Pat<(ret), (BLR)>;
906 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
907 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
908 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
909 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
912 def : Pat<(rotl GPRC:$in, GPRC:$sh),
913 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
914 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
915 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
918 def : Pat<(PPCcall tglobaladdr:$dst),
919 (BL tglobaladdr:$dst)>;
920 def : Pat<(PPCcall texternalsym:$dst),
921 (BL texternalsym:$dst)>;
923 // Hi and Lo for Darwin Global Addresses.
924 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
925 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
926 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
927 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
928 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
929 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
930 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
931 (ADDIS GPRC:$in, tglobaladdr:$g)>;
932 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
933 (ADDIS GPRC:$in, tconstpool:$g)>;
934 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
935 (ADDIS GPRC:$in, tjumptable:$g)>;
937 // Fused negative multiply subtract, alternate pattern
938 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
939 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
940 Requires<[FPContractions]>;
941 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
942 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
943 Requires<[FPContractions]>;
945 // Standard shifts. These are represented separately from the real shifts above
946 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
948 def : Pat<(sra GPRC:$rS, GPRC:$rB),
949 (SRAW GPRC:$rS, GPRC:$rB)>;
950 def : Pat<(srl GPRC:$rS, GPRC:$rB),
951 (SRW GPRC:$rS, GPRC:$rB)>;
952 def : Pat<(shl GPRC:$rS, GPRC:$rB),
953 (SLW GPRC:$rS, GPRC:$rB)>;
955 def : Pat<(zextload iaddr:$src, i1),
957 def : Pat<(zextload xaddr:$src, i1),
959 def : Pat<(extload iaddr:$src, i1),
961 def : Pat<(extload xaddr:$src, i1),
963 def : Pat<(extload iaddr:$src, i8),
965 def : Pat<(extload xaddr:$src, i8),
967 def : Pat<(extload iaddr:$src, i16),
969 def : Pat<(extload xaddr:$src, i16),
971 def : Pat<(extload iaddr:$src, f32),
972 (FMRSD (LFS iaddr:$src))>;
973 def : Pat<(extload xaddr:$src, f32),
974 (FMRSD (LFSX xaddr:$src))>;
976 include "PPCInstrAltivec.td"
977 include "PPCInstr64Bit.td"