1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
60 def tocentry32 : Operand<iPTR> {
61 let MIOperandInfo = (ops i32imm:$imm);
64 //===----------------------------------------------------------------------===//
65 // PowerPC specific DAG Nodes.
68 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
69 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
71 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
72 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
73 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
74 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
75 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
76 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
77 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
78 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
79 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
80 [SDNPHasChain, SDNPMayStore]>;
81 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
82 [SDNPHasChain, SDNPMayLoad]>;
83 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
84 [SDNPHasChain, SDNPMayLoad]>;
86 // Extract FPSCR (not modeled at the DAG level).
87 def PPCmffs : SDNode<"PPCISD::MFFS",
88 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
90 // Perform FADD in round-to-zero mode.
91 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
94 def PPCfsel : SDNode<"PPCISD::FSEL",
95 // Type constraint for fsel.
96 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
97 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
99 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
100 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
101 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
102 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
103 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
105 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
107 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
108 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
110 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
111 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
112 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
113 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
114 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
115 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
117 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
119 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
121 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
122 // amounts. These nodes are generated by the multi-precision shift code.
123 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
124 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
125 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
127 // These are target-independent nodes, but have target-specific formats.
128 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
129 [SDNPHasChain, SDNPOutGlue]>;
130 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
131 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
133 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
134 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
137 def PPCcall_tls : SDNode<"PPCISD::CALL_TLS", SDT_PPCCall,
138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
140 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
141 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
143 def PPCcall_nop_tls : SDNode<"PPCISD::CALL_NOP_TLS", SDT_PPCCall,
144 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
146 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
147 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
148 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
149 [SDNPHasChain, SDNPSideEffect,
150 SDNPInGlue, SDNPOutGlue]>;
151 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
152 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
153 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
154 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
157 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
158 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
160 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
161 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
163 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
164 SDTypeProfile<1, 1, [SDTCisInt<0>,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
168 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
169 [SDNPHasChain, SDNPSideEffect]>;
171 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
172 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
173 [SDNPHasChain, SDNPSideEffect]>;
175 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
176 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
178 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
179 [SDNPHasChain, SDNPOptInGlue]>;
181 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
182 [SDNPHasChain, SDNPMayLoad]>;
183 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
184 [SDNPHasChain, SDNPMayStore]>;
186 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
187 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
188 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
189 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
190 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
192 // Instructions to support atomic operations
193 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
194 [SDNPHasChain, SDNPMayLoad]>;
195 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
196 [SDNPHasChain, SDNPMayStore]>;
198 // Instructions to support medium and large code model
199 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
200 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
201 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
204 // Instructions to support dynamic alloca.
205 def SDTDynOp : SDTypeProfile<1, 2, []>;
206 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
208 //===----------------------------------------------------------------------===//
209 // PowerPC specific transformation functions and pattern fragments.
212 def SHL32 : SDNodeXForm<imm, [{
213 // Transformation function: 31 - imm
214 return getI32Imm(31 - N->getZExtValue());
217 def SRL32 : SDNodeXForm<imm, [{
218 // Transformation function: 32 - imm
219 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
222 def LO16 : SDNodeXForm<imm, [{
223 // Transformation function: get the low 16 bits.
224 return getI32Imm((unsigned short)N->getZExtValue());
227 def HI16 : SDNodeXForm<imm, [{
228 // Transformation function: shift the immediate value down into the low bits.
229 return getI32Imm((unsigned)N->getZExtValue() >> 16);
232 def HA16 : SDNodeXForm<imm, [{
233 // Transformation function: shift the immediate value down into the low bits.
234 signed int Val = N->getZExtValue();
235 return getI32Imm((Val - (signed short)Val) >> 16);
237 def MB : SDNodeXForm<imm, [{
238 // Transformation function: get the start bit of a mask
240 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
241 return getI32Imm(mb);
244 def ME : SDNodeXForm<imm, [{
245 // Transformation function: get the end bit of a mask
247 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
248 return getI32Imm(me);
250 def maskimm32 : PatLeaf<(imm), [{
251 // maskImm predicate - True if immediate is a run of ones.
253 if (N->getValueType(0) == MVT::i32)
254 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
259 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
260 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
261 // sign extended field. Used by instructions like 'addi'.
262 return (int32_t)Imm == (short)Imm;
264 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
265 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
266 // sign extended field. Used by instructions like 'addi'.
267 return (int64_t)Imm == (short)Imm;
269 def immZExt16 : PatLeaf<(imm), [{
270 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
271 // field. Used by instructions like 'ori'.
272 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
275 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
276 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
277 // identical in 32-bit mode, but in 64-bit mode, they return true if the
278 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
280 def imm16ShiftedZExt : PatLeaf<(imm), [{
281 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
282 // immediate are set. Used by instructions like 'xoris'.
283 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
286 def imm16ShiftedSExt : PatLeaf<(imm), [{
287 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
288 // immediate are set. Used by instructions like 'addis'. Identical to
289 // imm16ShiftedZExt in 32-bit mode.
290 if (N->getZExtValue() & 0xFFFF) return false;
291 if (N->getValueType(0) == MVT::i32)
293 // For 64-bit, make sure it is sext right.
294 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
297 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
298 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
299 // zero extended field.
300 return isUInt<32>(Imm);
303 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
304 // restricted memrix (4-aligned) constants are alignment sensitive. If these
305 // offsets are hidden behind TOC entries than the values of the lower-order
306 // bits cannot be checked directly. As a result, we need to also incorporate
307 // an alignment check into the relevant patterns.
309 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
310 return cast<LoadSDNode>(N)->getAlignment() >= 4;
312 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
313 (store node:$val, node:$ptr), [{
314 return cast<StoreSDNode>(N)->getAlignment() >= 4;
316 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
317 return cast<LoadSDNode>(N)->getAlignment() >= 4;
319 def aligned4pre_store : PatFrag<
320 (ops node:$val, node:$base, node:$offset),
321 (pre_store node:$val, node:$base, node:$offset), [{
322 return cast<StoreSDNode>(N)->getAlignment() >= 4;
325 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
326 return cast<LoadSDNode>(N)->getAlignment() < 4;
328 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
329 (store node:$val, node:$ptr), [{
330 return cast<StoreSDNode>(N)->getAlignment() < 4;
332 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
333 return cast<LoadSDNode>(N)->getAlignment() < 4;
336 //===----------------------------------------------------------------------===//
337 // PowerPC Flag Definitions.
339 class isPPC64 { bit PPC64 = 1; }
340 class isDOT { bit RC = 1; }
342 class RegConstraint<string C> {
343 string Constraints = C;
345 class NoEncode<string E> {
346 string DisableEncoding = E;
350 //===----------------------------------------------------------------------===//
351 // PowerPC Operand Definitions.
353 // In the default PowerPC assembler syntax, registers are specified simply
354 // by number, so they cannot be distinguished from immediate values (without
355 // looking at the opcode). This means that the default operand matching logic
356 // for the asm parser does not work, and we need to specify custom matchers.
357 // Since those can only be specified with RegisterOperand classes and not
358 // directly on the RegisterClass, all instructions patterns used by the asm
359 // parser need to use a RegisterOperand (instead of a RegisterClass) for
360 // all their register operands.
361 // For this purpose, we define one RegisterOperand for each RegisterClass,
362 // using the same name as the class, just in lower case.
364 def PPCRegGPRCAsmOperand : AsmOperandClass {
365 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
367 def gprc : RegisterOperand<GPRC> {
368 let ParserMatchClass = PPCRegGPRCAsmOperand;
370 def PPCRegG8RCAsmOperand : AsmOperandClass {
371 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
373 def g8rc : RegisterOperand<G8RC> {
374 let ParserMatchClass = PPCRegG8RCAsmOperand;
376 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
377 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
379 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
380 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
382 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
383 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
385 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
386 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
388 def PPCRegF8RCAsmOperand : AsmOperandClass {
389 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
391 def f8rc : RegisterOperand<F8RC> {
392 let ParserMatchClass = PPCRegF8RCAsmOperand;
394 def PPCRegF4RCAsmOperand : AsmOperandClass {
395 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
397 def f4rc : RegisterOperand<F4RC> {
398 let ParserMatchClass = PPCRegF4RCAsmOperand;
400 def PPCRegVRRCAsmOperand : AsmOperandClass {
401 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
403 def vrrc : RegisterOperand<VRRC> {
404 let ParserMatchClass = PPCRegVRRCAsmOperand;
406 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
407 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
409 def crbitrc : RegisterOperand<CRBITRC> {
410 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
412 def PPCRegCRRCAsmOperand : AsmOperandClass {
413 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
415 def crrc : RegisterOperand<CRRC> {
416 let ParserMatchClass = PPCRegCRRCAsmOperand;
419 def PPCU2ImmAsmOperand : AsmOperandClass {
420 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
421 let RenderMethod = "addImmOperands";
423 def u2imm : Operand<i32> {
424 let PrintMethod = "printU2ImmOperand";
425 let ParserMatchClass = PPCU2ImmAsmOperand;
428 def PPCU4ImmAsmOperand : AsmOperandClass {
429 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
430 let RenderMethod = "addImmOperands";
432 def u4imm : Operand<i32> {
433 let PrintMethod = "printU4ImmOperand";
434 let ParserMatchClass = PPCU4ImmAsmOperand;
436 def PPCS5ImmAsmOperand : AsmOperandClass {
437 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
438 let RenderMethod = "addImmOperands";
440 def s5imm : Operand<i32> {
441 let PrintMethod = "printS5ImmOperand";
442 let ParserMatchClass = PPCS5ImmAsmOperand;
443 let DecoderMethod = "decodeSImmOperand<5>";
445 def PPCU5ImmAsmOperand : AsmOperandClass {
446 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
447 let RenderMethod = "addImmOperands";
449 def u5imm : Operand<i32> {
450 let PrintMethod = "printU5ImmOperand";
451 let ParserMatchClass = PPCU5ImmAsmOperand;
452 let DecoderMethod = "decodeUImmOperand<5>";
454 def PPCU6ImmAsmOperand : AsmOperandClass {
455 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
456 let RenderMethod = "addImmOperands";
458 def u6imm : Operand<i32> {
459 let PrintMethod = "printU6ImmOperand";
460 let ParserMatchClass = PPCU6ImmAsmOperand;
461 let DecoderMethod = "decodeUImmOperand<6>";
463 def PPCS16ImmAsmOperand : AsmOperandClass {
464 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
465 let RenderMethod = "addS16ImmOperands";
467 def s16imm : Operand<i32> {
468 let PrintMethod = "printS16ImmOperand";
469 let EncoderMethod = "getImm16Encoding";
470 let ParserMatchClass = PPCS16ImmAsmOperand;
471 let DecoderMethod = "decodeSImmOperand<16>";
473 def PPCU16ImmAsmOperand : AsmOperandClass {
474 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
475 let RenderMethod = "addU16ImmOperands";
477 def u16imm : Operand<i32> {
478 let PrintMethod = "printU16ImmOperand";
479 let EncoderMethod = "getImm16Encoding";
480 let ParserMatchClass = PPCU16ImmAsmOperand;
481 let DecoderMethod = "decodeUImmOperand<16>";
483 def PPCS17ImmAsmOperand : AsmOperandClass {
484 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
485 let RenderMethod = "addS16ImmOperands";
487 def s17imm : Operand<i32> {
488 // This operand type is used for addis/lis to allow the assembler parser
489 // to accept immediates in the range -65536..65535 for compatibility with
490 // the GNU assembler. The operand is treated as 16-bit otherwise.
491 let PrintMethod = "printS16ImmOperand";
492 let EncoderMethod = "getImm16Encoding";
493 let ParserMatchClass = PPCS17ImmAsmOperand;
494 let DecoderMethod = "decodeSImmOperand<16>";
496 def PPCDirectBrAsmOperand : AsmOperandClass {
497 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
498 let RenderMethod = "addBranchTargetOperands";
500 def directbrtarget : Operand<OtherVT> {
501 let PrintMethod = "printBranchOperand";
502 let EncoderMethod = "getDirectBrEncoding";
503 let ParserMatchClass = PPCDirectBrAsmOperand;
505 def absdirectbrtarget : Operand<OtherVT> {
506 let PrintMethod = "printAbsBranchOperand";
507 let EncoderMethod = "getAbsDirectBrEncoding";
508 let ParserMatchClass = PPCDirectBrAsmOperand;
510 def PPCCondBrAsmOperand : AsmOperandClass {
511 let Name = "CondBr"; let PredicateMethod = "isCondBr";
512 let RenderMethod = "addBranchTargetOperands";
514 def condbrtarget : Operand<OtherVT> {
515 let PrintMethod = "printBranchOperand";
516 let EncoderMethod = "getCondBrEncoding";
517 let ParserMatchClass = PPCCondBrAsmOperand;
519 def abscondbrtarget : Operand<OtherVT> {
520 let PrintMethod = "printAbsBranchOperand";
521 let EncoderMethod = "getAbsCondBrEncoding";
522 let ParserMatchClass = PPCCondBrAsmOperand;
524 def calltarget : Operand<iPTR> {
525 let PrintMethod = "printBranchOperand";
526 let EncoderMethod = "getDirectBrEncoding";
527 let ParserMatchClass = PPCDirectBrAsmOperand;
529 def abscalltarget : Operand<iPTR> {
530 let PrintMethod = "printAbsBranchOperand";
531 let EncoderMethod = "getAbsDirectBrEncoding";
532 let ParserMatchClass = PPCDirectBrAsmOperand;
534 def PPCCRBitMaskOperand : AsmOperandClass {
535 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
537 def crbitm: Operand<i8> {
538 let PrintMethod = "printcrbitm";
539 let EncoderMethod = "get_crbitm_encoding";
540 let DecoderMethod = "decodeCRBitMOperand";
541 let ParserMatchClass = PPCCRBitMaskOperand;
544 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
545 def PPCRegGxRCNoR0Operand : AsmOperandClass {
546 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
548 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
549 let ParserMatchClass = PPCRegGxRCNoR0Operand;
551 // A version of ptr_rc usable with the asm parser.
552 def PPCRegGxRCOperand : AsmOperandClass {
553 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
555 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
556 let ParserMatchClass = PPCRegGxRCOperand;
559 def PPCDispRIOperand : AsmOperandClass {
560 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
561 let RenderMethod = "addS16ImmOperands";
563 def dispRI : Operand<iPTR> {
564 let ParserMatchClass = PPCDispRIOperand;
566 def PPCDispRIXOperand : AsmOperandClass {
567 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
568 let RenderMethod = "addImmOperands";
570 def dispRIX : Operand<iPTR> {
571 let ParserMatchClass = PPCDispRIXOperand;
573 def PPCDispSPE8Operand : AsmOperandClass {
574 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
575 let RenderMethod = "addImmOperands";
577 def dispSPE8 : Operand<iPTR> {
578 let ParserMatchClass = PPCDispSPE8Operand;
580 def PPCDispSPE4Operand : AsmOperandClass {
581 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
582 let RenderMethod = "addImmOperands";
584 def dispSPE4 : Operand<iPTR> {
585 let ParserMatchClass = PPCDispSPE4Operand;
587 def PPCDispSPE2Operand : AsmOperandClass {
588 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
589 let RenderMethod = "addImmOperands";
591 def dispSPE2 : Operand<iPTR> {
592 let ParserMatchClass = PPCDispSPE2Operand;
595 def memri : Operand<iPTR> {
596 let PrintMethod = "printMemRegImm";
597 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
598 let EncoderMethod = "getMemRIEncoding";
599 let DecoderMethod = "decodeMemRIOperands";
601 def memrr : Operand<iPTR> {
602 let PrintMethod = "printMemRegReg";
603 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
605 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
606 let PrintMethod = "printMemRegImm";
607 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
608 let EncoderMethod = "getMemRIXEncoding";
609 let DecoderMethod = "decodeMemRIXOperands";
611 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
612 let PrintMethod = "printMemRegImm";
613 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
614 let EncoderMethod = "getSPE8DisEncoding";
616 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
617 let PrintMethod = "printMemRegImm";
618 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
619 let EncoderMethod = "getSPE4DisEncoding";
621 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
622 let PrintMethod = "printMemRegImm";
623 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
624 let EncoderMethod = "getSPE2DisEncoding";
627 // A single-register address. This is used with the SjLj
628 // pseudo-instructions.
629 def memr : Operand<iPTR> {
630 let MIOperandInfo = (ops ptr_rc:$ptrreg);
632 def PPCTLSRegOperand : AsmOperandClass {
633 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
634 let RenderMethod = "addTLSRegOperands";
636 def tlsreg32 : Operand<i32> {
637 let EncoderMethod = "getTLSRegEncoding";
638 let ParserMatchClass = PPCTLSRegOperand;
640 def tlsgd32 : Operand<i32> {}
641 def tlscall32 : Operand<i32> {
642 let PrintMethod = "printTLSCall";
643 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
644 let EncoderMethod = "getTLSCallEncoding";
647 // PowerPC Predicate operand.
648 def pred : Operand<OtherVT> {
649 let PrintMethod = "printPredicateOperand";
650 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
653 // Define PowerPC specific addressing mode.
654 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
655 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
656 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
657 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
659 // The address in a single register. This is used with the SjLj
660 // pseudo-instructions.
661 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
663 /// This is just the offset part of iaddr, used for preinc.
664 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
666 //===----------------------------------------------------------------------===//
667 // PowerPC Instruction Predicate Definitions.
668 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
669 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
670 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
671 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
672 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
673 def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
674 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
675 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
676 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
677 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
679 //===----------------------------------------------------------------------===//
680 // PowerPC Multiclass Definitions.
682 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
683 string asmbase, string asmstr, InstrItinClass itin,
685 let BaseName = asmbase in {
686 def NAME : XForm_6<opcode, xo, OOL, IOL,
687 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
688 pattern>, RecFormRel;
690 def o : XForm_6<opcode, xo, OOL, IOL,
691 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
692 []>, isDOT, RecFormRel;
696 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
697 string asmbase, string asmstr, InstrItinClass itin,
699 let BaseName = asmbase in {
700 let Defs = [CARRY] in
701 def NAME : XForm_6<opcode, xo, OOL, IOL,
702 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
703 pattern>, RecFormRel;
704 let Defs = [CARRY, CR0] in
705 def o : XForm_6<opcode, xo, OOL, IOL,
706 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
707 []>, isDOT, RecFormRel;
711 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
712 string asmbase, string asmstr, InstrItinClass itin,
714 let BaseName = asmbase in {
715 let Defs = [CARRY] in
716 def NAME : XForm_10<opcode, xo, OOL, IOL,
717 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
718 pattern>, RecFormRel;
719 let Defs = [CARRY, CR0] in
720 def o : XForm_10<opcode, xo, OOL, IOL,
721 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
722 []>, isDOT, RecFormRel;
726 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
727 string asmbase, string asmstr, InstrItinClass itin,
729 let BaseName = asmbase in {
730 def NAME : XForm_11<opcode, xo, OOL, IOL,
731 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
732 pattern>, RecFormRel;
734 def o : XForm_11<opcode, xo, OOL, IOL,
735 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
736 []>, isDOT, RecFormRel;
740 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
741 string asmbase, string asmstr, InstrItinClass itin,
743 let BaseName = asmbase in {
744 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
745 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
746 pattern>, RecFormRel;
748 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
749 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
750 []>, isDOT, RecFormRel;
754 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
755 string asmbase, string asmstr, InstrItinClass itin,
757 let BaseName = asmbase in {
758 let Defs = [CARRY] in
759 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
760 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
761 pattern>, RecFormRel;
762 let Defs = [CARRY, CR0] in
763 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
764 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
765 []>, isDOT, RecFormRel;
769 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
770 string asmbase, string asmstr, InstrItinClass itin,
772 let BaseName = asmbase in {
773 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
774 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
775 pattern>, RecFormRel;
777 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
778 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
779 []>, isDOT, RecFormRel;
783 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
784 string asmbase, string asmstr, InstrItinClass itin,
786 let BaseName = asmbase in {
787 let Defs = [CARRY] in
788 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
789 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
790 pattern>, RecFormRel;
791 let Defs = [CARRY, CR0] in
792 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
793 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
794 []>, isDOT, RecFormRel;
798 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
799 string asmbase, string asmstr, InstrItinClass itin,
801 let BaseName = asmbase in {
802 def NAME : MForm_2<opcode, OOL, IOL,
803 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
804 pattern>, RecFormRel;
806 def o : MForm_2<opcode, OOL, IOL,
807 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
808 []>, isDOT, RecFormRel;
812 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
813 string asmbase, string asmstr, InstrItinClass itin,
815 let BaseName = asmbase in {
816 def NAME : MDForm_1<opcode, xo, OOL, IOL,
817 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
818 pattern>, RecFormRel;
820 def o : MDForm_1<opcode, xo, OOL, IOL,
821 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
822 []>, isDOT, RecFormRel;
826 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
827 string asmbase, string asmstr, InstrItinClass itin,
829 let BaseName = asmbase in {
830 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
831 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
832 pattern>, RecFormRel;
834 def o : MDSForm_1<opcode, xo, OOL, IOL,
835 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
836 []>, isDOT, RecFormRel;
840 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
841 string asmbase, string asmstr, InstrItinClass itin,
843 let BaseName = asmbase in {
844 let Defs = [CARRY] in
845 def NAME : XSForm_1<opcode, xo, OOL, IOL,
846 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
847 pattern>, RecFormRel;
848 let Defs = [CARRY, CR0] in
849 def o : XSForm_1<opcode, xo, OOL, IOL,
850 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
851 []>, isDOT, RecFormRel;
855 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
856 string asmbase, string asmstr, InstrItinClass itin,
858 let BaseName = asmbase in {
859 def NAME : XForm_26<opcode, xo, OOL, IOL,
860 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
861 pattern>, RecFormRel;
863 def o : XForm_26<opcode, xo, OOL, IOL,
864 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
865 []>, isDOT, RecFormRel;
869 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
870 string asmbase, string asmstr, InstrItinClass itin,
872 let BaseName = asmbase in {
873 def NAME : XForm_28<opcode, xo, OOL, IOL,
874 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
875 pattern>, RecFormRel;
877 def o : XForm_28<opcode, xo, OOL, IOL,
878 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
879 []>, isDOT, RecFormRel;
883 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
884 string asmbase, string asmstr, InstrItinClass itin,
886 let BaseName = asmbase in {
887 def NAME : AForm_1<opcode, xo, OOL, IOL,
888 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
889 pattern>, RecFormRel;
891 def o : AForm_1<opcode, xo, OOL, IOL,
892 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
893 []>, isDOT, RecFormRel;
897 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
898 string asmbase, string asmstr, InstrItinClass itin,
900 let BaseName = asmbase in {
901 def NAME : AForm_2<opcode, xo, OOL, IOL,
902 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
903 pattern>, RecFormRel;
905 def o : AForm_2<opcode, xo, OOL, IOL,
906 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
907 []>, isDOT, RecFormRel;
911 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
912 string asmbase, string asmstr, InstrItinClass itin,
914 let BaseName = asmbase in {
915 def NAME : AForm_3<opcode, xo, OOL, IOL,
916 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
917 pattern>, RecFormRel;
919 def o : AForm_3<opcode, xo, OOL, IOL,
920 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
921 []>, isDOT, RecFormRel;
925 //===----------------------------------------------------------------------===//
926 // PowerPC Instruction Definitions.
928 // Pseudo-instructions:
930 let hasCtrlDep = 1 in {
931 let Defs = [R1], Uses = [R1] in {
932 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
933 [(callseq_start timm:$amt)]>;
934 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
935 [(callseq_end timm:$amt1, timm:$amt2)]>;
938 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
939 "UPDATE_VRSAVE $rD, $rS", []>;
942 let Defs = [R1], Uses = [R1] in
943 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
945 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
947 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
948 // instruction selection into a branch sequence.
949 let usesCustomInserter = 1, // Expanded after instruction selection.
950 PPC970_Single = 1 in {
951 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
952 // because either operand might become the first operand in an isel, and
953 // that operand cannot be r0.
954 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
955 gprc_nor0:$T, gprc_nor0:$F,
956 i32imm:$BROPC), "#SELECT_CC_I4",
958 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
959 g8rc_nox0:$T, g8rc_nox0:$F,
960 i32imm:$BROPC), "#SELECT_CC_I8",
962 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
963 i32imm:$BROPC), "#SELECT_CC_F4",
965 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
966 i32imm:$BROPC), "#SELECT_CC_F8",
968 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
969 i32imm:$BROPC), "#SELECT_CC_VRRC",
972 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
973 // register bit directly.
974 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
975 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
976 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
977 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
978 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
979 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
980 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
981 f4rc:$T, f4rc:$F), "#SELECT_F4",
982 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
983 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
984 f8rc:$T, f8rc:$F), "#SELECT_F8",
985 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
986 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
987 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
989 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
992 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
993 // scavenge a register for it.
994 let mayStore = 1 in {
995 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
997 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1001 // RESTORE_CR - Indicate that we're restoring the CR register (previously
1002 // spilled), so we'll need to scavenge a register for it.
1003 let mayLoad = 1 in {
1004 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1006 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1007 "#RESTORE_CRBIT", []>;
1010 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1011 let isReturn = 1, Uses = [LR, RM] in
1012 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1014 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1015 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1018 let isCodeGenOnly = 1 in {
1019 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1020 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1023 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1024 "bcctr 12, $bi, 0", IIC_BrB, []>;
1025 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1026 "bcctr 4, $bi, 0", IIC_BrB, []>;
1032 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1035 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1036 let isBarrier = 1 in {
1037 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1040 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1041 "ba $dst", IIC_BrB, []>;
1044 // BCC represents an arbitrary conditional branch on a predicate.
1045 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1046 // a two-value operand where a dag node expects two operands. :(
1047 let isCodeGenOnly = 1 in {
1048 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1049 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1050 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1051 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1052 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1054 let isReturn = 1, Uses = [LR, RM] in
1055 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1056 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1059 let isCodeGenOnly = 1 in {
1060 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1061 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1062 "bc 12, $bi, $dst">;
1064 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1065 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1068 let isReturn = 1, Uses = [LR, RM] in
1069 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1070 "bclr 12, $bi, 0", IIC_BrB, []>;
1071 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1072 "bclr 4, $bi, 0", IIC_BrB, []>;
1075 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1076 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1077 "bdzlr", IIC_BrB, []>;
1078 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1079 "bdnzlr", IIC_BrB, []>;
1080 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1081 "bdzlr+", IIC_BrB, []>;
1082 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1083 "bdnzlr+", IIC_BrB, []>;
1084 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1085 "bdzlr-", IIC_BrB, []>;
1086 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1087 "bdnzlr-", IIC_BrB, []>;
1090 let Defs = [CTR], Uses = [CTR] in {
1091 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1093 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1095 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1097 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1099 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1101 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1103 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1105 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1107 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1109 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1111 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1113 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1118 // The unconditional BCL used by the SjLj setjmp code.
1119 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1120 let Defs = [LR], Uses = [RM] in {
1121 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1122 "bcl 20, 31, $dst">;
1126 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1127 // Convenient aliases for call instructions
1128 let Uses = [RM] in {
1129 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1130 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1131 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1132 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1134 let isCodeGenOnly = 1 in {
1135 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1136 "bl $func", IIC_BrB, []>;
1137 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1138 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1139 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1140 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1142 def BCL : BForm_4<16, 12, 0, 1, (outs),
1143 (ins crbitrc:$bi, condbrtarget:$dst),
1144 "bcl 12, $bi, $dst">;
1145 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1146 (ins crbitrc:$bi, condbrtarget:$dst),
1147 "bcl 4, $bi, $dst">;
1150 let Uses = [CTR, RM] in {
1151 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1152 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1153 Requires<[In32BitMode]>;
1155 let isCodeGenOnly = 1 in {
1156 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1157 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1160 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1161 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1162 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1163 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1166 let Uses = [LR, RM] in {
1167 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1168 "blrl", IIC_BrB, []>;
1170 let isCodeGenOnly = 1 in {
1171 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1172 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1175 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1176 "bclrl 12, $bi, 0", IIC_BrB, []>;
1177 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1178 "bclrl 4, $bi, 0", IIC_BrB, []>;
1181 let Defs = [CTR], Uses = [CTR, RM] in {
1182 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1184 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1186 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1188 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1190 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1192 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1194 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1196 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1198 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1200 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1202 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1204 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1207 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1208 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1209 "bdzlrl", IIC_BrB, []>;
1210 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1211 "bdnzlrl", IIC_BrB, []>;
1212 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1213 "bdzlrl+", IIC_BrB, []>;
1214 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1215 "bdnzlrl+", IIC_BrB, []>;
1216 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1217 "bdzlrl-", IIC_BrB, []>;
1218 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1219 "bdnzlrl-", IIC_BrB, []>;
1223 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1224 def TCRETURNdi :Pseudo< (outs),
1225 (ins calltarget:$dst, i32imm:$offset),
1226 "#TC_RETURNd $dst $offset",
1230 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1231 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1232 "#TC_RETURNa $func $offset",
1233 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1235 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1236 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1237 "#TC_RETURNr $dst $offset",
1241 let isCodeGenOnly = 1 in {
1243 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1244 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1245 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1246 []>, Requires<[In32BitMode]>;
1248 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1249 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1250 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1254 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1255 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1256 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1262 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1264 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1265 "#EH_SJLJ_SETJMP32",
1266 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1267 Requires<[In32BitMode]>;
1268 let isTerminator = 1 in
1269 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1270 "#EH_SJLJ_LONGJMP32",
1271 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1272 Requires<[In32BitMode]>;
1275 let isBranch = 1, isTerminator = 1 in {
1276 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1277 "#EH_SjLj_Setup\t$dst", []>;
1281 let PPC970_Unit = 7 in {
1282 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1283 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1286 // DCB* instructions.
1287 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1288 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1289 PPC970_DGroup_Single;
1290 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1291 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1292 PPC970_DGroup_Single;
1293 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1294 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1295 PPC970_DGroup_Single;
1296 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1297 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1298 PPC970_DGroup_Single;
1299 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1300 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1301 PPC970_DGroup_Single;
1302 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1303 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1304 PPC970_DGroup_Single;
1305 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1306 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1307 PPC970_DGroup_Single;
1308 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1309 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1310 PPC970_DGroup_Single;
1312 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1313 "icbt $CT, $src", IIC_LdStLoad>, Requires<[IsBookE]>;
1315 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1316 (DCBT xoaddr:$dst)>; // data prefetch for loads
1317 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1318 (DCBTST xoaddr:$dst)>; // data prefetch for stores
1319 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1320 (ICBT 0, xoaddr:$dst)>; // inst prefetch (for read)
1322 // Atomic operations
1323 let usesCustomInserter = 1 in {
1324 let Defs = [CR0] in {
1325 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1326 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1327 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1328 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1329 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1330 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1331 def ATOMIC_LOAD_AND_I8 : Pseudo<
1332 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1333 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1334 def ATOMIC_LOAD_OR_I8 : Pseudo<
1335 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1336 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1337 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1338 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1339 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1340 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1341 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1342 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1343 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1344 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1345 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1346 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1347 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1348 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1349 def ATOMIC_LOAD_AND_I16 : Pseudo<
1350 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1351 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1352 def ATOMIC_LOAD_OR_I16 : Pseudo<
1353 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1354 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1355 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1356 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1357 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1358 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1359 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1360 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1361 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1362 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1363 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1364 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1365 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1366 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1367 def ATOMIC_LOAD_AND_I32 : Pseudo<
1368 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1369 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1370 def ATOMIC_LOAD_OR_I32 : Pseudo<
1371 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1372 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1373 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1374 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1375 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1376 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1377 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1378 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1380 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1381 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1382 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1383 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1384 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1385 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1386 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1387 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1388 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1390 def ATOMIC_SWAP_I8 : Pseudo<
1391 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1392 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1393 def ATOMIC_SWAP_I16 : Pseudo<
1394 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1395 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1396 def ATOMIC_SWAP_I32 : Pseudo<
1397 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1398 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1402 // Instructions to support atomic operations
1403 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1404 "lwarx $rD, $src", IIC_LdStLWARX,
1405 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1408 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1409 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1410 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1413 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1414 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1416 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1417 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1418 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1419 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1420 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1421 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1422 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1423 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1425 //===----------------------------------------------------------------------===//
1426 // PPC32 Load Instructions.
1429 // Unindexed (r+i) Loads.
1430 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1431 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1432 "lbz $rD, $src", IIC_LdStLoad,
1433 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1434 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1435 "lha $rD, $src", IIC_LdStLHA,
1436 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1437 PPC970_DGroup_Cracked;
1438 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1439 "lhz $rD, $src", IIC_LdStLoad,
1440 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1441 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1442 "lwz $rD, $src", IIC_LdStLoad,
1443 [(set i32:$rD, (load iaddr:$src))]>;
1445 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1446 "lfs $rD, $src", IIC_LdStLFD,
1447 [(set f32:$rD, (load iaddr:$src))]>;
1448 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1449 "lfd $rD, $src", IIC_LdStLFD,
1450 [(set f64:$rD, (load iaddr:$src))]>;
1453 // Unindexed (r+i) Loads with Update (preinc).
1454 let mayLoad = 1, neverHasSideEffects = 1 in {
1455 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1456 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1457 []>, RegConstraint<"$addr.reg = $ea_result">,
1458 NoEncode<"$ea_result">;
1460 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1461 "lhau $rD, $addr", IIC_LdStLHAU,
1462 []>, RegConstraint<"$addr.reg = $ea_result">,
1463 NoEncode<"$ea_result">;
1465 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1466 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1467 []>, RegConstraint<"$addr.reg = $ea_result">,
1468 NoEncode<"$ea_result">;
1470 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1471 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1472 []>, RegConstraint<"$addr.reg = $ea_result">,
1473 NoEncode<"$ea_result">;
1475 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1476 "lfsu $rD, $addr", IIC_LdStLFDU,
1477 []>, RegConstraint<"$addr.reg = $ea_result">,
1478 NoEncode<"$ea_result">;
1480 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1481 "lfdu $rD, $addr", IIC_LdStLFDU,
1482 []>, RegConstraint<"$addr.reg = $ea_result">,
1483 NoEncode<"$ea_result">;
1486 // Indexed (r+r) Loads with Update (preinc).
1487 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1489 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1490 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1491 NoEncode<"$ea_result">;
1493 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1495 "lhaux $rD, $addr", IIC_LdStLHAUX,
1496 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1497 NoEncode<"$ea_result">;
1499 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1501 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1502 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1503 NoEncode<"$ea_result">;
1505 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1507 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1508 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1509 NoEncode<"$ea_result">;
1511 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1513 "lfsux $rD, $addr", IIC_LdStLFDUX,
1514 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1515 NoEncode<"$ea_result">;
1517 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1519 "lfdux $rD, $addr", IIC_LdStLFDUX,
1520 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1521 NoEncode<"$ea_result">;
1525 // Indexed (r+r) Loads.
1527 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1528 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1529 "lbzx $rD, $src", IIC_LdStLoad,
1530 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1531 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1532 "lhax $rD, $src", IIC_LdStLHA,
1533 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1534 PPC970_DGroup_Cracked;
1535 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1536 "lhzx $rD, $src", IIC_LdStLoad,
1537 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1538 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1539 "lwzx $rD, $src", IIC_LdStLoad,
1540 [(set i32:$rD, (load xaddr:$src))]>;
1543 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1544 "lhbrx $rD, $src", IIC_LdStLoad,
1545 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1546 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1547 "lwbrx $rD, $src", IIC_LdStLoad,
1548 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1550 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1551 "lfsx $frD, $src", IIC_LdStLFD,
1552 [(set f32:$frD, (load xaddr:$src))]>;
1553 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1554 "lfdx $frD, $src", IIC_LdStLFD,
1555 [(set f64:$frD, (load xaddr:$src))]>;
1557 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1558 "lfiwax $frD, $src", IIC_LdStLFD,
1559 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1560 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1561 "lfiwzx $frD, $src", IIC_LdStLFD,
1562 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1566 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1567 "lmw $rD, $src", IIC_LdStLMW, []>;
1569 //===----------------------------------------------------------------------===//
1570 // PPC32 Store Instructions.
1573 // Unindexed (r+i) Stores.
1574 let PPC970_Unit = 2 in {
1575 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1576 "stb $rS, $src", IIC_LdStStore,
1577 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1578 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1579 "sth $rS, $src", IIC_LdStStore,
1580 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1581 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1582 "stw $rS, $src", IIC_LdStStore,
1583 [(store i32:$rS, iaddr:$src)]>;
1584 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1585 "stfs $rS, $dst", IIC_LdStSTFD,
1586 [(store f32:$rS, iaddr:$dst)]>;
1587 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1588 "stfd $rS, $dst", IIC_LdStSTFD,
1589 [(store f64:$rS, iaddr:$dst)]>;
1592 // Unindexed (r+i) Stores with Update (preinc).
1593 let PPC970_Unit = 2, mayStore = 1 in {
1594 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1595 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1596 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1597 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1598 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1599 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1600 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1601 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1602 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1603 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1604 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1605 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1606 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1607 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1608 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1611 // Patterns to match the pre-inc stores. We can't put the patterns on
1612 // the instruction definitions directly as ISel wants the address base
1613 // and offset to be separate operands, not a single complex operand.
1614 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1615 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1616 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1617 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1618 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1619 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1620 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1621 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1622 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1623 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1625 // Indexed (r+r) Stores.
1626 let PPC970_Unit = 2 in {
1627 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1628 "stbx $rS, $dst", IIC_LdStStore,
1629 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1630 PPC970_DGroup_Cracked;
1631 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1632 "sthx $rS, $dst", IIC_LdStStore,
1633 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1634 PPC970_DGroup_Cracked;
1635 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1636 "stwx $rS, $dst", IIC_LdStStore,
1637 [(store i32:$rS, xaddr:$dst)]>,
1638 PPC970_DGroup_Cracked;
1640 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1641 "sthbrx $rS, $dst", IIC_LdStStore,
1642 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1643 PPC970_DGroup_Cracked;
1644 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1645 "stwbrx $rS, $dst", IIC_LdStStore,
1646 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1647 PPC970_DGroup_Cracked;
1649 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1650 "stfiwx $frS, $dst", IIC_LdStSTFD,
1651 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1653 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1654 "stfsx $frS, $dst", IIC_LdStSTFD,
1655 [(store f32:$frS, xaddr:$dst)]>;
1656 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1657 "stfdx $frS, $dst", IIC_LdStSTFD,
1658 [(store f64:$frS, xaddr:$dst)]>;
1661 // Indexed (r+r) Stores with Update (preinc).
1662 let PPC970_Unit = 2, mayStore = 1 in {
1663 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1664 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1665 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1666 PPC970_DGroup_Cracked;
1667 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1668 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1669 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1670 PPC970_DGroup_Cracked;
1671 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1672 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1673 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1674 PPC970_DGroup_Cracked;
1675 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1676 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1677 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1678 PPC970_DGroup_Cracked;
1679 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1680 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1681 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1682 PPC970_DGroup_Cracked;
1685 // Patterns to match the pre-inc stores. We can't put the patterns on
1686 // the instruction definitions directly as ISel wants the address base
1687 // and offset to be separate operands, not a single complex operand.
1688 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1689 (STBUX $rS, $ptrreg, $ptroff)>;
1690 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1691 (STHUX $rS, $ptrreg, $ptroff)>;
1692 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1693 (STWUX $rS, $ptrreg, $ptroff)>;
1694 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1695 (STFSUX $rS, $ptrreg, $ptroff)>;
1696 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1697 (STFDUX $rS, $ptrreg, $ptroff)>;
1700 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1701 "stmw $rS, $dst", IIC_LdStLMW, []>;
1703 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1704 "sync $L", IIC_LdStSync, []>;
1706 let isCodeGenOnly = 1 in {
1707 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1708 "msync", IIC_LdStSync, []> {
1713 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>;
1714 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1715 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1716 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1718 //===----------------------------------------------------------------------===//
1719 // PPC32 Arithmetic Instructions.
1722 let PPC970_Unit = 1 in { // FXU Operations.
1723 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1724 "addi $rD, $rA, $imm", IIC_IntSimple,
1725 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1726 let BaseName = "addic" in {
1727 let Defs = [CARRY] in
1728 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1729 "addic $rD, $rA, $imm", IIC_IntGeneral,
1730 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1731 RecFormRel, PPC970_DGroup_Cracked;
1732 let Defs = [CARRY, CR0] in
1733 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1734 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1735 []>, isDOT, RecFormRel;
1737 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1738 "addis $rD, $rA, $imm", IIC_IntSimple,
1739 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1740 let isCodeGenOnly = 1 in
1741 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1742 "la $rD, $sym($rA)", IIC_IntGeneral,
1743 [(set i32:$rD, (add i32:$rA,
1744 (PPClo tglobaladdr:$sym, 0)))]>;
1745 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1746 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1747 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1748 let Defs = [CARRY] in
1749 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1750 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1751 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1753 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1754 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1755 "li $rD, $imm", IIC_IntSimple,
1756 [(set i32:$rD, imm32SExt16:$imm)]>;
1757 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1758 "lis $rD, $imm", IIC_IntSimple,
1759 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1763 let PPC970_Unit = 1 in { // FXU Operations.
1764 let Defs = [CR0] in {
1765 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1766 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1767 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1769 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1770 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1771 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1774 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1775 "ori $dst, $src1, $src2", IIC_IntSimple,
1776 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1777 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1778 "oris $dst, $src1, $src2", IIC_IntSimple,
1779 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1780 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1781 "xori $dst, $src1, $src2", IIC_IntSimple,
1782 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1783 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1784 "xoris $dst, $src1, $src2", IIC_IntSimple,
1785 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1787 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1789 let isCodeGenOnly = 1 in {
1790 // The POWER6 and POWER7 have special group-terminating nops.
1791 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1792 "ori 1, 1, 0", IIC_IntSimple, []>;
1793 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1794 "ori 2, 2, 0", IIC_IntSimple, []>;
1797 let isCompare = 1, neverHasSideEffects = 1 in {
1798 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1799 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1800 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1801 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1805 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1806 let isCommutable = 1 in {
1807 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1808 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1809 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1810 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1811 "and", "$rA, $rS, $rB", IIC_IntSimple,
1812 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1814 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1815 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1816 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1817 let isCommutable = 1 in {
1818 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1819 "or", "$rA, $rS, $rB", IIC_IntSimple,
1820 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1821 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1822 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1823 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1825 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1826 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1827 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1828 let isCommutable = 1 in {
1829 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1830 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1831 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1832 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1833 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1834 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1836 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1837 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1838 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1839 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1840 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1841 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1842 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1843 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1844 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1847 let PPC970_Unit = 1 in { // FXU Operations.
1848 let neverHasSideEffects = 1 in {
1849 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1850 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1851 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1852 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1853 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1854 [(set i32:$rA, (ctlz i32:$rS))]>;
1855 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1856 "extsb", "$rA, $rS", IIC_IntSimple,
1857 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1858 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1859 "extsh", "$rA, $rS", IIC_IntSimple,
1860 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1862 let isCompare = 1, neverHasSideEffects = 1 in {
1863 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1864 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1865 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1866 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1869 let PPC970_Unit = 3 in { // FPU Operations.
1870 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1871 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1872 let isCompare = 1, neverHasSideEffects = 1 in {
1873 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1874 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1875 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1876 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1877 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1880 let Uses = [RM] in {
1881 let neverHasSideEffects = 1 in {
1882 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1883 "fctiw", "$frD, $frB", IIC_FPGeneral,
1885 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1886 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1887 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1889 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1890 "frsp", "$frD, $frB", IIC_FPGeneral,
1891 [(set f32:$frD, (fround f64:$frB))]>;
1893 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1894 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1895 "frin", "$frD, $frB", IIC_FPGeneral,
1896 [(set f64:$frD, (frnd f64:$frB))]>;
1897 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1898 "frin", "$frD, $frB", IIC_FPGeneral,
1899 [(set f32:$frD, (frnd f32:$frB))]>;
1902 let neverHasSideEffects = 1 in {
1903 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1904 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1905 "frip", "$frD, $frB", IIC_FPGeneral,
1906 [(set f64:$frD, (fceil f64:$frB))]>;
1907 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1908 "frip", "$frD, $frB", IIC_FPGeneral,
1909 [(set f32:$frD, (fceil f32:$frB))]>;
1910 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1911 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1912 "friz", "$frD, $frB", IIC_FPGeneral,
1913 [(set f64:$frD, (ftrunc f64:$frB))]>;
1914 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1915 "friz", "$frD, $frB", IIC_FPGeneral,
1916 [(set f32:$frD, (ftrunc f32:$frB))]>;
1917 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1918 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1919 "frim", "$frD, $frB", IIC_FPGeneral,
1920 [(set f64:$frD, (ffloor f64:$frB))]>;
1921 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1922 "frim", "$frD, $frB", IIC_FPGeneral,
1923 [(set f32:$frD, (ffloor f32:$frB))]>;
1925 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1926 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1927 [(set f64:$frD, (fsqrt f64:$frB))]>;
1928 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1929 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1930 [(set f32:$frD, (fsqrt f32:$frB))]>;
1935 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1936 /// often coalesced away and we don't want the dispatch group builder to think
1937 /// that they will fill slots (which could cause the load of a LSU reject to
1938 /// sneak into a d-group with a store).
1939 let neverHasSideEffects = 1 in
1940 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1941 "fmr", "$frD, $frB", IIC_FPGeneral,
1942 []>, // (set f32:$frD, f32:$frB)
1945 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1946 // These are artificially split into two different forms, for 4/8 byte FP.
1947 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1948 "fabs", "$frD, $frB", IIC_FPGeneral,
1949 [(set f32:$frD, (fabs f32:$frB))]>;
1950 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1951 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1952 "fabs", "$frD, $frB", IIC_FPGeneral,
1953 [(set f64:$frD, (fabs f64:$frB))]>;
1954 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1955 "fnabs", "$frD, $frB", IIC_FPGeneral,
1956 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1957 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1958 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1959 "fnabs", "$frD, $frB", IIC_FPGeneral,
1960 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1961 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1962 "fneg", "$frD, $frB", IIC_FPGeneral,
1963 [(set f32:$frD, (fneg f32:$frB))]>;
1964 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1965 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1966 "fneg", "$frD, $frB", IIC_FPGeneral,
1967 [(set f64:$frD, (fneg f64:$frB))]>;
1969 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1970 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1971 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1972 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1973 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1974 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1975 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1977 // Reciprocal estimates.
1978 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1979 "fre", "$frD, $frB", IIC_FPGeneral,
1980 [(set f64:$frD, (PPCfre f64:$frB))]>;
1981 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1982 "fres", "$frD, $frB", IIC_FPGeneral,
1983 [(set f32:$frD, (PPCfre f32:$frB))]>;
1984 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1985 "frsqrte", "$frD, $frB", IIC_FPGeneral,
1986 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1987 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1988 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
1989 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1992 // XL-Form instructions. condition register logical ops.
1994 let neverHasSideEffects = 1 in
1995 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1996 "mcrf $BF, $BFA", IIC_BrMCR>,
1997 PPC970_DGroup_First, PPC970_Unit_CRU;
1999 let isCommutable = 1 in {
2000 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
2001 (ins crbitrc:$CRA, crbitrc:$CRB),
2002 "crand $CRD, $CRA, $CRB", IIC_BrCR,
2003 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2005 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2006 (ins crbitrc:$CRA, crbitrc:$CRB),
2007 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2008 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2010 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
2011 (ins crbitrc:$CRA, crbitrc:$CRB),
2012 "cror $CRD, $CRA, $CRB", IIC_BrCR,
2013 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2015 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
2016 (ins crbitrc:$CRA, crbitrc:$CRB),
2017 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2018 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2020 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
2021 (ins crbitrc:$CRA, crbitrc:$CRB),
2022 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2023 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2025 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
2026 (ins crbitrc:$CRA, crbitrc:$CRB),
2027 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2028 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2031 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2032 (ins crbitrc:$CRA, crbitrc:$CRB),
2033 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2034 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2036 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
2037 (ins crbitrc:$CRA, crbitrc:$CRB),
2038 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2039 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2041 let isCodeGenOnly = 1 in {
2042 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2043 "creqv $dst, $dst, $dst", IIC_BrCR,
2044 [(set i1:$dst, 1)]>;
2046 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2047 "crxor $dst, $dst, $dst", IIC_BrCR,
2048 [(set i1:$dst, 0)]>;
2050 let Defs = [CR1EQ], CRD = 6 in {
2051 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2052 "creqv 6, 6, 6", IIC_BrCR,
2055 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2056 "crxor 6, 6, 6", IIC_BrCR,
2061 // XFX-Form instructions. Instructions that deal with SPRs.
2064 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2065 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2066 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2067 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2069 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2070 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2072 let Uses = [CTR] in {
2073 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2074 "mfctr $rT", IIC_SprMFSPR>,
2075 PPC970_DGroup_First, PPC970_Unit_FXU;
2077 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2078 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2079 "mtctr $rS", IIC_SprMTSPR>,
2080 PPC970_DGroup_First, PPC970_Unit_FXU;
2082 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2083 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2084 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2085 "mtctr $rS", IIC_SprMTSPR>,
2086 PPC970_DGroup_First, PPC970_Unit_FXU;
2089 let Defs = [LR] in {
2090 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2091 "mtlr $rS", IIC_SprMTSPR>,
2092 PPC970_DGroup_First, PPC970_Unit_FXU;
2094 let Uses = [LR] in {
2095 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2096 "mflr $rT", IIC_SprMFSPR>,
2097 PPC970_DGroup_First, PPC970_Unit_FXU;
2100 let isCodeGenOnly = 1 in {
2101 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2102 // like a GPR on the PPC970. As such, copies in and out have the same
2103 // performance characteristics as an OR instruction.
2104 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2105 "mtspr 256, $rS", IIC_IntGeneral>,
2106 PPC970_DGroup_Single, PPC970_Unit_FXU;
2107 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2108 "mfspr $rT, 256", IIC_IntGeneral>,
2109 PPC970_DGroup_First, PPC970_Unit_FXU;
2111 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2112 (outs VRSAVERC:$reg), (ins gprc:$rS),
2113 "mtspr 256, $rS", IIC_IntGeneral>,
2114 PPC970_DGroup_Single, PPC970_Unit_FXU;
2115 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2116 (ins VRSAVERC:$reg),
2117 "mfspr $rT, 256", IIC_IntGeneral>,
2118 PPC970_DGroup_First, PPC970_Unit_FXU;
2121 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2122 // so we'll need to scavenge a register for it.
2124 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2125 "#SPILL_VRSAVE", []>;
2127 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2128 // spilled), so we'll need to scavenge a register for it.
2130 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2131 "#RESTORE_VRSAVE", []>;
2133 let neverHasSideEffects = 1 in {
2134 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2135 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2136 PPC970_DGroup_First, PPC970_Unit_CRU;
2138 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2139 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2140 PPC970_MicroCode, PPC970_Unit_CRU;
2142 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2143 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2144 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2145 PPC970_DGroup_First, PPC970_Unit_CRU;
2147 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2148 "mfcr $rT", IIC_SprMFCR>,
2149 PPC970_MicroCode, PPC970_Unit_CRU;
2150 } // neverHasSideEffects = 1
2152 // Pseudo instruction to perform FADD in round-to-zero mode.
2153 let usesCustomInserter = 1, Uses = [RM] in {
2154 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2155 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2158 // The above pseudo gets expanded to make use of the following instructions
2159 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2160 let Uses = [RM], Defs = [RM] in {
2161 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2162 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2163 PPC970_DGroup_Single, PPC970_Unit_FPU;
2164 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2165 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2166 PPC970_DGroup_Single, PPC970_Unit_FPU;
2167 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2168 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2169 PPC970_DGroup_Single, PPC970_Unit_FPU;
2171 let Uses = [RM] in {
2172 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2173 "mffs $rT", IIC_IntMFFS,
2174 [(set f64:$rT, (PPCmffs))]>,
2175 PPC970_DGroup_Single, PPC970_Unit_FPU;
2179 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
2180 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2181 let isCommutable = 1 in
2182 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2183 "add", "$rT, $rA, $rB", IIC_IntSimple,
2184 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2185 let isCodeGenOnly = 1 in
2186 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2187 "add $rT, $rA, $rB", IIC_IntSimple,
2188 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2189 let isCommutable = 1 in
2190 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2191 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2192 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2193 PPC970_DGroup_Cracked;
2195 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2196 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2197 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2198 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2199 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2200 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2201 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2202 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2203 let isCommutable = 1 in {
2204 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2205 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2206 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2207 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2208 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2209 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2210 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2211 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2212 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2214 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2215 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2216 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2217 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2218 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2219 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2220 PPC970_DGroup_Cracked;
2221 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2222 "neg", "$rT, $rA", IIC_IntSimple,
2223 [(set i32:$rT, (ineg i32:$rA))]>;
2224 let Uses = [CARRY] in {
2225 let isCommutable = 1 in
2226 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2227 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2228 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2229 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2230 "addme", "$rT, $rA", IIC_IntGeneral,
2231 [(set i32:$rT, (adde i32:$rA, -1))]>;
2232 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2233 "addze", "$rT, $rA", IIC_IntGeneral,
2234 [(set i32:$rT, (adde i32:$rA, 0))]>;
2235 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2236 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2237 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2238 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2239 "subfme", "$rT, $rA", IIC_IntGeneral,
2240 [(set i32:$rT, (sube -1, i32:$rA))]>;
2241 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2242 "subfze", "$rT, $rA", IIC_IntGeneral,
2243 [(set i32:$rT, (sube 0, i32:$rA))]>;
2247 // A-Form instructions. Most of the instructions executed in the FPU are of
2250 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
2251 let Uses = [RM] in {
2252 let isCommutable = 1 in {
2253 defm FMADD : AForm_1r<63, 29,
2254 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2255 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2256 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2257 defm FMADDS : AForm_1r<59, 29,
2258 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2259 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2260 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2261 defm FMSUB : AForm_1r<63, 28,
2262 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2263 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2265 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2266 defm FMSUBS : AForm_1r<59, 28,
2267 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2268 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2270 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2271 defm FNMADD : AForm_1r<63, 31,
2272 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2273 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2275 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2276 defm FNMADDS : AForm_1r<59, 31,
2277 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2278 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2280 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2281 defm FNMSUB : AForm_1r<63, 30,
2282 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2283 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2284 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2285 (fneg f64:$FRB))))]>;
2286 defm FNMSUBS : AForm_1r<59, 30,
2287 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2288 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2289 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2290 (fneg f32:$FRB))))]>;
2293 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2294 // having 4 of these, force the comparison to always be an 8-byte double (code
2295 // should use an FMRSD if the input comparison value really wants to be a float)
2296 // and 4/8 byte forms for the result and operand type..
2297 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2298 defm FSELD : AForm_1r<63, 23,
2299 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2300 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2301 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2302 defm FSELS : AForm_1r<63, 23,
2303 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2304 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2305 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2306 let Uses = [RM] in {
2307 let isCommutable = 1 in {
2308 defm FADD : AForm_2r<63, 21,
2309 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2310 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2311 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2312 defm FADDS : AForm_2r<59, 21,
2313 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2314 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2315 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2317 defm FDIV : AForm_2r<63, 18,
2318 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2319 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2320 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2321 defm FDIVS : AForm_2r<59, 18,
2322 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2323 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2324 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2325 let isCommutable = 1 in {
2326 defm FMUL : AForm_3r<63, 25,
2327 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2328 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2329 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2330 defm FMULS : AForm_3r<59, 25,
2331 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2332 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2333 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2335 defm FSUB : AForm_2r<63, 20,
2336 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2337 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2338 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2339 defm FSUBS : AForm_2r<59, 20,
2340 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2341 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2342 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2346 let neverHasSideEffects = 1 in {
2347 let PPC970_Unit = 1 in { // FXU Operations.
2349 def ISEL : AForm_4<31, 15,
2350 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2351 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
2355 let PPC970_Unit = 1 in { // FXU Operations.
2356 // M-Form instructions. rotate and mask instructions.
2358 let isCommutable = 1 in {
2359 // RLWIMI can be commuted if the rotate amount is zero.
2360 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2361 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2362 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2363 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2364 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2366 let BaseName = "rlwinm" in {
2367 def RLWINM : MForm_2<21,
2368 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2369 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2372 def RLWINMo : MForm_2<21,
2373 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2374 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2375 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2377 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2378 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2379 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2382 } // neverHasSideEffects = 1
2384 //===----------------------------------------------------------------------===//
2385 // PowerPC Instruction Patterns
2388 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2389 def : Pat<(i32 imm:$imm),
2390 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2392 // Implement the 'not' operation with the NOR instruction.
2393 def i32not : OutPatFrag<(ops node:$in),
2395 def : Pat<(not i32:$in),
2398 // ADD an arbitrary immediate.
2399 def : Pat<(add i32:$in, imm:$imm),
2400 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2401 // OR an arbitrary immediate.
2402 def : Pat<(or i32:$in, imm:$imm),
2403 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2404 // XOR an arbitrary immediate.
2405 def : Pat<(xor i32:$in, imm:$imm),
2406 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2408 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2409 (SUBFIC $in, imm:$imm)>;
2412 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2413 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2414 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2415 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2418 def : Pat<(rotl i32:$in, i32:$sh),
2419 (RLWNM $in, $sh, 0, 31)>;
2420 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2421 (RLWINM $in, imm:$imm, 0, 31)>;
2424 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2425 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2428 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2429 (BL tglobaladdr:$dst)>;
2430 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2431 (BL texternalsym:$dst)>;
2433 def : Pat<(PPCcall_tls texternalsym:$func, tglobaltlsaddr:$sym),
2434 (BL_TLS texternalsym:$func, tglobaltlsaddr:$sym)>;
2436 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2437 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2439 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2440 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2442 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2443 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2447 // Hi and Lo for Darwin Global Addresses.
2448 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2449 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2450 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2451 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2452 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2453 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2454 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2455 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2456 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2457 (ADDIS $in, tglobaltlsaddr:$g)>;
2458 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2459 (ADDI $in, tglobaltlsaddr:$g)>;
2460 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2461 (ADDIS $in, tglobaladdr:$g)>;
2462 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2463 (ADDIS $in, tconstpool:$g)>;
2464 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2465 (ADDIS $in, tjumptable:$g)>;
2466 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2467 (ADDIS $in, tblockaddress:$g)>;
2469 // Support for thread-local storage.
2470 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2471 [(set i32:$rD, (PPCppc32GOT))]>;
2473 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2474 // This uses two output registers, the first as the real output, the second as a
2475 // temporary register, used internally in code generation.
2476 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2477 []>, NoEncode<"$rT">;
2479 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2482 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2483 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2484 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2486 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2489 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2490 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2493 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2494 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2497 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2498 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2501 (PPCaddisDtprelHA i32:$reg,
2502 tglobaltlsaddr:$disp))]>;
2504 // Support for Position-independent code
2505 def LWZtoc: Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2508 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2509 // Get Global (GOT) Base Register offset, from the word immediately preceding
2510 // the function label.
2511 def GetGBRO: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#GetGBRO", []>;
2512 // Update the Global(GOT) Base Register with the above offset.
2513 def UpdateGBR: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2516 // Standard shifts. These are represented separately from the real shifts above
2517 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2519 def : Pat<(sra i32:$rS, i32:$rB),
2521 def : Pat<(srl i32:$rS, i32:$rB),
2523 def : Pat<(shl i32:$rS, i32:$rB),
2526 def : Pat<(zextloadi1 iaddr:$src),
2528 def : Pat<(zextloadi1 xaddr:$src),
2530 def : Pat<(extloadi1 iaddr:$src),
2532 def : Pat<(extloadi1 xaddr:$src),
2534 def : Pat<(extloadi8 iaddr:$src),
2536 def : Pat<(extloadi8 xaddr:$src),
2538 def : Pat<(extloadi16 iaddr:$src),
2540 def : Pat<(extloadi16 xaddr:$src),
2542 def : Pat<(f64 (extloadf32 iaddr:$src)),
2543 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2544 def : Pat<(f64 (extloadf32 xaddr:$src)),
2545 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2547 def : Pat<(f64 (fextend f32:$src)),
2548 (COPY_TO_REGCLASS $src, F8RC)>;
2550 // Only seq_cst fences require the heavyweight sync (SYNC 0).
2551 // All others can use the lightweight sync (SYNC 1).
2552 // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2553 // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2554 // versions of Power.
2555 def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2556 def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2557 def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2558 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2560 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2561 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2562 (FNMSUB $A, $C, $B)>;
2563 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2564 (FNMSUB $A, $C, $B)>;
2565 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2566 (FNMSUBS $A, $C, $B)>;
2567 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2568 (FNMSUBS $A, $C, $B)>;
2570 // FCOPYSIGN's operand types need not agree.
2571 def : Pat<(fcopysign f64:$frB, f32:$frA),
2572 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2573 def : Pat<(fcopysign f32:$frB, f64:$frA),
2574 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2576 include "PPCInstrAltivec.td"
2577 include "PPCInstrSPE.td"
2578 include "PPCInstr64Bit.td"
2579 include "PPCInstrVSX.td"
2581 def crnot : OutPatFrag<(ops node:$in),
2583 def : Pat<(not i1:$in),
2586 // Patterns for arithmetic i1 operations.
2587 def : Pat<(add i1:$a, i1:$b),
2589 def : Pat<(sub i1:$a, i1:$b),
2591 def : Pat<(mul i1:$a, i1:$b),
2594 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2595 // (-1 is used to mean all bits set).
2596 def : Pat<(i1 -1), (CRSET)>;
2598 // i1 extensions, implemented in terms of isel.
2599 def : Pat<(i32 (zext i1:$in)),
2600 (SELECT_I4 $in, (LI 1), (LI 0))>;
2601 def : Pat<(i32 (sext i1:$in)),
2602 (SELECT_I4 $in, (LI -1), (LI 0))>;
2604 def : Pat<(i64 (zext i1:$in)),
2605 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2606 def : Pat<(i64 (sext i1:$in)),
2607 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2609 // FIXME: We should choose either a zext or a sext based on other constants
2611 def : Pat<(i32 (anyext i1:$in)),
2612 (SELECT_I4 $in, (LI 1), (LI 0))>;
2613 def : Pat<(i64 (anyext i1:$in)),
2614 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2616 // match setcc on i1 variables.
2617 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2619 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2621 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2623 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2625 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2627 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2629 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2631 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2633 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2635 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2638 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2639 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2640 // floating-point types.
2642 multiclass CRNotPat<dag pattern, dag result> {
2643 def : Pat<pattern, (crnot result)>;
2644 def : Pat<(not pattern), result>;
2646 // We can also fold the crnot into an extension:
2647 def : Pat<(i32 (zext pattern)),
2648 (SELECT_I4 result, (LI 0), (LI 1))>;
2649 def : Pat<(i32 (sext pattern)),
2650 (SELECT_I4 result, (LI 0), (LI -1))>;
2652 // We can also fold the crnot into an extension:
2653 def : Pat<(i64 (zext pattern)),
2654 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2655 def : Pat<(i64 (sext pattern)),
2656 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2658 // FIXME: We should choose either a zext or a sext based on other constants
2660 def : Pat<(i32 (anyext pattern)),
2661 (SELECT_I4 result, (LI 0), (LI 1))>;
2663 def : Pat<(i64 (anyext pattern)),
2664 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2667 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2668 // we need to write imm:$imm in the output patterns below, not just $imm, or
2669 // else the resulting matcher will not correctly add the immediate operand
2670 // (making it a register operand instead).
2673 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2674 OutPatFrag rfrag, OutPatFrag rfrag8> {
2675 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2677 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2679 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2680 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2681 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2682 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2684 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2686 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2688 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2689 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2690 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2691 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2694 // Note that we do all inversions below with i(32|64)not, instead of using
2695 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2696 // has 2-cycle latency.
2698 defm : ExtSetCCPat<SETEQ,
2699 PatFrag<(ops node:$in, node:$cc),
2700 (setcc $in, 0, $cc)>,
2701 OutPatFrag<(ops node:$in),
2702 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2703 OutPatFrag<(ops node:$in),
2704 (RLDICL (CNTLZD $in), 58, 63)> >;
2706 defm : ExtSetCCPat<SETNE,
2707 PatFrag<(ops node:$in, node:$cc),
2708 (setcc $in, 0, $cc)>,
2709 OutPatFrag<(ops node:$in),
2710 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2711 OutPatFrag<(ops node:$in),
2712 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2714 defm : ExtSetCCPat<SETLT,
2715 PatFrag<(ops node:$in, node:$cc),
2716 (setcc $in, 0, $cc)>,
2717 OutPatFrag<(ops node:$in),
2718 (RLWINM $in, 1, 31, 31)>,
2719 OutPatFrag<(ops node:$in),
2720 (RLDICL $in, 1, 63)> >;
2722 defm : ExtSetCCPat<SETGE,
2723 PatFrag<(ops node:$in, node:$cc),
2724 (setcc $in, 0, $cc)>,
2725 OutPatFrag<(ops node:$in),
2726 (RLWINM (i32not $in), 1, 31, 31)>,
2727 OutPatFrag<(ops node:$in),
2728 (RLDICL (i64not $in), 1, 63)> >;
2730 defm : ExtSetCCPat<SETGT,
2731 PatFrag<(ops node:$in, node:$cc),
2732 (setcc $in, 0, $cc)>,
2733 OutPatFrag<(ops node:$in),
2734 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2735 OutPatFrag<(ops node:$in),
2736 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2738 defm : ExtSetCCPat<SETLE,
2739 PatFrag<(ops node:$in, node:$cc),
2740 (setcc $in, 0, $cc)>,
2741 OutPatFrag<(ops node:$in),
2742 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2743 OutPatFrag<(ops node:$in),
2744 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2746 defm : ExtSetCCPat<SETLT,
2747 PatFrag<(ops node:$in, node:$cc),
2748 (setcc $in, -1, $cc)>,
2749 OutPatFrag<(ops node:$in),
2750 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2751 OutPatFrag<(ops node:$in),
2752 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2754 defm : ExtSetCCPat<SETGE,
2755 PatFrag<(ops node:$in, node:$cc),
2756 (setcc $in, -1, $cc)>,
2757 OutPatFrag<(ops node:$in),
2758 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2759 OutPatFrag<(ops node:$in),
2760 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2762 defm : ExtSetCCPat<SETGT,
2763 PatFrag<(ops node:$in, node:$cc),
2764 (setcc $in, -1, $cc)>,
2765 OutPatFrag<(ops node:$in),
2766 (RLWINM (i32not $in), 1, 31, 31)>,
2767 OutPatFrag<(ops node:$in),
2768 (RLDICL (i64not $in), 1, 63)> >;
2770 defm : ExtSetCCPat<SETLE,
2771 PatFrag<(ops node:$in, node:$cc),
2772 (setcc $in, -1, $cc)>,
2773 OutPatFrag<(ops node:$in),
2774 (RLWINM $in, 1, 31, 31)>,
2775 OutPatFrag<(ops node:$in),
2776 (RLDICL $in, 1, 63)> >;
2779 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2780 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2781 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2782 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2783 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2784 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2785 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2786 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2787 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2788 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2789 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2790 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2792 // For non-equality comparisons, the default code would materialize the
2793 // constant, then compare against it, like this:
2795 // ori r2, r2, 22136
2798 // Since we are just comparing for equality, we can emit this instead:
2799 // xoris r0,r3,0x1234
2800 // cmplwi cr0,r0,0x5678
2803 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2804 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2805 (LO16 imm:$imm)), sub_eq)>;
2807 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2808 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2809 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2810 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2811 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2812 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2813 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2814 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2815 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2816 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2817 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2818 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2820 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2821 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2822 (LO16 imm:$imm)), sub_eq)>;
2824 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
2825 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2826 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2827 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2828 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2829 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2830 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
2831 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2832 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2833 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2835 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2836 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2837 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
2838 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2839 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2840 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2841 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
2842 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2843 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2844 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2847 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
2848 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2849 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2850 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2851 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2852 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2853 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
2854 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2855 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
2856 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2857 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
2858 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2860 // For non-equality comparisons, the default code would materialize the
2861 // constant, then compare against it, like this:
2863 // ori r2, r2, 22136
2866 // Since we are just comparing for equality, we can emit this instead:
2867 // xoris r0,r3,0x1234
2868 // cmpldi cr0,r0,0x5678
2871 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
2872 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2873 (LO16 imm:$imm)), sub_eq)>;
2875 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
2876 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2877 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
2878 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2879 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
2880 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2881 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
2882 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2883 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
2884 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2885 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
2886 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2888 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
2889 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2890 (LO16 imm:$imm)), sub_eq)>;
2892 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
2893 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2894 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
2895 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2896 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
2897 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2898 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
2899 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2900 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
2901 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2903 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
2904 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2905 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
2906 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2907 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
2908 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2909 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
2910 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2911 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
2912 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2915 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
2916 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2917 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
2918 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2919 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
2920 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2921 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
2922 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2923 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
2924 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2925 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
2926 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2927 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
2928 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2930 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
2931 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2932 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
2933 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2934 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
2935 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2936 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
2937 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2938 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
2939 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2940 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
2941 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2942 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
2943 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2946 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
2947 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2948 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
2949 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2950 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
2951 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2952 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
2953 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2954 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
2955 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2956 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
2957 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2958 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
2959 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2961 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
2962 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2963 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
2964 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2965 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
2966 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2967 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
2968 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2969 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
2970 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2971 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
2972 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2973 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
2974 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2976 // match select on i1 variables:
2977 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
2978 (CROR (CRAND $cond , $tval),
2979 (CRAND (crnot $cond), $fval))>;
2981 // match selectcc on i1 variables:
2982 // select (lhs == rhs), tval, fval is:
2983 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
2984 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
2985 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
2986 (CRAND (CRORC $lhs, $rhs), $fval))>;
2987 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
2988 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
2989 (CRAND (CRANDC $lhs, $rhs), $fval))>;
2990 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
2991 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
2992 (CRAND (CRXOR $lhs, $rhs), $fval))>;
2993 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
2994 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
2995 (CRAND (CRANDC $rhs, $lhs), $fval))>;
2996 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
2997 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
2998 (CRAND (CRORC $rhs, $lhs), $fval))>;
2999 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3000 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3001 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3003 // match selectcc on i1 variables with non-i1 output.
3004 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3005 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3006 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3007 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3008 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3009 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3010 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3011 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3012 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3013 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3014 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3015 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3017 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3018 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3019 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3020 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3021 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3022 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3023 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3024 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3025 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3026 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3027 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3028 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3030 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3031 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3032 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3033 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3034 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3035 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3036 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3037 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3038 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3039 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3040 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3041 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3043 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3044 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3045 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3046 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3047 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3048 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3049 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3050 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3051 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3052 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3053 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3054 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3056 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3057 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3058 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3059 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3060 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3061 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3062 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3063 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3064 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3065 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3066 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3067 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3069 let usesCustomInserter = 1 in {
3070 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3072 [(set i1:$dst, (trunc (not i32:$in)))]>;
3073 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3075 [(set i1:$dst, (trunc i32:$in))]>;
3077 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3079 [(set i1:$dst, (trunc (not i64:$in)))]>;
3080 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3082 [(set i1:$dst, (trunc i64:$in))]>;
3085 def : Pat<(i1 (not (trunc i32:$in))),
3086 (ANDIo_1_EQ_BIT $in)>;
3087 def : Pat<(i1 (not (trunc i64:$in))),
3088 (ANDIo_1_EQ_BIT8 $in)>;
3090 //===----------------------------------------------------------------------===//
3091 // PowerPC Instructions used for assembler/disassembler only
3094 // FIXME: For B=0 or B > 8, the registers following RT are used.
3095 // WARNING: Do not add patterns for this instruction without fixing this.
3096 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3097 "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3099 // FIXME: For B=0 or B > 8, the registers following RT are used.
3100 // WARNING: Do not add patterns for this instruction without fixing this.
3101 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3102 "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3104 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3105 "isync", IIC_SprISYNC, []>;
3107 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3108 "icbi $src", IIC_LdStICBI, []>;
3110 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3111 "eieio", IIC_LdStLoad, []>;
3113 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3114 "wait $L", IIC_LdStLoad, []>;
3116 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3117 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3119 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3120 "mtsr $SR, $RS", IIC_SprMTSR>;
3122 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3123 "mfsr $RS, $SR", IIC_SprMFSR>;
3125 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3126 "mtsrin $RS, $RB", IIC_SprMTSR>;
3128 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3129 "mfsrin $RS, $RB", IIC_SprMFSR>;
3131 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3132 "mtmsr $RS, $L", IIC_SprMTMSR>;
3134 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3135 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3139 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3140 Requires<[IsBookE]> {
3144 let Inst{21-30} = 163;
3147 def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3148 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3149 def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3150 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3152 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3153 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3154 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3155 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3157 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3158 "mfmsr $RT", IIC_SprMFMSR, []>;
3160 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3161 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3163 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3164 "slbie $RB", IIC_SprSLBIE, []>;
3166 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3167 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3169 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3170 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3172 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3174 def TLBIA : XForm_0<31, 370, (outs), (ins),
3175 "tlbia", IIC_SprTLBIA, []>;
3177 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3178 "tlbsync", IIC_SprTLBSYNC, []>;
3180 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3181 "tlbiel $RB", IIC_SprTLBIEL, []>;
3183 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3184 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3185 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3186 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3188 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3189 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3191 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3192 IIC_LdStLoad>, Requires<[IsBookE]>;
3194 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3195 IIC_LdStLoad>, Requires<[IsBookE]>;
3197 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3198 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3200 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3201 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3203 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3204 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3206 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3207 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3209 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3210 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3211 Requires<[IsPPC4xx]>;
3212 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3213 (ins gprc:$RST, gprc:$A, gprc:$B),
3214 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3215 Requires<[IsPPC4xx]>, isDOT;
3217 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3219 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3220 Requires<[IsBookE]>;
3221 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3222 Requires<[IsBookE]>;
3224 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3226 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3229 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3230 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3231 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3232 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3234 //===----------------------------------------------------------------------===//
3235 // PowerPC Assembler Instruction Aliases
3238 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3239 // These are aliases that require C++ handling to convert to the target
3240 // instruction, while InstAliases can be handled directly by tblgen.
3241 class PPCAsmPseudo<string asm, dag iops>
3243 let Namespace = "PPC";
3244 bit PPC64 = 0; // Default value, override with isPPC64
3246 let OutOperandList = (outs);
3247 let InOperandList = iops;
3249 let AsmString = asm;
3250 let isAsmParserOnly = 1;
3254 def : InstAlias<"sc", (SC 0)>;
3256 def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3257 def : InstAlias<"msync", (SYNC 0)>, Requires<[HasSYNC]>;
3258 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3259 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3261 def : InstAlias<"wait", (WAIT 0)>;
3262 def : InstAlias<"waitrsv", (WAIT 1)>;
3263 def : InstAlias<"waitimpl", (WAIT 2)>;
3265 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3267 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3268 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3269 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3270 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3272 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3273 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3275 def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3276 def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3278 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3279 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3281 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3282 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3284 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3285 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3287 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3288 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3290 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3291 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3293 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3294 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3296 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3297 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3299 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3300 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3302 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3303 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3305 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3306 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3308 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3309 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3311 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3312 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3314 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3315 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3316 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3318 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3319 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3321 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3322 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3323 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3324 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3326 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3328 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3329 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3331 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3332 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3334 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3336 foreach BATR = 0-3 in {
3337 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3338 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3339 Requires<[IsPPC6xx]>;
3340 def : InstAlias<"mfdbatu $Rx, "#BATR,
3341 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3342 Requires<[IsPPC6xx]>;
3343 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3344 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3345 Requires<[IsPPC6xx]>;
3346 def : InstAlias<"mfdbatl $Rx, "#BATR,
3347 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3348 Requires<[IsPPC6xx]>;
3349 def : InstAlias<"mtibatu "#BATR#", $Rx",
3350 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3351 Requires<[IsPPC6xx]>;
3352 def : InstAlias<"mfibatu $Rx, "#BATR,
3353 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3354 Requires<[IsPPC6xx]>;
3355 def : InstAlias<"mtibatl "#BATR#", $Rx",
3356 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3357 Requires<[IsPPC6xx]>;
3358 def : InstAlias<"mfibatl $Rx, "#BATR,
3359 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3360 Requires<[IsPPC6xx]>;
3363 foreach BR = 0-7 in {
3364 def : InstAlias<"mfbr"#BR#" $Rx",
3365 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3366 Requires<[IsPPC4xx]>;
3367 def : InstAlias<"mtbr"#BR#" $Rx",
3368 (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3369 Requires<[IsPPC4xx]>;
3372 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3373 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3375 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3376 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3378 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3379 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3381 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3382 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3384 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3385 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3387 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3388 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3390 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3392 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3393 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3394 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3395 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3396 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3397 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3398 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3399 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3401 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3402 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3403 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3404 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3406 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3407 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3409 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3410 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3412 foreach SPRG = 0-3 in {
3413 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3414 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3415 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3416 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3418 foreach SPRG = 4-7 in {
3419 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3420 Requires<[IsBookE]>;
3421 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3422 Requires<[IsBookE]>;
3423 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3424 Requires<[IsBookE]>;
3425 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3426 Requires<[IsBookE]>;
3429 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3431 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3432 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3434 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3436 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3437 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3439 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3440 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3441 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3442 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3444 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3446 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3447 Requires<[IsPPC4xx]>;
3448 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3449 Requires<[IsPPC4xx]>;
3450 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3451 Requires<[IsPPC4xx]>;
3452 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3453 Requires<[IsPPC4xx]>;
3455 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3456 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3457 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3458 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3459 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3460 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3461 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3462 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3463 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3464 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3465 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3466 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3467 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3468 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3469 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3470 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3471 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3472 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3473 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3474 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3475 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3476 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3477 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3478 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3479 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3480 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3481 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3482 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3483 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3484 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3485 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3486 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3487 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3488 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3489 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3490 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3492 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3493 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3494 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3495 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3496 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3497 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3499 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3500 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3501 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3502 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3503 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3504 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3505 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3506 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3507 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3508 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3509 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3510 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3511 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3512 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3513 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3514 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3515 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3516 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3517 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3518 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3519 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3520 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3521 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3522 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3523 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3524 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3525 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3526 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3527 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3528 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3529 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3530 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3532 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3533 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3534 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3535 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3536 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3537 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3539 // These generic branch instruction forms are used for the assembler parser only.
3540 // Defs and Uses are conservative, since we don't know the BO value.
3541 let PPC970_Unit = 7 in {
3542 let Defs = [CTR], Uses = [CTR, RM] in {
3543 def gBC : BForm_3<16, 0, 0, (outs),
3544 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3545 "bc $bo, $bi, $dst">;
3546 def gBCA : BForm_3<16, 1, 0, (outs),
3547 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3548 "bca $bo, $bi, $dst">;
3550 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3551 def gBCL : BForm_3<16, 0, 1, (outs),
3552 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3553 "bcl $bo, $bi, $dst">;
3554 def gBCLA : BForm_3<16, 1, 1, (outs),
3555 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3556 "bcla $bo, $bi, $dst">;
3558 let Defs = [CTR], Uses = [CTR, LR, RM] in
3559 def gBCLR : XLForm_2<19, 16, 0, (outs),
3560 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3561 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3562 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3563 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3564 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3565 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3566 let Defs = [CTR], Uses = [CTR, LR, RM] in
3567 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3568 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3569 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3570 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3571 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3572 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3573 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3575 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3576 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3577 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3578 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3580 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3581 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3582 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3583 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3584 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3585 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3586 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3588 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3589 : BranchSimpleMnemonic1<name, pm, bo> {
3590 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3591 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3593 defm : BranchSimpleMnemonic2<"t", "", 12>;
3594 defm : BranchSimpleMnemonic2<"f", "", 4>;
3595 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3596 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3597 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3598 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3599 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3600 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3601 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3602 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3604 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3605 def : InstAlias<"b"#name#pm#" $cc, $dst",
3606 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3607 def : InstAlias<"b"#name#pm#" $dst",
3608 (BCC bibo, CR0, condbrtarget:$dst)>;
3610 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3611 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3612 def : InstAlias<"b"#name#"a"#pm#" $dst",
3613 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3615 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3616 (BCCLR bibo, crrc:$cc)>;
3617 def : InstAlias<"b"#name#"lr"#pm,
3620 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3621 (BCCCTR bibo, crrc:$cc)>;
3622 def : InstAlias<"b"#name#"ctr"#pm,
3623 (BCCCTR bibo, CR0)>;
3625 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3626 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3627 def : InstAlias<"b"#name#"l"#pm#" $dst",
3628 (BCCL bibo, CR0, condbrtarget:$dst)>;
3630 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3631 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3632 def : InstAlias<"b"#name#"la"#pm#" $dst",
3633 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3635 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3636 (BCCLRL bibo, crrc:$cc)>;
3637 def : InstAlias<"b"#name#"lrl"#pm,
3638 (BCCLRL bibo, CR0)>;
3640 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3641 (BCCCTRL bibo, crrc:$cc)>;
3642 def : InstAlias<"b"#name#"ctrl"#pm,
3643 (BCCCTRL bibo, CR0)>;
3645 multiclass BranchExtendedMnemonic<string name, int bibo> {
3646 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3647 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3648 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3650 defm : BranchExtendedMnemonic<"lt", 12>;
3651 defm : BranchExtendedMnemonic<"gt", 44>;
3652 defm : BranchExtendedMnemonic<"eq", 76>;
3653 defm : BranchExtendedMnemonic<"un", 108>;
3654 defm : BranchExtendedMnemonic<"so", 108>;
3655 defm : BranchExtendedMnemonic<"ge", 4>;
3656 defm : BranchExtendedMnemonic<"nl", 4>;
3657 defm : BranchExtendedMnemonic<"le", 36>;
3658 defm : BranchExtendedMnemonic<"ng", 36>;
3659 defm : BranchExtendedMnemonic<"ne", 68>;
3660 defm : BranchExtendedMnemonic<"nu", 100>;
3661 defm : BranchExtendedMnemonic<"ns", 100>;
3663 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3664 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3665 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3666 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3667 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3668 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3669 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3670 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3672 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3673 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3674 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3675 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3676 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3677 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3678 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3679 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3681 multiclass TrapExtendedMnemonic<string name, int to> {
3682 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3683 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3684 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3685 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3687 defm : TrapExtendedMnemonic<"lt", 16>;
3688 defm : TrapExtendedMnemonic<"le", 20>;
3689 defm : TrapExtendedMnemonic<"eq", 4>;
3690 defm : TrapExtendedMnemonic<"ge", 12>;
3691 defm : TrapExtendedMnemonic<"gt", 8>;
3692 defm : TrapExtendedMnemonic<"nl", 12>;
3693 defm : TrapExtendedMnemonic<"ne", 24>;
3694 defm : TrapExtendedMnemonic<"ng", 20>;
3695 defm : TrapExtendedMnemonic<"llt", 2>;
3696 defm : TrapExtendedMnemonic<"lle", 6>;
3697 defm : TrapExtendedMnemonic<"lge", 5>;
3698 defm : TrapExtendedMnemonic<"lgt", 1>;
3699 defm : TrapExtendedMnemonic<"lnl", 5>;
3700 defm : TrapExtendedMnemonic<"lng", 6>;
3701 defm : TrapExtendedMnemonic<"u", 31>;
3704 def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>;
3705 def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>;
3706 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>;
3707 def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>;
3708 def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
3709 def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
3712 def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>;
3713 def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>;
3714 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>;
3715 def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
3716 def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
3717 def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;