1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
61 //===----------------------------------------------------------------------===//
62 // PowerPC specific DAG Nodes.
65 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
66 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
68 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
69 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
70 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
71 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
72 def PPCfctid : SDNode<"PPCISD::FCTID", SDTFPUnaryOp, []>;
73 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
74 def PPCfctiw : SDNode<"PPCISD::FCTIW", SDTFPUnaryOp, []>;
75 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
76 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
77 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
78 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
79 [SDNPHasChain, SDNPMayStore]>;
80 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
81 [SDNPHasChain, SDNPMayLoad]>;
82 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
83 [SDNPHasChain, SDNPMayLoad]>;
85 // Extract FPSCR (not modeled at the DAG level).
86 def PPCmffs : SDNode<"PPCISD::MFFS",
87 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
89 // Perform FADD in round-to-zero mode.
90 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
93 def PPCfsel : SDNode<"PPCISD::FSEL",
94 // Type constraint for fsel.
95 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
96 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
98 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
99 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
100 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
101 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
102 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
104 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
105 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
107 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
108 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
109 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
110 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
111 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
112 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
113 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
114 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
116 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
118 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
120 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
121 // amounts. These nodes are generated by the multi-precision shift code.
122 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
123 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
124 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
126 // These are target-independent nodes, but have target-specific formats.
127 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
128 [SDNPHasChain, SDNPOutGlue]>;
129 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
132 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
133 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
134 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
136 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
139 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
141 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
142 [SDNPHasChain, SDNPSideEffect,
143 SDNPInGlue, SDNPOutGlue]>;
144 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
145 [SDNPHasChain, SDNPSideEffect,
146 SDNPInGlue, SDNPOutGlue]>;
147 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
149 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
150 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
153 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
154 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
156 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
157 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
159 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
160 SDTypeProfile<1, 1, [SDTCisInt<0>,
162 [SDNPHasChain, SDNPSideEffect]>;
163 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
164 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
165 [SDNPHasChain, SDNPSideEffect]>;
167 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
168 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
169 [SDNPHasChain, SDNPSideEffect]>;
171 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
172 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
174 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
175 [SDNPHasChain, SDNPOptInGlue]>;
177 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
178 [SDNPHasChain, SDNPMayLoad]>;
179 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
180 [SDNPHasChain, SDNPMayStore]>;
182 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
183 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
186 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
188 // Instructions to support atomic operations
189 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
190 [SDNPHasChain, SDNPMayLoad]>;
191 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
192 [SDNPHasChain, SDNPMayStore]>;
194 // Instructions to support medium and large code model
195 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
196 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
197 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
200 // Instructions to support dynamic alloca.
201 def SDTDynOp : SDTypeProfile<1, 2, []>;
202 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
204 //===----------------------------------------------------------------------===//
205 // PowerPC specific transformation functions and pattern fragments.
208 def SHL32 : SDNodeXForm<imm, [{
209 // Transformation function: 31 - imm
210 return getI32Imm(31 - N->getZExtValue());
213 def SRL32 : SDNodeXForm<imm, [{
214 // Transformation function: 32 - imm
215 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
218 def LO16 : SDNodeXForm<imm, [{
219 // Transformation function: get the low 16 bits.
220 return getI32Imm((unsigned short)N->getZExtValue());
223 def HI16 : SDNodeXForm<imm, [{
224 // Transformation function: shift the immediate value down into the low bits.
225 return getI32Imm((unsigned)N->getZExtValue() >> 16);
228 def HA16 : SDNodeXForm<imm, [{
229 // Transformation function: shift the immediate value down into the low bits.
230 signed int Val = N->getZExtValue();
231 return getI32Imm((Val - (signed short)Val) >> 16);
233 def MB : SDNodeXForm<imm, [{
234 // Transformation function: get the start bit of a mask
236 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
237 return getI32Imm(mb);
240 def ME : SDNodeXForm<imm, [{
241 // Transformation function: get the end bit of a mask
243 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
244 return getI32Imm(me);
246 def maskimm32 : PatLeaf<(imm), [{
247 // maskImm predicate - True if immediate is a run of ones.
249 if (N->getValueType(0) == MVT::i32)
250 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
255 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
256 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
257 // sign extended field. Used by instructions like 'addi'.
258 return (int32_t)Imm == (short)Imm;
260 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
261 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
262 // sign extended field. Used by instructions like 'addi'.
263 return (int64_t)Imm == (short)Imm;
265 def immZExt16 : PatLeaf<(imm), [{
266 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
267 // field. Used by instructions like 'ori'.
268 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
271 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
272 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
273 // identical in 32-bit mode, but in 64-bit mode, they return true if the
274 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
276 def imm16ShiftedZExt : PatLeaf<(imm), [{
277 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
278 // immediate are set. Used by instructions like 'xoris'.
279 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
282 def imm16ShiftedSExt : PatLeaf<(imm), [{
283 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
284 // immediate are set. Used by instructions like 'addis'. Identical to
285 // imm16ShiftedZExt in 32-bit mode.
286 if (N->getZExtValue() & 0xFFFF) return false;
287 if (N->getValueType(0) == MVT::i32)
289 // For 64-bit, make sure it is sext right.
290 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
293 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
294 // restricted memrix (4-aligned) constants are alignment sensitive. If these
295 // offsets are hidden behind TOC entries than the values of the lower-order
296 // bits cannot be checked directly. As a result, we need to also incorporate
297 // an alignment check into the relevant patterns.
299 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
300 return cast<LoadSDNode>(N)->getAlignment() >= 4;
302 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
303 (store node:$val, node:$ptr), [{
304 return cast<StoreSDNode>(N)->getAlignment() >= 4;
306 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
307 return cast<LoadSDNode>(N)->getAlignment() >= 4;
309 def aligned4pre_store : PatFrag<
310 (ops node:$val, node:$base, node:$offset),
311 (pre_store node:$val, node:$base, node:$offset), [{
312 return cast<StoreSDNode>(N)->getAlignment() >= 4;
315 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
316 return cast<LoadSDNode>(N)->getAlignment() < 4;
318 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
319 (store node:$val, node:$ptr), [{
320 return cast<StoreSDNode>(N)->getAlignment() < 4;
322 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
323 return cast<LoadSDNode>(N)->getAlignment() < 4;
326 //===----------------------------------------------------------------------===//
327 // PowerPC Flag Definitions.
329 class isPPC64 { bit PPC64 = 1; }
330 class isDOT { bit RC = 1; }
332 class RegConstraint<string C> {
333 string Constraints = C;
335 class NoEncode<string E> {
336 string DisableEncoding = E;
340 //===----------------------------------------------------------------------===//
341 // PowerPC Operand Definitions.
343 // In the default PowerPC assembler syntax, registers are specified simply
344 // by number, so they cannot be distinguished from immediate values (without
345 // looking at the opcode). This means that the default operand matching logic
346 // for the asm parser does not work, and we need to specify custom matchers.
347 // Since those can only be specified with RegisterOperand classes and not
348 // directly on the RegisterClass, all instructions patterns used by the asm
349 // parser need to use a RegisterOperand (instead of a RegisterClass) for
350 // all their register operands.
351 // For this purpose, we define one RegisterOperand for each RegisterClass,
352 // using the same name as the class, just in lower case.
354 def PPCRegGPRCAsmOperand : AsmOperandClass {
355 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
357 def gprc : RegisterOperand<GPRC> {
358 let ParserMatchClass = PPCRegGPRCAsmOperand;
360 def PPCRegG8RCAsmOperand : AsmOperandClass {
361 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
363 def g8rc : RegisterOperand<G8RC> {
364 let ParserMatchClass = PPCRegG8RCAsmOperand;
366 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
367 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
369 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
370 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
372 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
373 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
375 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
376 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
378 def PPCRegF8RCAsmOperand : AsmOperandClass {
379 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
381 def f8rc : RegisterOperand<F8RC> {
382 let ParserMatchClass = PPCRegF8RCAsmOperand;
384 def PPCRegF4RCAsmOperand : AsmOperandClass {
385 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
387 def f4rc : RegisterOperand<F4RC> {
388 let ParserMatchClass = PPCRegF4RCAsmOperand;
390 def PPCRegVRRCAsmOperand : AsmOperandClass {
391 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
393 def vrrc : RegisterOperand<VRRC> {
394 let ParserMatchClass = PPCRegVRRCAsmOperand;
396 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
397 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
399 def crbitrc : RegisterOperand<CRBITRC> {
400 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
402 def PPCRegCRRCAsmOperand : AsmOperandClass {
403 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
405 def crrc : RegisterOperand<CRRC> {
406 let ParserMatchClass = PPCRegCRRCAsmOperand;
409 def PPCS5ImmAsmOperand : AsmOperandClass {
410 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
411 let RenderMethod = "addImmOperands";
413 def s5imm : Operand<i32> {
414 let PrintMethod = "printS5ImmOperand";
415 let ParserMatchClass = PPCS5ImmAsmOperand;
417 def PPCU5ImmAsmOperand : AsmOperandClass {
418 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
419 let RenderMethod = "addImmOperands";
421 def u5imm : Operand<i32> {
422 let PrintMethod = "printU5ImmOperand";
423 let ParserMatchClass = PPCU5ImmAsmOperand;
425 def PPCU6ImmAsmOperand : AsmOperandClass {
426 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
427 let RenderMethod = "addImmOperands";
429 def u6imm : Operand<i32> {
430 let PrintMethod = "printU6ImmOperand";
431 let ParserMatchClass = PPCU6ImmAsmOperand;
433 def PPCS16ImmAsmOperand : AsmOperandClass {
434 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
435 let RenderMethod = "addImmOperands";
437 def s16imm : Operand<i32> {
438 let PrintMethod = "printS16ImmOperand";
439 let EncoderMethod = "getImm16Encoding";
440 let ParserMatchClass = PPCS16ImmAsmOperand;
442 def PPCU16ImmAsmOperand : AsmOperandClass {
443 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
444 let RenderMethod = "addImmOperands";
446 def u16imm : Operand<i32> {
447 let PrintMethod = "printU16ImmOperand";
448 let EncoderMethod = "getImm16Encoding";
449 let ParserMatchClass = PPCU16ImmAsmOperand;
451 def PPCS17ImmAsmOperand : AsmOperandClass {
452 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
453 let RenderMethod = "addImmOperands";
455 def s17imm : Operand<i32> {
456 // This operand type is used for addis/lis to allow the assembler parser
457 // to accept immediates in the range -65536..65535 for compatibility with
458 // the GNU assembler. The operand is treated as 16-bit otherwise.
459 let PrintMethod = "printS16ImmOperand";
460 let EncoderMethod = "getImm16Encoding";
461 let ParserMatchClass = PPCS17ImmAsmOperand;
463 def PPCDirectBrAsmOperand : AsmOperandClass {
464 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
465 let RenderMethod = "addBranchTargetOperands";
467 def directbrtarget : Operand<OtherVT> {
468 let PrintMethod = "printBranchOperand";
469 let EncoderMethod = "getDirectBrEncoding";
470 let ParserMatchClass = PPCDirectBrAsmOperand;
472 def absdirectbrtarget : Operand<OtherVT> {
473 let PrintMethod = "printAbsBranchOperand";
474 let EncoderMethod = "getAbsDirectBrEncoding";
475 let ParserMatchClass = PPCDirectBrAsmOperand;
477 def PPCCondBrAsmOperand : AsmOperandClass {
478 let Name = "CondBr"; let PredicateMethod = "isCondBr";
479 let RenderMethod = "addBranchTargetOperands";
481 def condbrtarget : Operand<OtherVT> {
482 let PrintMethod = "printBranchOperand";
483 let EncoderMethod = "getCondBrEncoding";
484 let ParserMatchClass = PPCCondBrAsmOperand;
486 def abscondbrtarget : Operand<OtherVT> {
487 let PrintMethod = "printAbsBranchOperand";
488 let EncoderMethod = "getAbsCondBrEncoding";
489 let ParserMatchClass = PPCCondBrAsmOperand;
491 def calltarget : Operand<iPTR> {
492 let PrintMethod = "printBranchOperand";
493 let EncoderMethod = "getDirectBrEncoding";
494 let ParserMatchClass = PPCDirectBrAsmOperand;
496 def abscalltarget : Operand<iPTR> {
497 let PrintMethod = "printAbsBranchOperand";
498 let EncoderMethod = "getAbsDirectBrEncoding";
499 let ParserMatchClass = PPCDirectBrAsmOperand;
501 def PPCCRBitMaskOperand : AsmOperandClass {
502 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
504 def crbitm: Operand<i8> {
505 let PrintMethod = "printcrbitm";
506 let EncoderMethod = "get_crbitm_encoding";
507 let ParserMatchClass = PPCCRBitMaskOperand;
510 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
511 def PPCRegGxRCNoR0Operand : AsmOperandClass {
512 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
514 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
515 let ParserMatchClass = PPCRegGxRCNoR0Operand;
517 // A version of ptr_rc usable with the asm parser.
518 def PPCRegGxRCOperand : AsmOperandClass {
519 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
521 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
522 let ParserMatchClass = PPCRegGxRCOperand;
525 def PPCDispRIOperand : AsmOperandClass {
526 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
527 let RenderMethod = "addImmOperands";
529 def dispRI : Operand<iPTR> {
530 let ParserMatchClass = PPCDispRIOperand;
532 def PPCDispRIXOperand : AsmOperandClass {
533 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
534 let RenderMethod = "addImmOperands";
536 def dispRIX : Operand<iPTR> {
537 let ParserMatchClass = PPCDispRIXOperand;
540 def memri : Operand<iPTR> {
541 let PrintMethod = "printMemRegImm";
542 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
543 let EncoderMethod = "getMemRIEncoding";
545 def memrr : Operand<iPTR> {
546 let PrintMethod = "printMemRegReg";
547 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
549 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
550 let PrintMethod = "printMemRegImm";
551 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
552 let EncoderMethod = "getMemRIXEncoding";
555 // A single-register address. This is used with the SjLj
556 // pseudo-instructions.
557 def memr : Operand<iPTR> {
558 let MIOperandInfo = (ops ptr_rc:$ptrreg);
561 // PowerPC Predicate operand.
562 def pred : Operand<OtherVT> {
563 let PrintMethod = "printPredicateOperand";
564 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
567 // Define PowerPC specific addressing mode.
568 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
569 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
570 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
571 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
573 // The address in a single register. This is used with the SjLj
574 // pseudo-instructions.
575 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
577 /// This is just the offset part of iaddr, used for preinc.
578 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
580 //===----------------------------------------------------------------------===//
581 // PowerPC Instruction Predicate Definitions.
582 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
583 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
584 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
586 //===----------------------------------------------------------------------===//
587 // PowerPC Multiclass Definitions.
589 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
590 string asmbase, string asmstr, InstrItinClass itin,
592 let BaseName = asmbase in {
593 def NAME : XForm_6<opcode, xo, OOL, IOL,
594 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
595 pattern>, RecFormRel;
597 def o : XForm_6<opcode, xo, OOL, IOL,
598 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
599 []>, isDOT, RecFormRel;
603 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
604 string asmbase, string asmstr, InstrItinClass itin,
606 let BaseName = asmbase in {
607 let Defs = [CARRY] in
608 def NAME : XForm_6<opcode, xo, OOL, IOL,
609 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
610 pattern>, RecFormRel;
611 let Defs = [CARRY, CR0] in
612 def o : XForm_6<opcode, xo, OOL, IOL,
613 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
614 []>, isDOT, RecFormRel;
618 multiclass XForm_10r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
619 string asmbase, string asmstr, InstrItinClass itin,
621 let BaseName = asmbase in {
622 def NAME : XForm_10<opcode, xo, OOL, IOL,
623 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
624 pattern>, RecFormRel;
626 def o : XForm_10<opcode, xo, OOL, IOL,
627 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
628 []>, isDOT, RecFormRel;
632 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
633 string asmbase, string asmstr, InstrItinClass itin,
635 let BaseName = asmbase in {
636 let Defs = [CARRY] in
637 def NAME : XForm_10<opcode, xo, OOL, IOL,
638 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
639 pattern>, RecFormRel;
640 let Defs = [CARRY, CR0] in
641 def o : XForm_10<opcode, xo, OOL, IOL,
642 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
643 []>, isDOT, RecFormRel;
647 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
648 string asmbase, string asmstr, InstrItinClass itin,
650 let BaseName = asmbase in {
651 def NAME : XForm_11<opcode, xo, OOL, IOL,
652 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
653 pattern>, RecFormRel;
655 def o : XForm_11<opcode, xo, OOL, IOL,
656 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
657 []>, isDOT, RecFormRel;
661 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
662 string asmbase, string asmstr, InstrItinClass itin,
664 let BaseName = asmbase in {
665 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
666 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
667 pattern>, RecFormRel;
669 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
670 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
671 []>, isDOT, RecFormRel;
675 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
676 string asmbase, string asmstr, InstrItinClass itin,
678 let BaseName = asmbase in {
679 let Defs = [CARRY] in
680 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
681 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
682 pattern>, RecFormRel;
683 let Defs = [CARRY, CR0] in
684 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
685 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
686 []>, isDOT, RecFormRel;
690 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
691 string asmbase, string asmstr, InstrItinClass itin,
693 let BaseName = asmbase in {
694 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
695 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
696 pattern>, RecFormRel;
698 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
699 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
700 []>, isDOT, RecFormRel;
704 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
705 string asmbase, string asmstr, InstrItinClass itin,
707 let BaseName = asmbase in {
708 let Defs = [CARRY] in
709 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
710 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
711 pattern>, RecFormRel;
712 let Defs = [CARRY, CR0] in
713 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
714 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
715 []>, isDOT, RecFormRel;
719 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
720 string asmbase, string asmstr, InstrItinClass itin,
722 let BaseName = asmbase in {
723 def NAME : MForm_2<opcode, OOL, IOL,
724 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
725 pattern>, RecFormRel;
727 def o : MForm_2<opcode, OOL, IOL,
728 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
729 []>, isDOT, RecFormRel;
733 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
734 string asmbase, string asmstr, InstrItinClass itin,
736 let BaseName = asmbase in {
737 def NAME : MDForm_1<opcode, xo, OOL, IOL,
738 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
739 pattern>, RecFormRel;
741 def o : MDForm_1<opcode, xo, OOL, IOL,
742 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
743 []>, isDOT, RecFormRel;
747 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
748 string asmbase, string asmstr, InstrItinClass itin,
750 let BaseName = asmbase in {
751 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
752 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
753 pattern>, RecFormRel;
755 def o : MDSForm_1<opcode, xo, OOL, IOL,
756 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
757 []>, isDOT, RecFormRel;
761 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
762 string asmbase, string asmstr, InstrItinClass itin,
764 let BaseName = asmbase in {
765 let Defs = [CARRY] in
766 def NAME : XSForm_1<opcode, xo, OOL, IOL,
767 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
768 pattern>, RecFormRel;
769 let Defs = [CARRY, CR0] in
770 def o : XSForm_1<opcode, xo, OOL, IOL,
771 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
772 []>, isDOT, RecFormRel;
776 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
777 string asmbase, string asmstr, InstrItinClass itin,
779 let BaseName = asmbase in {
780 def NAME : XForm_26<opcode, xo, OOL, IOL,
781 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
782 pattern>, RecFormRel;
784 def o : XForm_26<opcode, xo, OOL, IOL,
785 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
786 []>, isDOT, RecFormRel;
790 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
791 string asmbase, string asmstr, InstrItinClass itin,
793 let BaseName = asmbase in {
794 def NAME : XForm_28<opcode, xo, OOL, IOL,
795 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
796 pattern>, RecFormRel;
798 def o : XForm_28<opcode, xo, OOL, IOL,
799 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
800 []>, isDOT, RecFormRel;
804 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
805 string asmbase, string asmstr, InstrItinClass itin,
807 let BaseName = asmbase in {
808 def NAME : AForm_1<opcode, xo, OOL, IOL,
809 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
810 pattern>, RecFormRel;
812 def o : AForm_1<opcode, xo, OOL, IOL,
813 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
814 []>, isDOT, RecFormRel;
818 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
819 string asmbase, string asmstr, InstrItinClass itin,
821 let BaseName = asmbase in {
822 def NAME : AForm_2<opcode, xo, OOL, IOL,
823 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
824 pattern>, RecFormRel;
826 def o : AForm_2<opcode, xo, OOL, IOL,
827 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
828 []>, isDOT, RecFormRel;
832 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
833 string asmbase, string asmstr, InstrItinClass itin,
835 let BaseName = asmbase in {
836 def NAME : AForm_3<opcode, xo, OOL, IOL,
837 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
838 pattern>, RecFormRel;
840 def o : AForm_3<opcode, xo, OOL, IOL,
841 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
842 []>, isDOT, RecFormRel;
846 //===----------------------------------------------------------------------===//
847 // PowerPC Instruction Definitions.
849 // Pseudo-instructions:
851 let hasCtrlDep = 1 in {
852 let Defs = [R1], Uses = [R1] in {
853 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
854 [(callseq_start timm:$amt)]>;
855 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
856 [(callseq_end timm:$amt1, timm:$amt2)]>;
859 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
860 "UPDATE_VRSAVE $rD, $rS", []>;
863 let Defs = [R1], Uses = [R1] in
864 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
866 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
868 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
869 // instruction selection into a branch sequence.
870 let usesCustomInserter = 1, // Expanded after instruction selection.
871 PPC970_Single = 1 in {
872 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
873 // because either operand might become the first operand in an isel, and
874 // that operand cannot be r0.
875 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
876 gprc_nor0:$T, gprc_nor0:$F,
877 i32imm:$BROPC), "#SELECT_CC_I4",
879 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
880 g8rc_nox0:$T, g8rc_nox0:$F,
881 i32imm:$BROPC), "#SELECT_CC_I8",
883 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
884 i32imm:$BROPC), "#SELECT_CC_F4",
886 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
887 i32imm:$BROPC), "#SELECT_CC_F8",
889 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
890 i32imm:$BROPC), "#SELECT_CC_VRRC",
894 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
895 // scavenge a register for it.
897 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
900 // RESTORE_CR - Indicate that we're restoring the CR register (previously
901 // spilled), so we'll need to scavenge a register for it.
903 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
906 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
907 let isReturn = 1, Uses = [LR, RM] in
908 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", BrB,
910 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
911 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
913 let isCodeGenOnly = 1 in
914 def BCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
915 "b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>;
920 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
923 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
924 let isBarrier = 1 in {
925 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
928 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
932 // BCC represents an arbitrary conditional branch on a predicate.
933 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
934 // a two-value operand where a dag node expects two operands. :(
935 let isCodeGenOnly = 1 in {
936 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
937 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
938 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
939 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
940 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
942 let isReturn = 1, Uses = [LR, RM] in
943 def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
944 "b${cond:cc}lr${cond:pm} ${cond:reg}", BrB, []>;
947 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
948 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
950 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
952 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
954 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
956 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
958 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
962 let Defs = [CTR], Uses = [CTR] in {
963 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
965 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
967 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
969 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
971 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
973 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
975 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
977 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
979 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
981 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
983 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
985 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
990 // The unconditional BCL used by the SjLj setjmp code.
991 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
992 let Defs = [LR], Uses = [RM] in {
993 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
998 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
999 // Convenient aliases for call instructions
1000 let Uses = [RM] in {
1001 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1002 "bl $func", BrB, []>; // See Pat patterns below.
1003 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1004 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
1006 let isCodeGenOnly = 1 in {
1007 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1008 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1009 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1010 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1013 let Uses = [CTR, RM] in {
1014 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1015 "bctrl", BrB, [(PPCbctrl)]>,
1016 Requires<[In32BitMode]>;
1018 let isCodeGenOnly = 1 in
1019 def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1020 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>;
1022 let Uses = [LR, RM] in {
1023 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1026 let isCodeGenOnly = 1 in
1027 def BCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1028 "b${cond:cc}lrl${cond:pm} ${cond:reg}", BrB, []>;
1030 let Defs = [CTR], Uses = [CTR, RM] in {
1031 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1033 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1035 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1037 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1039 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1041 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1043 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1045 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1047 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1049 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1051 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1053 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1056 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1057 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1059 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1060 "bdnzlrl", BrB, []>;
1061 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1062 "bdzlrl+", BrB, []>;
1063 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1064 "bdnzlrl+", BrB, []>;
1065 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1066 "bdzlrl-", BrB, []>;
1067 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1068 "bdnzlrl-", BrB, []>;
1072 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1073 def TCRETURNdi :Pseudo< (outs),
1074 (ins calltarget:$dst, i32imm:$offset),
1075 "#TC_RETURNd $dst $offset",
1079 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1080 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1081 "#TC_RETURNa $func $offset",
1082 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1084 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1085 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1086 "#TC_RETURNr $dst $offset",
1090 let isCodeGenOnly = 1 in {
1092 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1093 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1094 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
1095 Requires<[In32BitMode]>;
1097 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1098 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1099 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1103 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1104 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1105 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1111 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1113 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1114 "#EH_SJLJ_SETJMP32",
1115 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1116 Requires<[In32BitMode]>;
1117 let isTerminator = 1 in
1118 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1119 "#EH_SJLJ_LONGJMP32",
1120 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1121 Requires<[In32BitMode]>;
1124 let isBranch = 1, isTerminator = 1 in {
1125 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1126 "#EH_SjLj_Setup\t$dst", []>;
1130 let PPC970_Unit = 7 in {
1131 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1132 "sc $lev", BrB, [(PPCsc (i32 imm:$lev))]>;
1135 // DCB* instructions.
1136 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
1137 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1138 PPC970_DGroup_Single;
1139 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
1140 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1141 PPC970_DGroup_Single;
1142 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
1143 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1144 PPC970_DGroup_Single;
1145 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
1146 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1147 PPC970_DGroup_Single;
1148 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
1149 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1150 PPC970_DGroup_Single;
1151 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
1152 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1153 PPC970_DGroup_Single;
1154 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
1155 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1156 PPC970_DGroup_Single;
1157 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
1158 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1159 PPC970_DGroup_Single;
1161 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1162 (DCBT xoaddr:$dst)>;
1164 // Atomic operations
1165 let usesCustomInserter = 1 in {
1166 let Defs = [CR0] in {
1167 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1168 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1169 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1170 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1171 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1172 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1173 def ATOMIC_LOAD_AND_I8 : Pseudo<
1174 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1175 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1176 def ATOMIC_LOAD_OR_I8 : Pseudo<
1177 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1178 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1179 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1180 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1181 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1182 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1183 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1184 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1185 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1186 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1187 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1188 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1189 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1190 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1191 def ATOMIC_LOAD_AND_I16 : Pseudo<
1192 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1193 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1194 def ATOMIC_LOAD_OR_I16 : Pseudo<
1195 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1196 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1197 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1198 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1199 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1200 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1201 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1202 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1203 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1204 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1205 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1206 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1207 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1208 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1209 def ATOMIC_LOAD_AND_I32 : Pseudo<
1210 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1211 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1212 def ATOMIC_LOAD_OR_I32 : Pseudo<
1213 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1214 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1215 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1216 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1217 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1218 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1219 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1220 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1222 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1223 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1224 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1225 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1226 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1227 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1228 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1229 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1230 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1232 def ATOMIC_SWAP_I8 : Pseudo<
1233 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1234 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1235 def ATOMIC_SWAP_I16 : Pseudo<
1236 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1237 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1238 def ATOMIC_SWAP_I32 : Pseudo<
1239 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1240 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1244 // Instructions to support atomic operations
1245 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1246 "lwarx $rD, $src", LdStLWARX,
1247 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1250 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1251 "stwcx. $rS, $dst", LdStSTWCX,
1252 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1255 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1256 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
1258 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1259 "twi $to, $rA, $imm", IntTrapW, []>;
1260 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1261 "tw $to, $rA, $rB", IntTrapW, []>;
1262 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1263 "tdi $to, $rA, $imm", IntTrapD, []>;
1264 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1265 "td $to, $rA, $rB", IntTrapD, []>;
1267 //===----------------------------------------------------------------------===//
1268 // PPC32 Load Instructions.
1271 // Unindexed (r+i) Loads.
1272 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1273 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1274 "lbz $rD, $src", LdStLoad,
1275 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1276 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1277 "lha $rD, $src", LdStLHA,
1278 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1279 PPC970_DGroup_Cracked;
1280 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1281 "lhz $rD, $src", LdStLoad,
1282 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1283 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1284 "lwz $rD, $src", LdStLoad,
1285 [(set i32:$rD, (load iaddr:$src))]>;
1287 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1288 "lfs $rD, $src", LdStLFD,
1289 [(set f32:$rD, (load iaddr:$src))]>;
1290 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1291 "lfd $rD, $src", LdStLFD,
1292 [(set f64:$rD, (load iaddr:$src))]>;
1295 // Unindexed (r+i) Loads with Update (preinc).
1296 let mayLoad = 1, neverHasSideEffects = 1 in {
1297 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1298 "lbzu $rD, $addr", LdStLoadUpd,
1299 []>, RegConstraint<"$addr.reg = $ea_result">,
1300 NoEncode<"$ea_result">;
1302 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1303 "lhau $rD, $addr", LdStLHAU,
1304 []>, RegConstraint<"$addr.reg = $ea_result">,
1305 NoEncode<"$ea_result">;
1307 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1308 "lhzu $rD, $addr", LdStLoadUpd,
1309 []>, RegConstraint<"$addr.reg = $ea_result">,
1310 NoEncode<"$ea_result">;
1312 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1313 "lwzu $rD, $addr", LdStLoadUpd,
1314 []>, RegConstraint<"$addr.reg = $ea_result">,
1315 NoEncode<"$ea_result">;
1317 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1318 "lfsu $rD, $addr", LdStLFDU,
1319 []>, RegConstraint<"$addr.reg = $ea_result">,
1320 NoEncode<"$ea_result">;
1322 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1323 "lfdu $rD, $addr", LdStLFDU,
1324 []>, RegConstraint<"$addr.reg = $ea_result">,
1325 NoEncode<"$ea_result">;
1328 // Indexed (r+r) Loads with Update (preinc).
1329 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1331 "lbzux $rD, $addr", LdStLoadUpd,
1332 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1333 NoEncode<"$ea_result">;
1335 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1337 "lhaux $rD, $addr", LdStLHAU,
1338 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1339 NoEncode<"$ea_result">;
1341 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1343 "lhzux $rD, $addr", LdStLoadUpd,
1344 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1345 NoEncode<"$ea_result">;
1347 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1349 "lwzux $rD, $addr", LdStLoadUpd,
1350 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1351 NoEncode<"$ea_result">;
1353 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1355 "lfsux $rD, $addr", LdStLFDU,
1356 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1357 NoEncode<"$ea_result">;
1359 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1361 "lfdux $rD, $addr", LdStLFDU,
1362 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1363 NoEncode<"$ea_result">;
1367 // Indexed (r+r) Loads.
1369 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1370 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1371 "lbzx $rD, $src", LdStLoad,
1372 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1373 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1374 "lhax $rD, $src", LdStLHA,
1375 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1376 PPC970_DGroup_Cracked;
1377 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1378 "lhzx $rD, $src", LdStLoad,
1379 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1380 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1381 "lwzx $rD, $src", LdStLoad,
1382 [(set i32:$rD, (load xaddr:$src))]>;
1385 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1386 "lhbrx $rD, $src", LdStLoad,
1387 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1388 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1389 "lwbrx $rD, $src", LdStLoad,
1390 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1392 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1393 "lfsx $frD, $src", LdStLFD,
1394 [(set f32:$frD, (load xaddr:$src))]>;
1395 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1396 "lfdx $frD, $src", LdStLFD,
1397 [(set f64:$frD, (load xaddr:$src))]>;
1399 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1400 "lfiwax $frD, $src", LdStLFD,
1401 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1402 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1403 "lfiwzx $frD, $src", LdStLFD,
1404 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1408 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1409 "lmw $rD, $src", LdStLMW, []>;
1411 //===----------------------------------------------------------------------===//
1412 // PPC32 Store Instructions.
1415 // Unindexed (r+i) Stores.
1416 let PPC970_Unit = 2 in {
1417 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1418 "stb $rS, $src", LdStStore,
1419 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1420 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1421 "sth $rS, $src", LdStStore,
1422 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1423 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1424 "stw $rS, $src", LdStStore,
1425 [(store i32:$rS, iaddr:$src)]>;
1426 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1427 "stfs $rS, $dst", LdStSTFD,
1428 [(store f32:$rS, iaddr:$dst)]>;
1429 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1430 "stfd $rS, $dst", LdStSTFD,
1431 [(store f64:$rS, iaddr:$dst)]>;
1434 // Unindexed (r+i) Stores with Update (preinc).
1435 let PPC970_Unit = 2, mayStore = 1 in {
1436 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1437 "stbu $rS, $dst", LdStStoreUpd, []>,
1438 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1439 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1440 "sthu $rS, $dst", LdStStoreUpd, []>,
1441 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1442 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1443 "stwu $rS, $dst", LdStStoreUpd, []>,
1444 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1445 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1446 "stfsu $rS, $dst", LdStSTFDU, []>,
1447 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1448 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1449 "stfdu $rS, $dst", LdStSTFDU, []>,
1450 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1453 // Patterns to match the pre-inc stores. We can't put the patterns on
1454 // the instruction definitions directly as ISel wants the address base
1455 // and offset to be separate operands, not a single complex operand.
1456 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1457 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1458 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1459 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1460 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1461 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1462 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1463 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1464 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1465 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1467 // Indexed (r+r) Stores.
1468 let PPC970_Unit = 2 in {
1469 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1470 "stbx $rS, $dst", LdStStore,
1471 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1472 PPC970_DGroup_Cracked;
1473 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1474 "sthx $rS, $dst", LdStStore,
1475 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1476 PPC970_DGroup_Cracked;
1477 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1478 "stwx $rS, $dst", LdStStore,
1479 [(store i32:$rS, xaddr:$dst)]>,
1480 PPC970_DGroup_Cracked;
1482 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1483 "sthbrx $rS, $dst", LdStStore,
1484 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1485 PPC970_DGroup_Cracked;
1486 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1487 "stwbrx $rS, $dst", LdStStore,
1488 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1489 PPC970_DGroup_Cracked;
1491 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1492 "stfiwx $frS, $dst", LdStSTFD,
1493 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1495 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1496 "stfsx $frS, $dst", LdStSTFD,
1497 [(store f32:$frS, xaddr:$dst)]>;
1498 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1499 "stfdx $frS, $dst", LdStSTFD,
1500 [(store f64:$frS, xaddr:$dst)]>;
1503 // Indexed (r+r) Stores with Update (preinc).
1504 let PPC970_Unit = 2, mayStore = 1 in {
1505 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1506 "stbux $rS, $dst", LdStStoreUpd, []>,
1507 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1508 PPC970_DGroup_Cracked;
1509 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1510 "sthux $rS, $dst", LdStStoreUpd, []>,
1511 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1512 PPC970_DGroup_Cracked;
1513 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1514 "stwux $rS, $dst", LdStStoreUpd, []>,
1515 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1516 PPC970_DGroup_Cracked;
1517 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1518 "stfsux $rS, $dst", LdStSTFDU, []>,
1519 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1520 PPC970_DGroup_Cracked;
1521 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1522 "stfdux $rS, $dst", LdStSTFDU, []>,
1523 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1524 PPC970_DGroup_Cracked;
1527 // Patterns to match the pre-inc stores. We can't put the patterns on
1528 // the instruction definitions directly as ISel wants the address base
1529 // and offset to be separate operands, not a single complex operand.
1530 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1531 (STBUX $rS, $ptrreg, $ptroff)>;
1532 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1533 (STHUX $rS, $ptrreg, $ptroff)>;
1534 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1535 (STWUX $rS, $ptrreg, $ptroff)>;
1536 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1537 (STFSUX $rS, $ptrreg, $ptroff)>;
1538 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1539 (STFDUX $rS, $ptrreg, $ptroff)>;
1542 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1543 "stmw $rS, $dst", LdStLMW, []>;
1545 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1546 "sync $L", LdStSync, []>;
1547 def : Pat<(int_ppc_sync), (SYNC 0)>;
1549 //===----------------------------------------------------------------------===//
1550 // PPC32 Arithmetic Instructions.
1553 let PPC970_Unit = 1 in { // FXU Operations.
1554 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1555 "addi $rD, $rA, $imm", IntSimple,
1556 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1557 let BaseName = "addic" in {
1558 let Defs = [CARRY] in
1559 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1560 "addic $rD, $rA, $imm", IntGeneral,
1561 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1562 RecFormRel, PPC970_DGroup_Cracked;
1563 let Defs = [CARRY, CR0] in
1564 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1565 "addic. $rD, $rA, $imm", IntGeneral,
1566 []>, isDOT, RecFormRel;
1568 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1569 "addis $rD, $rA, $imm", IntSimple,
1570 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1571 let isCodeGenOnly = 1 in
1572 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1573 "la $rD, $sym($rA)", IntGeneral,
1574 [(set i32:$rD, (add i32:$rA,
1575 (PPClo tglobaladdr:$sym, 0)))]>;
1576 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1577 "mulli $rD, $rA, $imm", IntMulLI,
1578 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1579 let Defs = [CARRY] in
1580 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1581 "subfic $rD, $rA, $imm", IntGeneral,
1582 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1584 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1585 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1586 "li $rD, $imm", IntSimple,
1587 [(set i32:$rD, imm32SExt16:$imm)]>;
1588 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1589 "lis $rD, $imm", IntSimple,
1590 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1594 let PPC970_Unit = 1 in { // FXU Operations.
1595 let Defs = [CR0] in {
1596 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1597 "andi. $dst, $src1, $src2", IntGeneral,
1598 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1600 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1601 "andis. $dst, $src1, $src2", IntGeneral,
1602 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1605 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1606 "ori $dst, $src1, $src2", IntSimple,
1607 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1608 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1609 "oris $dst, $src1, $src2", IntSimple,
1610 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1611 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1612 "xori $dst, $src1, $src2", IntSimple,
1613 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1614 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1615 "xoris $dst, $src1, $src2", IntSimple,
1616 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1617 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1619 let isCompare = 1, neverHasSideEffects = 1 in {
1620 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1621 "cmpwi $crD, $rA, $imm", IntCompare>;
1622 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1623 "cmplwi $dst, $src1, $src2", IntCompare>;
1627 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1628 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1629 "nand", "$rA, $rS, $rB", IntSimple,
1630 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1631 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1632 "and", "$rA, $rS, $rB", IntSimple,
1633 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1634 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1635 "andc", "$rA, $rS, $rB", IntSimple,
1636 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1637 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1638 "or", "$rA, $rS, $rB", IntSimple,
1639 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1640 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1641 "nor", "$rA, $rS, $rB", IntSimple,
1642 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1643 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1644 "orc", "$rA, $rS, $rB", IntSimple,
1645 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1646 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1647 "eqv", "$rA, $rS, $rB", IntSimple,
1648 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1649 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1650 "xor", "$rA, $rS, $rB", IntSimple,
1651 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1652 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1653 "slw", "$rA, $rS, $rB", IntGeneral,
1654 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1655 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1656 "srw", "$rA, $rS, $rB", IntGeneral,
1657 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1658 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1659 "sraw", "$rA, $rS, $rB", IntShift,
1660 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1663 let PPC970_Unit = 1 in { // FXU Operations.
1664 let neverHasSideEffects = 1 in {
1665 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1666 "srawi", "$rA, $rS, $SH", IntShift,
1667 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1668 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1669 "cntlzw", "$rA, $rS", IntGeneral,
1670 [(set i32:$rA, (ctlz i32:$rS))]>;
1671 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1672 "extsb", "$rA, $rS", IntSimple,
1673 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1674 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1675 "extsh", "$rA, $rS", IntSimple,
1676 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1678 let isCompare = 1, neverHasSideEffects = 1 in {
1679 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1680 "cmpw $crD, $rA, $rB", IntCompare>;
1681 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1682 "cmplw $crD, $rA, $rB", IntCompare>;
1685 let PPC970_Unit = 3 in { // FPU Operations.
1686 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1687 // "fcmpo $crD, $fA, $fB", FPCompare>;
1688 let isCompare = 1, neverHasSideEffects = 1 in {
1689 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1690 "fcmpu $crD, $fA, $fB", FPCompare>;
1691 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1692 "fcmpu $crD, $fA, $fB", FPCompare>;
1695 let Uses = [RM] in {
1696 let neverHasSideEffects = 1 in {
1697 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1698 "fctiw", "$frD, $frB", FPGeneral,
1699 [(set f64:$frD, (PPCfctiw f64:$frB))]>;
1700 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1701 "fctiwz", "$frD, $frB", FPGeneral,
1702 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1704 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1705 "frsp", "$frD, $frB", FPGeneral,
1706 [(set f32:$frD, (fround f64:$frB))]>;
1708 let Interpretation64Bit = 1 in
1709 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1710 "frin", "$frD, $frB", FPGeneral,
1711 [(set f64:$frD, (frnd f64:$frB))]>;
1712 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1713 "frin", "$frD, $frB", FPGeneral,
1714 [(set f32:$frD, (frnd f32:$frB))]>;
1717 let neverHasSideEffects = 1 in {
1718 let Interpretation64Bit = 1 in
1719 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1720 "frip", "$frD, $frB", FPGeneral,
1721 [(set f64:$frD, (fceil f64:$frB))]>;
1722 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1723 "frip", "$frD, $frB", FPGeneral,
1724 [(set f32:$frD, (fceil f32:$frB))]>;
1725 let Interpretation64Bit = 1 in
1726 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1727 "friz", "$frD, $frB", FPGeneral,
1728 [(set f64:$frD, (ftrunc f64:$frB))]>;
1729 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1730 "friz", "$frD, $frB", FPGeneral,
1731 [(set f32:$frD, (ftrunc f32:$frB))]>;
1732 let Interpretation64Bit = 1 in
1733 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1734 "frim", "$frD, $frB", FPGeneral,
1735 [(set f64:$frD, (ffloor f64:$frB))]>;
1736 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1737 "frim", "$frD, $frB", FPGeneral,
1738 [(set f32:$frD, (ffloor f32:$frB))]>;
1740 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1741 "fsqrt", "$frD, $frB", FPSqrt,
1742 [(set f64:$frD, (fsqrt f64:$frB))]>;
1743 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1744 "fsqrts", "$frD, $frB", FPSqrt,
1745 [(set f32:$frD, (fsqrt f32:$frB))]>;
1750 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1751 /// often coalesced away and we don't want the dispatch group builder to think
1752 /// that they will fill slots (which could cause the load of a LSU reject to
1753 /// sneak into a d-group with a store).
1754 let neverHasSideEffects = 1 in
1755 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1756 "fmr", "$frD, $frB", FPGeneral,
1757 []>, // (set f32:$frD, f32:$frB)
1760 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1761 // These are artificially split into two different forms, for 4/8 byte FP.
1762 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1763 "fabs", "$frD, $frB", FPGeneral,
1764 [(set f32:$frD, (fabs f32:$frB))]>;
1765 let Interpretation64Bit = 1 in
1766 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1767 "fabs", "$frD, $frB", FPGeneral,
1768 [(set f64:$frD, (fabs f64:$frB))]>;
1769 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1770 "fnabs", "$frD, $frB", FPGeneral,
1771 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1772 let Interpretation64Bit = 1 in
1773 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1774 "fnabs", "$frD, $frB", FPGeneral,
1775 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1776 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1777 "fneg", "$frD, $frB", FPGeneral,
1778 [(set f32:$frD, (fneg f32:$frB))]>;
1779 let Interpretation64Bit = 1 in
1780 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1781 "fneg", "$frD, $frB", FPGeneral,
1782 [(set f64:$frD, (fneg f64:$frB))]>;
1784 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1785 "fcpsgn", "$frD, $frA, $frB", FPGeneral,
1786 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1787 let Interpretation64Bit = 1 in
1788 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1789 "fcpsgn", "$frD, $frA, $frB", FPGeneral,
1790 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1792 // Reciprocal estimates.
1793 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1794 "fre", "$frD, $frB", FPGeneral,
1795 [(set f64:$frD, (PPCfre f64:$frB))]>;
1796 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1797 "fres", "$frD, $frB", FPGeneral,
1798 [(set f32:$frD, (PPCfre f32:$frB))]>;
1799 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1800 "frsqrte", "$frD, $frB", FPGeneral,
1801 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1802 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1803 "frsqrtes", "$frD, $frB", FPGeneral,
1804 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1807 // XL-Form instructions. condition register logical ops.
1809 let neverHasSideEffects = 1 in
1810 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1811 "mcrf $BF, $BFA", BrMCR>,
1812 PPC970_DGroup_First, PPC970_Unit_CRU;
1814 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
1815 (ins crbitrc:$CRA, crbitrc:$CRB),
1816 "crand $CRD, $CRA, $CRB", BrCR, []>;
1818 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
1819 (ins crbitrc:$CRA, crbitrc:$CRB),
1820 "crnand $CRD, $CRA, $CRB", BrCR, []>;
1822 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
1823 (ins crbitrc:$CRA, crbitrc:$CRB),
1824 "cror $CRD, $CRA, $CRB", BrCR, []>;
1826 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
1827 (ins crbitrc:$CRA, crbitrc:$CRB),
1828 "crxor $CRD, $CRA, $CRB", BrCR, []>;
1830 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
1831 (ins crbitrc:$CRA, crbitrc:$CRB),
1832 "crnor $CRD, $CRA, $CRB", BrCR, []>;
1834 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
1835 (ins crbitrc:$CRA, crbitrc:$CRB),
1836 "creqv $CRD, $CRA, $CRB", BrCR, []>;
1838 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
1839 (ins crbitrc:$CRA, crbitrc:$CRB),
1840 "crandc $CRD, $CRA, $CRB", BrCR, []>;
1842 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
1843 (ins crbitrc:$CRA, crbitrc:$CRB),
1844 "crorc $CRD, $CRA, $CRB", BrCR, []>;
1846 let isCodeGenOnly = 1 in {
1847 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
1848 "creqv $dst, $dst, $dst", BrCR,
1851 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
1852 "crxor $dst, $dst, $dst", BrCR,
1855 let Defs = [CR1EQ], CRD = 6 in {
1856 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1857 "creqv 6, 6, 6", BrCR,
1860 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1861 "crxor 6, 6, 6", BrCR,
1866 // XFX-Form instructions. Instructions that deal with SPRs.
1869 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
1870 "mfspr $RT, $SPR", SprMFSPR>;
1871 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
1872 "mtspr $SPR, $RT", SprMTSPR>;
1874 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
1875 "mftb $RT, $SPR", SprMFTB>, Deprecated<DeprecatedMFTB>;
1877 let Uses = [CTR] in {
1878 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
1879 "mfctr $rT", SprMFSPR>,
1880 PPC970_DGroup_First, PPC970_Unit_FXU;
1882 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1883 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1884 "mtctr $rS", SprMTSPR>,
1885 PPC970_DGroup_First, PPC970_Unit_FXU;
1887 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
1888 let Pattern = [(int_ppc_mtctr i32:$rS)] in
1889 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1890 "mtctr $rS", SprMTSPR>,
1891 PPC970_DGroup_First, PPC970_Unit_FXU;
1894 let Defs = [LR] in {
1895 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
1896 "mtlr $rS", SprMTSPR>,
1897 PPC970_DGroup_First, PPC970_Unit_FXU;
1899 let Uses = [LR] in {
1900 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
1901 "mflr $rT", SprMFSPR>,
1902 PPC970_DGroup_First, PPC970_Unit_FXU;
1905 let isCodeGenOnly = 1 in {
1906 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
1907 // like a GPR on the PPC970. As such, copies in and out have the same
1908 // performance characteristics as an OR instruction.
1909 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
1910 "mtspr 256, $rS", IntGeneral>,
1911 PPC970_DGroup_Single, PPC970_Unit_FXU;
1912 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
1913 "mfspr $rT, 256", IntGeneral>,
1914 PPC970_DGroup_First, PPC970_Unit_FXU;
1916 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1917 (outs VRSAVERC:$reg), (ins gprc:$rS),
1918 "mtspr 256, $rS", IntGeneral>,
1919 PPC970_DGroup_Single, PPC970_Unit_FXU;
1920 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
1921 (ins VRSAVERC:$reg),
1922 "mfspr $rT, 256", IntGeneral>,
1923 PPC970_DGroup_First, PPC970_Unit_FXU;
1926 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1927 // so we'll need to scavenge a register for it.
1929 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1930 "#SPILL_VRSAVE", []>;
1932 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1933 // spilled), so we'll need to scavenge a register for it.
1935 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1936 "#RESTORE_VRSAVE", []>;
1938 let neverHasSideEffects = 1 in {
1939 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
1940 "mtocrf $FXM, $ST", BrMCRX>,
1941 PPC970_DGroup_First, PPC970_Unit_CRU;
1943 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
1944 "mtcrf $FXM, $rS", BrMCRX>,
1945 PPC970_MicroCode, PPC970_Unit_CRU;
1947 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
1948 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
1949 "mfocrf $rT, $FXM", SprMFCR>,
1950 PPC970_DGroup_First, PPC970_Unit_CRU;
1952 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
1953 "mfcr $rT", SprMFCR>,
1954 PPC970_MicroCode, PPC970_Unit_CRU;
1955 } // neverHasSideEffects = 1
1957 // Pseudo instruction to perform FADD in round-to-zero mode.
1958 let usesCustomInserter = 1, Uses = [RM] in {
1959 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
1960 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
1963 // The above pseudo gets expanded to make use of the following instructions
1964 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
1965 let Uses = [RM], Defs = [RM] in {
1966 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1967 "mtfsb0 $FM", IntMTFSB0, []>,
1968 PPC970_DGroup_Single, PPC970_Unit_FPU;
1969 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1970 "mtfsb1 $FM", IntMTFSB0, []>,
1971 PPC970_DGroup_Single, PPC970_Unit_FPU;
1972 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
1973 "mtfsf $FM, $rT", IntMTFSB0, []>,
1974 PPC970_DGroup_Single, PPC970_Unit_FPU;
1976 let Uses = [RM] in {
1977 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
1978 "mffs $rT", IntMFFS,
1979 [(set f64:$rT, (PPCmffs))]>,
1980 PPC970_DGroup_Single, PPC970_Unit_FPU;
1984 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1985 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1987 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1988 "add", "$rT, $rA, $rB", IntSimple,
1989 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
1990 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1991 "addc", "$rT, $rA, $rB", IntGeneral,
1992 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
1993 PPC970_DGroup_Cracked;
1994 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1995 "divw", "$rT, $rA, $rB", IntDivW,
1996 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
1997 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1998 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1999 "divwu", "$rT, $rA, $rB", IntDivW,
2000 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2001 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2002 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2003 "mulhw", "$rT, $rA, $rB", IntMulHW,
2004 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2005 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2006 "mulhwu", "$rT, $rA, $rB", IntMulHWU,
2007 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2008 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2009 "mullw", "$rT, $rA, $rB", IntMulHW,
2010 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2011 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2012 "subf", "$rT, $rA, $rB", IntGeneral,
2013 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2014 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2015 "subfc", "$rT, $rA, $rB", IntGeneral,
2016 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2017 PPC970_DGroup_Cracked;
2018 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2019 "neg", "$rT, $rA", IntSimple,
2020 [(set i32:$rT, (ineg i32:$rA))]>;
2021 let Uses = [CARRY] in {
2022 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2023 "adde", "$rT, $rA, $rB", IntGeneral,
2024 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2025 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2026 "addme", "$rT, $rA", IntGeneral,
2027 [(set i32:$rT, (adde i32:$rA, -1))]>;
2028 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2029 "addze", "$rT, $rA", IntGeneral,
2030 [(set i32:$rT, (adde i32:$rA, 0))]>;
2031 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2032 "subfe", "$rT, $rA, $rB", IntGeneral,
2033 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2034 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2035 "subfme", "$rT, $rA", IntGeneral,
2036 [(set i32:$rT, (sube -1, i32:$rA))]>;
2037 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2038 "subfze", "$rT, $rA", IntGeneral,
2039 [(set i32:$rT, (sube 0, i32:$rA))]>;
2043 // A-Form instructions. Most of the instructions executed in the FPU are of
2046 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
2047 let Uses = [RM] in {
2048 defm FMADD : AForm_1r<63, 29,
2049 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2050 "fmadd", "$FRT, $FRA, $FRC, $FRB", FPFused,
2051 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2052 defm FMADDS : AForm_1r<59, 29,
2053 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2054 "fmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2055 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2056 defm FMSUB : AForm_1r<63, 28,
2057 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2058 "fmsub", "$FRT, $FRA, $FRC, $FRB", FPFused,
2060 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2061 defm FMSUBS : AForm_1r<59, 28,
2062 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2063 "fmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2065 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2066 defm FNMADD : AForm_1r<63, 31,
2067 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2068 "fnmadd", "$FRT, $FRA, $FRC, $FRB", FPFused,
2070 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2071 defm FNMADDS : AForm_1r<59, 31,
2072 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2073 "fnmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2075 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2076 defm FNMSUB : AForm_1r<63, 30,
2077 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2078 "fnmsub", "$FRT, $FRA, $FRC, $FRB", FPFused,
2079 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2080 (fneg f64:$FRB))))]>;
2081 defm FNMSUBS : AForm_1r<59, 30,
2082 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2083 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2084 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2085 (fneg f32:$FRB))))]>;
2087 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2088 // having 4 of these, force the comparison to always be an 8-byte double (code
2089 // should use an FMRSD if the input comparison value really wants to be a float)
2090 // and 4/8 byte forms for the result and operand type..
2091 let Interpretation64Bit = 1 in
2092 defm FSELD : AForm_1r<63, 23,
2093 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2094 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2095 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2096 defm FSELS : AForm_1r<63, 23,
2097 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2098 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2099 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2100 let Uses = [RM] in {
2101 defm FADD : AForm_2r<63, 21,
2102 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2103 "fadd", "$FRT, $FRA, $FRB", FPAddSub,
2104 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2105 defm FADDS : AForm_2r<59, 21,
2106 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2107 "fadds", "$FRT, $FRA, $FRB", FPGeneral,
2108 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2109 defm FDIV : AForm_2r<63, 18,
2110 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2111 "fdiv", "$FRT, $FRA, $FRB", FPDivD,
2112 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2113 defm FDIVS : AForm_2r<59, 18,
2114 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2115 "fdivs", "$FRT, $FRA, $FRB", FPDivS,
2116 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2117 defm FMUL : AForm_3r<63, 25,
2118 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2119 "fmul", "$FRT, $FRA, $FRC", FPFused,
2120 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2121 defm FMULS : AForm_3r<59, 25,
2122 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2123 "fmuls", "$FRT, $FRA, $FRC", FPGeneral,
2124 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2125 defm FSUB : AForm_2r<63, 20,
2126 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2127 "fsub", "$FRT, $FRA, $FRB", FPAddSub,
2128 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2129 defm FSUBS : AForm_2r<59, 20,
2130 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2131 "fsubs", "$FRT, $FRA, $FRB", FPGeneral,
2132 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2136 let neverHasSideEffects = 1 in {
2137 let PPC970_Unit = 1 in { // FXU Operations.
2139 def ISEL : AForm_4<31, 15,
2140 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2141 "isel $rT, $rA, $rB, $cond", IntGeneral,
2145 let PPC970_Unit = 1 in { // FXU Operations.
2146 // M-Form instructions. rotate and mask instructions.
2148 let isCommutable = 1 in {
2149 // RLWIMI can be commuted if the rotate amount is zero.
2150 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2151 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2152 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", IntRotate,
2153 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
2156 let BaseName = "rlwinm" in {
2157 def RLWINM : MForm_2<21,
2158 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2159 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
2162 def RLWINMo : MForm_2<21,
2163 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2164 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
2165 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2167 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2168 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2169 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IntGeneral,
2172 } // neverHasSideEffects = 1
2174 //===----------------------------------------------------------------------===//
2175 // PowerPC Instruction Patterns
2178 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2179 def : Pat<(i32 imm:$imm),
2180 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2182 // Implement the 'not' operation with the NOR instruction.
2183 def NOT : Pat<(not i32:$in),
2186 // ADD an arbitrary immediate.
2187 def : Pat<(add i32:$in, imm:$imm),
2188 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2189 // OR an arbitrary immediate.
2190 def : Pat<(or i32:$in, imm:$imm),
2191 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2192 // XOR an arbitrary immediate.
2193 def : Pat<(xor i32:$in, imm:$imm),
2194 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2196 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2197 (SUBFIC $in, imm:$imm)>;
2200 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2201 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2202 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2203 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2206 def : Pat<(rotl i32:$in, i32:$sh),
2207 (RLWNM $in, $sh, 0, 31)>;
2208 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2209 (RLWINM $in, imm:$imm, 0, 31)>;
2212 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2213 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2216 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2217 (BL tglobaladdr:$dst)>;
2218 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2219 (BL texternalsym:$dst)>;
2222 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2223 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2225 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2226 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2228 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2229 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2233 // Hi and Lo for Darwin Global Addresses.
2234 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2235 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2236 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2237 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2238 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2239 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2240 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2241 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2242 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2243 (ADDIS $in, tglobaltlsaddr:$g)>;
2244 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2245 (ADDI $in, tglobaltlsaddr:$g)>;
2246 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2247 (ADDIS $in, tglobaladdr:$g)>;
2248 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2249 (ADDIS $in, tconstpool:$g)>;
2250 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2251 (ADDIS $in, tjumptable:$g)>;
2252 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2253 (ADDIS $in, tblockaddress:$g)>;
2255 // Standard shifts. These are represented separately from the real shifts above
2256 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2258 def : Pat<(sra i32:$rS, i32:$rB),
2260 def : Pat<(srl i32:$rS, i32:$rB),
2262 def : Pat<(shl i32:$rS, i32:$rB),
2265 def : Pat<(zextloadi1 iaddr:$src),
2267 def : Pat<(zextloadi1 xaddr:$src),
2269 def : Pat<(extloadi1 iaddr:$src),
2271 def : Pat<(extloadi1 xaddr:$src),
2273 def : Pat<(extloadi8 iaddr:$src),
2275 def : Pat<(extloadi8 xaddr:$src),
2277 def : Pat<(extloadi16 iaddr:$src),
2279 def : Pat<(extloadi16 xaddr:$src),
2281 def : Pat<(f64 (extloadf32 iaddr:$src)),
2282 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2283 def : Pat<(f64 (extloadf32 xaddr:$src)),
2284 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2286 def : Pat<(f64 (fextend f32:$src)),
2287 (COPY_TO_REGCLASS $src, F8RC)>;
2289 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>;
2291 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2292 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2293 (FNMSUB $A, $C, $B)>;
2294 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2295 (FNMSUB $A, $C, $B)>;
2296 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2297 (FNMSUBS $A, $C, $B)>;
2298 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2299 (FNMSUBS $A, $C, $B)>;
2301 // FCOPYSIGN's operand types need not agree.
2302 def : Pat<(fcopysign f64:$frB, f32:$frA),
2303 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2304 def : Pat<(fcopysign f32:$frB, f64:$frA),
2305 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2307 include "PPCInstrAltivec.td"
2308 include "PPCInstr64Bit.td"
2311 //===----------------------------------------------------------------------===//
2312 // PowerPC Instructions used for assembler/disassembler only
2315 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
2316 "isync", SprISYNC, []>;
2318 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
2319 "icbi $src", LdStICBI, []>;
2321 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
2322 "eieio", LdStLoad, []>;
2324 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
2325 "wait $L", LdStLoad, []>;
2327 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
2328 "mtmsr $RS, $L", SprMTMSR>;
2330 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
2331 "mfmsr $RT", SprMFMSR, []>;
2333 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
2334 "mtmsrd $RS, $L", SprMTMSRD>;
2336 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
2337 "slbie $RB", SprSLBIE, []>;
2339 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
2340 "slbmte $RS, $RB", SprSLBMTE, []>;
2342 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
2343 "slbmfee $RT, $RB", SprSLBMFEE, []>;
2345 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", SprSLBIA, []>;
2347 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
2348 "tlbsync", SprTLBSYNC, []>;
2350 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
2351 "tlbiel $RB", SprTLBIEL, []>;
2353 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
2354 "tlbie $RB,$RS", SprTLBIE, []>;
2356 //===----------------------------------------------------------------------===//
2357 // PowerPC Assembler Instruction Aliases
2360 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
2361 // These are aliases that require C++ handling to convert to the target
2362 // instruction, while InstAliases can be handled directly by tblgen.
2363 class PPCAsmPseudo<string asm, dag iops>
2365 let Namespace = "PPC";
2366 bit PPC64 = 0; // Default value, override with isPPC64
2368 let OutOperandList = (outs);
2369 let InOperandList = iops;
2371 let AsmString = asm;
2372 let isAsmParserOnly = 1;
2376 def : InstAlias<"sc", (SC 0)>;
2378 def : InstAlias<"sync", (SYNC 0)>;
2379 def : InstAlias<"msync", (SYNC 0)>;
2380 def : InstAlias<"lwsync", (SYNC 1)>;
2381 def : InstAlias<"ptesync", (SYNC 2)>;
2383 def : InstAlias<"wait", (WAIT 0)>;
2384 def : InstAlias<"waitrsv", (WAIT 1)>;
2385 def : InstAlias<"waitimpl", (WAIT 2)>;
2387 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
2388 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
2389 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
2390 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
2392 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
2393 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
2395 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
2396 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
2398 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
2400 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2401 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2403 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2404 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2406 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
2408 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
2410 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
2411 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2412 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
2413 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2414 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
2415 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2416 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
2417 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2419 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2420 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2421 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2422 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2424 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
2425 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
2427 def : InstAlias<"mfsprg $RT, 0", (MFSPR gprc:$RT, 272)>;
2428 def : InstAlias<"mfsprg $RT, 1", (MFSPR gprc:$RT, 273)>;
2429 def : InstAlias<"mfsprg $RT, 2", (MFSPR gprc:$RT, 274)>;
2430 def : InstAlias<"mfsprg $RT, 3", (MFSPR gprc:$RT, 275)>;
2432 def : InstAlias<"mfsprg0 $RT", (MFSPR gprc:$RT, 272)>;
2433 def : InstAlias<"mfsprg1 $RT", (MFSPR gprc:$RT, 273)>;
2434 def : InstAlias<"mfsprg2 $RT", (MFSPR gprc:$RT, 274)>;
2435 def : InstAlias<"mfsprg3 $RT", (MFSPR gprc:$RT, 275)>;
2437 def : InstAlias<"mtsprg 0, $RT", (MTSPR 272, gprc:$RT)>;
2438 def : InstAlias<"mtsprg 1, $RT", (MTSPR 273, gprc:$RT)>;
2439 def : InstAlias<"mtsprg 2, $RT", (MTSPR 274, gprc:$RT)>;
2440 def : InstAlias<"mtsprg 3, $RT", (MTSPR 275, gprc:$RT)>;
2442 def : InstAlias<"mtsprg0 $RT", (MTSPR 272, gprc:$RT)>;
2443 def : InstAlias<"mtsprg1 $RT", (MTSPR 273, gprc:$RT)>;
2444 def : InstAlias<"mtsprg2 $RT", (MTSPR 274, gprc:$RT)>;
2445 def : InstAlias<"mtsprg3 $RT", (MTSPR 275, gprc:$RT)>;
2447 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
2449 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
2450 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
2452 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
2454 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
2455 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
2457 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
2458 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
2459 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
2460 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
2462 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
2464 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
2465 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2466 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
2467 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2468 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
2469 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2470 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
2471 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2472 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
2473 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2474 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
2475 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2476 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
2477 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2478 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
2479 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2480 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
2481 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2482 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
2483 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2484 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
2485 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2486 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
2487 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2488 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
2489 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2490 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
2491 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2492 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
2493 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2494 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
2495 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2496 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
2497 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
2498 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
2499 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
2501 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
2502 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
2503 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
2504 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
2505 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
2506 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
2508 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
2509 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2510 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
2511 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2512 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
2513 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2514 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
2515 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2516 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
2517 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2518 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
2519 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2520 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
2521 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2522 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
2523 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2524 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
2525 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2526 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
2527 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2528 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
2529 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2530 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
2531 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2532 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
2533 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2534 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
2535 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2536 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
2537 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
2538 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
2539 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
2541 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
2542 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
2543 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
2544 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
2545 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
2546 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
2548 // These generic branch instruction forms are used for the assembler parser only.
2549 // Defs and Uses are conservative, since we don't know the BO value.
2550 let PPC970_Unit = 7 in {
2551 let Defs = [CTR], Uses = [CTR, RM] in {
2552 def gBC : BForm_3<16, 0, 0, (outs),
2553 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
2554 "bc $bo, $bi, $dst">;
2555 def gBCA : BForm_3<16, 1, 0, (outs),
2556 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
2557 "bca $bo, $bi, $dst">;
2559 let Defs = [LR, CTR], Uses = [CTR, RM] in {
2560 def gBCL : BForm_3<16, 0, 1, (outs),
2561 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
2562 "bcl $bo, $bi, $dst">;
2563 def gBCLA : BForm_3<16, 1, 1, (outs),
2564 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
2565 "bcla $bo, $bi, $dst">;
2567 let Defs = [CTR], Uses = [CTR, LR, RM] in
2568 def gBCLR : XLForm_2<19, 16, 0, (outs),
2569 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2570 "bclr $bo, $bi, $bh", BrB, []>;
2571 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
2572 def gBCLRL : XLForm_2<19, 16, 1, (outs),
2573 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2574 "bclrl $bo, $bi, $bh", BrB, []>;
2575 let Defs = [CTR], Uses = [CTR, LR, RM] in
2576 def gBCCTR : XLForm_2<19, 528, 0, (outs),
2577 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2578 "bcctr $bo, $bi, $bh", BrB, []>;
2579 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
2580 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
2581 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2582 "bcctrl $bo, $bi, $bh", BrB, []>;
2584 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
2585 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
2586 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
2587 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
2589 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
2590 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
2591 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
2592 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
2593 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
2594 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
2595 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
2597 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
2598 : BranchSimpleMnemonic1<name, pm, bo> {
2599 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
2600 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
2602 defm : BranchSimpleMnemonic2<"t", "", 12>;
2603 defm : BranchSimpleMnemonic2<"f", "", 4>;
2604 defm : BranchSimpleMnemonic2<"t", "-", 14>;
2605 defm : BranchSimpleMnemonic2<"f", "-", 6>;
2606 defm : BranchSimpleMnemonic2<"t", "+", 15>;
2607 defm : BranchSimpleMnemonic2<"f", "+", 7>;
2608 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
2609 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
2610 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
2611 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
2613 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
2614 def : InstAlias<"b"#name#pm#" $cc, $dst",
2615 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
2616 def : InstAlias<"b"#name#pm#" $dst",
2617 (BCC bibo, CR0, condbrtarget:$dst)>;
2619 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
2620 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
2621 def : InstAlias<"b"#name#"a"#pm#" $dst",
2622 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
2624 def : InstAlias<"b"#name#"lr"#pm#" $cc",
2625 (BCLR bibo, crrc:$cc)>;
2626 def : InstAlias<"b"#name#"lr"#pm,
2629 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
2630 (BCCTR bibo, crrc:$cc)>;
2631 def : InstAlias<"b"#name#"ctr"#pm,
2634 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
2635 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
2636 def : InstAlias<"b"#name#"l"#pm#" $dst",
2637 (BCCL bibo, CR0, condbrtarget:$dst)>;
2639 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
2640 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
2641 def : InstAlias<"b"#name#"la"#pm#" $dst",
2642 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
2644 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
2645 (BCLRL bibo, crrc:$cc)>;
2646 def : InstAlias<"b"#name#"lrl"#pm,
2649 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
2650 (BCCTRL bibo, crrc:$cc)>;
2651 def : InstAlias<"b"#name#"ctrl"#pm,
2652 (BCCTRL bibo, CR0)>;
2654 multiclass BranchExtendedMnemonic<string name, int bibo> {
2655 defm : BranchExtendedMnemonicPM<name, "", bibo>;
2656 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
2657 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
2659 defm : BranchExtendedMnemonic<"lt", 12>;
2660 defm : BranchExtendedMnemonic<"gt", 44>;
2661 defm : BranchExtendedMnemonic<"eq", 76>;
2662 defm : BranchExtendedMnemonic<"un", 108>;
2663 defm : BranchExtendedMnemonic<"so", 108>;
2664 defm : BranchExtendedMnemonic<"ge", 4>;
2665 defm : BranchExtendedMnemonic<"nl", 4>;
2666 defm : BranchExtendedMnemonic<"le", 36>;
2667 defm : BranchExtendedMnemonic<"ng", 36>;
2668 defm : BranchExtendedMnemonic<"ne", 68>;
2669 defm : BranchExtendedMnemonic<"nu", 100>;
2670 defm : BranchExtendedMnemonic<"ns", 100>;
2672 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
2673 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
2674 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
2675 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
2676 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
2677 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
2678 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
2679 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
2681 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
2682 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
2683 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
2684 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
2685 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm:$imm)>;
2686 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
2687 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm:$imm)>;
2688 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
2690 multiclass TrapExtendedMnemonic<string name, int to> {
2691 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
2692 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
2693 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
2694 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
2696 defm : TrapExtendedMnemonic<"lt", 16>;
2697 defm : TrapExtendedMnemonic<"le", 20>;
2698 defm : TrapExtendedMnemonic<"eq", 4>;
2699 defm : TrapExtendedMnemonic<"ge", 12>;
2700 defm : TrapExtendedMnemonic<"gt", 8>;
2701 defm : TrapExtendedMnemonic<"nl", 12>;
2702 defm : TrapExtendedMnemonic<"ne", 24>;
2703 defm : TrapExtendedMnemonic<"ng", 20>;
2704 defm : TrapExtendedMnemonic<"llt", 2>;
2705 defm : TrapExtendedMnemonic<"lle", 6>;
2706 defm : TrapExtendedMnemonic<"lge", 5>;
2707 defm : TrapExtendedMnemonic<"lgt", 1>;
2708 defm : TrapExtendedMnemonic<"lnl", 5>;
2709 defm : TrapExtendedMnemonic<"lng", 6>;
2710 defm : TrapExtendedMnemonic<"u", 31>;