1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
61 //===----------------------------------------------------------------------===//
62 // PowerPC specific DAG Nodes.
65 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
66 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
68 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
69 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
70 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
71 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
72 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
73 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
74 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
75 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
76 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
77 [SDNPHasChain, SDNPMayStore]>;
78 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
79 [SDNPHasChain, SDNPMayLoad]>;
80 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
81 [SDNPHasChain, SDNPMayLoad]>;
83 // Extract FPSCR (not modeled at the DAG level).
84 def PPCmffs : SDNode<"PPCISD::MFFS",
85 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
87 // Perform FADD in round-to-zero mode.
88 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
91 def PPCfsel : SDNode<"PPCISD::FSEL",
92 // Type constraint for fsel.
93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
96 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
97 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
98 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
99 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
100 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
102 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
103 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
105 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
106 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
107 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
108 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
109 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
110 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
111 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
112 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
114 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
116 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
118 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
119 // amounts. These nodes are generated by the multi-precision shift code.
120 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
121 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
122 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
124 // These are target-independent nodes, but have target-specific formats.
125 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
126 [SDNPHasChain, SDNPOutGlue]>;
127 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
130 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
131 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
134 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
137 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
139 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
140 [SDNPHasChain, SDNPSideEffect,
141 SDNPInGlue, SDNPOutGlue]>;
142 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
143 [SDNPHasChain, SDNPSideEffect,
144 SDNPInGlue, SDNPOutGlue]>;
145 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
147 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
151 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
152 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
154 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
157 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
158 SDTypeProfile<1, 1, [SDTCisInt<0>,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
162 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
166 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
167 [SDNPHasChain, SDNPSideEffect]>;
169 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
170 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
172 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
173 [SDNPHasChain, SDNPOptInGlue]>;
175 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
176 [SDNPHasChain, SDNPMayLoad]>;
177 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
178 [SDNPHasChain, SDNPMayStore]>;
180 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
181 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
182 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
183 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
186 // Instructions to support atomic operations
187 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
188 [SDNPHasChain, SDNPMayLoad]>;
189 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
190 [SDNPHasChain, SDNPMayStore]>;
192 // Instructions to support medium and large code model
193 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
194 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
195 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
198 // Instructions to support dynamic alloca.
199 def SDTDynOp : SDTypeProfile<1, 2, []>;
200 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
202 //===----------------------------------------------------------------------===//
203 // PowerPC specific transformation functions and pattern fragments.
206 def SHL32 : SDNodeXForm<imm, [{
207 // Transformation function: 31 - imm
208 return getI32Imm(31 - N->getZExtValue());
211 def SRL32 : SDNodeXForm<imm, [{
212 // Transformation function: 32 - imm
213 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
216 def LO16 : SDNodeXForm<imm, [{
217 // Transformation function: get the low 16 bits.
218 return getI32Imm((unsigned short)N->getZExtValue());
221 def HI16 : SDNodeXForm<imm, [{
222 // Transformation function: shift the immediate value down into the low bits.
223 return getI32Imm((unsigned)N->getZExtValue() >> 16);
226 def HA16 : SDNodeXForm<imm, [{
227 // Transformation function: shift the immediate value down into the low bits.
228 signed int Val = N->getZExtValue();
229 return getI32Imm((Val - (signed short)Val) >> 16);
231 def MB : SDNodeXForm<imm, [{
232 // Transformation function: get the start bit of a mask
234 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
235 return getI32Imm(mb);
238 def ME : SDNodeXForm<imm, [{
239 // Transformation function: get the end bit of a mask
241 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
242 return getI32Imm(me);
244 def maskimm32 : PatLeaf<(imm), [{
245 // maskImm predicate - True if immediate is a run of ones.
247 if (N->getValueType(0) == MVT::i32)
248 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
253 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
254 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
255 // sign extended field. Used by instructions like 'addi'.
256 return (int32_t)Imm == (short)Imm;
258 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
259 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
260 // sign extended field. Used by instructions like 'addi'.
261 return (int64_t)Imm == (short)Imm;
263 def immZExt16 : PatLeaf<(imm), [{
264 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
265 // field. Used by instructions like 'ori'.
266 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
269 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
270 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
271 // identical in 32-bit mode, but in 64-bit mode, they return true if the
272 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
274 def imm16ShiftedZExt : PatLeaf<(imm), [{
275 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
276 // immediate are set. Used by instructions like 'xoris'.
277 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
280 def imm16ShiftedSExt : PatLeaf<(imm), [{
281 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
282 // immediate are set. Used by instructions like 'addis'. Identical to
283 // imm16ShiftedZExt in 32-bit mode.
284 if (N->getZExtValue() & 0xFFFF) return false;
285 if (N->getValueType(0) == MVT::i32)
287 // For 64-bit, make sure it is sext right.
288 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
291 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
292 // restricted memrix (4-aligned) constants are alignment sensitive. If these
293 // offsets are hidden behind TOC entries than the values of the lower-order
294 // bits cannot be checked directly. As a result, we need to also incorporate
295 // an alignment check into the relevant patterns.
297 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
298 return cast<LoadSDNode>(N)->getAlignment() >= 4;
300 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
301 (store node:$val, node:$ptr), [{
302 return cast<StoreSDNode>(N)->getAlignment() >= 4;
304 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
305 return cast<LoadSDNode>(N)->getAlignment() >= 4;
307 def aligned4pre_store : PatFrag<
308 (ops node:$val, node:$base, node:$offset),
309 (pre_store node:$val, node:$base, node:$offset), [{
310 return cast<StoreSDNode>(N)->getAlignment() >= 4;
313 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
314 return cast<LoadSDNode>(N)->getAlignment() < 4;
316 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
317 (store node:$val, node:$ptr), [{
318 return cast<StoreSDNode>(N)->getAlignment() < 4;
320 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
321 return cast<LoadSDNode>(N)->getAlignment() < 4;
324 //===----------------------------------------------------------------------===//
325 // PowerPC Flag Definitions.
327 class isPPC64 { bit PPC64 = 1; }
328 class isDOT { bit RC = 1; }
330 class RegConstraint<string C> {
331 string Constraints = C;
333 class NoEncode<string E> {
334 string DisableEncoding = E;
338 //===----------------------------------------------------------------------===//
339 // PowerPC Operand Definitions.
341 // In the default PowerPC assembler syntax, registers are specified simply
342 // by number, so they cannot be distinguished from immediate values (without
343 // looking at the opcode). This means that the default operand matching logic
344 // for the asm parser does not work, and we need to specify custom matchers.
345 // Since those can only be specified with RegisterOperand classes and not
346 // directly on the RegisterClass, all instructions patterns used by the asm
347 // parser need to use a RegisterOperand (instead of a RegisterClass) for
348 // all their register operands.
349 // For this purpose, we define one RegisterOperand for each RegisterClass,
350 // using the same name as the class, just in lower case.
352 def PPCRegGPRCAsmOperand : AsmOperandClass {
353 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
355 def gprc : RegisterOperand<GPRC> {
356 let ParserMatchClass = PPCRegGPRCAsmOperand;
358 def PPCRegG8RCAsmOperand : AsmOperandClass {
359 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
361 def g8rc : RegisterOperand<G8RC> {
362 let ParserMatchClass = PPCRegG8RCAsmOperand;
364 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
365 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
367 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
368 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
370 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
371 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
373 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
374 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
376 def PPCRegF8RCAsmOperand : AsmOperandClass {
377 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
379 def f8rc : RegisterOperand<F8RC> {
380 let ParserMatchClass = PPCRegF8RCAsmOperand;
382 def PPCRegF4RCAsmOperand : AsmOperandClass {
383 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
385 def f4rc : RegisterOperand<F4RC> {
386 let ParserMatchClass = PPCRegF4RCAsmOperand;
388 def PPCRegVRRCAsmOperand : AsmOperandClass {
389 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
391 def vrrc : RegisterOperand<VRRC> {
392 let ParserMatchClass = PPCRegVRRCAsmOperand;
394 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
395 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
397 def crbitrc : RegisterOperand<CRBITRC> {
398 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
400 def PPCRegCRRCAsmOperand : AsmOperandClass {
401 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
403 def crrc : RegisterOperand<CRRC> {
404 let ParserMatchClass = PPCRegCRRCAsmOperand;
407 def PPCS5ImmAsmOperand : AsmOperandClass {
408 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
409 let RenderMethod = "addImmOperands";
411 def s5imm : Operand<i32> {
412 let PrintMethod = "printS5ImmOperand";
413 let ParserMatchClass = PPCS5ImmAsmOperand;
415 def PPCU5ImmAsmOperand : AsmOperandClass {
416 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
417 let RenderMethod = "addImmOperands";
419 def u5imm : Operand<i32> {
420 let PrintMethod = "printU5ImmOperand";
421 let ParserMatchClass = PPCU5ImmAsmOperand;
423 def PPCU6ImmAsmOperand : AsmOperandClass {
424 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
425 let RenderMethod = "addImmOperands";
427 def u6imm : Operand<i32> {
428 let PrintMethod = "printU6ImmOperand";
429 let ParserMatchClass = PPCU6ImmAsmOperand;
431 def PPCS16ImmAsmOperand : AsmOperandClass {
432 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
433 let RenderMethod = "addImmOperands";
435 def s16imm : Operand<i32> {
436 let PrintMethod = "printS16ImmOperand";
437 let EncoderMethod = "getImm16Encoding";
438 let ParserMatchClass = PPCS16ImmAsmOperand;
440 def PPCU16ImmAsmOperand : AsmOperandClass {
441 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
442 let RenderMethod = "addImmOperands";
444 def u16imm : Operand<i32> {
445 let PrintMethod = "printU16ImmOperand";
446 let EncoderMethod = "getImm16Encoding";
447 let ParserMatchClass = PPCU16ImmAsmOperand;
449 def PPCS17ImmAsmOperand : AsmOperandClass {
450 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
451 let RenderMethod = "addImmOperands";
453 def s17imm : Operand<i32> {
454 // This operand type is used for addis/lis to allow the assembler parser
455 // to accept immediates in the range -65536..65535 for compatibility with
456 // the GNU assembler. The operand is treated as 16-bit otherwise.
457 let PrintMethod = "printS16ImmOperand";
458 let EncoderMethod = "getImm16Encoding";
459 let ParserMatchClass = PPCS17ImmAsmOperand;
461 def PPCDirectBrAsmOperand : AsmOperandClass {
462 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
463 let RenderMethod = "addBranchTargetOperands";
465 def directbrtarget : Operand<OtherVT> {
466 let PrintMethod = "printBranchOperand";
467 let EncoderMethod = "getDirectBrEncoding";
468 let ParserMatchClass = PPCDirectBrAsmOperand;
470 def absdirectbrtarget : Operand<OtherVT> {
471 let PrintMethod = "printAbsBranchOperand";
472 let EncoderMethod = "getAbsDirectBrEncoding";
473 let ParserMatchClass = PPCDirectBrAsmOperand;
475 def PPCCondBrAsmOperand : AsmOperandClass {
476 let Name = "CondBr"; let PredicateMethod = "isCondBr";
477 let RenderMethod = "addBranchTargetOperands";
479 def condbrtarget : Operand<OtherVT> {
480 let PrintMethod = "printBranchOperand";
481 let EncoderMethod = "getCondBrEncoding";
482 let ParserMatchClass = PPCCondBrAsmOperand;
484 def abscondbrtarget : Operand<OtherVT> {
485 let PrintMethod = "printAbsBranchOperand";
486 let EncoderMethod = "getAbsCondBrEncoding";
487 let ParserMatchClass = PPCCondBrAsmOperand;
489 def calltarget : Operand<iPTR> {
490 let PrintMethod = "printBranchOperand";
491 let EncoderMethod = "getDirectBrEncoding";
492 let ParserMatchClass = PPCDirectBrAsmOperand;
494 def abscalltarget : Operand<iPTR> {
495 let PrintMethod = "printAbsBranchOperand";
496 let EncoderMethod = "getAbsDirectBrEncoding";
497 let ParserMatchClass = PPCDirectBrAsmOperand;
499 def PPCCRBitMaskOperand : AsmOperandClass {
500 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
502 def crbitm: Operand<i8> {
503 let PrintMethod = "printcrbitm";
504 let EncoderMethod = "get_crbitm_encoding";
505 let ParserMatchClass = PPCCRBitMaskOperand;
508 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
509 def PPCRegGxRCNoR0Operand : AsmOperandClass {
510 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
512 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
513 let ParserMatchClass = PPCRegGxRCNoR0Operand;
515 // A version of ptr_rc usable with the asm parser.
516 def PPCRegGxRCOperand : AsmOperandClass {
517 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
519 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
520 let ParserMatchClass = PPCRegGxRCOperand;
523 def PPCDispRIOperand : AsmOperandClass {
524 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
525 let RenderMethod = "addImmOperands";
527 def dispRI : Operand<iPTR> {
528 let ParserMatchClass = PPCDispRIOperand;
530 def PPCDispRIXOperand : AsmOperandClass {
531 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
532 let RenderMethod = "addImmOperands";
534 def dispRIX : Operand<iPTR> {
535 let ParserMatchClass = PPCDispRIXOperand;
538 def memri : Operand<iPTR> {
539 let PrintMethod = "printMemRegImm";
540 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
541 let EncoderMethod = "getMemRIEncoding";
543 def memrr : Operand<iPTR> {
544 let PrintMethod = "printMemRegReg";
545 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
547 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
548 let PrintMethod = "printMemRegImm";
549 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
550 let EncoderMethod = "getMemRIXEncoding";
553 // A single-register address. This is used with the SjLj
554 // pseudo-instructions.
555 def memr : Operand<iPTR> {
556 let MIOperandInfo = (ops ptr_rc:$ptrreg);
559 // PowerPC Predicate operand.
560 def pred : Operand<OtherVT> {
561 let PrintMethod = "printPredicateOperand";
562 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
565 // Define PowerPC specific addressing mode.
566 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
567 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
568 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
569 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
571 // The address in a single register. This is used with the SjLj
572 // pseudo-instructions.
573 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
575 /// This is just the offset part of iaddr, used for preinc.
576 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
578 //===----------------------------------------------------------------------===//
579 // PowerPC Instruction Predicate Definitions.
580 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
581 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
582 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
584 //===----------------------------------------------------------------------===//
585 // PowerPC Multiclass Definitions.
587 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
588 string asmbase, string asmstr, InstrItinClass itin,
590 let BaseName = asmbase in {
591 def NAME : XForm_6<opcode, xo, OOL, IOL,
592 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
593 pattern>, RecFormRel;
595 def o : XForm_6<opcode, xo, OOL, IOL,
596 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
597 []>, isDOT, RecFormRel;
601 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
602 string asmbase, string asmstr, InstrItinClass itin,
604 let BaseName = asmbase in {
605 let Defs = [CARRY] in
606 def NAME : XForm_6<opcode, xo, OOL, IOL,
607 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
608 pattern>, RecFormRel;
609 let Defs = [CARRY, CR0] in
610 def o : XForm_6<opcode, xo, OOL, IOL,
611 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
612 []>, isDOT, RecFormRel;
616 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
617 string asmbase, string asmstr, InstrItinClass itin,
619 let BaseName = asmbase in {
620 let Defs = [CARRY] in
621 def NAME : XForm_10<opcode, xo, OOL, IOL,
622 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
623 pattern>, RecFormRel;
624 let Defs = [CARRY, CR0] in
625 def o : XForm_10<opcode, xo, OOL, IOL,
626 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
627 []>, isDOT, RecFormRel;
631 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
632 string asmbase, string asmstr, InstrItinClass itin,
634 let BaseName = asmbase in {
635 def NAME : XForm_11<opcode, xo, OOL, IOL,
636 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
637 pattern>, RecFormRel;
639 def o : XForm_11<opcode, xo, OOL, IOL,
640 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
641 []>, isDOT, RecFormRel;
645 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
646 string asmbase, string asmstr, InstrItinClass itin,
648 let BaseName = asmbase in {
649 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
650 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
651 pattern>, RecFormRel;
653 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
654 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
655 []>, isDOT, RecFormRel;
659 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
660 string asmbase, string asmstr, InstrItinClass itin,
662 let BaseName = asmbase in {
663 let Defs = [CARRY] in
664 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
665 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
666 pattern>, RecFormRel;
667 let Defs = [CARRY, CR0] in
668 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
669 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
670 []>, isDOT, RecFormRel;
674 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
675 string asmbase, string asmstr, InstrItinClass itin,
677 let BaseName = asmbase in {
678 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
679 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
680 pattern>, RecFormRel;
682 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
683 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
684 []>, isDOT, RecFormRel;
688 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
689 string asmbase, string asmstr, InstrItinClass itin,
691 let BaseName = asmbase in {
692 let Defs = [CARRY] in
693 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
694 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
695 pattern>, RecFormRel;
696 let Defs = [CARRY, CR0] in
697 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
698 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
699 []>, isDOT, RecFormRel;
703 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
704 string asmbase, string asmstr, InstrItinClass itin,
706 let BaseName = asmbase in {
707 def NAME : MForm_2<opcode, OOL, IOL,
708 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
709 pattern>, RecFormRel;
711 def o : MForm_2<opcode, OOL, IOL,
712 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
713 []>, isDOT, RecFormRel;
717 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
718 string asmbase, string asmstr, InstrItinClass itin,
720 let BaseName = asmbase in {
721 def NAME : MDForm_1<opcode, xo, OOL, IOL,
722 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
723 pattern>, RecFormRel;
725 def o : MDForm_1<opcode, xo, OOL, IOL,
726 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
727 []>, isDOT, RecFormRel;
731 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
732 string asmbase, string asmstr, InstrItinClass itin,
734 let BaseName = asmbase in {
735 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
736 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
737 pattern>, RecFormRel;
739 def o : MDSForm_1<opcode, xo, OOL, IOL,
740 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
741 []>, isDOT, RecFormRel;
745 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
746 string asmbase, string asmstr, InstrItinClass itin,
748 let BaseName = asmbase in {
749 let Defs = [CARRY] in
750 def NAME : XSForm_1<opcode, xo, OOL, IOL,
751 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
752 pattern>, RecFormRel;
753 let Defs = [CARRY, CR0] in
754 def o : XSForm_1<opcode, xo, OOL, IOL,
755 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
756 []>, isDOT, RecFormRel;
760 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
761 string asmbase, string asmstr, InstrItinClass itin,
763 let BaseName = asmbase in {
764 def NAME : XForm_26<opcode, xo, OOL, IOL,
765 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
766 pattern>, RecFormRel;
768 def o : XForm_26<opcode, xo, OOL, IOL,
769 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
770 []>, isDOT, RecFormRel;
774 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
775 string asmbase, string asmstr, InstrItinClass itin,
777 let BaseName = asmbase in {
778 def NAME : XForm_28<opcode, xo, OOL, IOL,
779 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
780 pattern>, RecFormRel;
782 def o : XForm_28<opcode, xo, OOL, IOL,
783 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
784 []>, isDOT, RecFormRel;
788 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
789 string asmbase, string asmstr, InstrItinClass itin,
791 let BaseName = asmbase in {
792 def NAME : AForm_1<opcode, xo, OOL, IOL,
793 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
794 pattern>, RecFormRel;
796 def o : AForm_1<opcode, xo, OOL, IOL,
797 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
798 []>, isDOT, RecFormRel;
802 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
803 string asmbase, string asmstr, InstrItinClass itin,
805 let BaseName = asmbase in {
806 def NAME : AForm_2<opcode, xo, OOL, IOL,
807 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
808 pattern>, RecFormRel;
810 def o : AForm_2<opcode, xo, OOL, IOL,
811 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
812 []>, isDOT, RecFormRel;
816 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
817 string asmbase, string asmstr, InstrItinClass itin,
819 let BaseName = asmbase in {
820 def NAME : AForm_3<opcode, xo, OOL, IOL,
821 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
822 pattern>, RecFormRel;
824 def o : AForm_3<opcode, xo, OOL, IOL,
825 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
826 []>, isDOT, RecFormRel;
830 //===----------------------------------------------------------------------===//
831 // PowerPC Instruction Definitions.
833 // Pseudo-instructions:
835 let hasCtrlDep = 1 in {
836 let Defs = [R1], Uses = [R1] in {
837 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
838 [(callseq_start timm:$amt)]>;
839 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
840 [(callseq_end timm:$amt1, timm:$amt2)]>;
843 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
844 "UPDATE_VRSAVE $rD, $rS", []>;
847 let Defs = [R1], Uses = [R1] in
848 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
850 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
852 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
853 // instruction selection into a branch sequence.
854 let usesCustomInserter = 1, // Expanded after instruction selection.
855 PPC970_Single = 1 in {
856 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
857 // because either operand might become the first operand in an isel, and
858 // that operand cannot be r0.
859 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
860 gprc_nor0:$T, gprc_nor0:$F,
861 i32imm:$BROPC), "#SELECT_CC_I4",
863 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
864 g8rc_nox0:$T, g8rc_nox0:$F,
865 i32imm:$BROPC), "#SELECT_CC_I8",
867 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
868 i32imm:$BROPC), "#SELECT_CC_F4",
870 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
871 i32imm:$BROPC), "#SELECT_CC_F8",
873 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
874 i32imm:$BROPC), "#SELECT_CC_VRRC",
878 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
879 // scavenge a register for it.
881 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
884 // RESTORE_CR - Indicate that we're restoring the CR register (previously
885 // spilled), so we'll need to scavenge a register for it.
887 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
890 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
891 let isReturn = 1, Uses = [LR, RM] in
892 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
894 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
895 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
898 let isCodeGenOnly = 1 in
899 def BCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
900 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
906 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
909 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
910 let isBarrier = 1 in {
911 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
914 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
915 "ba $dst", IIC_BrB, []>;
918 // BCC represents an arbitrary conditional branch on a predicate.
919 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
920 // a two-value operand where a dag node expects two operands. :(
921 let isCodeGenOnly = 1 in {
922 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
923 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
924 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
925 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
926 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
928 let isReturn = 1, Uses = [LR, RM] in
929 def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
930 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
933 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
934 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
935 "bdzlr", IIC_BrB, []>;
936 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
937 "bdnzlr", IIC_BrB, []>;
938 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
939 "bdzlr+", IIC_BrB, []>;
940 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
941 "bdnzlr+", IIC_BrB, []>;
942 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
943 "bdzlr-", IIC_BrB, []>;
944 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
945 "bdnzlr-", IIC_BrB, []>;
948 let Defs = [CTR], Uses = [CTR] in {
949 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
951 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
953 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
955 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
957 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
959 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
961 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
963 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
965 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
967 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
969 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
971 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
976 // The unconditional BCL used by the SjLj setjmp code.
977 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
978 let Defs = [LR], Uses = [RM] in {
979 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
984 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
985 // Convenient aliases for call instructions
987 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
988 "bl $func", IIC_BrB, []>; // See Pat patterns below.
989 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
990 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
992 let isCodeGenOnly = 1 in {
993 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
994 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
995 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
996 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
999 let Uses = [CTR, RM] in {
1000 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1001 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1002 Requires<[In32BitMode]>;
1004 let isCodeGenOnly = 1 in
1005 def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1006 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1009 let Uses = [LR, RM] in {
1010 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1011 "blrl", IIC_BrB, []>;
1013 let isCodeGenOnly = 1 in
1014 def BCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1015 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1018 let Defs = [CTR], Uses = [CTR, RM] in {
1019 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1021 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1023 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1025 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1027 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1029 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1031 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1033 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1035 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1037 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1039 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1041 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1044 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1045 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1046 "bdzlrl", IIC_BrB, []>;
1047 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1048 "bdnzlrl", IIC_BrB, []>;
1049 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1050 "bdzlrl+", IIC_BrB, []>;
1051 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1052 "bdnzlrl+", IIC_BrB, []>;
1053 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1054 "bdzlrl-", IIC_BrB, []>;
1055 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1056 "bdnzlrl-", IIC_BrB, []>;
1060 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1061 def TCRETURNdi :Pseudo< (outs),
1062 (ins calltarget:$dst, i32imm:$offset),
1063 "#TC_RETURNd $dst $offset",
1067 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1068 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1069 "#TC_RETURNa $func $offset",
1070 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1072 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1073 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1074 "#TC_RETURNr $dst $offset",
1078 let isCodeGenOnly = 1 in {
1080 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1081 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1082 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1083 []>, Requires<[In32BitMode]>;
1085 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1086 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1087 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1091 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1092 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1093 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1099 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1101 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1102 "#EH_SJLJ_SETJMP32",
1103 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1104 Requires<[In32BitMode]>;
1105 let isTerminator = 1 in
1106 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1107 "#EH_SJLJ_LONGJMP32",
1108 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1109 Requires<[In32BitMode]>;
1112 let isBranch = 1, isTerminator = 1 in {
1113 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1114 "#EH_SjLj_Setup\t$dst", []>;
1118 let PPC970_Unit = 7 in {
1119 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1120 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1123 // DCB* instructions.
1124 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1125 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1126 PPC970_DGroup_Single;
1127 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1128 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1129 PPC970_DGroup_Single;
1130 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1131 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1132 PPC970_DGroup_Single;
1133 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1134 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1135 PPC970_DGroup_Single;
1136 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1137 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1138 PPC970_DGroup_Single;
1139 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1140 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1141 PPC970_DGroup_Single;
1142 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1143 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1144 PPC970_DGroup_Single;
1145 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1146 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1147 PPC970_DGroup_Single;
1149 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1150 (DCBT xoaddr:$dst)>;
1152 // Atomic operations
1153 let usesCustomInserter = 1 in {
1154 let Defs = [CR0] in {
1155 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1156 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1157 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1158 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1159 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1160 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1161 def ATOMIC_LOAD_AND_I8 : Pseudo<
1162 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1163 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1164 def ATOMIC_LOAD_OR_I8 : Pseudo<
1165 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1166 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1167 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1168 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1169 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1170 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1171 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1172 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1173 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1174 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1175 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1176 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1177 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1178 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1179 def ATOMIC_LOAD_AND_I16 : Pseudo<
1180 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1181 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1182 def ATOMIC_LOAD_OR_I16 : Pseudo<
1183 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1184 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1185 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1186 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1187 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1188 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1189 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1190 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1191 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1192 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1193 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1194 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1195 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1196 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1197 def ATOMIC_LOAD_AND_I32 : Pseudo<
1198 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1199 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1200 def ATOMIC_LOAD_OR_I32 : Pseudo<
1201 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1202 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1203 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1204 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1205 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1206 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1207 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1208 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1210 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1211 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1212 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1213 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1214 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1215 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1216 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1217 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1218 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1220 def ATOMIC_SWAP_I8 : Pseudo<
1221 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1222 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1223 def ATOMIC_SWAP_I16 : Pseudo<
1224 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1225 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1226 def ATOMIC_SWAP_I32 : Pseudo<
1227 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1228 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1232 // Instructions to support atomic operations
1233 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1234 "lwarx $rD, $src", IIC_LdStLWARX,
1235 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1238 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1239 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1240 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1243 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1244 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1246 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1247 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1248 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1249 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1250 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1251 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1252 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1253 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1255 //===----------------------------------------------------------------------===//
1256 // PPC32 Load Instructions.
1259 // Unindexed (r+i) Loads.
1260 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1261 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1262 "lbz $rD, $src", IIC_LdStLoad,
1263 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1264 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1265 "lha $rD, $src", IIC_LdStLHA,
1266 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1267 PPC970_DGroup_Cracked;
1268 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1269 "lhz $rD, $src", IIC_LdStLoad,
1270 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1271 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1272 "lwz $rD, $src", IIC_LdStLoad,
1273 [(set i32:$rD, (load iaddr:$src))]>;
1275 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1276 "lfs $rD, $src", IIC_LdStLFD,
1277 [(set f32:$rD, (load iaddr:$src))]>;
1278 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1279 "lfd $rD, $src", IIC_LdStLFD,
1280 [(set f64:$rD, (load iaddr:$src))]>;
1283 // Unindexed (r+i) Loads with Update (preinc).
1284 let mayLoad = 1, neverHasSideEffects = 1 in {
1285 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1286 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1287 []>, RegConstraint<"$addr.reg = $ea_result">,
1288 NoEncode<"$ea_result">;
1290 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1291 "lhau $rD, $addr", IIC_LdStLHAU,
1292 []>, RegConstraint<"$addr.reg = $ea_result">,
1293 NoEncode<"$ea_result">;
1295 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1296 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1297 []>, RegConstraint<"$addr.reg = $ea_result">,
1298 NoEncode<"$ea_result">;
1300 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1301 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1302 []>, RegConstraint<"$addr.reg = $ea_result">,
1303 NoEncode<"$ea_result">;
1305 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1306 "lfsu $rD, $addr", IIC_LdStLFDU,
1307 []>, RegConstraint<"$addr.reg = $ea_result">,
1308 NoEncode<"$ea_result">;
1310 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1311 "lfdu $rD, $addr", IIC_LdStLFDU,
1312 []>, RegConstraint<"$addr.reg = $ea_result">,
1313 NoEncode<"$ea_result">;
1316 // Indexed (r+r) Loads with Update (preinc).
1317 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1319 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1320 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1321 NoEncode<"$ea_result">;
1323 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1325 "lhaux $rD, $addr", IIC_LdStLHAUX,
1326 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1327 NoEncode<"$ea_result">;
1329 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1331 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1332 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1333 NoEncode<"$ea_result">;
1335 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1337 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1338 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1339 NoEncode<"$ea_result">;
1341 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1343 "lfsux $rD, $addr", IIC_LdStLFDUX,
1344 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1345 NoEncode<"$ea_result">;
1347 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1349 "lfdux $rD, $addr", IIC_LdStLFDUX,
1350 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1351 NoEncode<"$ea_result">;
1355 // Indexed (r+r) Loads.
1357 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1358 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1359 "lbzx $rD, $src", IIC_LdStLoad,
1360 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1361 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1362 "lhax $rD, $src", IIC_LdStLHA,
1363 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1364 PPC970_DGroup_Cracked;
1365 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1366 "lhzx $rD, $src", IIC_LdStLoad,
1367 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1368 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1369 "lwzx $rD, $src", IIC_LdStLoad,
1370 [(set i32:$rD, (load xaddr:$src))]>;
1373 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1374 "lhbrx $rD, $src", IIC_LdStLoad,
1375 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1376 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1377 "lwbrx $rD, $src", IIC_LdStLoad,
1378 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1380 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1381 "lfsx $frD, $src", IIC_LdStLFD,
1382 [(set f32:$frD, (load xaddr:$src))]>;
1383 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1384 "lfdx $frD, $src", IIC_LdStLFD,
1385 [(set f64:$frD, (load xaddr:$src))]>;
1387 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1388 "lfiwax $frD, $src", IIC_LdStLFD,
1389 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1390 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1391 "lfiwzx $frD, $src", IIC_LdStLFD,
1392 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1396 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1397 "lmw $rD, $src", IIC_LdStLMW, []>;
1399 //===----------------------------------------------------------------------===//
1400 // PPC32 Store Instructions.
1403 // Unindexed (r+i) Stores.
1404 let PPC970_Unit = 2 in {
1405 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1406 "stb $rS, $src", IIC_LdStStore,
1407 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1408 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1409 "sth $rS, $src", IIC_LdStStore,
1410 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1411 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1412 "stw $rS, $src", IIC_LdStStore,
1413 [(store i32:$rS, iaddr:$src)]>;
1414 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1415 "stfs $rS, $dst", IIC_LdStSTFD,
1416 [(store f32:$rS, iaddr:$dst)]>;
1417 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1418 "stfd $rS, $dst", IIC_LdStSTFD,
1419 [(store f64:$rS, iaddr:$dst)]>;
1422 // Unindexed (r+i) Stores with Update (preinc).
1423 let PPC970_Unit = 2, mayStore = 1 in {
1424 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1425 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1426 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1427 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1428 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1429 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1430 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1431 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1432 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1433 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1434 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1435 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1436 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1437 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1438 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1441 // Patterns to match the pre-inc stores. We can't put the patterns on
1442 // the instruction definitions directly as ISel wants the address base
1443 // and offset to be separate operands, not a single complex operand.
1444 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1445 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1446 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1447 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1448 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1449 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1450 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1451 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1452 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1453 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1455 // Indexed (r+r) Stores.
1456 let PPC970_Unit = 2 in {
1457 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1458 "stbx $rS, $dst", IIC_LdStStore,
1459 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1460 PPC970_DGroup_Cracked;
1461 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1462 "sthx $rS, $dst", IIC_LdStStore,
1463 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1464 PPC970_DGroup_Cracked;
1465 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1466 "stwx $rS, $dst", IIC_LdStStore,
1467 [(store i32:$rS, xaddr:$dst)]>,
1468 PPC970_DGroup_Cracked;
1470 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1471 "sthbrx $rS, $dst", IIC_LdStStore,
1472 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1473 PPC970_DGroup_Cracked;
1474 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1475 "stwbrx $rS, $dst", IIC_LdStStore,
1476 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1477 PPC970_DGroup_Cracked;
1479 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1480 "stfiwx $frS, $dst", IIC_LdStSTFD,
1481 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1483 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1484 "stfsx $frS, $dst", IIC_LdStSTFD,
1485 [(store f32:$frS, xaddr:$dst)]>;
1486 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1487 "stfdx $frS, $dst", IIC_LdStSTFD,
1488 [(store f64:$frS, xaddr:$dst)]>;
1491 // Indexed (r+r) Stores with Update (preinc).
1492 let PPC970_Unit = 2, mayStore = 1 in {
1493 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1494 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1495 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1496 PPC970_DGroup_Cracked;
1497 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1498 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1499 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1500 PPC970_DGroup_Cracked;
1501 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1502 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1503 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1504 PPC970_DGroup_Cracked;
1505 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1506 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1507 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1508 PPC970_DGroup_Cracked;
1509 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1510 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1511 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1512 PPC970_DGroup_Cracked;
1515 // Patterns to match the pre-inc stores. We can't put the patterns on
1516 // the instruction definitions directly as ISel wants the address base
1517 // and offset to be separate operands, not a single complex operand.
1518 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1519 (STBUX $rS, $ptrreg, $ptroff)>;
1520 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1521 (STHUX $rS, $ptrreg, $ptroff)>;
1522 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1523 (STWUX $rS, $ptrreg, $ptroff)>;
1524 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1525 (STFSUX $rS, $ptrreg, $ptroff)>;
1526 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1527 (STFDUX $rS, $ptrreg, $ptroff)>;
1530 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1531 "stmw $rS, $dst", IIC_LdStLMW, []>;
1533 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1534 "sync $L", IIC_LdStSync, []>;
1535 def : Pat<(int_ppc_sync), (SYNC 0)>;
1537 //===----------------------------------------------------------------------===//
1538 // PPC32 Arithmetic Instructions.
1541 let PPC970_Unit = 1 in { // FXU Operations.
1542 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1543 "addi $rD, $rA, $imm", IIC_IntSimple,
1544 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1545 let BaseName = "addic" in {
1546 let Defs = [CARRY] in
1547 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1548 "addic $rD, $rA, $imm", IIC_IntGeneral,
1549 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1550 RecFormRel, PPC970_DGroup_Cracked;
1551 let Defs = [CARRY, CR0] in
1552 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1553 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1554 []>, isDOT, RecFormRel;
1556 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1557 "addis $rD, $rA, $imm", IIC_IntSimple,
1558 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1559 let isCodeGenOnly = 1 in
1560 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1561 "la $rD, $sym($rA)", IIC_IntGeneral,
1562 [(set i32:$rD, (add i32:$rA,
1563 (PPClo tglobaladdr:$sym, 0)))]>;
1564 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1565 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1566 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1567 let Defs = [CARRY] in
1568 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1569 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1570 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1572 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1573 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1574 "li $rD, $imm", IIC_IntSimple,
1575 [(set i32:$rD, imm32SExt16:$imm)]>;
1576 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1577 "lis $rD, $imm", IIC_IntSimple,
1578 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1582 let PPC970_Unit = 1 in { // FXU Operations.
1583 let Defs = [CR0] in {
1584 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1585 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1586 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1588 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1589 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1590 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1593 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1594 "ori $dst, $src1, $src2", IIC_IntSimple,
1595 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1596 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1597 "oris $dst, $src1, $src2", IIC_IntSimple,
1598 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1599 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1600 "xori $dst, $src1, $src2", IIC_IntSimple,
1601 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1602 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1603 "xoris $dst, $src1, $src2", IIC_IntSimple,
1604 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1606 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1608 let isCodeGenOnly = 1 in {
1609 // The POWER6 and POWER7 have special group-terminating nops.
1610 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1611 "ori 1, 1, 0", IIC_IntSimple, []>;
1612 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1613 "ori 2, 2, 0", IIC_IntSimple, []>;
1616 let isCompare = 1, neverHasSideEffects = 1 in {
1617 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1618 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1619 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1620 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1624 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1625 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1626 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1627 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1628 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1629 "and", "$rA, $rS, $rB", IIC_IntSimple,
1630 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1631 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1632 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1633 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1634 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1635 "or", "$rA, $rS, $rB", IIC_IntSimple,
1636 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1637 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1638 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1639 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1640 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1641 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1642 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1643 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1644 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1645 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1646 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1647 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1648 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1649 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1650 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1651 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1652 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1653 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1654 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1655 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1656 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1657 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1660 let PPC970_Unit = 1 in { // FXU Operations.
1661 let neverHasSideEffects = 1 in {
1662 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1663 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1664 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1665 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1666 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1667 [(set i32:$rA, (ctlz i32:$rS))]>;
1668 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1669 "extsb", "$rA, $rS", IIC_IntSimple,
1670 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1671 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1672 "extsh", "$rA, $rS", IIC_IntSimple,
1673 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1675 let isCompare = 1, neverHasSideEffects = 1 in {
1676 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1677 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1678 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1679 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1682 let PPC970_Unit = 3 in { // FPU Operations.
1683 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1684 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1685 let isCompare = 1, neverHasSideEffects = 1 in {
1686 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1687 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1688 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1689 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1690 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1693 let Uses = [RM] in {
1694 let neverHasSideEffects = 1 in {
1695 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1696 "fctiw", "$frD, $frB", IIC_FPGeneral,
1698 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1699 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1700 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1702 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1703 "frsp", "$frD, $frB", IIC_FPGeneral,
1704 [(set f32:$frD, (fround f64:$frB))]>;
1706 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1707 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1708 "frin", "$frD, $frB", IIC_FPGeneral,
1709 [(set f64:$frD, (frnd f64:$frB))]>;
1710 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1711 "frin", "$frD, $frB", IIC_FPGeneral,
1712 [(set f32:$frD, (frnd f32:$frB))]>;
1715 let neverHasSideEffects = 1 in {
1716 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1717 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1718 "frip", "$frD, $frB", IIC_FPGeneral,
1719 [(set f64:$frD, (fceil f64:$frB))]>;
1720 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1721 "frip", "$frD, $frB", IIC_FPGeneral,
1722 [(set f32:$frD, (fceil f32:$frB))]>;
1723 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1724 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1725 "friz", "$frD, $frB", IIC_FPGeneral,
1726 [(set f64:$frD, (ftrunc f64:$frB))]>;
1727 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1728 "friz", "$frD, $frB", IIC_FPGeneral,
1729 [(set f32:$frD, (ftrunc f32:$frB))]>;
1730 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1731 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1732 "frim", "$frD, $frB", IIC_FPGeneral,
1733 [(set f64:$frD, (ffloor f64:$frB))]>;
1734 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1735 "frim", "$frD, $frB", IIC_FPGeneral,
1736 [(set f32:$frD, (ffloor f32:$frB))]>;
1738 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1739 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1740 [(set f64:$frD, (fsqrt f64:$frB))]>;
1741 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1742 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1743 [(set f32:$frD, (fsqrt f32:$frB))]>;
1748 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1749 /// often coalesced away and we don't want the dispatch group builder to think
1750 /// that they will fill slots (which could cause the load of a LSU reject to
1751 /// sneak into a d-group with a store).
1752 let neverHasSideEffects = 1 in
1753 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1754 "fmr", "$frD, $frB", IIC_FPGeneral,
1755 []>, // (set f32:$frD, f32:$frB)
1758 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1759 // These are artificially split into two different forms, for 4/8 byte FP.
1760 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1761 "fabs", "$frD, $frB", IIC_FPGeneral,
1762 [(set f32:$frD, (fabs f32:$frB))]>;
1763 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1764 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1765 "fabs", "$frD, $frB", IIC_FPGeneral,
1766 [(set f64:$frD, (fabs f64:$frB))]>;
1767 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1768 "fnabs", "$frD, $frB", IIC_FPGeneral,
1769 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1770 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1771 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1772 "fnabs", "$frD, $frB", IIC_FPGeneral,
1773 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1774 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1775 "fneg", "$frD, $frB", IIC_FPGeneral,
1776 [(set f32:$frD, (fneg f32:$frB))]>;
1777 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1778 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1779 "fneg", "$frD, $frB", IIC_FPGeneral,
1780 [(set f64:$frD, (fneg f64:$frB))]>;
1782 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1783 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1784 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1785 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1786 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1787 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1788 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1790 // Reciprocal estimates.
1791 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1792 "fre", "$frD, $frB", IIC_FPGeneral,
1793 [(set f64:$frD, (PPCfre f64:$frB))]>;
1794 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1795 "fres", "$frD, $frB", IIC_FPGeneral,
1796 [(set f32:$frD, (PPCfre f32:$frB))]>;
1797 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1798 "frsqrte", "$frD, $frB", IIC_FPGeneral,
1799 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1800 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1801 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
1802 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1805 // XL-Form instructions. condition register logical ops.
1807 let neverHasSideEffects = 1 in
1808 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1809 "mcrf $BF, $BFA", IIC_BrMCR>,
1810 PPC970_DGroup_First, PPC970_Unit_CRU;
1812 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
1813 (ins crbitrc:$CRA, crbitrc:$CRB),
1814 "crand $CRD, $CRA, $CRB", IIC_BrCR, []>;
1816 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
1817 (ins crbitrc:$CRA, crbitrc:$CRB),
1818 "crnand $CRD, $CRA, $CRB", IIC_BrCR, []>;
1820 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
1821 (ins crbitrc:$CRA, crbitrc:$CRB),
1822 "cror $CRD, $CRA, $CRB", IIC_BrCR, []>;
1824 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
1825 (ins crbitrc:$CRA, crbitrc:$CRB),
1826 "crxor $CRD, $CRA, $CRB", IIC_BrCR, []>;
1828 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
1829 (ins crbitrc:$CRA, crbitrc:$CRB),
1830 "crnor $CRD, $CRA, $CRB", IIC_BrCR, []>;
1832 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
1833 (ins crbitrc:$CRA, crbitrc:$CRB),
1834 "creqv $CRD, $CRA, $CRB", IIC_BrCR, []>;
1836 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
1837 (ins crbitrc:$CRA, crbitrc:$CRB),
1838 "crandc $CRD, $CRA, $CRB", IIC_BrCR, []>;
1840 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
1841 (ins crbitrc:$CRA, crbitrc:$CRB),
1842 "crorc $CRD, $CRA, $CRB", IIC_BrCR, []>;
1844 let isCodeGenOnly = 1 in {
1845 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
1846 "creqv $dst, $dst, $dst", IIC_BrCR,
1849 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
1850 "crxor $dst, $dst, $dst", IIC_BrCR,
1853 let Defs = [CR1EQ], CRD = 6 in {
1854 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1855 "creqv 6, 6, 6", IIC_BrCR,
1858 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1859 "crxor 6, 6, 6", IIC_BrCR,
1864 // XFX-Form instructions. Instructions that deal with SPRs.
1867 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
1868 "mfspr $RT, $SPR", IIC_SprMFSPR>;
1869 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
1870 "mtspr $SPR, $RT", IIC_SprMTSPR>;
1872 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
1873 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
1875 let Uses = [CTR] in {
1876 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
1877 "mfctr $rT", IIC_SprMFSPR>,
1878 PPC970_DGroup_First, PPC970_Unit_FXU;
1880 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1881 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1882 "mtctr $rS", IIC_SprMTSPR>,
1883 PPC970_DGroup_First, PPC970_Unit_FXU;
1885 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
1886 let Pattern = [(int_ppc_mtctr i32:$rS)] in
1887 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1888 "mtctr $rS", IIC_SprMTSPR>,
1889 PPC970_DGroup_First, PPC970_Unit_FXU;
1892 let Defs = [LR] in {
1893 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
1894 "mtlr $rS", IIC_SprMTSPR>,
1895 PPC970_DGroup_First, PPC970_Unit_FXU;
1897 let Uses = [LR] in {
1898 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
1899 "mflr $rT", IIC_SprMFSPR>,
1900 PPC970_DGroup_First, PPC970_Unit_FXU;
1903 let isCodeGenOnly = 1 in {
1904 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
1905 // like a GPR on the PPC970. As such, copies in and out have the same
1906 // performance characteristics as an OR instruction.
1907 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
1908 "mtspr 256, $rS", IIC_IntGeneral>,
1909 PPC970_DGroup_Single, PPC970_Unit_FXU;
1910 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
1911 "mfspr $rT, 256", IIC_IntGeneral>,
1912 PPC970_DGroup_First, PPC970_Unit_FXU;
1914 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1915 (outs VRSAVERC:$reg), (ins gprc:$rS),
1916 "mtspr 256, $rS", IIC_IntGeneral>,
1917 PPC970_DGroup_Single, PPC970_Unit_FXU;
1918 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
1919 (ins VRSAVERC:$reg),
1920 "mfspr $rT, 256", IIC_IntGeneral>,
1921 PPC970_DGroup_First, PPC970_Unit_FXU;
1924 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1925 // so we'll need to scavenge a register for it.
1927 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1928 "#SPILL_VRSAVE", []>;
1930 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1931 // spilled), so we'll need to scavenge a register for it.
1933 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1934 "#RESTORE_VRSAVE", []>;
1936 let neverHasSideEffects = 1 in {
1937 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
1938 "mtocrf $FXM, $ST", IIC_BrMCRX>,
1939 PPC970_DGroup_First, PPC970_Unit_CRU;
1941 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
1942 "mtcrf $FXM, $rS", IIC_BrMCRX>,
1943 PPC970_MicroCode, PPC970_Unit_CRU;
1945 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
1946 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
1947 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
1948 PPC970_DGroup_First, PPC970_Unit_CRU;
1950 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
1951 "mfcr $rT", IIC_SprMFCR>,
1952 PPC970_MicroCode, PPC970_Unit_CRU;
1953 } // neverHasSideEffects = 1
1955 // Pseudo instruction to perform FADD in round-to-zero mode.
1956 let usesCustomInserter = 1, Uses = [RM] in {
1957 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
1958 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
1961 // The above pseudo gets expanded to make use of the following instructions
1962 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
1963 let Uses = [RM], Defs = [RM] in {
1964 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1965 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
1966 PPC970_DGroup_Single, PPC970_Unit_FPU;
1967 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1968 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
1969 PPC970_DGroup_Single, PPC970_Unit_FPU;
1970 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
1971 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
1972 PPC970_DGroup_Single, PPC970_Unit_FPU;
1974 let Uses = [RM] in {
1975 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
1976 "mffs $rT", IIC_IntMFFS,
1977 [(set f64:$rT, (PPCmffs))]>,
1978 PPC970_DGroup_Single, PPC970_Unit_FPU;
1982 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1983 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1985 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1986 "add", "$rT, $rA, $rB", IIC_IntSimple,
1987 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
1988 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1989 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
1990 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
1991 PPC970_DGroup_Cracked;
1992 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1993 "divw", "$rT, $rA, $rB", IIC_IntDivW,
1994 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
1995 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1996 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1997 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
1998 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
1999 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2000 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2001 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2002 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2003 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2004 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2005 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2006 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2007 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2008 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2009 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2010 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2011 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2012 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2013 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2014 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2015 PPC970_DGroup_Cracked;
2016 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2017 "neg", "$rT, $rA", IIC_IntSimple,
2018 [(set i32:$rT, (ineg i32:$rA))]>;
2019 let Uses = [CARRY] in {
2020 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2021 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2022 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2023 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2024 "addme", "$rT, $rA", IIC_IntGeneral,
2025 [(set i32:$rT, (adde i32:$rA, -1))]>;
2026 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2027 "addze", "$rT, $rA", IIC_IntGeneral,
2028 [(set i32:$rT, (adde i32:$rA, 0))]>;
2029 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2030 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2031 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2032 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2033 "subfme", "$rT, $rA", IIC_IntGeneral,
2034 [(set i32:$rT, (sube -1, i32:$rA))]>;
2035 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2036 "subfze", "$rT, $rA", IIC_IntGeneral,
2037 [(set i32:$rT, (sube 0, i32:$rA))]>;
2041 // A-Form instructions. Most of the instructions executed in the FPU are of
2044 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
2045 let Uses = [RM] in {
2046 defm FMADD : AForm_1r<63, 29,
2047 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2048 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2049 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2050 defm FMADDS : AForm_1r<59, 29,
2051 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2052 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2053 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2054 defm FMSUB : AForm_1r<63, 28,
2055 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2056 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2058 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2059 defm FMSUBS : AForm_1r<59, 28,
2060 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2061 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2063 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2064 defm FNMADD : AForm_1r<63, 31,
2065 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2066 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2068 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2069 defm FNMADDS : AForm_1r<59, 31,
2070 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2071 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2073 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2074 defm FNMSUB : AForm_1r<63, 30,
2075 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2076 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2077 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2078 (fneg f64:$FRB))))]>;
2079 defm FNMSUBS : AForm_1r<59, 30,
2080 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2081 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2082 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2083 (fneg f32:$FRB))))]>;
2085 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2086 // having 4 of these, force the comparison to always be an 8-byte double (code
2087 // should use an FMRSD if the input comparison value really wants to be a float)
2088 // and 4/8 byte forms for the result and operand type..
2089 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2090 defm FSELD : AForm_1r<63, 23,
2091 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2092 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2093 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2094 defm FSELS : AForm_1r<63, 23,
2095 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2096 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2097 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2098 let Uses = [RM] in {
2099 defm FADD : AForm_2r<63, 21,
2100 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2101 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2102 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2103 defm FADDS : AForm_2r<59, 21,
2104 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2105 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2106 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2107 defm FDIV : AForm_2r<63, 18,
2108 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2109 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2110 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2111 defm FDIVS : AForm_2r<59, 18,
2112 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2113 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2114 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2115 defm FMUL : AForm_3r<63, 25,
2116 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2117 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2118 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2119 defm FMULS : AForm_3r<59, 25,
2120 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2121 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2122 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2123 defm FSUB : AForm_2r<63, 20,
2124 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2125 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2126 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2127 defm FSUBS : AForm_2r<59, 20,
2128 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2129 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2130 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2134 let neverHasSideEffects = 1 in {
2135 let PPC970_Unit = 1 in { // FXU Operations.
2137 def ISEL : AForm_4<31, 15,
2138 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2139 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
2143 let PPC970_Unit = 1 in { // FXU Operations.
2144 // M-Form instructions. rotate and mask instructions.
2146 let isCommutable = 1 in {
2147 // RLWIMI can be commuted if the rotate amount is zero.
2148 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2149 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2150 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2151 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2152 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2154 let BaseName = "rlwinm" in {
2155 def RLWINM : MForm_2<21,
2156 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2157 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2160 def RLWINMo : MForm_2<21,
2161 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2162 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2163 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2165 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2166 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2167 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2170 } // neverHasSideEffects = 1
2172 //===----------------------------------------------------------------------===//
2173 // PowerPC Instruction Patterns
2176 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2177 def : Pat<(i32 imm:$imm),
2178 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2180 // Implement the 'not' operation with the NOR instruction.
2181 def NOT : Pat<(not i32:$in),
2184 // ADD an arbitrary immediate.
2185 def : Pat<(add i32:$in, imm:$imm),
2186 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2187 // OR an arbitrary immediate.
2188 def : Pat<(or i32:$in, imm:$imm),
2189 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2190 // XOR an arbitrary immediate.
2191 def : Pat<(xor i32:$in, imm:$imm),
2192 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2194 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2195 (SUBFIC $in, imm:$imm)>;
2198 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2199 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2200 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2201 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2204 def : Pat<(rotl i32:$in, i32:$sh),
2205 (RLWNM $in, $sh, 0, 31)>;
2206 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2207 (RLWINM $in, imm:$imm, 0, 31)>;
2210 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2211 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2214 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2215 (BL tglobaladdr:$dst)>;
2216 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2217 (BL texternalsym:$dst)>;
2220 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2221 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2223 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2224 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2226 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2227 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2231 // Hi and Lo for Darwin Global Addresses.
2232 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2233 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2234 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2235 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2236 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2237 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2238 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2239 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2240 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2241 (ADDIS $in, tglobaltlsaddr:$g)>;
2242 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2243 (ADDI $in, tglobaltlsaddr:$g)>;
2244 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2245 (ADDIS $in, tglobaladdr:$g)>;
2246 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2247 (ADDIS $in, tconstpool:$g)>;
2248 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2249 (ADDIS $in, tjumptable:$g)>;
2250 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2251 (ADDIS $in, tblockaddress:$g)>;
2253 // Standard shifts. These are represented separately from the real shifts above
2254 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2256 def : Pat<(sra i32:$rS, i32:$rB),
2258 def : Pat<(srl i32:$rS, i32:$rB),
2260 def : Pat<(shl i32:$rS, i32:$rB),
2263 def : Pat<(zextloadi1 iaddr:$src),
2265 def : Pat<(zextloadi1 xaddr:$src),
2267 def : Pat<(extloadi1 iaddr:$src),
2269 def : Pat<(extloadi1 xaddr:$src),
2271 def : Pat<(extloadi8 iaddr:$src),
2273 def : Pat<(extloadi8 xaddr:$src),
2275 def : Pat<(extloadi16 iaddr:$src),
2277 def : Pat<(extloadi16 xaddr:$src),
2279 def : Pat<(f64 (extloadf32 iaddr:$src)),
2280 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2281 def : Pat<(f64 (extloadf32 xaddr:$src)),
2282 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2284 def : Pat<(f64 (fextend f32:$src)),
2285 (COPY_TO_REGCLASS $src, F8RC)>;
2287 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>;
2289 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2290 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2291 (FNMSUB $A, $C, $B)>;
2292 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2293 (FNMSUB $A, $C, $B)>;
2294 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2295 (FNMSUBS $A, $C, $B)>;
2296 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2297 (FNMSUBS $A, $C, $B)>;
2299 // FCOPYSIGN's operand types need not agree.
2300 def : Pat<(fcopysign f64:$frB, f32:$frA),
2301 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2302 def : Pat<(fcopysign f32:$frB, f64:$frA),
2303 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2305 include "PPCInstrAltivec.td"
2306 include "PPCInstr64Bit.td"
2309 //===----------------------------------------------------------------------===//
2310 // PowerPC Instructions used for assembler/disassembler only
2313 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
2314 "isync", IIC_SprISYNC, []>;
2316 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
2317 "icbi $src", IIC_LdStICBI, []>;
2319 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
2320 "eieio", IIC_LdStLoad, []>;
2322 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
2323 "wait $L", IIC_LdStLoad, []>;
2325 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
2326 "mtmsr $RS, $L", IIC_SprMTMSR>;
2328 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
2329 "mfmsr $RT", IIC_SprMFMSR, []>;
2331 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
2332 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
2334 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
2335 "slbie $RB", IIC_SprSLBIE, []>;
2337 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
2338 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
2340 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
2341 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
2343 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
2345 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
2346 "tlbsync", IIC_SprTLBSYNC, []>;
2348 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
2349 "tlbiel $RB", IIC_SprTLBIEL, []>;
2351 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
2352 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
2354 //===----------------------------------------------------------------------===//
2355 // PowerPC Assembler Instruction Aliases
2358 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
2359 // These are aliases that require C++ handling to convert to the target
2360 // instruction, while InstAliases can be handled directly by tblgen.
2361 class PPCAsmPseudo<string asm, dag iops>
2363 let Namespace = "PPC";
2364 bit PPC64 = 0; // Default value, override with isPPC64
2366 let OutOperandList = (outs);
2367 let InOperandList = iops;
2369 let AsmString = asm;
2370 let isAsmParserOnly = 1;
2374 def : InstAlias<"sc", (SC 0)>;
2376 def : InstAlias<"sync", (SYNC 0)>;
2377 def : InstAlias<"msync", (SYNC 0)>;
2378 def : InstAlias<"lwsync", (SYNC 1)>;
2379 def : InstAlias<"ptesync", (SYNC 2)>;
2381 def : InstAlias<"wait", (WAIT 0)>;
2382 def : InstAlias<"waitrsv", (WAIT 1)>;
2383 def : InstAlias<"waitimpl", (WAIT 2)>;
2385 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
2386 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
2387 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
2388 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
2390 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
2391 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
2393 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
2394 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
2396 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
2398 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2399 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2401 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2402 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2404 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
2406 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
2408 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
2409 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2410 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
2411 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2412 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
2413 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2414 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
2415 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2417 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2418 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2419 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2420 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2422 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
2423 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
2425 def : InstAlias<"mfsprg $RT, 0", (MFSPR gprc:$RT, 272)>;
2426 def : InstAlias<"mfsprg $RT, 1", (MFSPR gprc:$RT, 273)>;
2427 def : InstAlias<"mfsprg $RT, 2", (MFSPR gprc:$RT, 274)>;
2428 def : InstAlias<"mfsprg $RT, 3", (MFSPR gprc:$RT, 275)>;
2430 def : InstAlias<"mfsprg0 $RT", (MFSPR gprc:$RT, 272)>;
2431 def : InstAlias<"mfsprg1 $RT", (MFSPR gprc:$RT, 273)>;
2432 def : InstAlias<"mfsprg2 $RT", (MFSPR gprc:$RT, 274)>;
2433 def : InstAlias<"mfsprg3 $RT", (MFSPR gprc:$RT, 275)>;
2435 def : InstAlias<"mtsprg 0, $RT", (MTSPR 272, gprc:$RT)>;
2436 def : InstAlias<"mtsprg 1, $RT", (MTSPR 273, gprc:$RT)>;
2437 def : InstAlias<"mtsprg 2, $RT", (MTSPR 274, gprc:$RT)>;
2438 def : InstAlias<"mtsprg 3, $RT", (MTSPR 275, gprc:$RT)>;
2440 def : InstAlias<"mtsprg0 $RT", (MTSPR 272, gprc:$RT)>;
2441 def : InstAlias<"mtsprg1 $RT", (MTSPR 273, gprc:$RT)>;
2442 def : InstAlias<"mtsprg2 $RT", (MTSPR 274, gprc:$RT)>;
2443 def : InstAlias<"mtsprg3 $RT", (MTSPR 275, gprc:$RT)>;
2445 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
2447 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
2448 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
2450 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
2452 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
2453 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
2455 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
2456 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
2457 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
2458 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
2460 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
2462 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
2463 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2464 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
2465 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2466 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
2467 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2468 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
2469 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2470 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
2471 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2472 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
2473 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2474 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
2475 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2476 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
2477 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2478 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
2479 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2480 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
2481 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2482 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
2483 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2484 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
2485 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2486 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
2487 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2488 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
2489 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2490 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
2491 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2492 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
2493 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2494 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
2495 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
2496 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
2497 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
2499 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
2500 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
2501 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
2502 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
2503 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
2504 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
2506 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
2507 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2508 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
2509 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2510 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
2511 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2512 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
2513 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2514 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
2515 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2516 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
2517 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2518 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
2519 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2520 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
2521 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2522 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
2523 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2524 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
2525 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2526 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
2527 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2528 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
2529 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2530 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
2531 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2532 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
2533 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2534 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
2535 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
2536 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
2537 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
2539 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
2540 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
2541 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
2542 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
2543 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
2544 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
2546 // These generic branch instruction forms are used for the assembler parser only.
2547 // Defs and Uses are conservative, since we don't know the BO value.
2548 let PPC970_Unit = 7 in {
2549 let Defs = [CTR], Uses = [CTR, RM] in {
2550 def gBC : BForm_3<16, 0, 0, (outs),
2551 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
2552 "bc $bo, $bi, $dst">;
2553 def gBCA : BForm_3<16, 1, 0, (outs),
2554 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
2555 "bca $bo, $bi, $dst">;
2557 let Defs = [LR, CTR], Uses = [CTR, RM] in {
2558 def gBCL : BForm_3<16, 0, 1, (outs),
2559 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
2560 "bcl $bo, $bi, $dst">;
2561 def gBCLA : BForm_3<16, 1, 1, (outs),
2562 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
2563 "bcla $bo, $bi, $dst">;
2565 let Defs = [CTR], Uses = [CTR, LR, RM] in
2566 def gBCLR : XLForm_2<19, 16, 0, (outs),
2567 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2568 "bclr $bo, $bi, $bh", IIC_BrB, []>;
2569 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
2570 def gBCLRL : XLForm_2<19, 16, 1, (outs),
2571 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2572 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
2573 let Defs = [CTR], Uses = [CTR, LR, RM] in
2574 def gBCCTR : XLForm_2<19, 528, 0, (outs),
2575 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2576 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
2577 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
2578 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
2579 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2580 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
2582 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
2583 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
2584 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
2585 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
2587 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
2588 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
2589 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
2590 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
2591 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
2592 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
2593 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
2595 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
2596 : BranchSimpleMnemonic1<name, pm, bo> {
2597 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
2598 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
2600 defm : BranchSimpleMnemonic2<"t", "", 12>;
2601 defm : BranchSimpleMnemonic2<"f", "", 4>;
2602 defm : BranchSimpleMnemonic2<"t", "-", 14>;
2603 defm : BranchSimpleMnemonic2<"f", "-", 6>;
2604 defm : BranchSimpleMnemonic2<"t", "+", 15>;
2605 defm : BranchSimpleMnemonic2<"f", "+", 7>;
2606 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
2607 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
2608 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
2609 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
2611 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
2612 def : InstAlias<"b"#name#pm#" $cc, $dst",
2613 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
2614 def : InstAlias<"b"#name#pm#" $dst",
2615 (BCC bibo, CR0, condbrtarget:$dst)>;
2617 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
2618 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
2619 def : InstAlias<"b"#name#"a"#pm#" $dst",
2620 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
2622 def : InstAlias<"b"#name#"lr"#pm#" $cc",
2623 (BCLR bibo, crrc:$cc)>;
2624 def : InstAlias<"b"#name#"lr"#pm,
2627 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
2628 (BCCTR bibo, crrc:$cc)>;
2629 def : InstAlias<"b"#name#"ctr"#pm,
2632 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
2633 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
2634 def : InstAlias<"b"#name#"l"#pm#" $dst",
2635 (BCCL bibo, CR0, condbrtarget:$dst)>;
2637 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
2638 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
2639 def : InstAlias<"b"#name#"la"#pm#" $dst",
2640 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
2642 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
2643 (BCLRL bibo, crrc:$cc)>;
2644 def : InstAlias<"b"#name#"lrl"#pm,
2647 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
2648 (BCCTRL bibo, crrc:$cc)>;
2649 def : InstAlias<"b"#name#"ctrl"#pm,
2650 (BCCTRL bibo, CR0)>;
2652 multiclass BranchExtendedMnemonic<string name, int bibo> {
2653 defm : BranchExtendedMnemonicPM<name, "", bibo>;
2654 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
2655 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
2657 defm : BranchExtendedMnemonic<"lt", 12>;
2658 defm : BranchExtendedMnemonic<"gt", 44>;
2659 defm : BranchExtendedMnemonic<"eq", 76>;
2660 defm : BranchExtendedMnemonic<"un", 108>;
2661 defm : BranchExtendedMnemonic<"so", 108>;
2662 defm : BranchExtendedMnemonic<"ge", 4>;
2663 defm : BranchExtendedMnemonic<"nl", 4>;
2664 defm : BranchExtendedMnemonic<"le", 36>;
2665 defm : BranchExtendedMnemonic<"ng", 36>;
2666 defm : BranchExtendedMnemonic<"ne", 68>;
2667 defm : BranchExtendedMnemonic<"nu", 100>;
2668 defm : BranchExtendedMnemonic<"ns", 100>;
2670 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
2671 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
2672 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
2673 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
2674 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
2675 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
2676 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
2677 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
2679 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
2680 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
2681 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
2682 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
2683 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm:$imm)>;
2684 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
2685 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm:$imm)>;
2686 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
2688 multiclass TrapExtendedMnemonic<string name, int to> {
2689 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
2690 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
2691 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
2692 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
2694 defm : TrapExtendedMnemonic<"lt", 16>;
2695 defm : TrapExtendedMnemonic<"le", 20>;
2696 defm : TrapExtendedMnemonic<"eq", 4>;
2697 defm : TrapExtendedMnemonic<"ge", 12>;
2698 defm : TrapExtendedMnemonic<"gt", 8>;
2699 defm : TrapExtendedMnemonic<"nl", 12>;
2700 defm : TrapExtendedMnemonic<"ne", 24>;
2701 defm : TrapExtendedMnemonic<"ng", 20>;
2702 defm : TrapExtendedMnemonic<"llt", 2>;
2703 defm : TrapExtendedMnemonic<"lle", 6>;
2704 defm : TrapExtendedMnemonic<"lge", 5>;
2705 defm : TrapExtendedMnemonic<"lgt", 1>;
2706 defm : TrapExtendedMnemonic<"lnl", 5>;
2707 defm : TrapExtendedMnemonic<"lng", 6>;
2708 defm : TrapExtendedMnemonic<"u", 31>;