1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
28 def SDT_PPCvperm : SDTypeProfile<1, 3, [
29 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
32 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
33 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
36 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
37 SDTCisVT<1, i32>, SDTCisVT<2, OtherVT>
40 def SDT_PPClbrx : SDTypeProfile<1, 3, [
41 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
43 def SDT_PPCstbrx : SDTypeProfile<0, 4, [
44 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
47 //===----------------------------------------------------------------------===//
48 // PowerPC specific DAG Nodes.
51 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
52 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
53 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
54 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
56 def PPCfsel : SDNode<"PPCISD::FSEL",
57 // Type constraint for fsel.
58 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
59 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
61 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
62 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
63 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
64 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
66 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
68 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
69 // amounts. These nodes are generated by the multi-precision shift code.
70 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
71 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
72 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
74 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
75 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
77 // These are target-independent nodes, but have target-specific formats.
78 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,
79 [SDNPHasChain, SDNPOutFlag]>;
80 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,
81 [SDNPHasChain, SDNPOutFlag]>;
83 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
84 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
85 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
86 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
87 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
88 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTRet,
89 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
91 def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet,
92 [SDNPHasChain, SDNPOptInFlag]>;
94 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
95 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
97 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
98 [SDNPHasChain, SDNPOptInFlag]>;
100 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
101 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>;
103 // Instructions to support dynamic alloca.
104 def SDTDynOp : SDTypeProfile<1, 2, []>;
105 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
107 //===----------------------------------------------------------------------===//
108 // PowerPC specific transformation functions and pattern fragments.
111 def SHL32 : SDNodeXForm<imm, [{
112 // Transformation function: 31 - imm
113 return getI32Imm(31 - N->getValue());
116 def SRL32 : SDNodeXForm<imm, [{
117 // Transformation function: 32 - imm
118 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
121 def LO16 : SDNodeXForm<imm, [{
122 // Transformation function: get the low 16 bits.
123 return getI32Imm((unsigned short)N->getValue());
126 def HI16 : SDNodeXForm<imm, [{
127 // Transformation function: shift the immediate value down into the low bits.
128 return getI32Imm((unsigned)N->getValue() >> 16);
131 def HA16 : SDNodeXForm<imm, [{
132 // Transformation function: shift the immediate value down into the low bits.
133 signed int Val = N->getValue();
134 return getI32Imm((Val - (signed short)Val) >> 16);
136 def MB : SDNodeXForm<imm, [{
137 // Transformation function: get the start bit of a mask
139 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
140 return getI32Imm(mb);
143 def ME : SDNodeXForm<imm, [{
144 // Transformation function: get the end bit of a mask
146 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
147 return getI32Imm(me);
149 def maskimm32 : PatLeaf<(imm), [{
150 // maskImm predicate - True if immediate is a run of ones.
152 if (N->getValueType(0) == MVT::i32)
153 return isRunOfOnes((unsigned)N->getValue(), mb, me);
158 def immSExt16 : PatLeaf<(imm), [{
159 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
160 // field. Used by instructions like 'addi'.
161 if (N->getValueType(0) == MVT::i32)
162 return (int32_t)N->getValue() == (short)N->getValue();
164 return (int64_t)N->getValue() == (short)N->getValue();
166 def immZExt16 : PatLeaf<(imm), [{
167 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
168 // field. Used by instructions like 'ori'.
169 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
172 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
173 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
174 // identical in 32-bit mode, but in 64-bit mode, they return true if the
175 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
177 def imm16ShiftedZExt : PatLeaf<(imm), [{
178 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
179 // immediate are set. Used by instructions like 'xoris'.
180 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
183 def imm16ShiftedSExt : PatLeaf<(imm), [{
184 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
185 // immediate are set. Used by instructions like 'addis'. Identical to
186 // imm16ShiftedZExt in 32-bit mode.
187 if (N->getValue() & 0xFFFF) return false;
188 if (N->getValueType(0) == MVT::i32)
190 // For 64-bit, make sure it is sext right.
191 return N->getValue() == (uint64_t)(int)N->getValue();
195 //===----------------------------------------------------------------------===//
196 // PowerPC Flag Definitions.
198 class isPPC64 { bit PPC64 = 1; }
200 list<Register> Defs = [CR0];
204 class RegConstraint<string C> {
205 string Constraints = C;
207 class NoEncode<string E> {
208 string DisableEncoding = E;
212 //===----------------------------------------------------------------------===//
213 // PowerPC Operand Definitions.
215 def s5imm : Operand<i32> {
216 let PrintMethod = "printS5ImmOperand";
218 def u5imm : Operand<i32> {
219 let PrintMethod = "printU5ImmOperand";
221 def u6imm : Operand<i32> {
222 let PrintMethod = "printU6ImmOperand";
224 def s16imm : Operand<i32> {
225 let PrintMethod = "printS16ImmOperand";
227 def u16imm : Operand<i32> {
228 let PrintMethod = "printU16ImmOperand";
230 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
231 let PrintMethod = "printS16X4ImmOperand";
233 def target : Operand<OtherVT> {
234 let PrintMethod = "printBranchOperand";
236 def calltarget : Operand<iPTR> {
237 let PrintMethod = "printCallOperand";
239 def aaddr : Operand<iPTR> {
240 let PrintMethod = "printAbsAddrOperand";
242 def piclabel: Operand<iPTR> {
243 let PrintMethod = "printPICLabel";
245 def symbolHi: Operand<i32> {
246 let PrintMethod = "printSymbolHi";
248 def symbolLo: Operand<i32> {
249 let PrintMethod = "printSymbolLo";
251 def crbitm: Operand<i8> {
252 let PrintMethod = "printcrbitm";
255 def memri : Operand<iPTR> {
256 let PrintMethod = "printMemRegImm";
257 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
259 def memrr : Operand<iPTR> {
260 let PrintMethod = "printMemRegReg";
261 let MIOperandInfo = (ops ptr_rc, ptr_rc);
263 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
264 let PrintMethod = "printMemRegImmShifted";
265 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
268 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
269 // that doesn't matter.
270 def pred : PredicateOperand<(ops imm, CRRC), (ops (i32 20), CR0)> {
271 let PrintMethod = "printPredicateOperand";
274 // Define PowerPC specific addressing mode.
275 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
276 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
277 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
278 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
280 /// This is just the offset part of iaddr, used for preinc.
281 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
283 //===----------------------------------------------------------------------===//
284 // PowerPC Instruction Predicate Definitions.
285 def FPContractions : Predicate<"!NoExcessFPPrecision">;
288 //===----------------------------------------------------------------------===//
289 // PowerPC Instruction Definitions.
291 // Pseudo-instructions:
293 let hasCtrlDep = 1 in {
294 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
295 "${:comment} ADJCALLSTACKDOWN",
296 [(callseq_start imm:$amt)]>, Imp<[R1],[R1]>;
297 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
298 "${:comment} ADJCALLSTACKUP",
299 [(callseq_end imm:$amt)]>, Imp<[R1],[R1]>;
301 def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
302 "UPDATE_VRSAVE $rD, $rS", []>;
305 def DYNALLOC : Pseudo<(ops GPRC:$result, GPRC:$negsize, memri:$fpsi),
306 "${:comment} DYNALLOC $result, $negsize, $fpsi",
308 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>,
311 def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD),"${:comment}IMPLICIT_DEF_GPRC $rD",
312 [(set GPRC:$rD, (undef))]>;
313 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "${:comment} IMPLICIT_DEF_F8 $rD",
314 [(set F8RC:$rD, (undef))]>;
315 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "${:comment} IMPLICIT_DEF_F4 $rD",
316 [(set F4RC:$rD, (undef))]>;
318 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
319 // scheduler into a branch sequence.
320 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
321 PPC970_Single = 1 in {
322 def SELECT_CC_I4 : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
323 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
325 def SELECT_CC_I8 : Pseudo<(ops G8RC:$dst, CRRC:$cond, G8RC:$T, G8RC:$F,
326 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
328 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
329 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
331 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
332 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
334 def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F,
335 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
339 let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
341 def BLR : XLForm_2_br<19, 16, 0, (ops pred:$p),
342 "b${p:cc}lr ${p:reg}", BrB,
344 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
350 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
353 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
354 noResults = 1, PPC970_Unit = 7 in {
355 let isBarrier = 1 in {
356 def B : IForm<18, 0, 0, (ops target:$dst),
361 // BCC is formed before branch selection, it is turned into Bxx below.
362 // 'opc' is a 'PPC::Predicate' value.
363 def BCC : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
364 "${:comment} BCC $crS, $opc, $dst",
365 [(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
367 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
368 "blt $crS, $block", BrB>;
369 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
370 "ble $crS, $block", BrB>;
371 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
372 "beq $crS, $block", BrB>;
373 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
374 "bge $crS, $block", BrB>;
375 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
376 "bgt $crS, $block", BrB>;
377 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
378 "bne $crS, $block", BrB>;
379 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
380 "bun $crS, $block", BrB>;
381 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
382 "bnu $crS, $block", BrB>;
385 let isCall = 1, noResults = 1, PPC970_Unit = 7,
386 // All calls clobber the non-callee saved registers...
387 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
388 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
389 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
391 CR0,CR1,CR5,CR6,CR7] in {
392 // Convenient aliases for call instructions
393 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
394 "bl $func", BrB, []>; // See Pat patterns below.
395 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
396 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
397 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB,
401 // DCB* instructions.
402 def DCBA : DCB_Form<758, 0, (ops memrr:$dst),
403 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
404 PPC970_DGroup_Single;
405 def DCBF : DCB_Form<86, 0, (ops memrr:$dst),
406 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
407 PPC970_DGroup_Single;
408 def DCBI : DCB_Form<470, 0, (ops memrr:$dst),
409 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
410 PPC970_DGroup_Single;
411 def DCBST : DCB_Form<54, 0, (ops memrr:$dst),
412 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
413 PPC970_DGroup_Single;
414 def DCBT : DCB_Form<278, 0, (ops memrr:$dst),
415 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
416 PPC970_DGroup_Single;
417 def DCBTST : DCB_Form<246, 0, (ops memrr:$dst),
418 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
419 PPC970_DGroup_Single;
420 def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
421 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
422 PPC970_DGroup_Single;
423 def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
424 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
425 PPC970_DGroup_Single;
427 //===----------------------------------------------------------------------===//
428 // PPC32 Load Instructions.
431 // Unindexed (r+i) Loads.
432 let isLoad = 1, PPC970_Unit = 2 in {
433 def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
434 "lbz $rD, $src", LdStGeneral,
435 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
436 def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
437 "lha $rD, $src", LdStLHA,
438 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
439 PPC970_DGroup_Cracked;
440 def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
441 "lhz $rD, $src", LdStGeneral,
442 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
443 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
444 "lwz $rD, $src", LdStGeneral,
445 [(set GPRC:$rD, (load iaddr:$src))]>;
447 def LFS : DForm_1<48, (ops F4RC:$rD, memri:$src),
448 "lfs $rD, $src", LdStLFDU,
449 [(set F4RC:$rD, (load iaddr:$src))]>;
450 def LFD : DForm_1<50, (ops F8RC:$rD, memri:$src),
451 "lfd $rD, $src", LdStLFD,
452 [(set F8RC:$rD, (load iaddr:$src))]>;
455 // Unindexed (r+i) Loads with Update (preinc).
456 def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
457 "lbzu $rD, $addr", LdStGeneral,
458 []>, RegConstraint<"$addr.reg = $ea_result">,
459 NoEncode<"$ea_result">;
461 def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
462 "lhau $rD, $addr", LdStGeneral,
463 []>, RegConstraint<"$addr.reg = $ea_result">,
464 NoEncode<"$ea_result">;
466 def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
467 "lhzu $rD, $addr", LdStGeneral,
468 []>, RegConstraint<"$addr.reg = $ea_result">,
469 NoEncode<"$ea_result">;
471 def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
472 "lwzu $rD, $addr", LdStGeneral,
473 []>, RegConstraint<"$addr.reg = $ea_result">,
474 NoEncode<"$ea_result">;
476 def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$ea_result, memri:$addr),
477 "lfs $rD, $addr", LdStLFDU,
478 []>, RegConstraint<"$addr.reg = $ea_result">,
479 NoEncode<"$ea_result">;
481 def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$ea_result, memri:$addr),
482 "lfd $rD, $addr", LdStLFD,
483 []>, RegConstraint<"$addr.reg = $ea_result">,
484 NoEncode<"$ea_result">;
487 // Indexed (r+r) Loads.
489 let isLoad = 1, PPC970_Unit = 2 in {
490 def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
491 "lbzx $rD, $src", LdStGeneral,
492 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
493 def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
494 "lhax $rD, $src", LdStLHA,
495 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
496 PPC970_DGroup_Cracked;
497 def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
498 "lhzx $rD, $src", LdStGeneral,
499 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
500 def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
501 "lwzx $rD, $src", LdStGeneral,
502 [(set GPRC:$rD, (load xaddr:$src))]>;
505 def LHBRX : XForm_1<31, 790, (ops GPRC:$rD, memrr:$src),
506 "lhbrx $rD, $src", LdStGeneral,
507 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
508 def LWBRX : XForm_1<31, 534, (ops GPRC:$rD, memrr:$src),
509 "lwbrx $rD, $src", LdStGeneral,
510 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
512 def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
513 "lfsx $frD, $src", LdStLFDU,
514 [(set F4RC:$frD, (load xaddr:$src))]>;
515 def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
516 "lfdx $frD, $src", LdStLFDU,
517 [(set F8RC:$frD, (load xaddr:$src))]>;
520 //===----------------------------------------------------------------------===//
521 // PPC32 Store Instructions.
524 // Unindexed (r+i) Stores.
525 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
526 def STB : DForm_1<38, (ops GPRC:$rS, memri:$src),
527 "stb $rS, $src", LdStGeneral,
528 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
529 def STH : DForm_1<44, (ops GPRC:$rS, memri:$src),
530 "sth $rS, $src", LdStGeneral,
531 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
532 def STW : DForm_1<36, (ops GPRC:$rS, memri:$src),
533 "stw $rS, $src", LdStGeneral,
534 [(store GPRC:$rS, iaddr:$src)]>;
535 def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst),
536 "stfs $rS, $dst", LdStUX,
537 [(store F4RC:$rS, iaddr:$dst)]>;
538 def STFD : DForm_1<54, (ops F8RC:$rS, memri:$dst),
539 "stfd $rS, $dst", LdStUX,
540 [(store F8RC:$rS, iaddr:$dst)]>;
543 // Unindexed (r+i) Stores with Update (preinc).
544 let isStore = 1, PPC970_Unit = 2 in {
545 def STBU : DForm_1<39, (ops ptr_rc:$ea_res, GPRC:$rS,
546 symbolLo:$ptroff, ptr_rc:$ptrreg),
547 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
548 [(set ptr_rc:$ea_res,
549 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
550 iaddroff:$ptroff))]>,
551 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
552 def STHU : DForm_1<45, (ops ptr_rc:$ea_res, GPRC:$rS,
553 symbolLo:$ptroff, ptr_rc:$ptrreg),
554 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
555 [(set ptr_rc:$ea_res,
556 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
557 iaddroff:$ptroff))]>,
558 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
559 def STWU : DForm_1<37, (ops ptr_rc:$ea_res, GPRC:$rS,
560 symbolLo:$ptroff, ptr_rc:$ptrreg),
561 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
562 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
563 iaddroff:$ptroff))]>,
564 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
565 def STFSU : DForm_1<37, (ops ptr_rc:$ea_res, F4RC:$rS,
566 symbolLo:$ptroff, ptr_rc:$ptrreg),
567 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
568 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
569 iaddroff:$ptroff))]>,
570 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
571 def STFDU : DForm_1<37, (ops ptr_rc:$ea_res, F8RC:$rS,
572 symbolLo:$ptroff, ptr_rc:$ptrreg),
573 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
574 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
575 iaddroff:$ptroff))]>,
576 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
580 // Indexed (r+r) Stores.
582 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
583 def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
584 "stbx $rS, $dst", LdStGeneral,
585 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
586 PPC970_DGroup_Cracked;
587 def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
588 "sthx $rS, $dst", LdStGeneral,
589 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
590 PPC970_DGroup_Cracked;
591 def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
592 "stwx $rS, $dst", LdStGeneral,
593 [(store GPRC:$rS, xaddr:$dst)]>,
594 PPC970_DGroup_Cracked;
595 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
596 "stwux $rS, $rA, $rB", LdStGeneral,
598 def STHBRX: XForm_8<31, 918, (ops GPRC:$rS, memrr:$dst),
599 "sthbrx $rS, $dst", LdStGeneral,
600 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
601 PPC970_DGroup_Cracked;
602 def STWBRX: XForm_8<31, 662, (ops GPRC:$rS, memrr:$dst),
603 "stwbrx $rS, $dst", LdStGeneral,
604 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
605 PPC970_DGroup_Cracked;
607 def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst),
608 "stfiwx $frS, $dst", LdStUX,
609 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
610 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
611 "stfsx $frS, $dst", LdStUX,
612 [(store F4RC:$frS, xaddr:$dst)]>;
613 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
614 "stfdx $frS, $dst", LdStUX,
615 [(store F8RC:$frS, xaddr:$dst)]>;
619 //===----------------------------------------------------------------------===//
620 // PPC32 Arithmetic Instructions.
623 let PPC970_Unit = 1 in { // FXU Operations.
624 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
625 "addi $rD, $rA, $imm", IntGeneral,
626 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
627 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
628 "addic $rD, $rA, $imm", IntGeneral,
629 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
630 PPC970_DGroup_Cracked;
631 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
632 "addic. $rD, $rA, $imm", IntGeneral,
634 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
635 "addis $rD, $rA, $imm", IntGeneral,
636 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
637 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
638 "la $rD, $sym($rA)", IntGeneral,
639 [(set GPRC:$rD, (add GPRC:$rA,
640 (PPClo tglobaladdr:$sym, 0)))]>;
641 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
642 "mulli $rD, $rA, $imm", IntMulLI,
643 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
644 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
645 "subfic $rD, $rA, $imm", IntGeneral,
646 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
647 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
648 "li $rD, $imm", IntGeneral,
649 [(set GPRC:$rD, immSExt16:$imm)]>;
650 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
651 "lis $rD, $imm", IntGeneral,
652 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
655 let PPC970_Unit = 1 in { // FXU Operations.
656 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
657 "andi. $dst, $src1, $src2", IntGeneral,
658 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
660 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
661 "andis. $dst, $src1, $src2", IntGeneral,
662 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
664 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
665 "ori $dst, $src1, $src2", IntGeneral,
666 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
667 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
668 "oris $dst, $src1, $src2", IntGeneral,
669 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
670 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
671 "xori $dst, $src1, $src2", IntGeneral,
672 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
673 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
674 "xoris $dst, $src1, $src2", IntGeneral,
675 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
676 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
678 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
679 "cmpwi $crD, $rA, $imm", IntCompare>;
680 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
681 "cmplwi $dst, $src1, $src2", IntCompare>;
685 let PPC970_Unit = 1 in { // FXU Operations.
686 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
687 "nand $rA, $rS, $rB", IntGeneral,
688 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
689 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
690 "and $rA, $rS, $rB", IntGeneral,
691 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
692 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
693 "andc $rA, $rS, $rB", IntGeneral,
694 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
695 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
696 "or $rA, $rS, $rB", IntGeneral,
697 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
698 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
699 "nor $rA, $rS, $rB", IntGeneral,
700 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
701 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
702 "orc $rA, $rS, $rB", IntGeneral,
703 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
704 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
705 "eqv $rA, $rS, $rB", IntGeneral,
706 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
707 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
708 "xor $rA, $rS, $rB", IntGeneral,
709 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
710 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
711 "slw $rA, $rS, $rB", IntGeneral,
712 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
713 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
714 "srw $rA, $rS, $rB", IntGeneral,
715 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
716 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
717 "sraw $rA, $rS, $rB", IntShift,
718 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
721 let PPC970_Unit = 1 in { // FXU Operations.
722 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
723 "srawi $rA, $rS, $SH", IntShift,
724 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
725 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
726 "cntlzw $rA, $rS", IntGeneral,
727 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
728 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
729 "extsb $rA, $rS", IntGeneral,
730 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
731 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
732 "extsh $rA, $rS", IntGeneral,
733 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
735 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
736 "cmpw $crD, $rA, $rB", IntCompare>;
737 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
738 "cmplw $crD, $rA, $rB", IntCompare>;
740 let PPC970_Unit = 3 in { // FPU Operations.
741 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
742 // "fcmpo $crD, $fA, $fB", FPCompare>;
743 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
744 "fcmpu $crD, $fA, $fB", FPCompare>;
745 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
746 "fcmpu $crD, $fA, $fB", FPCompare>;
748 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
749 "fctiwz $frD, $frB", FPGeneral,
750 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
751 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
752 "frsp $frD, $frB", FPGeneral,
753 [(set F4RC:$frD, (fround F8RC:$frB))]>;
754 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
755 "fsqrt $frD, $frB", FPSqrt,
756 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
757 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
758 "fsqrts $frD, $frB", FPSqrt,
759 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
762 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
764 /// Note that these are defined as pseudo-ops on the PPC970 because they are
765 /// often coalesced away and we don't want the dispatch group builder to think
766 /// that they will fill slots (which could cause the load of a LSU reject to
767 /// sneak into a d-group with a store).
768 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
769 "fmr $frD, $frB", FPGeneral,
770 []>, // (set F4RC:$frD, F4RC:$frB)
772 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
773 "fmr $frD, $frB", FPGeneral,
774 []>, // (set F8RC:$frD, F8RC:$frB)
776 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
777 "fmr $frD, $frB", FPGeneral,
778 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
781 let PPC970_Unit = 3 in { // FPU Operations.
782 // These are artificially split into two different forms, for 4/8 byte FP.
783 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
784 "fabs $frD, $frB", FPGeneral,
785 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
786 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
787 "fabs $frD, $frB", FPGeneral,
788 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
789 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
790 "fnabs $frD, $frB", FPGeneral,
791 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
792 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
793 "fnabs $frD, $frB", FPGeneral,
794 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
795 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
796 "fneg $frD, $frB", FPGeneral,
797 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
798 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
799 "fneg $frD, $frB", FPGeneral,
800 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
804 // XL-Form instructions. condition register logical ops.
806 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
807 "mcrf $BF, $BFA", BrMCR>,
808 PPC970_DGroup_First, PPC970_Unit_CRU;
810 // XFX-Form instructions. Instructions that deal with SPRs.
812 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>,
813 PPC970_DGroup_First, PPC970_Unit_FXU;
814 let Pattern = [(PPCmtctr GPRC:$rS)] in {
815 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>,
816 PPC970_DGroup_First, PPC970_Unit_FXU;
819 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>,
820 PPC970_DGroup_First, PPC970_Unit_FXU;
821 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>,
822 PPC970_DGroup_First, PPC970_Unit_FXU;
824 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
825 // a GPR on the PPC970. As such, copies in and out have the same performance
826 // characteristics as an OR instruction.
827 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS),
828 "mtspr 256, $rS", IntGeneral>,
829 PPC970_DGroup_Single, PPC970_Unit_FXU;
830 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT),
831 "mfspr $rT, 256", IntGeneral>,
832 PPC970_DGroup_First, PPC970_Unit_FXU;
834 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
835 "mtcrf $FXM, $rS", BrMCRX>,
836 PPC970_MicroCode, PPC970_Unit_CRU;
837 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>,
838 PPC970_MicroCode, PPC970_Unit_CRU;
839 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
840 "mfcr $rT, $FXM", SprMFCR>,
841 PPC970_DGroup_First, PPC970_Unit_CRU;
843 let PPC970_Unit = 1 in { // FXU Operations.
845 // XO-Form instructions. Arithmetic instructions that can set overflow bit
847 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
848 "add $rT, $rA, $rB", IntGeneral,
849 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
850 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
851 "addc $rT, $rA, $rB", IntGeneral,
852 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
853 PPC970_DGroup_Cracked;
854 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
855 "adde $rT, $rA, $rB", IntGeneral,
856 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
857 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
858 "divw $rT, $rA, $rB", IntDivW,
859 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
860 PPC970_DGroup_First, PPC970_DGroup_Cracked;
861 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
862 "divwu $rT, $rA, $rB", IntDivW,
863 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
864 PPC970_DGroup_First, PPC970_DGroup_Cracked;
865 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
866 "mulhw $rT, $rA, $rB", IntMulHW,
867 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
868 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
869 "mulhwu $rT, $rA, $rB", IntMulHWU,
870 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
871 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
872 "mullw $rT, $rA, $rB", IntMulHW,
873 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
874 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
875 "subf $rT, $rA, $rB", IntGeneral,
876 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
877 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
878 "subfc $rT, $rA, $rB", IntGeneral,
879 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
880 PPC970_DGroup_Cracked;
881 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
882 "subfe $rT, $rA, $rB", IntGeneral,
883 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
884 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
885 "addme $rT, $rA", IntGeneral,
886 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
887 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
888 "addze $rT, $rA", IntGeneral,
889 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
890 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
891 "neg $rT, $rA", IntGeneral,
892 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
893 def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA),
894 "subfme $rT, $rA", IntGeneral,
895 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
896 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
897 "subfze $rT, $rA", IntGeneral,
898 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
901 // A-Form instructions. Most of the instructions executed in the FPU are of
904 let PPC970_Unit = 3 in { // FPU Operations.
905 def FMADD : AForm_1<63, 29,
906 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
907 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
908 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
910 Requires<[FPContractions]>;
911 def FMADDS : AForm_1<59, 29,
912 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
913 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
914 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
916 Requires<[FPContractions]>;
917 def FMSUB : AForm_1<63, 28,
918 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
919 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
920 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
922 Requires<[FPContractions]>;
923 def FMSUBS : AForm_1<59, 28,
924 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
925 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
926 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
928 Requires<[FPContractions]>;
929 def FNMADD : AForm_1<63, 31,
930 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
931 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
932 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
934 Requires<[FPContractions]>;
935 def FNMADDS : AForm_1<59, 31,
936 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
937 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
938 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
940 Requires<[FPContractions]>;
941 def FNMSUB : AForm_1<63, 30,
942 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
943 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
944 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
946 Requires<[FPContractions]>;
947 def FNMSUBS : AForm_1<59, 30,
948 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
949 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
950 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
952 Requires<[FPContractions]>;
953 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
954 // having 4 of these, force the comparison to always be an 8-byte double (code
955 // should use an FMRSD if the input comparison value really wants to be a float)
956 // and 4/8 byte forms for the result and operand type..
957 def FSELD : AForm_1<63, 23,
958 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
959 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
960 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
961 def FSELS : AForm_1<63, 23,
962 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
963 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
964 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
965 def FADD : AForm_2<63, 21,
966 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
967 "fadd $FRT, $FRA, $FRB", FPGeneral,
968 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
969 def FADDS : AForm_2<59, 21,
970 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
971 "fadds $FRT, $FRA, $FRB", FPGeneral,
972 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
973 def FDIV : AForm_2<63, 18,
974 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
975 "fdiv $FRT, $FRA, $FRB", FPDivD,
976 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
977 def FDIVS : AForm_2<59, 18,
978 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
979 "fdivs $FRT, $FRA, $FRB", FPDivS,
980 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
981 def FMUL : AForm_3<63, 25,
982 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
983 "fmul $FRT, $FRA, $FRB", FPFused,
984 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
985 def FMULS : AForm_3<59, 25,
986 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
987 "fmuls $FRT, $FRA, $FRB", FPGeneral,
988 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
989 def FSUB : AForm_2<63, 20,
990 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
991 "fsub $FRT, $FRA, $FRB", FPGeneral,
992 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
993 def FSUBS : AForm_2<59, 20,
994 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
995 "fsubs $FRT, $FRA, $FRB", FPGeneral,
996 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
999 let PPC970_Unit = 1 in { // FXU Operations.
1000 // M-Form instructions. rotate and mask instructions.
1002 let isCommutable = 1 in {
1003 // RLWIMI can be commuted if the rotate amount is zero.
1004 def RLWIMI : MForm_2<20,
1005 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1006 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1007 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1010 def RLWINM : MForm_2<21,
1011 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1012 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1014 def RLWINMo : MForm_2<21,
1015 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1016 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1017 []>, isDOT, PPC970_DGroup_Cracked;
1018 def RLWNM : MForm_2<23,
1019 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1020 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1025 //===----------------------------------------------------------------------===//
1026 // DWARF Pseudo Instructions
1029 def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
1030 "${:comment} .loc $file, $line, $col",
1031 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
1034 def DWARF_LABEL : Pseudo<(ops i32imm:$id),
1035 "\n${:private}debug_loc$id:",
1036 [(dwarf_label (i32 imm:$id))]>;
1038 //===----------------------------------------------------------------------===//
1039 // PowerPC Instruction Patterns
1042 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1043 def : Pat<(i32 imm:$imm),
1044 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1046 // Implement the 'not' operation with the NOR instruction.
1047 def NOT : Pat<(not GPRC:$in),
1048 (NOR GPRC:$in, GPRC:$in)>;
1050 // ADD an arbitrary immediate.
1051 def : Pat<(add GPRC:$in, imm:$imm),
1052 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1053 // OR an arbitrary immediate.
1054 def : Pat<(or GPRC:$in, imm:$imm),
1055 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1056 // XOR an arbitrary immediate.
1057 def : Pat<(xor GPRC:$in, imm:$imm),
1058 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1060 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1061 (SUBFIC GPRC:$in, imm:$imm)>;
1063 // Return void support.
1064 def : Pat<(ret), (BLR)>;
1067 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1068 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1069 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1070 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1073 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1074 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1075 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1076 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1079 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1080 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1083 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
1084 (BL tglobaladdr:$dst)>;
1085 def : Pat<(PPCcall (i32 texternalsym:$dst)),
1086 (BL texternalsym:$dst)>;
1088 // Hi and Lo for Darwin Global Addresses.
1089 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1090 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1091 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1092 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1093 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1094 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1095 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1096 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1097 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1098 (ADDIS GPRC:$in, tconstpool:$g)>;
1099 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1100 (ADDIS GPRC:$in, tjumptable:$g)>;
1102 // Fused negative multiply subtract, alternate pattern
1103 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1104 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1105 Requires<[FPContractions]>;
1106 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1107 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1108 Requires<[FPContractions]>;
1110 // Standard shifts. These are represented separately from the real shifts above
1111 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1113 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1114 (SRAW GPRC:$rS, GPRC:$rB)>;
1115 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1116 (SRW GPRC:$rS, GPRC:$rB)>;
1117 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1118 (SLW GPRC:$rS, GPRC:$rB)>;
1120 def : Pat<(zextloadi1 iaddr:$src),
1122 def : Pat<(zextloadi1 xaddr:$src),
1124 def : Pat<(extloadi1 iaddr:$src),
1126 def : Pat<(extloadi1 xaddr:$src),
1128 def : Pat<(extloadi8 iaddr:$src),
1130 def : Pat<(extloadi8 xaddr:$src),
1132 def : Pat<(extloadi16 iaddr:$src),
1134 def : Pat<(extloadi16 xaddr:$src),
1136 def : Pat<(extloadf32 iaddr:$src),
1137 (FMRSD (LFS iaddr:$src))>;
1138 def : Pat<(extloadf32 xaddr:$src),
1139 (FMRSD (LFSX xaddr:$src))>;
1141 include "PPCInstrAltivec.td"
1142 include "PPCInstr64Bit.td"