1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
28 def SDT_PPCvperm : SDTypeProfile<1, 3, [
29 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
32 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
33 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
36 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
37 SDTCisVT<1, i32>, SDTCisVT<2, OtherVT>
40 def SDT_PPClbrx : SDTypeProfile<1, 3, [
41 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
43 def SDT_PPCstbrx : SDTypeProfile<0, 4, [
44 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
47 //===----------------------------------------------------------------------===//
48 // PowerPC specific DAG Nodes.
51 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
52 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
53 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
54 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
56 def PPCfsel : SDNode<"PPCISD::FSEL",
57 // Type constraint for fsel.
58 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
59 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
61 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
62 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
63 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
64 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
66 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
68 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
69 // amounts. These nodes are generated by the multi-precision shift code.
70 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
71 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
72 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
74 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
75 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
77 // These are target-independent nodes, but have target-specific formats.
78 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
79 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
81 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
82 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
84 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
85 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
86 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTRet,
87 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
89 def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
93 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
95 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
96 [SDNPHasChain, SDNPOptInFlag]>;
98 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
99 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>;
101 //===----------------------------------------------------------------------===//
102 // PowerPC specific transformation functions and pattern fragments.
105 def SHL32 : SDNodeXForm<imm, [{
106 // Transformation function: 31 - imm
107 return getI32Imm(31 - N->getValue());
110 def SRL32 : SDNodeXForm<imm, [{
111 // Transformation function: 32 - imm
112 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
115 def LO16 : SDNodeXForm<imm, [{
116 // Transformation function: get the low 16 bits.
117 return getI32Imm((unsigned short)N->getValue());
120 def HI16 : SDNodeXForm<imm, [{
121 // Transformation function: shift the immediate value down into the low bits.
122 return getI32Imm((unsigned)N->getValue() >> 16);
125 def HA16 : SDNodeXForm<imm, [{
126 // Transformation function: shift the immediate value down into the low bits.
127 signed int Val = N->getValue();
128 return getI32Imm((Val - (signed short)Val) >> 16);
132 def immSExt16 : PatLeaf<(imm), [{
133 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
134 // field. Used by instructions like 'addi'.
135 if (N->getValueType(0) == MVT::i32)
136 return (int32_t)N->getValue() == (short)N->getValue();
138 return (int64_t)N->getValue() == (short)N->getValue();
140 def immZExt16 : PatLeaf<(imm), [{
141 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
142 // field. Used by instructions like 'ori'.
143 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
146 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
147 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
148 // identical in 32-bit mode, but in 64-bit mode, they return true if the
149 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
151 def imm16ShiftedZExt : PatLeaf<(imm), [{
152 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
153 // immediate are set. Used by instructions like 'xoris'.
154 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
157 def imm16ShiftedSExt : PatLeaf<(imm), [{
158 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
159 // immediate are set. Used by instructions like 'addis'. Identical to
160 // imm16ShiftedZExt in 32-bit mode.
161 if (N->getValue() & 0xFFFF) return false;
162 if (N->getValueType(0) == MVT::i32)
164 // For 64-bit, make sure it is sext right.
165 return N->getValue() == (uint64_t)(int)N->getValue();
169 //===----------------------------------------------------------------------===//
170 // PowerPC Flag Definitions.
172 class isPPC64 { bit PPC64 = 1; }
174 list<Register> Defs = [CR0];
180 //===----------------------------------------------------------------------===//
181 // PowerPC Operand Definitions.
183 def s5imm : Operand<i32> {
184 let PrintMethod = "printS5ImmOperand";
186 def u5imm : Operand<i32> {
187 let PrintMethod = "printU5ImmOperand";
189 def u6imm : Operand<i32> {
190 let PrintMethod = "printU6ImmOperand";
192 def s16imm : Operand<i32> {
193 let PrintMethod = "printS16ImmOperand";
195 def u16imm : Operand<i32> {
196 let PrintMethod = "printU16ImmOperand";
198 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
199 let PrintMethod = "printS16X4ImmOperand";
201 def target : Operand<OtherVT> {
202 let PrintMethod = "printBranchOperand";
204 def calltarget : Operand<iPTR> {
205 let PrintMethod = "printCallOperand";
207 def aaddr : Operand<iPTR> {
208 let PrintMethod = "printAbsAddrOperand";
210 def piclabel: Operand<iPTR> {
211 let PrintMethod = "printPICLabel";
213 def symbolHi: Operand<i32> {
214 let PrintMethod = "printSymbolHi";
216 def symbolLo: Operand<i32> {
217 let PrintMethod = "printSymbolLo";
219 def crbitm: Operand<i8> {
220 let PrintMethod = "printcrbitm";
223 def memri : Operand<iPTR> {
224 let PrintMethod = "printMemRegImm";
225 let NumMIOperands = 2;
226 let MIOperandInfo = (ops i32imm, ptr_rc);
228 def memrr : Operand<iPTR> {
229 let PrintMethod = "printMemRegReg";
230 let NumMIOperands = 2;
231 let MIOperandInfo = (ops ptr_rc, ptr_rc);
233 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
234 let PrintMethod = "printMemRegImmShifted";
235 let NumMIOperands = 2;
236 let MIOperandInfo = (ops i32imm, ptr_rc);
239 // Define PowerPC specific addressing mode.
240 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", []>;
241 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", []>;
242 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[]>;
243 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", []>; // "std"
245 //===----------------------------------------------------------------------===//
246 // PowerPC Instruction Predicate Definitions.
247 def FPContractions : Predicate<"!NoExcessFPPrecision">;
249 //===----------------------------------------------------------------------===//
250 // PowerPC Instruction Definitions.
252 // Pseudo-instructions:
254 let hasCtrlDep = 1 in {
255 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
256 "; ADJCALLSTACKDOWN",
257 [(callseq_start imm:$amt)]>;
258 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
260 [(callseq_end imm:$amt)]>;
262 def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
263 "UPDATE_VRSAVE $rD, $rS", []>;
265 def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD), "; IMPLICIT_DEF_GPRC $rD",
266 [(set GPRC:$rD, (undef))]>;
267 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; IMPLICIT_DEF_F8 $rD",
268 [(set F8RC:$rD, (undef))]>;
269 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; IMPLICIT_DEF_F4 $rD",
270 [(set F4RC:$rD, (undef))]>;
272 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
273 // scheduler into a branch sequence.
274 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
275 PPC970_Single = 1 in {
276 def SELECT_CC_I4 : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
277 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
278 def SELECT_CC_I8 : Pseudo<(ops G8RC:$dst, CRRC:$cond, G8RC:$T, G8RC:$F,
279 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
280 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
281 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
282 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
283 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
284 def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F,
285 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
288 let isTerminator = 1, noResults = 1, PPC970_Unit = 7 in {
290 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
291 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
295 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
298 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
299 noResults = 1, PPC970_Unit = 7 in {
300 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
301 "; COND_BRANCH $crS, $opc, $dst",
302 [(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
303 def B : IForm<18, 0, 0, (ops target:$dst),
307 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
308 "blt $crS, $block", BrB>;
309 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
310 "ble $crS, $block", BrB>;
311 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
312 "beq $crS, $block", BrB>;
313 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
314 "bge $crS, $block", BrB>;
315 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
316 "bgt $crS, $block", BrB>;
317 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
318 "bne $crS, $block", BrB>;
319 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
320 "bun $crS, $block", BrB>;
321 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
322 "bnu $crS, $block", BrB>;
325 let isCall = 1, noResults = 1, PPC970_Unit = 7,
326 // All calls clobber the non-callee saved registers...
327 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
328 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
329 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
331 CR0,CR1,CR5,CR6,CR7] in {
332 // Convenient aliases for call instructions
333 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
334 "bl $func", BrB, []>; // See Pat patterns below.
335 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
336 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
337 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB,
341 // DCB* instructions.
342 def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
343 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
344 PPC970_DGroup_Single;
345 def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
346 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
347 PPC970_DGroup_Single;
349 // D-Form instructions. Most instructions that perform an operation on a
350 // register and an immediate are of this type.
352 let isLoad = 1, PPC970_Unit = 2 in {
353 def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
354 "lbz $rD, $src", LdStGeneral,
355 [(set GPRC:$rD, (zextload iaddr:$src, i8))]>;
356 def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
357 "lha $rD, $src", LdStLHA,
358 [(set GPRC:$rD, (sextload iaddr:$src, i16))]>,
359 PPC970_DGroup_Cracked;
360 def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
361 "lhz $rD, $src", LdStGeneral,
362 [(set GPRC:$rD, (zextload iaddr:$src, i16))]>;
363 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
364 "lwz $rD, $src", LdStGeneral,
365 [(set GPRC:$rD, (load iaddr:$src))]>;
366 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
367 "lwzu $rD, $disp($rA)", LdStGeneral,
370 let PPC970_Unit = 1 in { // FXU Operations.
371 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
372 "addi $rD, $rA, $imm", IntGeneral,
373 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
374 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
375 "addic $rD, $rA, $imm", IntGeneral,
376 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
377 PPC970_DGroup_Cracked;
378 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
379 "addic. $rD, $rA, $imm", IntGeneral,
381 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
382 "addis $rD, $rA, $imm", IntGeneral,
383 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
384 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
385 "la $rD, $sym($rA)", IntGeneral,
386 [(set GPRC:$rD, (add GPRC:$rA,
387 (PPClo tglobaladdr:$sym, 0)))]>;
388 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
389 "mulli $rD, $rA, $imm", IntMulLI,
390 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
391 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
392 "subfic $rD, $rA, $imm", IntGeneral,
393 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
394 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
395 "li $rD, $imm", IntGeneral,
396 [(set GPRC:$rD, immSExt16:$imm)]>;
397 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
398 "lis $rD, $imm", IntGeneral,
399 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
401 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
402 def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
403 "stb $rS, $src", LdStGeneral,
404 [(truncstore GPRC:$rS, iaddr:$src, i8)]>;
405 def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
406 "sth $rS, $src", LdStGeneral,
407 [(truncstore GPRC:$rS, iaddr:$src, i16)]>;
408 def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
409 "stw $rS, $src", LdStGeneral,
410 [(store GPRC:$rS, iaddr:$src)]>;
411 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
412 "stwu $rS, $disp($rA)", LdStGeneral,
415 let PPC970_Unit = 1 in { // FXU Operations.
416 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
417 "andi. $dst, $src1, $src2", IntGeneral,
418 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
420 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
421 "andis. $dst, $src1, $src2", IntGeneral,
422 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
424 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
425 "ori $dst, $src1, $src2", IntGeneral,
426 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
427 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
428 "oris $dst, $src1, $src2", IntGeneral,
429 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
430 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
431 "xori $dst, $src1, $src2", IntGeneral,
432 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
433 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
434 "xoris $dst, $src1, $src2", IntGeneral,
435 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
436 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
438 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
439 "cmpwi $crD, $rA, $imm", IntCompare>;
440 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
441 "cmplwi $dst, $src1, $src2", IntCompare>;
443 let isLoad = 1, PPC970_Unit = 2 in {
444 def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src),
445 "lfs $rD, $src", LdStLFDU,
446 [(set F4RC:$rD, (load iaddr:$src))]>;
447 def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src),
448 "lfd $rD, $src", LdStLFD,
449 [(set F8RC:$rD, (load iaddr:$src))]>;
451 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
452 def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst),
453 "stfs $rS, $dst", LdStUX,
454 [(store F4RC:$rS, iaddr:$dst)]>;
455 def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst),
456 "stfd $rS, $dst", LdStUX,
457 [(store F8RC:$rS, iaddr:$dst)]>;
460 // X-Form instructions. Most instructions that perform an operation on a
461 // register and another register are of this type.
463 let isLoad = 1, PPC970_Unit = 2 in {
464 def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
465 "lbzx $rD, $src", LdStGeneral,
466 [(set GPRC:$rD, (zextload xaddr:$src, i8))]>;
467 def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
468 "lhax $rD, $src", LdStLHA,
469 [(set GPRC:$rD, (sextload xaddr:$src, i16))]>,
470 PPC970_DGroup_Cracked;
471 def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
472 "lhzx $rD, $src", LdStGeneral,
473 [(set GPRC:$rD, (zextload xaddr:$src, i16))]>;
474 def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
475 "lwzx $rD, $src", LdStGeneral,
476 [(set GPRC:$rD, (load xaddr:$src))]>;
479 def LHBRX : XForm_1<31, 790, (ops GPRC:$rD, memrr:$src),
480 "lhbrx $rD, $src", LdStGeneral,
481 [(set GPRC:$rD, (PPClbrx xaddr:$src,srcvalue:$dummy, i16))]>;
482 def LWBRX : XForm_1<31, 534, (ops GPRC:$rD, memrr:$src),
483 "lwbrx $rD, $src", LdStGeneral,
484 [(set GPRC:$rD, (PPClbrx xaddr:$src,srcvalue:$dummy, i32))]>;
488 let PPC970_Unit = 1 in { // FXU Operations.
489 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
490 "nand $rA, $rS, $rB", IntGeneral,
491 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
492 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
493 "and $rA, $rS, $rB", IntGeneral,
494 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
495 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
496 "andc $rA, $rS, $rB", IntGeneral,
497 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
498 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
499 "or $rA, $rS, $rB", IntGeneral,
500 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
501 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
502 "nor $rA, $rS, $rB", IntGeneral,
503 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
504 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
505 "orc $rA, $rS, $rB", IntGeneral,
506 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
507 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
508 "eqv $rA, $rS, $rB", IntGeneral,
509 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
510 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
511 "xor $rA, $rS, $rB", IntGeneral,
512 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
513 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
514 "slw $rA, $rS, $rB", IntGeneral,
515 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
516 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
517 "srw $rA, $rS, $rB", IntGeneral,
518 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
519 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
520 "sraw $rA, $rS, $rB", IntShift,
521 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
523 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
524 def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
525 "stbx $rS, $dst", LdStGeneral,
526 [(truncstore GPRC:$rS, xaddr:$dst, i8)]>,
527 PPC970_DGroup_Cracked;
528 def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
529 "sthx $rS, $dst", LdStGeneral,
530 [(truncstore GPRC:$rS, xaddr:$dst, i16)]>,
531 PPC970_DGroup_Cracked;
532 def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
533 "stwx $rS, $dst", LdStGeneral,
534 [(store GPRC:$rS, xaddr:$dst)]>,
535 PPC970_DGroup_Cracked;
536 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
537 "stwux $rS, $rA, $rB", LdStGeneral,
539 def STHBRX: XForm_8<31, 918, (ops GPRC:$rS, memrr:$dst),
540 "sthbrx $rS, $dst", LdStGeneral,
541 [(PPCstbrx GPRC:$rS, xaddr:$dst, srcvalue:$dummy, i16)]>,
542 PPC970_DGroup_Cracked;
543 def STWBRX: XForm_8<31, 662, (ops GPRC:$rS, memrr:$dst),
544 "stwbrx $rS, $dst", LdStGeneral,
545 [(PPCstbrx GPRC:$rS, xaddr:$dst, srcvalue:$dummy, i32)]>,
546 PPC970_DGroup_Cracked;
548 let PPC970_Unit = 1 in { // FXU Operations.
549 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
550 "srawi $rA, $rS, $SH", IntShift,
551 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
552 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
553 "cntlzw $rA, $rS", IntGeneral,
554 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
555 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
556 "extsb $rA, $rS", IntGeneral,
557 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
558 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
559 "extsh $rA, $rS", IntGeneral,
560 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
562 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
563 "cmpw $crD, $rA, $rB", IntCompare>;
564 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
565 "cmplw $crD, $rA, $rB", IntCompare>;
567 let PPC970_Unit = 3 in { // FPU Operations.
568 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
569 // "fcmpo $crD, $fA, $fB", FPCompare>;
570 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
571 "fcmpu $crD, $fA, $fB", FPCompare>;
572 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
573 "fcmpu $crD, $fA, $fB", FPCompare>;
575 let isLoad = 1, PPC970_Unit = 2 in {
576 def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
577 "lfsx $frD, $src", LdStLFDU,
578 [(set F4RC:$frD, (load xaddr:$src))]>;
579 def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
580 "lfdx $frD, $src", LdStLFDU,
581 [(set F8RC:$frD, (load xaddr:$src))]>;
583 let PPC970_Unit = 3 in { // FPU Operations.
584 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
585 "fctiwz $frD, $frB", FPGeneral,
586 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
587 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
588 "frsp $frD, $frB", FPGeneral,
589 [(set F4RC:$frD, (fround F8RC:$frB))]>;
590 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
591 "fsqrt $frD, $frB", FPSqrt,
592 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
593 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
594 "fsqrts $frD, $frB", FPSqrt,
595 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
598 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
600 /// Note that these are defined as pseudo-ops on the PPC970 because they are
601 /// often coalesced away and we don't want the dispatch group builder to think
602 /// that they will fill slots (which could cause the load of a LSU reject to
603 /// sneak into a d-group with a store).
604 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
605 "fmr $frD, $frB", FPGeneral,
606 []>, // (set F4RC:$frD, F4RC:$frB)
608 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
609 "fmr $frD, $frB", FPGeneral,
610 []>, // (set F8RC:$frD, F8RC:$frB)
612 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
613 "fmr $frD, $frB", FPGeneral,
614 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
617 let PPC970_Unit = 3 in { // FPU Operations.
618 // These are artificially split into two different forms, for 4/8 byte FP.
619 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
620 "fabs $frD, $frB", FPGeneral,
621 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
622 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
623 "fabs $frD, $frB", FPGeneral,
624 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
625 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
626 "fnabs $frD, $frB", FPGeneral,
627 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
628 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
629 "fnabs $frD, $frB", FPGeneral,
630 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
631 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
632 "fneg $frD, $frB", FPGeneral,
633 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
634 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
635 "fneg $frD, $frB", FPGeneral,
636 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
639 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
640 def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst),
641 "stfiwx $frS, $dst", LdStUX,
642 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
643 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
644 "stfsx $frS, $dst", LdStUX,
645 [(store F4RC:$frS, xaddr:$dst)]>;
646 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
647 "stfdx $frS, $dst", LdStUX,
648 [(store F8RC:$frS, xaddr:$dst)]>;
651 // XL-Form instructions. condition register logical ops.
653 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
654 "mcrf $BF, $BFA", BrMCR>,
655 PPC970_DGroup_First, PPC970_Unit_CRU;
657 // XFX-Form instructions. Instructions that deal with SPRs.
659 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>,
660 PPC970_DGroup_First, PPC970_Unit_FXU;
661 let Pattern = [(PPCmtctr GPRC:$rS)] in {
662 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>,
663 PPC970_DGroup_First, PPC970_Unit_FXU;
666 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>,
667 PPC970_DGroup_First, PPC970_Unit_FXU;
668 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>,
669 PPC970_DGroup_First, PPC970_Unit_FXU;
671 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
672 // a GPR on the PPC970. As such, copies in and out have the same performance
673 // characteristics as an OR instruction.
674 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS),
675 "mtspr 256, $rS", IntGeneral>,
676 PPC970_DGroup_Single, PPC970_Unit_FXU;
677 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT),
678 "mfspr $rT, 256", IntGeneral>,
679 PPC970_DGroup_First, PPC970_Unit_FXU;
681 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
682 "mtcrf $FXM, $rS", BrMCRX>,
683 PPC970_MicroCode, PPC970_Unit_CRU;
684 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>,
685 PPC970_MicroCode, PPC970_Unit_CRU;
686 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
687 "mfcr $rT, $FXM", SprMFCR>,
688 PPC970_DGroup_First, PPC970_Unit_CRU;
690 let PPC970_Unit = 1 in { // FXU Operations.
692 // XO-Form instructions. Arithmetic instructions that can set overflow bit
694 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
695 "add $rT, $rA, $rB", IntGeneral,
696 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
697 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
698 "addc $rT, $rA, $rB", IntGeneral,
699 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
700 PPC970_DGroup_Cracked;
701 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
702 "adde $rT, $rA, $rB", IntGeneral,
703 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
704 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
705 "divw $rT, $rA, $rB", IntDivW,
706 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
707 PPC970_DGroup_First, PPC970_DGroup_Cracked;
708 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
709 "divwu $rT, $rA, $rB", IntDivW,
710 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
711 PPC970_DGroup_First, PPC970_DGroup_Cracked;
712 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
713 "mulhw $rT, $rA, $rB", IntMulHW,
714 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
715 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
716 "mulhwu $rT, $rA, $rB", IntMulHWU,
717 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
718 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
719 "mullw $rT, $rA, $rB", IntMulHW,
720 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
721 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
722 "subf $rT, $rA, $rB", IntGeneral,
723 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
724 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
725 "subfc $rT, $rA, $rB", IntGeneral,
726 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
727 PPC970_DGroup_Cracked;
728 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
729 "subfe $rT, $rA, $rB", IntGeneral,
730 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
731 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
732 "addme $rT, $rA", IntGeneral,
733 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
734 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
735 "addze $rT, $rA", IntGeneral,
736 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
737 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
738 "neg $rT, $rA", IntGeneral,
739 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
740 def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA),
741 "subfme $rT, $rA", IntGeneral,
742 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
743 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
744 "subfze $rT, $rA", IntGeneral,
745 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
748 // A-Form instructions. Most of the instructions executed in the FPU are of
751 let PPC970_Unit = 3 in { // FPU Operations.
752 def FMADD : AForm_1<63, 29,
753 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
754 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
755 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
757 Requires<[FPContractions]>;
758 def FMADDS : AForm_1<59, 29,
759 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
760 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
761 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
763 Requires<[FPContractions]>;
764 def FMSUB : AForm_1<63, 28,
765 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
766 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
767 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
769 Requires<[FPContractions]>;
770 def FMSUBS : AForm_1<59, 28,
771 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
772 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
773 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
775 Requires<[FPContractions]>;
776 def FNMADD : AForm_1<63, 31,
777 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
778 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
779 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
781 Requires<[FPContractions]>;
782 def FNMADDS : AForm_1<59, 31,
783 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
784 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
785 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
787 Requires<[FPContractions]>;
788 def FNMSUB : AForm_1<63, 30,
789 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
790 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
791 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
793 Requires<[FPContractions]>;
794 def FNMSUBS : AForm_1<59, 30,
795 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
796 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
797 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
799 Requires<[FPContractions]>;
800 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
801 // having 4 of these, force the comparison to always be an 8-byte double (code
802 // should use an FMRSD if the input comparison value really wants to be a float)
803 // and 4/8 byte forms for the result and operand type..
804 def FSELD : AForm_1<63, 23,
805 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
806 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
807 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
808 def FSELS : AForm_1<63, 23,
809 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
810 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
811 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
812 def FADD : AForm_2<63, 21,
813 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
814 "fadd $FRT, $FRA, $FRB", FPGeneral,
815 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
816 def FADDS : AForm_2<59, 21,
817 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
818 "fadds $FRT, $FRA, $FRB", FPGeneral,
819 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
820 def FDIV : AForm_2<63, 18,
821 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
822 "fdiv $FRT, $FRA, $FRB", FPDivD,
823 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
824 def FDIVS : AForm_2<59, 18,
825 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
826 "fdivs $FRT, $FRA, $FRB", FPDivS,
827 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
828 def FMUL : AForm_3<63, 25,
829 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
830 "fmul $FRT, $FRA, $FRB", FPFused,
831 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
832 def FMULS : AForm_3<59, 25,
833 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
834 "fmuls $FRT, $FRA, $FRB", FPGeneral,
835 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
836 def FSUB : AForm_2<63, 20,
837 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
838 "fsub $FRT, $FRA, $FRB", FPGeneral,
839 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
840 def FSUBS : AForm_2<59, 20,
841 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
842 "fsubs $FRT, $FRA, $FRB", FPGeneral,
843 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
846 let PPC970_Unit = 1 in { // FXU Operations.
847 // M-Form instructions. rotate and mask instructions.
849 let isTwoAddress = 1, isCommutable = 1 in {
850 // RLWIMI can be commuted if the rotate amount is zero.
851 def RLWIMI : MForm_2<20,
852 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
853 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
854 []>, PPC970_DGroup_Cracked;
856 def RLWINM : MForm_2<21,
857 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
858 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
860 def RLWINMo : MForm_2<21,
861 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
862 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
863 []>, isDOT, PPC970_DGroup_Cracked;
864 def RLWNM : MForm_2<23,
865 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
866 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
871 //===----------------------------------------------------------------------===//
872 // DWARF Pseudo Instructions
875 def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
876 "; .loc $file, $line, $col",
877 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
880 def DWARF_LABEL : Pseudo<(ops i32imm:$id),
882 [(dwarf_label (i32 imm:$id))]>;
884 //===----------------------------------------------------------------------===//
885 // PowerPC Instruction Patterns
888 // Arbitrary immediate support. Implement in terms of LIS/ORI.
889 def : Pat<(i32 imm:$imm),
890 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
892 // Implement the 'not' operation with the NOR instruction.
893 def NOT : Pat<(not GPRC:$in),
894 (NOR GPRC:$in, GPRC:$in)>;
896 // ADD an arbitrary immediate.
897 def : Pat<(add GPRC:$in, imm:$imm),
898 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
899 // OR an arbitrary immediate.
900 def : Pat<(or GPRC:$in, imm:$imm),
901 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
902 // XOR an arbitrary immediate.
903 def : Pat<(xor GPRC:$in, imm:$imm),
904 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
906 def : Pat<(sub immSExt16:$imm, GPRC:$in),
907 (SUBFIC GPRC:$in, imm:$imm)>;
909 // Return void support.
910 def : Pat<(ret), (BLR)>;
913 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
914 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
915 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
916 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
919 def : Pat<(rotl GPRC:$in, GPRC:$sh),
920 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
921 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
922 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
925 def : Pat<(PPCcall tglobaladdr:$dst),
926 (BL tglobaladdr:$dst)>;
927 def : Pat<(PPCcall texternalsym:$dst),
928 (BL texternalsym:$dst)>;
930 // Hi and Lo for Darwin Global Addresses.
931 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
932 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
933 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
934 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
935 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
936 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
937 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
938 (ADDIS GPRC:$in, tglobaladdr:$g)>;
939 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
940 (ADDIS GPRC:$in, tconstpool:$g)>;
941 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
942 (ADDIS GPRC:$in, tjumptable:$g)>;
944 // Fused negative multiply subtract, alternate pattern
945 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
946 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
947 Requires<[FPContractions]>;
948 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
949 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
950 Requires<[FPContractions]>;
952 // Standard shifts. These are represented separately from the real shifts above
953 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
955 def : Pat<(sra GPRC:$rS, GPRC:$rB),
956 (SRAW GPRC:$rS, GPRC:$rB)>;
957 def : Pat<(srl GPRC:$rS, GPRC:$rB),
958 (SRW GPRC:$rS, GPRC:$rB)>;
959 def : Pat<(shl GPRC:$rS, GPRC:$rB),
960 (SLW GPRC:$rS, GPRC:$rB)>;
962 def : Pat<(zextload iaddr:$src, i1),
964 def : Pat<(zextload xaddr:$src, i1),
966 def : Pat<(extload iaddr:$src, i1),
968 def : Pat<(extload xaddr:$src, i1),
970 def : Pat<(extload iaddr:$src, i8),
972 def : Pat<(extload xaddr:$src, i8),
974 def : Pat<(extload iaddr:$src, i16),
976 def : Pat<(extload xaddr:$src, i16),
978 def : Pat<(extload iaddr:$src, f32),
979 (FMRSD (LFS iaddr:$src))>;
980 def : Pat<(extload xaddr:$src, f32),
981 (FMRSD (LFSX xaddr:$src))>;
983 include "PPCInstrAltivec.td"
984 include "PPCInstr64Bit.td"