1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
60 def tocentry32 : Operand<iPTR> {
61 let MIOperandInfo = (ops i32imm:$imm);
64 //===----------------------------------------------------------------------===//
65 // PowerPC specific DAG Nodes.
68 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
69 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
71 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
72 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
73 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
74 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
75 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
76 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
77 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
78 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
79 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
80 [SDNPHasChain, SDNPMayStore]>;
81 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
82 [SDNPHasChain, SDNPMayLoad]>;
83 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
84 [SDNPHasChain, SDNPMayLoad]>;
86 // Extract FPSCR (not modeled at the DAG level).
87 def PPCmffs : SDNode<"PPCISD::MFFS",
88 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
90 // Perform FADD in round-to-zero mode.
91 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
94 def PPCfsel : SDNode<"PPCISD::FSEL",
95 // Type constraint for fsel.
96 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
97 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
99 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
100 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
101 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
102 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
103 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
105 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
107 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
108 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
110 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
111 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
112 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
113 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
114 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
115 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
116 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
117 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
119 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
121 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
123 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
124 // amounts. These nodes are generated by the multi-precision shift code.
125 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
126 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
127 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
129 // These are target-independent nodes, but have target-specific formats.
130 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
131 [SDNPHasChain, SDNPOutGlue]>;
132 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
135 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
136 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
139 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
142 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
143 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
144 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
145 [SDNPHasChain, SDNPSideEffect,
146 SDNPInGlue, SDNPOutGlue]>;
147 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
149 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
150 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
153 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
154 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
156 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
157 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
159 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
160 SDTypeProfile<1, 1, [SDTCisInt<0>,
162 [SDNPHasChain, SDNPSideEffect]>;
163 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
164 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
165 [SDNPHasChain, SDNPSideEffect]>;
167 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
168 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
169 [SDNPHasChain, SDNPSideEffect]>;
171 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
172 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
174 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
175 [SDNPHasChain, SDNPOptInGlue]>;
177 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
178 [SDNPHasChain, SDNPMayLoad]>;
179 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
180 [SDNPHasChain, SDNPMayStore]>;
182 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
183 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
186 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
188 // Instructions to support atomic operations
189 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
190 [SDNPHasChain, SDNPMayLoad]>;
191 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
192 [SDNPHasChain, SDNPMayStore]>;
194 // Instructions to support medium and large code model
195 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
196 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
197 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
200 // Instructions to support dynamic alloca.
201 def SDTDynOp : SDTypeProfile<1, 2, []>;
202 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
204 //===----------------------------------------------------------------------===//
205 // PowerPC specific transformation functions and pattern fragments.
208 def SHL32 : SDNodeXForm<imm, [{
209 // Transformation function: 31 - imm
210 return getI32Imm(31 - N->getZExtValue());
213 def SRL32 : SDNodeXForm<imm, [{
214 // Transformation function: 32 - imm
215 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
218 def LO16 : SDNodeXForm<imm, [{
219 // Transformation function: get the low 16 bits.
220 return getI32Imm((unsigned short)N->getZExtValue());
223 def HI16 : SDNodeXForm<imm, [{
224 // Transformation function: shift the immediate value down into the low bits.
225 return getI32Imm((unsigned)N->getZExtValue() >> 16);
228 def HA16 : SDNodeXForm<imm, [{
229 // Transformation function: shift the immediate value down into the low bits.
230 signed int Val = N->getZExtValue();
231 return getI32Imm((Val - (signed short)Val) >> 16);
233 def MB : SDNodeXForm<imm, [{
234 // Transformation function: get the start bit of a mask
236 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
237 return getI32Imm(mb);
240 def ME : SDNodeXForm<imm, [{
241 // Transformation function: get the end bit of a mask
243 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
244 return getI32Imm(me);
246 def maskimm32 : PatLeaf<(imm), [{
247 // maskImm predicate - True if immediate is a run of ones.
249 if (N->getValueType(0) == MVT::i32)
250 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
255 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
256 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
257 // sign extended field. Used by instructions like 'addi'.
258 return (int32_t)Imm == (short)Imm;
260 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
261 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
262 // sign extended field. Used by instructions like 'addi'.
263 return (int64_t)Imm == (short)Imm;
265 def immZExt16 : PatLeaf<(imm), [{
266 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
267 // field. Used by instructions like 'ori'.
268 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
271 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
272 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
273 // identical in 32-bit mode, but in 64-bit mode, they return true if the
274 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
276 def imm16ShiftedZExt : PatLeaf<(imm), [{
277 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
278 // immediate are set. Used by instructions like 'xoris'.
279 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
282 def imm16ShiftedSExt : PatLeaf<(imm), [{
283 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
284 // immediate are set. Used by instructions like 'addis'. Identical to
285 // imm16ShiftedZExt in 32-bit mode.
286 if (N->getZExtValue() & 0xFFFF) return false;
287 if (N->getValueType(0) == MVT::i32)
289 // For 64-bit, make sure it is sext right.
290 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
293 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
294 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
295 // zero extended field.
296 return isUInt<32>(Imm);
299 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
300 // restricted memrix (4-aligned) constants are alignment sensitive. If these
301 // offsets are hidden behind TOC entries than the values of the lower-order
302 // bits cannot be checked directly. As a result, we need to also incorporate
303 // an alignment check into the relevant patterns.
305 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
306 return cast<LoadSDNode>(N)->getAlignment() >= 4;
308 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
309 (store node:$val, node:$ptr), [{
310 return cast<StoreSDNode>(N)->getAlignment() >= 4;
312 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
313 return cast<LoadSDNode>(N)->getAlignment() >= 4;
315 def aligned4pre_store : PatFrag<
316 (ops node:$val, node:$base, node:$offset),
317 (pre_store node:$val, node:$base, node:$offset), [{
318 return cast<StoreSDNode>(N)->getAlignment() >= 4;
321 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
322 return cast<LoadSDNode>(N)->getAlignment() < 4;
324 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
325 (store node:$val, node:$ptr), [{
326 return cast<StoreSDNode>(N)->getAlignment() < 4;
328 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
329 return cast<LoadSDNode>(N)->getAlignment() < 4;
332 //===----------------------------------------------------------------------===//
333 // PowerPC Flag Definitions.
335 class isPPC64 { bit PPC64 = 1; }
336 class isDOT { bit RC = 1; }
338 class RegConstraint<string C> {
339 string Constraints = C;
341 class NoEncode<string E> {
342 string DisableEncoding = E;
346 //===----------------------------------------------------------------------===//
347 // PowerPC Operand Definitions.
349 // In the default PowerPC assembler syntax, registers are specified simply
350 // by number, so they cannot be distinguished from immediate values (without
351 // looking at the opcode). This means that the default operand matching logic
352 // for the asm parser does not work, and we need to specify custom matchers.
353 // Since those can only be specified with RegisterOperand classes and not
354 // directly on the RegisterClass, all instructions patterns used by the asm
355 // parser need to use a RegisterOperand (instead of a RegisterClass) for
356 // all their register operands.
357 // For this purpose, we define one RegisterOperand for each RegisterClass,
358 // using the same name as the class, just in lower case.
360 def PPCRegGPRCAsmOperand : AsmOperandClass {
361 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
363 def gprc : RegisterOperand<GPRC> {
364 let ParserMatchClass = PPCRegGPRCAsmOperand;
366 def PPCRegG8RCAsmOperand : AsmOperandClass {
367 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
369 def g8rc : RegisterOperand<G8RC> {
370 let ParserMatchClass = PPCRegG8RCAsmOperand;
372 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
373 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
375 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
376 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
378 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
379 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
381 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
382 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
384 def PPCRegF8RCAsmOperand : AsmOperandClass {
385 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
387 def f8rc : RegisterOperand<F8RC> {
388 let ParserMatchClass = PPCRegF8RCAsmOperand;
390 def PPCRegF4RCAsmOperand : AsmOperandClass {
391 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
393 def f4rc : RegisterOperand<F4RC> {
394 let ParserMatchClass = PPCRegF4RCAsmOperand;
396 def PPCRegVRRCAsmOperand : AsmOperandClass {
397 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
399 def vrrc : RegisterOperand<VRRC> {
400 let ParserMatchClass = PPCRegVRRCAsmOperand;
402 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
403 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
405 def crbitrc : RegisterOperand<CRBITRC> {
406 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
408 def PPCRegCRRCAsmOperand : AsmOperandClass {
409 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
411 def crrc : RegisterOperand<CRRC> {
412 let ParserMatchClass = PPCRegCRRCAsmOperand;
415 def PPCU2ImmAsmOperand : AsmOperandClass {
416 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
417 let RenderMethod = "addImmOperands";
419 def u2imm : Operand<i32> {
420 let PrintMethod = "printU2ImmOperand";
421 let ParserMatchClass = PPCU2ImmAsmOperand;
424 def PPCU4ImmAsmOperand : AsmOperandClass {
425 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
426 let RenderMethod = "addImmOperands";
428 def u4imm : Operand<i32> {
429 let PrintMethod = "printU4ImmOperand";
430 let ParserMatchClass = PPCU4ImmAsmOperand;
432 def PPCS5ImmAsmOperand : AsmOperandClass {
433 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
434 let RenderMethod = "addImmOperands";
436 def s5imm : Operand<i32> {
437 let PrintMethod = "printS5ImmOperand";
438 let ParserMatchClass = PPCS5ImmAsmOperand;
439 let DecoderMethod = "decodeSImmOperand<5>";
441 def PPCU5ImmAsmOperand : AsmOperandClass {
442 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
443 let RenderMethod = "addImmOperands";
445 def u5imm : Operand<i32> {
446 let PrintMethod = "printU5ImmOperand";
447 let ParserMatchClass = PPCU5ImmAsmOperand;
448 let DecoderMethod = "decodeUImmOperand<5>";
450 def PPCU6ImmAsmOperand : AsmOperandClass {
451 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
452 let RenderMethod = "addImmOperands";
454 def u6imm : Operand<i32> {
455 let PrintMethod = "printU6ImmOperand";
456 let ParserMatchClass = PPCU6ImmAsmOperand;
457 let DecoderMethod = "decodeUImmOperand<6>";
459 def PPCS16ImmAsmOperand : AsmOperandClass {
460 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
461 let RenderMethod = "addImmOperands";
463 def s16imm : Operand<i32> {
464 let PrintMethod = "printS16ImmOperand";
465 let EncoderMethod = "getImm16Encoding";
466 let ParserMatchClass = PPCS16ImmAsmOperand;
467 let DecoderMethod = "decodeSImmOperand<16>";
469 def PPCU16ImmAsmOperand : AsmOperandClass {
470 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
471 let RenderMethod = "addImmOperands";
473 def u16imm : Operand<i32> {
474 let PrintMethod = "printU16ImmOperand";
475 let EncoderMethod = "getImm16Encoding";
476 let ParserMatchClass = PPCU16ImmAsmOperand;
477 let DecoderMethod = "decodeUImmOperand<16>";
479 def PPCS17ImmAsmOperand : AsmOperandClass {
480 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
481 let RenderMethod = "addImmOperands";
483 def s17imm : Operand<i32> {
484 // This operand type is used for addis/lis to allow the assembler parser
485 // to accept immediates in the range -65536..65535 for compatibility with
486 // the GNU assembler. The operand is treated as 16-bit otherwise.
487 let PrintMethod = "printS16ImmOperand";
488 let EncoderMethod = "getImm16Encoding";
489 let ParserMatchClass = PPCS17ImmAsmOperand;
490 let DecoderMethod = "decodeSImmOperand<16>";
492 def PPCDirectBrAsmOperand : AsmOperandClass {
493 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
494 let RenderMethod = "addBranchTargetOperands";
496 def directbrtarget : Operand<OtherVT> {
497 let PrintMethod = "printBranchOperand";
498 let EncoderMethod = "getDirectBrEncoding";
499 let ParserMatchClass = PPCDirectBrAsmOperand;
501 def absdirectbrtarget : Operand<OtherVT> {
502 let PrintMethod = "printAbsBranchOperand";
503 let EncoderMethod = "getAbsDirectBrEncoding";
504 let ParserMatchClass = PPCDirectBrAsmOperand;
506 def PPCCondBrAsmOperand : AsmOperandClass {
507 let Name = "CondBr"; let PredicateMethod = "isCondBr";
508 let RenderMethod = "addBranchTargetOperands";
510 def condbrtarget : Operand<OtherVT> {
511 let PrintMethod = "printBranchOperand";
512 let EncoderMethod = "getCondBrEncoding";
513 let ParserMatchClass = PPCCondBrAsmOperand;
515 def abscondbrtarget : Operand<OtherVT> {
516 let PrintMethod = "printAbsBranchOperand";
517 let EncoderMethod = "getAbsCondBrEncoding";
518 let ParserMatchClass = PPCCondBrAsmOperand;
520 def calltarget : Operand<iPTR> {
521 let PrintMethod = "printBranchOperand";
522 let EncoderMethod = "getDirectBrEncoding";
523 let ParserMatchClass = PPCDirectBrAsmOperand;
525 def abscalltarget : Operand<iPTR> {
526 let PrintMethod = "printAbsBranchOperand";
527 let EncoderMethod = "getAbsDirectBrEncoding";
528 let ParserMatchClass = PPCDirectBrAsmOperand;
530 def PPCCRBitMaskOperand : AsmOperandClass {
531 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
533 def crbitm: Operand<i8> {
534 let PrintMethod = "printcrbitm";
535 let EncoderMethod = "get_crbitm_encoding";
536 let DecoderMethod = "decodeCRBitMOperand";
537 let ParserMatchClass = PPCCRBitMaskOperand;
540 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
541 def PPCRegGxRCNoR0Operand : AsmOperandClass {
542 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
544 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
545 let ParserMatchClass = PPCRegGxRCNoR0Operand;
547 // A version of ptr_rc usable with the asm parser.
548 def PPCRegGxRCOperand : AsmOperandClass {
549 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
551 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
552 let ParserMatchClass = PPCRegGxRCOperand;
555 def PPCDispRIOperand : AsmOperandClass {
556 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
557 let RenderMethod = "addImmOperands";
559 def dispRI : Operand<iPTR> {
560 let ParserMatchClass = PPCDispRIOperand;
562 def PPCDispRIXOperand : AsmOperandClass {
563 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
564 let RenderMethod = "addImmOperands";
566 def dispRIX : Operand<iPTR> {
567 let ParserMatchClass = PPCDispRIXOperand;
570 def memri : Operand<iPTR> {
571 let PrintMethod = "printMemRegImm";
572 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
573 let EncoderMethod = "getMemRIEncoding";
574 let DecoderMethod = "decodeMemRIOperands";
576 def memrr : Operand<iPTR> {
577 let PrintMethod = "printMemRegReg";
578 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
580 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
581 let PrintMethod = "printMemRegImm";
582 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
583 let EncoderMethod = "getMemRIXEncoding";
584 let DecoderMethod = "decodeMemRIXOperands";
587 // A single-register address. This is used with the SjLj
588 // pseudo-instructions.
589 def memr : Operand<iPTR> {
590 let MIOperandInfo = (ops ptr_rc:$ptrreg);
592 def PPCTLSRegOperand : AsmOperandClass {
593 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
594 let RenderMethod = "addTLSRegOperands";
596 def tlsreg32 : Operand<i32> {
597 let EncoderMethod = "getTLSRegEncoding";
598 let ParserMatchClass = PPCTLSRegOperand;
600 def tlsgd32 : Operand<i32> {}
601 def tlscall32 : Operand<i32> {
602 let PrintMethod = "printTLSCall";
603 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
604 let EncoderMethod = "getTLSCallEncoding";
607 // PowerPC Predicate operand.
608 def pred : Operand<OtherVT> {
609 let PrintMethod = "printPredicateOperand";
610 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
613 // Define PowerPC specific addressing mode.
614 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
615 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
616 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
617 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
619 // The address in a single register. This is used with the SjLj
620 // pseudo-instructions.
621 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
623 /// This is just the offset part of iaddr, used for preinc.
624 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
626 //===----------------------------------------------------------------------===//
627 // PowerPC Instruction Predicate Definitions.
628 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
629 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
630 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
631 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
632 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
633 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
634 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
636 //===----------------------------------------------------------------------===//
637 // PowerPC Multiclass Definitions.
639 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
640 string asmbase, string asmstr, InstrItinClass itin,
642 let BaseName = asmbase in {
643 def NAME : XForm_6<opcode, xo, OOL, IOL,
644 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
645 pattern>, RecFormRel;
647 def o : XForm_6<opcode, xo, OOL, IOL,
648 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
649 []>, isDOT, RecFormRel;
653 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
654 string asmbase, string asmstr, InstrItinClass itin,
656 let BaseName = asmbase in {
657 let Defs = [CARRY] in
658 def NAME : XForm_6<opcode, xo, OOL, IOL,
659 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
660 pattern>, RecFormRel;
661 let Defs = [CARRY, CR0] in
662 def o : XForm_6<opcode, xo, OOL, IOL,
663 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
664 []>, isDOT, RecFormRel;
668 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
669 string asmbase, string asmstr, InstrItinClass itin,
671 let BaseName = asmbase in {
672 let Defs = [CARRY] in
673 def NAME : XForm_10<opcode, xo, OOL, IOL,
674 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
675 pattern>, RecFormRel;
676 let Defs = [CARRY, CR0] in
677 def o : XForm_10<opcode, xo, OOL, IOL,
678 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
679 []>, isDOT, RecFormRel;
683 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
684 string asmbase, string asmstr, InstrItinClass itin,
686 let BaseName = asmbase in {
687 def NAME : XForm_11<opcode, xo, OOL, IOL,
688 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
689 pattern>, RecFormRel;
691 def o : XForm_11<opcode, xo, OOL, IOL,
692 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
693 []>, isDOT, RecFormRel;
697 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
698 string asmbase, string asmstr, InstrItinClass itin,
700 let BaseName = asmbase in {
701 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
702 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
703 pattern>, RecFormRel;
705 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
706 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
707 []>, isDOT, RecFormRel;
711 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
712 string asmbase, string asmstr, InstrItinClass itin,
714 let BaseName = asmbase in {
715 let Defs = [CARRY] in
716 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
717 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
718 pattern>, RecFormRel;
719 let Defs = [CARRY, CR0] in
720 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
721 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
722 []>, isDOT, RecFormRel;
726 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
727 string asmbase, string asmstr, InstrItinClass itin,
729 let BaseName = asmbase in {
730 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
731 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
732 pattern>, RecFormRel;
734 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
735 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
736 []>, isDOT, RecFormRel;
740 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
741 string asmbase, string asmstr, InstrItinClass itin,
743 let BaseName = asmbase in {
744 let Defs = [CARRY] in
745 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
746 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
747 pattern>, RecFormRel;
748 let Defs = [CARRY, CR0] in
749 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
750 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
751 []>, isDOT, RecFormRel;
755 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
756 string asmbase, string asmstr, InstrItinClass itin,
758 let BaseName = asmbase in {
759 def NAME : MForm_2<opcode, OOL, IOL,
760 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
761 pattern>, RecFormRel;
763 def o : MForm_2<opcode, OOL, IOL,
764 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
765 []>, isDOT, RecFormRel;
769 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
770 string asmbase, string asmstr, InstrItinClass itin,
772 let BaseName = asmbase in {
773 def NAME : MDForm_1<opcode, xo, OOL, IOL,
774 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
775 pattern>, RecFormRel;
777 def o : MDForm_1<opcode, xo, OOL, IOL,
778 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
779 []>, isDOT, RecFormRel;
783 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
784 string asmbase, string asmstr, InstrItinClass itin,
786 let BaseName = asmbase in {
787 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
788 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
789 pattern>, RecFormRel;
791 def o : MDSForm_1<opcode, xo, OOL, IOL,
792 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
793 []>, isDOT, RecFormRel;
797 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
798 string asmbase, string asmstr, InstrItinClass itin,
800 let BaseName = asmbase in {
801 let Defs = [CARRY] in
802 def NAME : XSForm_1<opcode, xo, OOL, IOL,
803 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
804 pattern>, RecFormRel;
805 let Defs = [CARRY, CR0] in
806 def o : XSForm_1<opcode, xo, OOL, IOL,
807 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
808 []>, isDOT, RecFormRel;
812 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
813 string asmbase, string asmstr, InstrItinClass itin,
815 let BaseName = asmbase in {
816 def NAME : XForm_26<opcode, xo, OOL, IOL,
817 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
818 pattern>, RecFormRel;
820 def o : XForm_26<opcode, xo, OOL, IOL,
821 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
822 []>, isDOT, RecFormRel;
826 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
827 string asmbase, string asmstr, InstrItinClass itin,
829 let BaseName = asmbase in {
830 def NAME : XForm_28<opcode, xo, OOL, IOL,
831 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
832 pattern>, RecFormRel;
834 def o : XForm_28<opcode, xo, OOL, IOL,
835 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
836 []>, isDOT, RecFormRel;
840 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
841 string asmbase, string asmstr, InstrItinClass itin,
843 let BaseName = asmbase in {
844 def NAME : AForm_1<opcode, xo, OOL, IOL,
845 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
846 pattern>, RecFormRel;
848 def o : AForm_1<opcode, xo, OOL, IOL,
849 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
850 []>, isDOT, RecFormRel;
854 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
855 string asmbase, string asmstr, InstrItinClass itin,
857 let BaseName = asmbase in {
858 def NAME : AForm_2<opcode, xo, OOL, IOL,
859 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
860 pattern>, RecFormRel;
862 def o : AForm_2<opcode, xo, OOL, IOL,
863 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
864 []>, isDOT, RecFormRel;
868 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
869 string asmbase, string asmstr, InstrItinClass itin,
871 let BaseName = asmbase in {
872 def NAME : AForm_3<opcode, xo, OOL, IOL,
873 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
874 pattern>, RecFormRel;
876 def o : AForm_3<opcode, xo, OOL, IOL,
877 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
878 []>, isDOT, RecFormRel;
882 //===----------------------------------------------------------------------===//
883 // PowerPC Instruction Definitions.
885 // Pseudo-instructions:
887 let hasCtrlDep = 1 in {
888 let Defs = [R1], Uses = [R1] in {
889 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
890 [(callseq_start timm:$amt)]>;
891 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
892 [(callseq_end timm:$amt1, timm:$amt2)]>;
895 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
896 "UPDATE_VRSAVE $rD, $rS", []>;
899 let Defs = [R1], Uses = [R1] in
900 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
902 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
904 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
905 // instruction selection into a branch sequence.
906 let usesCustomInserter = 1, // Expanded after instruction selection.
907 PPC970_Single = 1 in {
908 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
909 // because either operand might become the first operand in an isel, and
910 // that operand cannot be r0.
911 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
912 gprc_nor0:$T, gprc_nor0:$F,
913 i32imm:$BROPC), "#SELECT_CC_I4",
915 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
916 g8rc_nox0:$T, g8rc_nox0:$F,
917 i32imm:$BROPC), "#SELECT_CC_I8",
919 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
920 i32imm:$BROPC), "#SELECT_CC_F4",
922 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
923 i32imm:$BROPC), "#SELECT_CC_F8",
925 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
926 i32imm:$BROPC), "#SELECT_CC_VRRC",
929 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
930 // register bit directly.
931 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
932 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
933 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
934 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
935 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
936 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
937 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
938 f4rc:$T, f4rc:$F), "#SELECT_F4",
939 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
940 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
941 f8rc:$T, f8rc:$F), "#SELECT_F8",
942 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
943 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
944 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
946 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
949 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
950 // scavenge a register for it.
951 let mayStore = 1 in {
952 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
954 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
958 // RESTORE_CR - Indicate that we're restoring the CR register (previously
959 // spilled), so we'll need to scavenge a register for it.
961 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
963 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
964 "#RESTORE_CRBIT", []>;
967 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
968 let isReturn = 1, Uses = [LR, RM] in
969 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
971 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
972 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
975 let isCodeGenOnly = 1 in {
976 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
977 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
980 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
981 "bcctr 12, $bi, 0", IIC_BrB, []>;
982 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
983 "bcctr 4, $bi, 0", IIC_BrB, []>;
989 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
992 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
993 let isBarrier = 1 in {
994 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
997 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
998 "ba $dst", IIC_BrB, []>;
1001 // BCC represents an arbitrary conditional branch on a predicate.
1002 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1003 // a two-value operand where a dag node expects two operands. :(
1004 let isCodeGenOnly = 1 in {
1005 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1006 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1007 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1008 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1009 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1011 let isReturn = 1, Uses = [LR, RM] in
1012 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1013 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1016 let isCodeGenOnly = 1 in {
1017 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1018 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1019 "bc 12, $bi, $dst">;
1021 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1022 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1025 let isReturn = 1, Uses = [LR, RM] in
1026 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1027 "bclr 12, $bi, 0", IIC_BrB, []>;
1028 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1029 "bclr 4, $bi, 0", IIC_BrB, []>;
1032 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1033 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1034 "bdzlr", IIC_BrB, []>;
1035 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1036 "bdnzlr", IIC_BrB, []>;
1037 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1038 "bdzlr+", IIC_BrB, []>;
1039 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1040 "bdnzlr+", IIC_BrB, []>;
1041 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1042 "bdzlr-", IIC_BrB, []>;
1043 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1044 "bdnzlr-", IIC_BrB, []>;
1047 let Defs = [CTR], Uses = [CTR] in {
1048 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1050 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1052 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1054 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1056 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1058 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1060 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1062 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1064 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1066 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1068 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1070 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1075 // The unconditional BCL used by the SjLj setjmp code.
1076 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1077 let Defs = [LR], Uses = [RM] in {
1078 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1079 "bcl 20, 31, $dst">;
1083 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1084 // Convenient aliases for call instructions
1085 let Uses = [RM] in {
1086 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1087 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1088 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1089 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1091 let isCodeGenOnly = 1 in {
1092 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1093 "bl $func", IIC_BrB, []>;
1094 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1095 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1096 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1097 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1099 def BCL : BForm_4<16, 12, 0, 1, (outs),
1100 (ins crbitrc:$bi, condbrtarget:$dst),
1101 "bcl 12, $bi, $dst">;
1102 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1103 (ins crbitrc:$bi, condbrtarget:$dst),
1104 "bcl 4, $bi, $dst">;
1107 let Uses = [CTR, RM] in {
1108 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1109 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1110 Requires<[In32BitMode]>;
1112 let isCodeGenOnly = 1 in {
1113 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1114 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1117 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1118 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1119 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1120 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1123 let Uses = [LR, RM] in {
1124 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1125 "blrl", IIC_BrB, []>;
1127 let isCodeGenOnly = 1 in {
1128 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1129 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1132 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1133 "bclrl 12, $bi, 0", IIC_BrB, []>;
1134 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1135 "bclrl 4, $bi, 0", IIC_BrB, []>;
1138 let Defs = [CTR], Uses = [CTR, RM] in {
1139 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1141 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1143 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1145 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1147 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1149 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1151 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1153 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1155 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1157 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1159 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1161 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1164 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1165 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1166 "bdzlrl", IIC_BrB, []>;
1167 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1168 "bdnzlrl", IIC_BrB, []>;
1169 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1170 "bdzlrl+", IIC_BrB, []>;
1171 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1172 "bdnzlrl+", IIC_BrB, []>;
1173 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1174 "bdzlrl-", IIC_BrB, []>;
1175 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1176 "bdnzlrl-", IIC_BrB, []>;
1180 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1181 def TCRETURNdi :Pseudo< (outs),
1182 (ins calltarget:$dst, i32imm:$offset),
1183 "#TC_RETURNd $dst $offset",
1187 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1188 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1189 "#TC_RETURNa $func $offset",
1190 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1192 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1193 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1194 "#TC_RETURNr $dst $offset",
1198 let isCodeGenOnly = 1 in {
1200 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1201 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1202 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1203 []>, Requires<[In32BitMode]>;
1205 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1206 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1207 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1211 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1212 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1213 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1219 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1221 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1222 "#EH_SJLJ_SETJMP32",
1223 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1224 Requires<[In32BitMode]>;
1225 let isTerminator = 1 in
1226 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1227 "#EH_SJLJ_LONGJMP32",
1228 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1229 Requires<[In32BitMode]>;
1232 let isBranch = 1, isTerminator = 1 in {
1233 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1234 "#EH_SjLj_Setup\t$dst", []>;
1238 let PPC970_Unit = 7 in {
1239 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1240 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1243 // DCB* instructions.
1244 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1245 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1246 PPC970_DGroup_Single;
1247 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1248 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1249 PPC970_DGroup_Single;
1250 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1251 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1252 PPC970_DGroup_Single;
1253 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1254 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1255 PPC970_DGroup_Single;
1256 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1257 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1258 PPC970_DGroup_Single;
1259 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1260 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1261 PPC970_DGroup_Single;
1262 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1263 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1264 PPC970_DGroup_Single;
1265 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1266 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1267 PPC970_DGroup_Single;
1269 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1270 (DCBT xoaddr:$dst)>;
1272 // Atomic operations
1273 let usesCustomInserter = 1 in {
1274 let Defs = [CR0] in {
1275 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1276 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1277 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1278 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1279 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1280 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1281 def ATOMIC_LOAD_AND_I8 : Pseudo<
1282 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1283 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1284 def ATOMIC_LOAD_OR_I8 : Pseudo<
1285 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1286 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1287 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1288 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1289 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1290 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1291 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1292 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1293 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1294 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1295 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1296 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1297 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1298 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1299 def ATOMIC_LOAD_AND_I16 : Pseudo<
1300 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1301 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1302 def ATOMIC_LOAD_OR_I16 : Pseudo<
1303 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1304 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1305 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1306 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1307 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1308 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1309 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1310 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1311 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1312 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1313 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1314 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1315 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1316 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1317 def ATOMIC_LOAD_AND_I32 : Pseudo<
1318 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1319 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1320 def ATOMIC_LOAD_OR_I32 : Pseudo<
1321 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1322 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1323 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1324 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1325 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1326 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1327 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1328 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1330 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1331 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1332 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1333 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1334 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1335 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1336 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1337 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1338 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1340 def ATOMIC_SWAP_I8 : Pseudo<
1341 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1342 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1343 def ATOMIC_SWAP_I16 : Pseudo<
1344 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1345 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1346 def ATOMIC_SWAP_I32 : Pseudo<
1347 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1348 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1352 // Instructions to support atomic operations
1353 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1354 "lwarx $rD, $src", IIC_LdStLWARX,
1355 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1358 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1359 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1360 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1363 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1364 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1366 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1367 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1368 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1369 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1370 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1371 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1372 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1373 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1375 //===----------------------------------------------------------------------===//
1376 // PPC32 Load Instructions.
1379 // Unindexed (r+i) Loads.
1380 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1381 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1382 "lbz $rD, $src", IIC_LdStLoad,
1383 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1384 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1385 "lha $rD, $src", IIC_LdStLHA,
1386 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1387 PPC970_DGroup_Cracked;
1388 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1389 "lhz $rD, $src", IIC_LdStLoad,
1390 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1391 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1392 "lwz $rD, $src", IIC_LdStLoad,
1393 [(set i32:$rD, (load iaddr:$src))]>;
1395 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1396 "lfs $rD, $src", IIC_LdStLFD,
1397 [(set f32:$rD, (load iaddr:$src))]>;
1398 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1399 "lfd $rD, $src", IIC_LdStLFD,
1400 [(set f64:$rD, (load iaddr:$src))]>;
1403 // Unindexed (r+i) Loads with Update (preinc).
1404 let mayLoad = 1, neverHasSideEffects = 1 in {
1405 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1406 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1407 []>, RegConstraint<"$addr.reg = $ea_result">,
1408 NoEncode<"$ea_result">;
1410 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1411 "lhau $rD, $addr", IIC_LdStLHAU,
1412 []>, RegConstraint<"$addr.reg = $ea_result">,
1413 NoEncode<"$ea_result">;
1415 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1416 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1417 []>, RegConstraint<"$addr.reg = $ea_result">,
1418 NoEncode<"$ea_result">;
1420 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1421 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1422 []>, RegConstraint<"$addr.reg = $ea_result">,
1423 NoEncode<"$ea_result">;
1425 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1426 "lfsu $rD, $addr", IIC_LdStLFDU,
1427 []>, RegConstraint<"$addr.reg = $ea_result">,
1428 NoEncode<"$ea_result">;
1430 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1431 "lfdu $rD, $addr", IIC_LdStLFDU,
1432 []>, RegConstraint<"$addr.reg = $ea_result">,
1433 NoEncode<"$ea_result">;
1436 // Indexed (r+r) Loads with Update (preinc).
1437 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1439 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1440 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1441 NoEncode<"$ea_result">;
1443 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1445 "lhaux $rD, $addr", IIC_LdStLHAUX,
1446 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1447 NoEncode<"$ea_result">;
1449 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1451 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1452 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1453 NoEncode<"$ea_result">;
1455 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1457 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1458 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1459 NoEncode<"$ea_result">;
1461 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1463 "lfsux $rD, $addr", IIC_LdStLFDUX,
1464 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1465 NoEncode<"$ea_result">;
1467 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1469 "lfdux $rD, $addr", IIC_LdStLFDUX,
1470 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1471 NoEncode<"$ea_result">;
1475 // Indexed (r+r) Loads.
1477 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1478 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1479 "lbzx $rD, $src", IIC_LdStLoad,
1480 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1481 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1482 "lhax $rD, $src", IIC_LdStLHA,
1483 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1484 PPC970_DGroup_Cracked;
1485 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1486 "lhzx $rD, $src", IIC_LdStLoad,
1487 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1488 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1489 "lwzx $rD, $src", IIC_LdStLoad,
1490 [(set i32:$rD, (load xaddr:$src))]>;
1493 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1494 "lhbrx $rD, $src", IIC_LdStLoad,
1495 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1496 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1497 "lwbrx $rD, $src", IIC_LdStLoad,
1498 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1500 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1501 "lfsx $frD, $src", IIC_LdStLFD,
1502 [(set f32:$frD, (load xaddr:$src))]>;
1503 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1504 "lfdx $frD, $src", IIC_LdStLFD,
1505 [(set f64:$frD, (load xaddr:$src))]>;
1507 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1508 "lfiwax $frD, $src", IIC_LdStLFD,
1509 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1510 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1511 "lfiwzx $frD, $src", IIC_LdStLFD,
1512 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1516 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1517 "lmw $rD, $src", IIC_LdStLMW, []>;
1519 //===----------------------------------------------------------------------===//
1520 // PPC32 Store Instructions.
1523 // Unindexed (r+i) Stores.
1524 let PPC970_Unit = 2 in {
1525 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1526 "stb $rS, $src", IIC_LdStStore,
1527 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1528 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1529 "sth $rS, $src", IIC_LdStStore,
1530 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1531 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1532 "stw $rS, $src", IIC_LdStStore,
1533 [(store i32:$rS, iaddr:$src)]>;
1534 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1535 "stfs $rS, $dst", IIC_LdStSTFD,
1536 [(store f32:$rS, iaddr:$dst)]>;
1537 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1538 "stfd $rS, $dst", IIC_LdStSTFD,
1539 [(store f64:$rS, iaddr:$dst)]>;
1542 // Unindexed (r+i) Stores with Update (preinc).
1543 let PPC970_Unit = 2, mayStore = 1 in {
1544 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1545 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1546 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1547 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1548 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1549 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1550 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1551 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1552 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1553 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1554 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1555 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1556 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1557 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1558 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1561 // Patterns to match the pre-inc stores. We can't put the patterns on
1562 // the instruction definitions directly as ISel wants the address base
1563 // and offset to be separate operands, not a single complex operand.
1564 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1565 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1566 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1567 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1568 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1569 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1570 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1571 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1572 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1573 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1575 // Indexed (r+r) Stores.
1576 let PPC970_Unit = 2 in {
1577 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1578 "stbx $rS, $dst", IIC_LdStStore,
1579 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1580 PPC970_DGroup_Cracked;
1581 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1582 "sthx $rS, $dst", IIC_LdStStore,
1583 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1584 PPC970_DGroup_Cracked;
1585 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1586 "stwx $rS, $dst", IIC_LdStStore,
1587 [(store i32:$rS, xaddr:$dst)]>,
1588 PPC970_DGroup_Cracked;
1590 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1591 "sthbrx $rS, $dst", IIC_LdStStore,
1592 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1593 PPC970_DGroup_Cracked;
1594 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1595 "stwbrx $rS, $dst", IIC_LdStStore,
1596 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1597 PPC970_DGroup_Cracked;
1599 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1600 "stfiwx $frS, $dst", IIC_LdStSTFD,
1601 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1603 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1604 "stfsx $frS, $dst", IIC_LdStSTFD,
1605 [(store f32:$frS, xaddr:$dst)]>;
1606 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1607 "stfdx $frS, $dst", IIC_LdStSTFD,
1608 [(store f64:$frS, xaddr:$dst)]>;
1611 // Indexed (r+r) Stores with Update (preinc).
1612 let PPC970_Unit = 2, mayStore = 1 in {
1613 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1614 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1615 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1616 PPC970_DGroup_Cracked;
1617 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1618 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1619 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1620 PPC970_DGroup_Cracked;
1621 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1622 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1623 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1624 PPC970_DGroup_Cracked;
1625 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1626 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1627 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1628 PPC970_DGroup_Cracked;
1629 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1630 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1631 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1632 PPC970_DGroup_Cracked;
1635 // Patterns to match the pre-inc stores. We can't put the patterns on
1636 // the instruction definitions directly as ISel wants the address base
1637 // and offset to be separate operands, not a single complex operand.
1638 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1639 (STBUX $rS, $ptrreg, $ptroff)>;
1640 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1641 (STHUX $rS, $ptrreg, $ptroff)>;
1642 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1643 (STWUX $rS, $ptrreg, $ptroff)>;
1644 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1645 (STFSUX $rS, $ptrreg, $ptroff)>;
1646 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1647 (STFDUX $rS, $ptrreg, $ptroff)>;
1650 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1651 "stmw $rS, $dst", IIC_LdStLMW, []>;
1653 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1654 "sync $L", IIC_LdStSync, []>, Requires<[IsNotBookE]>;
1656 let isCodeGenOnly = 1 in {
1657 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1658 "msync", IIC_LdStSync, []>, Requires<[IsBookE]> {
1663 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[IsNotBookE]>;
1664 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[IsBookE]>;
1666 //===----------------------------------------------------------------------===//
1667 // PPC32 Arithmetic Instructions.
1670 let PPC970_Unit = 1 in { // FXU Operations.
1671 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1672 "addi $rD, $rA, $imm", IIC_IntSimple,
1673 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1674 let BaseName = "addic" in {
1675 let Defs = [CARRY] in
1676 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1677 "addic $rD, $rA, $imm", IIC_IntGeneral,
1678 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1679 RecFormRel, PPC970_DGroup_Cracked;
1680 let Defs = [CARRY, CR0] in
1681 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1682 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1683 []>, isDOT, RecFormRel;
1685 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1686 "addis $rD, $rA, $imm", IIC_IntSimple,
1687 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1688 let isCodeGenOnly = 1 in
1689 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1690 "la $rD, $sym($rA)", IIC_IntGeneral,
1691 [(set i32:$rD, (add i32:$rA,
1692 (PPClo tglobaladdr:$sym, 0)))]>;
1693 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1694 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1695 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1696 let Defs = [CARRY] in
1697 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1698 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1699 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1701 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1702 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1703 "li $rD, $imm", IIC_IntSimple,
1704 [(set i32:$rD, imm32SExt16:$imm)]>;
1705 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1706 "lis $rD, $imm", IIC_IntSimple,
1707 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1711 let PPC970_Unit = 1 in { // FXU Operations.
1712 let Defs = [CR0] in {
1713 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1714 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1715 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1717 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1718 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1719 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1722 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1723 "ori $dst, $src1, $src2", IIC_IntSimple,
1724 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1725 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1726 "oris $dst, $src1, $src2", IIC_IntSimple,
1727 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1728 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1729 "xori $dst, $src1, $src2", IIC_IntSimple,
1730 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1731 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1732 "xoris $dst, $src1, $src2", IIC_IntSimple,
1733 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1735 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1737 let isCodeGenOnly = 1 in {
1738 // The POWER6 and POWER7 have special group-terminating nops.
1739 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1740 "ori 1, 1, 0", IIC_IntSimple, []>;
1741 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1742 "ori 2, 2, 0", IIC_IntSimple, []>;
1745 let isCompare = 1, neverHasSideEffects = 1 in {
1746 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1747 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1748 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1749 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1753 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1754 let isCommutable = 1 in {
1755 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1756 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1757 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1758 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1759 "and", "$rA, $rS, $rB", IIC_IntSimple,
1760 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1762 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1763 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1764 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1765 let isCommutable = 1 in {
1766 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1767 "or", "$rA, $rS, $rB", IIC_IntSimple,
1768 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1769 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1770 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1771 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1773 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1774 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1775 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1776 let isCommutable = 1 in {
1777 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1778 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1779 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1780 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1781 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1782 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1784 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1785 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1786 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1787 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1788 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1789 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1790 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1791 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1792 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1795 let PPC970_Unit = 1 in { // FXU Operations.
1796 let neverHasSideEffects = 1 in {
1797 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1798 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1799 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1800 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1801 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1802 [(set i32:$rA, (ctlz i32:$rS))]>;
1803 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1804 "extsb", "$rA, $rS", IIC_IntSimple,
1805 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1806 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1807 "extsh", "$rA, $rS", IIC_IntSimple,
1808 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1810 let isCompare = 1, neverHasSideEffects = 1 in {
1811 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1812 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1813 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1814 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1817 let PPC970_Unit = 3 in { // FPU Operations.
1818 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1819 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1820 let isCompare = 1, neverHasSideEffects = 1 in {
1821 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1822 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1823 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1824 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1825 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1828 let Uses = [RM] in {
1829 let neverHasSideEffects = 1 in {
1830 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1831 "fctiw", "$frD, $frB", IIC_FPGeneral,
1833 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1834 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1835 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1837 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1838 "frsp", "$frD, $frB", IIC_FPGeneral,
1839 [(set f32:$frD, (fround f64:$frB))]>;
1841 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1842 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1843 "frin", "$frD, $frB", IIC_FPGeneral,
1844 [(set f64:$frD, (frnd f64:$frB))]>;
1845 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1846 "frin", "$frD, $frB", IIC_FPGeneral,
1847 [(set f32:$frD, (frnd f32:$frB))]>;
1850 let neverHasSideEffects = 1 in {
1851 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1852 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1853 "frip", "$frD, $frB", IIC_FPGeneral,
1854 [(set f64:$frD, (fceil f64:$frB))]>;
1855 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1856 "frip", "$frD, $frB", IIC_FPGeneral,
1857 [(set f32:$frD, (fceil f32:$frB))]>;
1858 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1859 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1860 "friz", "$frD, $frB", IIC_FPGeneral,
1861 [(set f64:$frD, (ftrunc f64:$frB))]>;
1862 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1863 "friz", "$frD, $frB", IIC_FPGeneral,
1864 [(set f32:$frD, (ftrunc f32:$frB))]>;
1865 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1866 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1867 "frim", "$frD, $frB", IIC_FPGeneral,
1868 [(set f64:$frD, (ffloor f64:$frB))]>;
1869 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1870 "frim", "$frD, $frB", IIC_FPGeneral,
1871 [(set f32:$frD, (ffloor f32:$frB))]>;
1873 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1874 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1875 [(set f64:$frD, (fsqrt f64:$frB))]>;
1876 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1877 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1878 [(set f32:$frD, (fsqrt f32:$frB))]>;
1883 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1884 /// often coalesced away and we don't want the dispatch group builder to think
1885 /// that they will fill slots (which could cause the load of a LSU reject to
1886 /// sneak into a d-group with a store).
1887 let neverHasSideEffects = 1 in
1888 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1889 "fmr", "$frD, $frB", IIC_FPGeneral,
1890 []>, // (set f32:$frD, f32:$frB)
1893 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1894 // These are artificially split into two different forms, for 4/8 byte FP.
1895 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1896 "fabs", "$frD, $frB", IIC_FPGeneral,
1897 [(set f32:$frD, (fabs f32:$frB))]>;
1898 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1899 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1900 "fabs", "$frD, $frB", IIC_FPGeneral,
1901 [(set f64:$frD, (fabs f64:$frB))]>;
1902 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1903 "fnabs", "$frD, $frB", IIC_FPGeneral,
1904 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1905 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1906 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1907 "fnabs", "$frD, $frB", IIC_FPGeneral,
1908 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1909 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1910 "fneg", "$frD, $frB", IIC_FPGeneral,
1911 [(set f32:$frD, (fneg f32:$frB))]>;
1912 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1913 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1914 "fneg", "$frD, $frB", IIC_FPGeneral,
1915 [(set f64:$frD, (fneg f64:$frB))]>;
1917 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1918 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1919 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1920 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1921 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1922 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1923 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1925 // Reciprocal estimates.
1926 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1927 "fre", "$frD, $frB", IIC_FPGeneral,
1928 [(set f64:$frD, (PPCfre f64:$frB))]>;
1929 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1930 "fres", "$frD, $frB", IIC_FPGeneral,
1931 [(set f32:$frD, (PPCfre f32:$frB))]>;
1932 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1933 "frsqrte", "$frD, $frB", IIC_FPGeneral,
1934 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1935 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1936 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
1937 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1940 // XL-Form instructions. condition register logical ops.
1942 let neverHasSideEffects = 1 in
1943 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1944 "mcrf $BF, $BFA", IIC_BrMCR>,
1945 PPC970_DGroup_First, PPC970_Unit_CRU;
1947 let isCommutable = 1 in {
1948 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
1949 (ins crbitrc:$CRA, crbitrc:$CRB),
1950 "crand $CRD, $CRA, $CRB", IIC_BrCR,
1951 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
1953 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
1954 (ins crbitrc:$CRA, crbitrc:$CRB),
1955 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
1956 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
1958 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
1959 (ins crbitrc:$CRA, crbitrc:$CRB),
1960 "cror $CRD, $CRA, $CRB", IIC_BrCR,
1961 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
1963 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
1964 (ins crbitrc:$CRA, crbitrc:$CRB),
1965 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
1966 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
1968 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
1969 (ins crbitrc:$CRA, crbitrc:$CRB),
1970 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
1971 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
1973 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
1974 (ins crbitrc:$CRA, crbitrc:$CRB),
1975 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
1976 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
1979 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
1980 (ins crbitrc:$CRA, crbitrc:$CRB),
1981 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
1982 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
1984 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
1985 (ins crbitrc:$CRA, crbitrc:$CRB),
1986 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
1987 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
1989 let isCodeGenOnly = 1 in {
1990 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
1991 "creqv $dst, $dst, $dst", IIC_BrCR,
1992 [(set i1:$dst, 1)]>;
1994 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
1995 "crxor $dst, $dst, $dst", IIC_BrCR,
1996 [(set i1:$dst, 0)]>;
1998 let Defs = [CR1EQ], CRD = 6 in {
1999 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2000 "creqv 6, 6, 6", IIC_BrCR,
2003 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2004 "crxor 6, 6, 6", IIC_BrCR,
2009 // XFX-Form instructions. Instructions that deal with SPRs.
2012 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2013 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2014 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2015 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2017 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2018 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2020 let Uses = [CTR] in {
2021 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2022 "mfctr $rT", IIC_SprMFSPR>,
2023 PPC970_DGroup_First, PPC970_Unit_FXU;
2025 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2026 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2027 "mtctr $rS", IIC_SprMTSPR>,
2028 PPC970_DGroup_First, PPC970_Unit_FXU;
2030 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2031 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2032 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2033 "mtctr $rS", IIC_SprMTSPR>,
2034 PPC970_DGroup_First, PPC970_Unit_FXU;
2037 let Defs = [LR] in {
2038 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2039 "mtlr $rS", IIC_SprMTSPR>,
2040 PPC970_DGroup_First, PPC970_Unit_FXU;
2042 let Uses = [LR] in {
2043 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2044 "mflr $rT", IIC_SprMFSPR>,
2045 PPC970_DGroup_First, PPC970_Unit_FXU;
2048 let isCodeGenOnly = 1 in {
2049 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2050 // like a GPR on the PPC970. As such, copies in and out have the same
2051 // performance characteristics as an OR instruction.
2052 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2053 "mtspr 256, $rS", IIC_IntGeneral>,
2054 PPC970_DGroup_Single, PPC970_Unit_FXU;
2055 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2056 "mfspr $rT, 256", IIC_IntGeneral>,
2057 PPC970_DGroup_First, PPC970_Unit_FXU;
2059 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2060 (outs VRSAVERC:$reg), (ins gprc:$rS),
2061 "mtspr 256, $rS", IIC_IntGeneral>,
2062 PPC970_DGroup_Single, PPC970_Unit_FXU;
2063 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2064 (ins VRSAVERC:$reg),
2065 "mfspr $rT, 256", IIC_IntGeneral>,
2066 PPC970_DGroup_First, PPC970_Unit_FXU;
2069 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2070 // so we'll need to scavenge a register for it.
2072 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2073 "#SPILL_VRSAVE", []>;
2075 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2076 // spilled), so we'll need to scavenge a register for it.
2078 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2079 "#RESTORE_VRSAVE", []>;
2081 let neverHasSideEffects = 1 in {
2082 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2083 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2084 PPC970_DGroup_First, PPC970_Unit_CRU;
2086 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2087 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2088 PPC970_MicroCode, PPC970_Unit_CRU;
2090 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2091 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2092 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2093 PPC970_DGroup_First, PPC970_Unit_CRU;
2095 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2096 "mfcr $rT", IIC_SprMFCR>,
2097 PPC970_MicroCode, PPC970_Unit_CRU;
2098 } // neverHasSideEffects = 1
2100 // Pseudo instruction to perform FADD in round-to-zero mode.
2101 let usesCustomInserter = 1, Uses = [RM] in {
2102 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2103 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2106 // The above pseudo gets expanded to make use of the following instructions
2107 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2108 let Uses = [RM], Defs = [RM] in {
2109 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2110 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2111 PPC970_DGroup_Single, PPC970_Unit_FPU;
2112 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2113 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2114 PPC970_DGroup_Single, PPC970_Unit_FPU;
2115 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2116 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2117 PPC970_DGroup_Single, PPC970_Unit_FPU;
2119 let Uses = [RM] in {
2120 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2121 "mffs $rT", IIC_IntMFFS,
2122 [(set f64:$rT, (PPCmffs))]>,
2123 PPC970_DGroup_Single, PPC970_Unit_FPU;
2127 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
2128 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2129 let isCommutable = 1 in
2130 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2131 "add", "$rT, $rA, $rB", IIC_IntSimple,
2132 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2133 let isCodeGenOnly = 1 in
2134 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2135 "add $rT, $rA, $rB", IIC_IntSimple,
2136 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2137 let isCommutable = 1 in
2138 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2139 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2140 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2141 PPC970_DGroup_Cracked;
2143 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2144 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2145 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2146 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2147 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2148 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2149 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2150 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2151 let isCommutable = 1 in {
2152 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2153 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2154 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2155 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2156 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2157 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2158 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2159 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2160 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2162 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2163 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2164 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2165 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2166 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2167 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2168 PPC970_DGroup_Cracked;
2169 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2170 "neg", "$rT, $rA", IIC_IntSimple,
2171 [(set i32:$rT, (ineg i32:$rA))]>;
2172 let Uses = [CARRY] in {
2173 let isCommutable = 1 in
2174 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2175 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2176 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2177 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2178 "addme", "$rT, $rA", IIC_IntGeneral,
2179 [(set i32:$rT, (adde i32:$rA, -1))]>;
2180 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2181 "addze", "$rT, $rA", IIC_IntGeneral,
2182 [(set i32:$rT, (adde i32:$rA, 0))]>;
2183 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2184 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2185 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2186 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2187 "subfme", "$rT, $rA", IIC_IntGeneral,
2188 [(set i32:$rT, (sube -1, i32:$rA))]>;
2189 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2190 "subfze", "$rT, $rA", IIC_IntGeneral,
2191 [(set i32:$rT, (sube 0, i32:$rA))]>;
2195 // A-Form instructions. Most of the instructions executed in the FPU are of
2198 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
2199 let Uses = [RM] in {
2200 let isCommutable = 1 in {
2201 defm FMADD : AForm_1r<63, 29,
2202 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2203 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2204 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2205 defm FMADDS : AForm_1r<59, 29,
2206 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2207 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2208 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2209 defm FMSUB : AForm_1r<63, 28,
2210 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2211 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2213 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2214 defm FMSUBS : AForm_1r<59, 28,
2215 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2216 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2218 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2219 defm FNMADD : AForm_1r<63, 31,
2220 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2221 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2223 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2224 defm FNMADDS : AForm_1r<59, 31,
2225 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2226 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2228 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2229 defm FNMSUB : AForm_1r<63, 30,
2230 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2231 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2232 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2233 (fneg f64:$FRB))))]>;
2234 defm FNMSUBS : AForm_1r<59, 30,
2235 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2236 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2237 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2238 (fneg f32:$FRB))))]>;
2241 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2242 // having 4 of these, force the comparison to always be an 8-byte double (code
2243 // should use an FMRSD if the input comparison value really wants to be a float)
2244 // and 4/8 byte forms for the result and operand type..
2245 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2246 defm FSELD : AForm_1r<63, 23,
2247 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2248 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2249 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2250 defm FSELS : AForm_1r<63, 23,
2251 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2252 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2253 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2254 let Uses = [RM] in {
2255 let isCommutable = 1 in {
2256 defm FADD : AForm_2r<63, 21,
2257 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2258 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2259 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2260 defm FADDS : AForm_2r<59, 21,
2261 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2262 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2263 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2265 defm FDIV : AForm_2r<63, 18,
2266 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2267 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2268 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2269 defm FDIVS : AForm_2r<59, 18,
2270 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2271 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2272 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2273 let isCommutable = 1 in {
2274 defm FMUL : AForm_3r<63, 25,
2275 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2276 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2277 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2278 defm FMULS : AForm_3r<59, 25,
2279 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2280 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2281 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2283 defm FSUB : AForm_2r<63, 20,
2284 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2285 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2286 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2287 defm FSUBS : AForm_2r<59, 20,
2288 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2289 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2290 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2294 let neverHasSideEffects = 1 in {
2295 let PPC970_Unit = 1 in { // FXU Operations.
2297 def ISEL : AForm_4<31, 15,
2298 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2299 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
2303 let PPC970_Unit = 1 in { // FXU Operations.
2304 // M-Form instructions. rotate and mask instructions.
2306 let isCommutable = 1 in {
2307 // RLWIMI can be commuted if the rotate amount is zero.
2308 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2309 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2310 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2311 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2312 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2314 let BaseName = "rlwinm" in {
2315 def RLWINM : MForm_2<21,
2316 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2317 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2320 def RLWINMo : MForm_2<21,
2321 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2322 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2323 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2325 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2326 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2327 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2330 } // neverHasSideEffects = 1
2332 //===----------------------------------------------------------------------===//
2333 // PowerPC Instruction Patterns
2336 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2337 def : Pat<(i32 imm:$imm),
2338 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2340 // Implement the 'not' operation with the NOR instruction.
2341 def i32not : OutPatFrag<(ops node:$in),
2343 def : Pat<(not i32:$in),
2346 // ADD an arbitrary immediate.
2347 def : Pat<(add i32:$in, imm:$imm),
2348 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2349 // OR an arbitrary immediate.
2350 def : Pat<(or i32:$in, imm:$imm),
2351 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2352 // XOR an arbitrary immediate.
2353 def : Pat<(xor i32:$in, imm:$imm),
2354 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2356 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2357 (SUBFIC $in, imm:$imm)>;
2360 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2361 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2362 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2363 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2366 def : Pat<(rotl i32:$in, i32:$sh),
2367 (RLWNM $in, $sh, 0, 31)>;
2368 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2369 (RLWINM $in, imm:$imm, 0, 31)>;
2372 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2373 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2376 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2377 (BL tglobaladdr:$dst)>;
2378 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2379 (BL texternalsym:$dst)>;
2382 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2383 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2385 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2386 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2388 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2389 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2393 // Hi and Lo for Darwin Global Addresses.
2394 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2395 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2396 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2397 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2398 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2399 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2400 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2401 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2402 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2403 (ADDIS $in, tglobaltlsaddr:$g)>;
2404 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2405 (ADDI $in, tglobaltlsaddr:$g)>;
2406 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2407 (ADDIS $in, tglobaladdr:$g)>;
2408 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2409 (ADDIS $in, tconstpool:$g)>;
2410 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2411 (ADDIS $in, tjumptable:$g)>;
2412 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2413 (ADDIS $in, tblockaddress:$g)>;
2415 // Support for thread-local storage.
2416 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2417 [(set i32:$rD, (PPCppc32GOT))]>;
2419 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2420 // This uses two output registers, the first as the real output, the second as a
2421 // temporary register, used internally in code generation.
2422 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2423 []>, NoEncode<"$rT">;
2425 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2428 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2429 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2430 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2432 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2435 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2436 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2439 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2440 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2443 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2444 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2447 (PPCgetTlsldAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2448 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2451 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2452 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2455 (PPCaddisDtprelHA i32:$reg,
2456 tglobaltlsaddr:$disp))]>;
2458 // Support for Position-independent code
2459 def LWZtoc: Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2462 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2463 // Get Global (GOT) Base Register offset, from the word immediately preceding
2464 // the function label.
2465 def GetGBRO: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#GetGBRO", []>;
2466 // Update the Global(GOT) Base Register with the above offset.
2467 def UpdateGBR: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2470 // Standard shifts. These are represented separately from the real shifts above
2471 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2473 def : Pat<(sra i32:$rS, i32:$rB),
2475 def : Pat<(srl i32:$rS, i32:$rB),
2477 def : Pat<(shl i32:$rS, i32:$rB),
2480 def : Pat<(zextloadi1 iaddr:$src),
2482 def : Pat<(zextloadi1 xaddr:$src),
2484 def : Pat<(extloadi1 iaddr:$src),
2486 def : Pat<(extloadi1 xaddr:$src),
2488 def : Pat<(extloadi8 iaddr:$src),
2490 def : Pat<(extloadi8 xaddr:$src),
2492 def : Pat<(extloadi16 iaddr:$src),
2494 def : Pat<(extloadi16 xaddr:$src),
2496 def : Pat<(f64 (extloadf32 iaddr:$src)),
2497 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2498 def : Pat<(f64 (extloadf32 xaddr:$src)),
2499 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2501 def : Pat<(f64 (fextend f32:$src)),
2502 (COPY_TO_REGCLASS $src, F8RC)>;
2504 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[IsNotBookE]>;
2505 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[IsBookE]>;
2507 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2508 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2509 (FNMSUB $A, $C, $B)>;
2510 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2511 (FNMSUB $A, $C, $B)>;
2512 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2513 (FNMSUBS $A, $C, $B)>;
2514 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2515 (FNMSUBS $A, $C, $B)>;
2517 // FCOPYSIGN's operand types need not agree.
2518 def : Pat<(fcopysign f64:$frB, f32:$frA),
2519 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2520 def : Pat<(fcopysign f32:$frB, f64:$frA),
2521 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2523 include "PPCInstrAltivec.td"
2524 include "PPCInstr64Bit.td"
2525 include "PPCInstrVSX.td"
2527 def crnot : OutPatFrag<(ops node:$in),
2529 def : Pat<(not i1:$in),
2532 // Patterns for arithmetic i1 operations.
2533 def : Pat<(add i1:$a, i1:$b),
2535 def : Pat<(sub i1:$a, i1:$b),
2537 def : Pat<(mul i1:$a, i1:$b),
2540 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2541 // (-1 is used to mean all bits set).
2542 def : Pat<(i1 -1), (CRSET)>;
2544 // i1 extensions, implemented in terms of isel.
2545 def : Pat<(i32 (zext i1:$in)),
2546 (SELECT_I4 $in, (LI 1), (LI 0))>;
2547 def : Pat<(i32 (sext i1:$in)),
2548 (SELECT_I4 $in, (LI -1), (LI 0))>;
2550 def : Pat<(i64 (zext i1:$in)),
2551 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2552 def : Pat<(i64 (sext i1:$in)),
2553 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2555 // FIXME: We should choose either a zext or a sext based on other constants
2557 def : Pat<(i32 (anyext i1:$in)),
2558 (SELECT_I4 $in, (LI 1), (LI 0))>;
2559 def : Pat<(i64 (anyext i1:$in)),
2560 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2562 // match setcc on i1 variables.
2563 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2565 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2567 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2569 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2571 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2573 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2575 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2577 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2579 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2581 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2584 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2585 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2586 // floating-point types.
2588 multiclass CRNotPat<dag pattern, dag result> {
2589 def : Pat<pattern, (crnot result)>;
2590 def : Pat<(not pattern), result>;
2592 // We can also fold the crnot into an extension:
2593 def : Pat<(i32 (zext pattern)),
2594 (SELECT_I4 result, (LI 0), (LI 1))>;
2595 def : Pat<(i32 (sext pattern)),
2596 (SELECT_I4 result, (LI 0), (LI -1))>;
2598 // We can also fold the crnot into an extension:
2599 def : Pat<(i64 (zext pattern)),
2600 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2601 def : Pat<(i64 (sext pattern)),
2602 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2604 // FIXME: We should choose either a zext or a sext based on other constants
2606 def : Pat<(i32 (anyext pattern)),
2607 (SELECT_I4 result, (LI 0), (LI 1))>;
2609 def : Pat<(i64 (anyext pattern)),
2610 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2613 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2614 // we need to write imm:$imm in the output patterns below, not just $imm, or
2615 // else the resulting matcher will not correctly add the immediate operand
2616 // (making it a register operand instead).
2619 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2620 OutPatFrag rfrag, OutPatFrag rfrag8> {
2621 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2623 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2625 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2626 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2627 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2628 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2630 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2632 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2634 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2635 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2636 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2637 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2640 // Note that we do all inversions below with i(32|64)not, instead of using
2641 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2642 // has 2-cycle latency.
2644 defm : ExtSetCCPat<SETEQ,
2645 PatFrag<(ops node:$in, node:$cc),
2646 (setcc $in, 0, $cc)>,
2647 OutPatFrag<(ops node:$in),
2648 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2649 OutPatFrag<(ops node:$in),
2650 (RLDICL (CNTLZD $in), 58, 63)> >;
2652 defm : ExtSetCCPat<SETNE,
2653 PatFrag<(ops node:$in, node:$cc),
2654 (setcc $in, 0, $cc)>,
2655 OutPatFrag<(ops node:$in),
2656 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2657 OutPatFrag<(ops node:$in),
2658 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2660 defm : ExtSetCCPat<SETLT,
2661 PatFrag<(ops node:$in, node:$cc),
2662 (setcc $in, 0, $cc)>,
2663 OutPatFrag<(ops node:$in),
2664 (RLWINM $in, 1, 31, 31)>,
2665 OutPatFrag<(ops node:$in),
2666 (RLDICL $in, 1, 63)> >;
2668 defm : ExtSetCCPat<SETGE,
2669 PatFrag<(ops node:$in, node:$cc),
2670 (setcc $in, 0, $cc)>,
2671 OutPatFrag<(ops node:$in),
2672 (RLWINM (i32not $in), 1, 31, 31)>,
2673 OutPatFrag<(ops node:$in),
2674 (RLDICL (i64not $in), 1, 63)> >;
2676 defm : ExtSetCCPat<SETGT,
2677 PatFrag<(ops node:$in, node:$cc),
2678 (setcc $in, 0, $cc)>,
2679 OutPatFrag<(ops node:$in),
2680 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2681 OutPatFrag<(ops node:$in),
2682 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2684 defm : ExtSetCCPat<SETLE,
2685 PatFrag<(ops node:$in, node:$cc),
2686 (setcc $in, 0, $cc)>,
2687 OutPatFrag<(ops node:$in),
2688 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2689 OutPatFrag<(ops node:$in),
2690 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2692 defm : ExtSetCCPat<SETLT,
2693 PatFrag<(ops node:$in, node:$cc),
2694 (setcc $in, -1, $cc)>,
2695 OutPatFrag<(ops node:$in),
2696 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2697 OutPatFrag<(ops node:$in),
2698 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2700 defm : ExtSetCCPat<SETGE,
2701 PatFrag<(ops node:$in, node:$cc),
2702 (setcc $in, -1, $cc)>,
2703 OutPatFrag<(ops node:$in),
2704 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2705 OutPatFrag<(ops node:$in),
2706 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2708 defm : ExtSetCCPat<SETGT,
2709 PatFrag<(ops node:$in, node:$cc),
2710 (setcc $in, -1, $cc)>,
2711 OutPatFrag<(ops node:$in),
2712 (RLWINM (i32not $in), 1, 31, 31)>,
2713 OutPatFrag<(ops node:$in),
2714 (RLDICL (i64not $in), 1, 63)> >;
2716 defm : ExtSetCCPat<SETLE,
2717 PatFrag<(ops node:$in, node:$cc),
2718 (setcc $in, -1, $cc)>,
2719 OutPatFrag<(ops node:$in),
2720 (RLWINM $in, 1, 31, 31)>,
2721 OutPatFrag<(ops node:$in),
2722 (RLDICL $in, 1, 63)> >;
2725 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2726 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2727 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2728 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2729 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2730 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2731 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2732 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2733 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2734 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2735 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2736 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2738 // For non-equality comparisons, the default code would materialize the
2739 // constant, then compare against it, like this:
2741 // ori r2, r2, 22136
2744 // Since we are just comparing for equality, we can emit this instead:
2745 // xoris r0,r3,0x1234
2746 // cmplwi cr0,r0,0x5678
2749 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2750 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2751 (LO16 imm:$imm)), sub_eq)>;
2753 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2754 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2755 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2756 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2757 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2758 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2759 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2760 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2761 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2762 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2763 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2764 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2766 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2767 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2768 (LO16 imm:$imm)), sub_eq)>;
2770 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
2771 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2772 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2773 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2774 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2775 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2776 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
2777 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2778 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2779 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2781 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2782 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2783 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
2784 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2785 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2786 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2787 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
2788 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2789 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2790 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2793 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
2794 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2795 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2796 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2797 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2798 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2799 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
2800 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2801 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
2802 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2803 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
2804 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2806 // For non-equality comparisons, the default code would materialize the
2807 // constant, then compare against it, like this:
2809 // ori r2, r2, 22136
2812 // Since we are just comparing for equality, we can emit this instead:
2813 // xoris r0,r3,0x1234
2814 // cmpldi cr0,r0,0x5678
2817 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
2818 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2819 (LO16 imm:$imm)), sub_eq)>;
2821 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
2822 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2823 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
2824 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2825 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
2826 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2827 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
2828 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2829 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
2830 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2831 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
2832 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2834 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
2835 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2836 (LO16 imm:$imm)), sub_eq)>;
2838 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
2839 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2840 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
2841 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2842 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
2843 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2844 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
2845 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2846 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
2847 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2849 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
2850 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2851 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
2852 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2853 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
2854 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2855 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
2856 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2857 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
2858 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2861 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
2862 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2863 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
2864 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2865 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
2866 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2867 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
2868 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2869 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
2870 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2871 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
2872 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2873 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
2874 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2876 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
2877 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2878 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
2879 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2880 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
2881 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2882 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
2883 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2884 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
2885 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2886 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
2887 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2888 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
2889 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2892 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
2893 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2894 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
2895 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2896 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
2897 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2898 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
2899 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2900 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
2901 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2902 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
2903 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2904 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
2905 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2907 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
2908 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2909 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
2910 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2911 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
2912 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2913 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
2914 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2915 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
2916 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2917 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
2918 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2919 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
2920 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2922 // match select on i1 variables:
2923 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
2924 (CROR (CRAND $cond , $tval),
2925 (CRAND (crnot $cond), $fval))>;
2927 // match selectcc on i1 variables:
2928 // select (lhs == rhs), tval, fval is:
2929 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
2930 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
2931 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
2932 (CRAND (CRORC $lhs, $rhs), $fval))>;
2933 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
2934 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
2935 (CRAND (CRANDC $lhs, $rhs), $fval))>;
2936 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
2937 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
2938 (CRAND (CRXOR $lhs, $rhs), $fval))>;
2939 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
2940 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
2941 (CRAND (CRANDC $rhs, $lhs), $fval))>;
2942 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
2943 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
2944 (CRAND (CRORC $rhs, $lhs), $fval))>;
2945 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
2946 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
2947 (CRAND (CRXOR $lhs, $rhs), $tval))>;
2949 // match selectcc on i1 variables with non-i1 output.
2950 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
2951 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
2952 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
2953 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
2954 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
2955 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
2956 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
2957 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
2958 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
2959 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
2960 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
2961 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
2963 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
2964 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
2965 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
2966 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
2967 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
2968 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
2969 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
2970 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
2971 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
2972 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
2973 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
2974 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
2976 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
2977 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
2978 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
2979 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
2980 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
2981 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
2982 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
2983 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
2984 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
2985 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
2986 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
2987 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
2989 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
2990 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
2991 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
2992 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
2993 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
2994 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
2995 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
2996 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
2997 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
2998 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
2999 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3000 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3002 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3003 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3004 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3005 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3006 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3007 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3008 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3009 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3010 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3011 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3012 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3013 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3015 let usesCustomInserter = 1 in {
3016 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3018 [(set i1:$dst, (trunc (not i32:$in)))]>;
3019 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3021 [(set i1:$dst, (trunc i32:$in))]>;
3023 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3025 [(set i1:$dst, (trunc (not i64:$in)))]>;
3026 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3028 [(set i1:$dst, (trunc i64:$in))]>;
3031 def : Pat<(i1 (not (trunc i32:$in))),
3032 (ANDIo_1_EQ_BIT $in)>;
3033 def : Pat<(i1 (not (trunc i64:$in))),
3034 (ANDIo_1_EQ_BIT8 $in)>;
3036 //===----------------------------------------------------------------------===//
3037 // PowerPC Instructions used for assembler/disassembler only
3040 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3041 "isync", IIC_SprISYNC, []>;
3043 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3044 "icbi $src", IIC_LdStICBI, []>;
3046 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3047 "eieio", IIC_LdStLoad, []>;
3049 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3050 "wait $L", IIC_LdStLoad, []>;
3052 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3053 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3055 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3056 "mtsr $SR, $RS", IIC_SprMTSR>;
3058 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3059 "mfsr $RS, $SR", IIC_SprMFSR>;
3061 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3062 "mtsrin $RS, $RB", IIC_SprMTSR>;
3064 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3065 "mfsrin $RS, $RB", IIC_SprMFSR>;
3067 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3068 "mtmsr $RS, $L", IIC_SprMTMSR>;
3070 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3071 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3075 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3076 Requires<[IsBookE]> {
3080 let Inst{21-30} = 163;
3083 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3084 "mfmsr $RT", IIC_SprMFMSR, []>;
3086 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3087 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3089 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3090 "slbie $RB", IIC_SprSLBIE, []>;
3092 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3093 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3095 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3096 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3098 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3100 def TLBIA : XForm_0<31, 370, (outs), (ins),
3101 "tlbia", IIC_SprTLBIA, []>;
3103 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3104 "tlbsync", IIC_SprTLBSYNC, []>;
3106 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3107 "tlbiel $RB", IIC_SprTLBIEL, []>;
3109 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3110 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3112 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3113 IIC_LdStLoad>, Requires<[IsBookE]>;
3115 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3116 IIC_LdStLoad>, Requires<[IsBookE]>;
3118 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3119 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3121 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3122 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3124 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_BrB, []>,
3125 Requires<[IsBookE]>;
3126 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3127 Requires<[IsBookE]>;
3129 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3131 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3134 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3135 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3136 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3137 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3139 //===----------------------------------------------------------------------===//
3140 // PowerPC Assembler Instruction Aliases
3143 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3144 // These are aliases that require C++ handling to convert to the target
3145 // instruction, while InstAliases can be handled directly by tblgen.
3146 class PPCAsmPseudo<string asm, dag iops>
3148 let Namespace = "PPC";
3149 bit PPC64 = 0; // Default value, override with isPPC64
3151 let OutOperandList = (outs);
3152 let InOperandList = iops;
3154 let AsmString = asm;
3155 let isAsmParserOnly = 1;
3159 def : InstAlias<"sc", (SC 0)>;
3161 def : InstAlias<"sync", (SYNC 0)>, Requires<[IsNotBookE]>;
3162 def : InstAlias<"msync", (SYNC 0)>, Requires<[IsNotBookE]>;
3163 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[IsNotBookE]>;
3164 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[IsNotBookE]>;
3166 def : InstAlias<"wait", (WAIT 0)>;
3167 def : InstAlias<"waitrsv", (WAIT 1)>;
3168 def : InstAlias<"waitimpl", (WAIT 2)>;
3170 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3172 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3173 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3174 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3175 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3177 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3178 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3180 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3181 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3183 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3184 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3186 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3187 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3189 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3190 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3192 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3193 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3195 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3196 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3198 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3199 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3201 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3202 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3204 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3205 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3207 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3208 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3210 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3211 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3212 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3214 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3216 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3217 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3219 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3220 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3222 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3224 foreach BATR = 0-3 in {
3225 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3226 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3227 Requires<[IsPPC6xx]>;
3228 def : InstAlias<"mfdbatu $Rx, "#BATR,
3229 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3230 Requires<[IsPPC6xx]>;
3231 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3232 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3233 Requires<[IsPPC6xx]>;
3234 def : InstAlias<"mfdbatl $Rx, "#BATR,
3235 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3236 Requires<[IsPPC6xx]>;
3237 def : InstAlias<"mtibatu "#BATR#", $Rx",
3238 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3239 Requires<[IsPPC6xx]>;
3240 def : InstAlias<"mfibatu $Rx, "#BATR,
3241 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3242 Requires<[IsPPC6xx]>;
3243 def : InstAlias<"mtibatl "#BATR#", $Rx",
3244 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3245 Requires<[IsPPC6xx]>;
3246 def : InstAlias<"mfibatl $Rx, "#BATR,
3247 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3248 Requires<[IsPPC6xx]>;
3251 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3253 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3254 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3255 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3256 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3257 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3258 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3259 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3260 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3262 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3263 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3264 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3265 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3267 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3268 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3270 foreach SPRG = 0-3 in {
3271 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3272 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3273 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3274 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3276 foreach SPRG = 4-7 in {
3277 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3278 Requires<[IsBookE]>;
3279 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3280 Requires<[IsBookE]>;
3281 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3282 Requires<[IsBookE]>;
3283 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3284 Requires<[IsBookE]>;
3287 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3289 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3290 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3292 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3294 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3295 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3297 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3298 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3299 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3300 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3302 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3304 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3305 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3306 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3307 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3308 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3309 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3310 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3311 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3312 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3313 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3314 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3315 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3316 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3317 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3318 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3319 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3320 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3321 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3322 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3323 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3324 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3325 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3326 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3327 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3328 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3329 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3330 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3331 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3332 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3333 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3334 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3335 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3336 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3337 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3338 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3339 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3341 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3342 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3343 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3344 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3345 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3346 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3348 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3349 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3350 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3351 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3352 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3353 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3354 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3355 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3356 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3357 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3358 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3359 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3360 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3361 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3362 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3363 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3364 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3365 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3366 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3367 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3368 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3369 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3370 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3371 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3372 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3373 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3374 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3375 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3376 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3377 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3378 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3379 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3381 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3382 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3383 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3384 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3385 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3386 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3388 // These generic branch instruction forms are used for the assembler parser only.
3389 // Defs and Uses are conservative, since we don't know the BO value.
3390 let PPC970_Unit = 7 in {
3391 let Defs = [CTR], Uses = [CTR, RM] in {
3392 def gBC : BForm_3<16, 0, 0, (outs),
3393 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3394 "bc $bo, $bi, $dst">;
3395 def gBCA : BForm_3<16, 1, 0, (outs),
3396 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3397 "bca $bo, $bi, $dst">;
3399 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3400 def gBCL : BForm_3<16, 0, 1, (outs),
3401 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3402 "bcl $bo, $bi, $dst">;
3403 def gBCLA : BForm_3<16, 1, 1, (outs),
3404 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3405 "bcla $bo, $bi, $dst">;
3407 let Defs = [CTR], Uses = [CTR, LR, RM] in
3408 def gBCLR : XLForm_2<19, 16, 0, (outs),
3409 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3410 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3411 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3412 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3413 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3414 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3415 let Defs = [CTR], Uses = [CTR, LR, RM] in
3416 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3417 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3418 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3419 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3420 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3421 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3422 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3424 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3425 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3426 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3427 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3429 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3430 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3431 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3432 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3433 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3434 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3435 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3437 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3438 : BranchSimpleMnemonic1<name, pm, bo> {
3439 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3440 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3442 defm : BranchSimpleMnemonic2<"t", "", 12>;
3443 defm : BranchSimpleMnemonic2<"f", "", 4>;
3444 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3445 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3446 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3447 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3448 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3449 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3450 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3451 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3453 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3454 def : InstAlias<"b"#name#pm#" $cc, $dst",
3455 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3456 def : InstAlias<"b"#name#pm#" $dst",
3457 (BCC bibo, CR0, condbrtarget:$dst)>;
3459 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3460 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3461 def : InstAlias<"b"#name#"a"#pm#" $dst",
3462 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3464 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3465 (BCCLR bibo, crrc:$cc)>;
3466 def : InstAlias<"b"#name#"lr"#pm,
3469 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3470 (BCCCTR bibo, crrc:$cc)>;
3471 def : InstAlias<"b"#name#"ctr"#pm,
3472 (BCCCTR bibo, CR0)>;
3474 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3475 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3476 def : InstAlias<"b"#name#"l"#pm#" $dst",
3477 (BCCL bibo, CR0, condbrtarget:$dst)>;
3479 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3480 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3481 def : InstAlias<"b"#name#"la"#pm#" $dst",
3482 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3484 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3485 (BCCLRL bibo, crrc:$cc)>;
3486 def : InstAlias<"b"#name#"lrl"#pm,
3487 (BCCLRL bibo, CR0)>;
3489 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3490 (BCCCTRL bibo, crrc:$cc)>;
3491 def : InstAlias<"b"#name#"ctrl"#pm,
3492 (BCCCTRL bibo, CR0)>;
3494 multiclass BranchExtendedMnemonic<string name, int bibo> {
3495 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3496 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3497 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3499 defm : BranchExtendedMnemonic<"lt", 12>;
3500 defm : BranchExtendedMnemonic<"gt", 44>;
3501 defm : BranchExtendedMnemonic<"eq", 76>;
3502 defm : BranchExtendedMnemonic<"un", 108>;
3503 defm : BranchExtendedMnemonic<"so", 108>;
3504 defm : BranchExtendedMnemonic<"ge", 4>;
3505 defm : BranchExtendedMnemonic<"nl", 4>;
3506 defm : BranchExtendedMnemonic<"le", 36>;
3507 defm : BranchExtendedMnemonic<"ng", 36>;
3508 defm : BranchExtendedMnemonic<"ne", 68>;
3509 defm : BranchExtendedMnemonic<"nu", 100>;
3510 defm : BranchExtendedMnemonic<"ns", 100>;
3512 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3513 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3514 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3515 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3516 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3517 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3518 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3519 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3521 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3522 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3523 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3524 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3525 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3526 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3527 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3528 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3530 multiclass TrapExtendedMnemonic<string name, int to> {
3531 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3532 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3533 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3534 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3536 defm : TrapExtendedMnemonic<"lt", 16>;
3537 defm : TrapExtendedMnemonic<"le", 20>;
3538 defm : TrapExtendedMnemonic<"eq", 4>;
3539 defm : TrapExtendedMnemonic<"ge", 12>;
3540 defm : TrapExtendedMnemonic<"gt", 8>;
3541 defm : TrapExtendedMnemonic<"nl", 12>;
3542 defm : TrapExtendedMnemonic<"ne", 24>;
3543 defm : TrapExtendedMnemonic<"ng", 20>;
3544 defm : TrapExtendedMnemonic<"llt", 2>;
3545 defm : TrapExtendedMnemonic<"lle", 6>;
3546 defm : TrapExtendedMnemonic<"lge", 5>;
3547 defm : TrapExtendedMnemonic<"lgt", 1>;
3548 defm : TrapExtendedMnemonic<"lnl", 5>;
3549 defm : TrapExtendedMnemonic<"lng", 6>;
3550 defm : TrapExtendedMnemonic<"u", 31>;