1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific DAG Nodes.
21 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
22 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
23 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
25 def PPCfsel : SDNode<"PPCISD::FSEL",
26 // Type constraint for fsel.
27 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
28 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
30 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
31 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
32 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
33 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
35 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
36 // amounts. These nodes are generated by the multi-precision shift code.
37 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
38 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
40 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
41 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
42 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
44 // These are target-independent nodes, but have target-specific formats.
45 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
46 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
47 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
49 //===----------------------------------------------------------------------===//
50 // PowerPC specific transformation functions and pattern fragments.
53 def SHL32 : SDNodeXForm<imm, [{
54 // Transformation function: 31 - imm
55 return getI32Imm(31 - N->getValue());
58 def SHL64 : SDNodeXForm<imm, [{
59 // Transformation function: 63 - imm
60 return getI32Imm(63 - N->getValue());
63 def SRL32 : SDNodeXForm<imm, [{
64 // Transformation function: 32 - imm
65 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
68 def SRL64 : SDNodeXForm<imm, [{
69 // Transformation function: 64 - imm
70 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
73 def LO16 : SDNodeXForm<imm, [{
74 // Transformation function: get the low 16 bits.
75 return getI32Imm((unsigned short)N->getValue());
78 def HI16 : SDNodeXForm<imm, [{
79 // Transformation function: shift the immediate value down into the low bits.
80 return getI32Imm((unsigned)N->getValue() >> 16);
83 def HA16 : SDNodeXForm<imm, [{
84 // Transformation function: shift the immediate value down into the low bits.
85 signed int Val = N->getValue();
86 return getI32Imm((Val - (signed short)Val) >> 16);
90 def immSExt16 : PatLeaf<(imm), [{
91 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
92 // field. Used by instructions like 'addi'.
93 return (int)N->getValue() == (short)N->getValue();
95 def immZExt16 : PatLeaf<(imm), [{
96 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
97 // field. Used by instructions like 'ori'.
98 return (unsigned)N->getValue() == (unsigned short)N->getValue();
101 def imm16Shifted : PatLeaf<(imm), [{
102 // imm16Shifted predicate - True if only bits in the top 16-bits of the
103 // immediate are set. Used by instructions like 'addis'.
104 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
108 // Example of a legalize expander: Only for PPC64.
109 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
110 [(set f64:$tmp , (FCTIDZ f64:$src)),
111 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
112 (store f64:$tmp, i32:$tmpFI),
113 (set i64:$dst, (load i32:$tmpFI))],
117 //===----------------------------------------------------------------------===//
118 // PowerPC Flag Definitions.
120 class isPPC64 { bit PPC64 = 1; }
121 class isVMX { bit VMX = 1; }
123 list<Register> Defs = [CR0];
129 //===----------------------------------------------------------------------===//
130 // PowerPC Operand Definitions.
132 def u5imm : Operand<i32> {
133 let PrintMethod = "printU5ImmOperand";
135 def u6imm : Operand<i32> {
136 let PrintMethod = "printU6ImmOperand";
138 def s16imm : Operand<i32> {
139 let PrintMethod = "printS16ImmOperand";
141 def u16imm : Operand<i32> {
142 let PrintMethod = "printU16ImmOperand";
144 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
145 let PrintMethod = "printS16X4ImmOperand";
147 def target : Operand<OtherVT> {
148 let PrintMethod = "printBranchOperand";
150 def calltarget : Operand<i32> {
151 let PrintMethod = "printCallOperand";
153 def aaddr : Operand<i32> {
154 let PrintMethod = "printAbsAddrOperand";
156 def piclabel: Operand<i32> {
157 let PrintMethod = "printPICLabel";
159 def symbolHi: Operand<i32> {
160 let PrintMethod = "printSymbolHi";
162 def symbolLo: Operand<i32> {
163 let PrintMethod = "printSymbolLo";
165 def crbitm: Operand<i8> {
166 let PrintMethod = "printcrbitm";
170 //===----------------------------------------------------------------------===//
171 // PowerPC Instruction Definitions.
173 // Pseudo-instructions:
174 def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
176 let isLoad = 1, hasCtrlDep = 1 in {
177 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
178 "; ADJCALLSTACKDOWN",
179 [(callseq_start imm:$amt)]>;
180 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
182 [(callseq_end imm:$amt)]>;
184 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
185 [(set GPRC:$rD, (undef))]>;
186 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8",
187 [(set F8RC:$rD, (undef))]>;
188 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4",
189 [(set F4RC:$rD, (undef))]>;
191 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
192 // scheduler into a branch sequence.
193 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
194 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
195 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
196 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
197 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
198 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
199 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
203 let isTerminator = 1 in {
205 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB>;
206 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB>;
210 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>;
212 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
213 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
214 target:$true, target:$false),
215 "; COND_BRANCH", []>;
216 def B : IForm<18, 0, 0, (ops target:$dst),
220 // FIXME: 4*CR# needs to be added to the BI field!
221 // This will only work for CR0 as it stands now
222 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
223 "blt $crS, $block", BrB>;
224 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
225 "ble $crS, $block", BrB>;
226 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
227 "beq $crS, $block", BrB>;
228 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
229 "bge $crS, $block", BrB>;
230 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
231 "bgt $crS, $block", BrB>;
232 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
233 "bne $crS, $block", BrB>;
234 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
235 "bun $crS, $block", BrB>;
236 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
237 "bnu $crS, $block", BrB>;
241 // All calls clobber the non-callee saved registers...
242 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
243 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
245 CR0,CR1,CR5,CR6,CR7] in {
246 // Convenient aliases for call instructions
247 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
248 "bl $func", BrB, []>;
249 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
250 "bla $func", BrB, []>;
251 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB>;
254 // D-Form instructions. Most instructions that perform an operation on a
255 // register and an immediate are of this type.
258 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
259 "lbz $rD, $disp($rA)", LdStGeneral,
261 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
262 "lha $rD, $disp($rA)", LdStLHA,
264 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
265 "lhz $rD, $disp($rA)", LdStGeneral,
267 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
268 "lmw $rD, $disp($rA)", LdStLMW,
270 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
271 "lwz $rD, $disp($rA)", LdStGeneral,
273 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
274 "lwzu $rD, $disp($rA)", LdStGeneral,
277 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
278 "addi $rD, $rA, $imm", IntGeneral,
279 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
280 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
281 "addic $rD, $rA, $imm", IntGeneral,
283 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
284 "addic. $rD, $rA, $imm", IntGeneral,
286 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
287 "addis $rD, $rA, $imm", IntGeneral,
288 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
289 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
290 "la $rD, $sym($rA)", IntGeneral,
291 [(set GPRC:$rD, (add GPRC:$rA,
292 (PPClo tglobaladdr:$sym, 0)))]>;
293 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
294 "mulli $rD, $rA, $imm", IntMulLI,
295 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
296 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
297 "subfic $rD, $rA, $imm", IntGeneral,
298 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
299 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
300 "li $rD, $imm", IntGeneral,
301 [(set GPRC:$rD, immSExt16:$imm)]>;
302 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
303 "lis $rD, $imm", IntGeneral,
304 [(set GPRC:$rD, imm16Shifted:$imm)]>;
306 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
307 "stmw $rS, $disp($rA)", LdStLMW,
309 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
310 "stb $rS, $disp($rA)", LdStGeneral,
312 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
313 "sth $rS, $disp($rA)", LdStGeneral,
315 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
316 "stw $rS, $disp($rA)", LdStGeneral,
318 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
319 "stwu $rS, $disp($rA)", LdStGeneral,
322 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
323 "andi. $dst, $src1, $src2", IntGeneral,
325 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
326 "andis. $dst, $src1, $src2", IntGeneral,
328 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
329 "ori $dst, $src1, $src2", IntGeneral,
330 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
331 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
332 "oris $dst, $src1, $src2", IntGeneral,
333 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
334 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
335 "xori $dst, $src1, $src2", IntGeneral,
336 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
337 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
338 "xoris $dst, $src1, $src2", IntGeneral,
339 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
340 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
342 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
343 "cmpi $crD, $L, $rA, $imm", IntCompare>;
344 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
345 "cmpwi $crD, $rA, $imm", IntCompare>;
346 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
347 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
348 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
349 "cmpli $dst, $size, $src1, $src2", IntCompare>;
350 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
351 "cmplwi $dst, $src1, $src2", IntCompare>;
352 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
353 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
355 def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
356 "lfs $rD, $disp($rA)", LdStLFDU,
358 def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
359 "lfd $rD, $disp($rA)", LdStLFD,
363 def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
364 "stfs $rS, $disp($rA)", LdStUX,
366 def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
367 "stfd $rS, $disp($rA)", LdStUX,
371 // DS-Form instructions. Load/Store instructions available in PPC-64
374 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
375 "lwa $rT, $DS($rA)", LdStLWA,
377 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
378 "ld $rT, $DS($rA)", LdStLD,
382 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
383 "std $rT, $DS($rA)", LdStSTD,
385 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
386 "stdu $rT, $DS($rA)", LdStSTD,
390 // X-Form instructions. Most instructions that perform an operation on a
391 // register and another register are of this type.
394 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
395 "lbzx $dst, $base, $index", LdStGeneral,
397 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
398 "lhax $dst, $base, $index", LdStLHA,
400 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
401 "lhzx $dst, $base, $index", LdStGeneral,
403 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
404 "lwax $dst, $base, $index", LdStLHA,
406 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
407 "lwzx $dst, $base, $index", LdStGeneral,
409 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
410 "ldx $dst, $base, $index", LdStLD,
412 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
413 "lvebx $vD, $base, $rA", LdStGeneral,
415 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
416 "lvehx $vD, $base, $rA", LdStGeneral,
418 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
419 "lvewx $vD, $base, $rA", LdStGeneral,
421 def LVX : XForm_1<31, 103, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
422 "lvx $vD, $base, $rA", LdStGeneral,
425 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
426 "lvsl $vD, $base, $rA", LdStGeneral,
428 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
429 "lvsl $vD, $base, $rA", LdStGeneral,
431 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
432 "nand $rA, $rS, $rB", IntGeneral,
433 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
434 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
435 "and $rA, $rS, $rB", IntGeneral,
436 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
437 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
438 "and. $rA, $rS, $rB", IntGeneral,
440 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
441 "andc $rA, $rS, $rB", IntGeneral,
442 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
443 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
444 "or $rA, $rS, $rB", IntGeneral,
445 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
446 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
447 "or $rA, $rS, $rB", IntGeneral,
448 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
449 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
450 "or $rA, $rS, $rB", IntGeneral,
452 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
453 "or $rA, $rS, $rB", IntGeneral,
455 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
456 "nor $rA, $rS, $rB", IntGeneral,
457 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
458 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
459 "or. $rA, $rS, $rB", IntGeneral,
461 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
462 "orc $rA, $rS, $rB", IntGeneral,
463 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
464 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
465 "eqv $rA, $rS, $rB", IntGeneral,
466 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
467 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
468 "xor $rA, $rS, $rB", IntGeneral,
469 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
470 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
471 "sld $rA, $rS, $rB", IntRotateD,
472 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
473 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
474 "slw $rA, $rS, $rB", IntGeneral,
475 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
476 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
477 "srd $rA, $rS, $rB", IntRotateD,
478 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
479 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
480 "srw $rA, $rS, $rB", IntGeneral,
481 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
482 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
483 "srad $rA, $rS, $rB", IntRotateD,
484 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
485 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
486 "sraw $rA, $rS, $rB", IntShift,
487 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
489 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
490 "stbx $rS, $rA, $rB", LdStGeneral,
492 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
493 "sthx $rS, $rA, $rB", LdStGeneral,
495 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
496 "stwx $rS, $rA, $rB", LdStGeneral,
498 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
499 "stwux $rS, $rA, $rB", LdStGeneral,
501 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
502 "stdx $rS, $rA, $rB", LdStSTD,
504 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
505 "stdux $rS, $rA, $rB", LdStSTD,
507 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
508 "stvebx $rS, $rA, $rB", LdStGeneral,
510 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
511 "stvehx $rS, $rA, $rB", LdStGeneral,
513 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
514 "stvewx $rS, $rA, $rB", LdStGeneral,
516 def STVX : XForm_8<31, 231, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
517 "stvx $rS, $rA, $rB", LdStGeneral,
520 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
521 "srawi $rA, $rS, $SH", IntShift,
522 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
523 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
524 "cntlzw $rA, $rS", IntGeneral,
525 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
526 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
527 "extsb $rA, $rS", IntGeneral,
528 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
529 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
530 "extsh $rA, $rS", IntGeneral,
531 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
532 def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
533 "extsw $rA, $rS", IntGeneral,
534 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
535 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
536 "cmp $crD, $long, $rA, $rB", IntCompare>;
537 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
538 "cmpl $crD, $long, $rA, $rB", IntCompare>;
539 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
540 "cmpw $crD, $rA, $rB", IntCompare>;
541 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
542 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
543 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
544 "cmplw $crD, $rA, $rB", IntCompare>;
545 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
546 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
547 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
548 // "fcmpo $crD, $fA, $fB", FPCompare>;
549 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
550 "fcmpu $crD, $fA, $fB", FPCompare>;
551 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
552 "fcmpu $crD, $fA, $fB", FPCompare>;
555 def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
556 "lfsx $dst, $base, $index", LdStLFDU,
558 def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
559 "lfdx $dst, $base, $index", LdStLFDU,
562 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
563 "fcfid $frD, $frB", FPGeneral,
564 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
565 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
566 "fctidz $frD, $frB", FPGeneral,
567 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
568 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
569 "fctiwz $frD, $frB", FPGeneral,
570 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
571 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
572 "frsp $frD, $frB", FPGeneral,
573 [(set F4RC:$frD, (fround F8RC:$frB))]>;
574 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
575 "fsqrt $frD, $frB", FPSqrt,
576 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
577 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
578 "fsqrts $frD, $frB", FPSqrt,
579 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
581 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
582 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
583 "fmr $frD, $frB", FPGeneral,
584 []>; // (set F4RC:$frD, F4RC:$frB)
585 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
586 "fmr $frD, $frB", FPGeneral,
587 []>; // (set F8RC:$frD, F8RC:$frB)
588 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
589 "fmr $frD, $frB", FPGeneral,
590 [(set F8RC:$frD, (fextend F4RC:$frB))]>;
592 // These are artificially split into two different forms, for 4/8 byte FP.
593 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
594 "fabs $frD, $frB", FPGeneral,
595 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
596 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
597 "fabs $frD, $frB", FPGeneral,
598 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
599 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
600 "fnabs $frD, $frB", FPGeneral,
601 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
602 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
603 "fnabs $frD, $frB", FPGeneral,
604 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
605 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
606 "fneg $frD, $frB", FPGeneral,
607 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
608 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
609 "fneg $frD, $frB", FPGeneral,
610 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
614 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
615 "stfsx $frS, $rA, $rB", LdStUX,
617 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
618 "stfdx $frS, $rA, $rB", LdStUX,
622 // XL-Form instructions. condition register logical ops.
624 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
625 "mcrf $BF, $BFA", BrMCR>;
627 // XFX-Form instructions. Instructions that deal with SPRs
629 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
630 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
631 // which means the SPR value needs to be multiplied by a factor of 32.
632 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
633 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
634 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
635 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
636 "mtcrf $FXM, $rS", BrMCRX>;
637 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
638 "mfcr $rT, $FXM", SprMFCR>;
639 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
640 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
641 def MTSPR : XFXForm_7<31, 467, (ops GPRC:$rS, u16imm:$UIMM), "mtspr $UIMM, $rS",
644 // XS-Form instructions. Just 'sradi'
646 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
647 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
649 // XO-Form instructions. Arithmetic instructions that can set overflow bit
651 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
652 "add $rT, $rA, $rB", IntGeneral,
653 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
654 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
655 "add $rT, $rA, $rB", IntGeneral,
656 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
657 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
658 "addc $rT, $rA, $rB", IntGeneral,
660 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
661 "adde $rT, $rA, $rB", IntGeneral,
663 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
664 "divd $rT, $rA, $rB", IntDivD,
665 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
666 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
667 "divdu $rT, $rA, $rB", IntDivD,
668 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
669 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
670 "divw $rT, $rA, $rB", IntDivW,
671 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
672 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
673 "divwu $rT, $rA, $rB", IntDivW,
674 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
675 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
676 "mulhd $rT, $rA, $rB", IntMulHW,
677 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
678 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
679 "mulhdu $rT, $rA, $rB", IntMulHWU,
680 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
681 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
682 "mulhw $rT, $rA, $rB", IntMulHW,
683 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
684 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
685 "mulhwu $rT, $rA, $rB", IntMulHWU,
686 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
687 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
688 "mulld $rT, $rA, $rB", IntMulHD,
689 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
690 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
691 "mullw $rT, $rA, $rB", IntMulHW,
692 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
693 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
694 "subf $rT, $rA, $rB", IntGeneral,
695 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
696 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
697 "subfc $rT, $rA, $rB", IntGeneral,
699 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
700 "subfe $rT, $rA, $rB", IntGeneral,
702 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
703 "addme $rT, $rA", IntGeneral,
705 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
706 "addze $rT, $rA", IntGeneral,
708 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
709 "neg $rT, $rA", IntGeneral,
710 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
711 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
712 "subfze $rT, $rA", IntGeneral,
715 // A-Form instructions. Most of the instructions executed in the FPU are of
718 def FMADD : AForm_1<63, 29,
719 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
720 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
721 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
723 def FMADDS : AForm_1<59, 29,
724 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
725 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
726 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
728 def FMSUB : AForm_1<63, 28,
729 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
730 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
731 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
733 def FMSUBS : AForm_1<59, 28,
734 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
735 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
736 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
738 def FNMADD : AForm_1<63, 31,
739 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
740 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
741 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
743 def FNMADDS : AForm_1<59, 31,
744 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
745 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
746 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
748 def FNMSUB : AForm_1<63, 30,
749 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
750 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
751 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
753 def FNMSUBS : AForm_1<59, 30,
754 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
755 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
756 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
758 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
759 // having 4 of these, force the comparison to always be an 8-byte double (code
760 // should use an FMRSD if the input comparison value really wants to be a float)
761 // and 4/8 byte forms for the result and operand type..
762 def FSELD : AForm_1<63, 23,
763 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
764 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
765 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
766 def FSELS : AForm_1<63, 23,
767 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
768 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
769 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
770 def FADD : AForm_2<63, 21,
771 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
772 "fadd $FRT, $FRA, $FRB", FPGeneral,
773 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
774 def FADDS : AForm_2<59, 21,
775 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
776 "fadds $FRT, $FRA, $FRB", FPGeneral,
777 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
778 def FDIV : AForm_2<63, 18,
779 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
780 "fdiv $FRT, $FRA, $FRB", FPDivD,
781 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
782 def FDIVS : AForm_2<59, 18,
783 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
784 "fdivs $FRT, $FRA, $FRB", FPDivS,
785 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
786 def FMUL : AForm_3<63, 25,
787 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
788 "fmul $FRT, $FRA, $FRB", FPFused,
789 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
790 def FMULS : AForm_3<59, 25,
791 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
792 "fmuls $FRT, $FRA, $FRB", FPGeneral,
793 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
794 def FSUB : AForm_2<63, 20,
795 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
796 "fsub $FRT, $FRA, $FRB", FPGeneral,
797 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
798 def FSUBS : AForm_2<59, 20,
799 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
800 "fsubs $FRT, $FRA, $FRB", FPGeneral,
801 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
803 // M-Form instructions. rotate and mask instructions.
805 let isTwoAddress = 1, isCommutable = 1 in {
806 // RLWIMI can be commuted if the rotate amount is zero.
807 def RLWIMI : MForm_2<20,
808 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
809 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
811 def RLDIMI : MDForm_1<30, 3,
812 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
813 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
816 def RLWINM : MForm_2<21,
817 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
818 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
820 def RLWINMo : MForm_2<21,
821 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
822 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
824 def RLWNM : MForm_2<23,
825 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
826 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
829 // MD-Form instructions. 64 bit rotate instructions.
831 def RLDICL : MDForm_1<30, 0,
832 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
833 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
835 def RLDICR : MDForm_1<30, 1,
836 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
837 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
840 // VA-Form instructions. 3-input AltiVec ops.
841 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
842 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
843 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
845 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
846 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
847 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA,
851 // VX-Form instructions. AltiVec arithmetic ops.
852 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
853 "vaddfp $vD, $vA, $vB", VecFP,
854 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
855 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
856 "vcfsx $vD, $vB, $UIMM", VecFP,
858 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
859 "vcfux $vD, $vB, $UIMM", VecFP,
861 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
862 "vctsxs $vD, $vB, $UIMM", VecFP,
864 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
865 "vctuxs $vD, $vB, $UIMM", VecFP,
867 def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
868 "vexptefp $vD, $vB", VecFP,
870 def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
871 "vlogefp $vD, $vB", VecFP,
873 def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
874 "vmaxfp $vD, $vA, $vB", VecFP,
876 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
877 "vminfp $vD, $vA, $vB", VecFP,
879 def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
880 "vrefp $vD, $vB", VecFP,
882 def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
883 "vrfim $vD, $vB", VecFP,
885 def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
886 "vrfin $vD, $vB", VecFP,
888 def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
889 "vrfip $vD, $vB", VecFP,
891 def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
892 "vrfiz $vD, $vB", VecFP,
894 def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
895 "vrsqrtefp $vD, $vB", VecFP,
897 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
898 "vsubfp $vD, $vA, $vB", VecFP,
899 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
900 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
901 "vxor $vD, $vA, $vB", VecFP,
904 // VX-Form Pseudo Instructions
906 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
907 "vxor $vD, $vD, $vD", VecFP,
911 //===----------------------------------------------------------------------===//
912 // PowerPC Instruction Patterns
915 // Arbitrary immediate support. Implement in terms of LIS/ORI.
916 def : Pat<(i32 imm:$imm),
917 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
919 // Implement the 'not' operation with the NOR instruction.
920 def NOT : Pat<(not GPRC:$in),
921 (NOR GPRC:$in, GPRC:$in)>;
923 // ADD an arbitrary immediate.
924 def : Pat<(add GPRC:$in, imm:$imm),
925 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
926 // OR an arbitrary immediate.
927 def : Pat<(or GPRC:$in, imm:$imm),
928 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
929 // XOR an arbitrary immediate.
930 def : Pat<(xor GPRC:$in, imm:$imm),
931 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
932 def : Pat<(or (shl GPRC:$rS, GPRC:$rB),
933 (srl GPRC:$rS, (sub 32, GPRC:$rB))),
934 (RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
936 def : Pat<(zext GPRC:$in),
937 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
938 def : Pat<(anyext GPRC:$in),
939 (OR4To8 GPRC:$in, GPRC:$in)>;
940 def : Pat<(trunc G8RC:$in),
941 (OR8To4 G8RC:$in, G8RC:$in)>;
944 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
945 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
946 def : Pat<(shl G8RC:$in, (i64 imm:$imm)),
947 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
949 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
950 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
951 def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
952 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
954 // Hi and Lo for Darwin Global Addresses.
955 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
956 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
957 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
958 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
959 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
960 (ADDIS GPRC:$in, tglobaladdr:$g)>;
961 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
962 (ADDIS GPRC:$in, tconstpool:$g)>;
964 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
965 (VMADDFP VRRC:$vA, (V_SET0), VRRC:$vB)>;
967 // Fused multiply add and multiply sub for packed float. These are represented
968 // separately from the real instructions above, for operations that must have
969 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
970 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
971 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
972 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
973 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
975 // Standard shifts. These are represented separately from the real shifts above
976 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
978 def : Pat<(sra GPRC:$rS, GPRC:$rB),
979 (SRAW GPRC:$rS, GPRC:$rB)>;
980 def : Pat<(srl GPRC:$rS, GPRC:$rB),
981 (SRW GPRC:$rS, GPRC:$rB)>;
982 def : Pat<(shl GPRC:$rS, GPRC:$rB),
983 (SLW GPRC:$rS, GPRC:$rB)>;
985 // Same as above, but using a temporary. FIXME: implement temporaries :)
987 def : Pattern<(xor GPRC:$in, imm:$imm),
988 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
989 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
992 //===----------------------------------------------------------------------===//
993 // PowerPCInstrInfo Definition
995 def PowerPCInstrInfo : InstrInfo {
998 let TSFlagsFields = [ "VMX", "PPC64" ];
999 let TSFlagsShifts = [ 0, 1 ];
1001 let isLittleEndianEncoding = 1;