1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
60 def tocentry32 : Operand<iPTR> {
61 let MIOperandInfo = (ops i32imm:$imm);
64 //===----------------------------------------------------------------------===//
65 // PowerPC specific DAG Nodes.
68 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
69 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
71 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
72 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
73 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
74 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
75 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
76 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
77 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
78 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
79 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
80 [SDNPHasChain, SDNPMayStore]>;
81 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
82 [SDNPHasChain, SDNPMayLoad]>;
83 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
84 [SDNPHasChain, SDNPMayLoad]>;
86 // Extract FPSCR (not modeled at the DAG level).
87 def PPCmffs : SDNode<"PPCISD::MFFS",
88 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
90 // Perform FADD in round-to-zero mode.
91 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
94 def PPCfsel : SDNode<"PPCISD::FSEL",
95 // Type constraint for fsel.
96 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
97 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
99 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
100 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
101 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
102 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
103 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
105 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
107 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
108 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
110 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
111 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
112 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
113 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
114 def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
115 SDTypeProfile<1, 3, [
116 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
117 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
118 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
119 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
120 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
121 def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
122 SDTypeProfile<1, 3, [
123 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
124 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
125 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
126 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
128 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
130 def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
132 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
133 // amounts. These nodes are generated by the multi-precision shift code.
134 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
135 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
136 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
138 // These are target-independent nodes, but have target-specific formats.
139 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
140 [SDNPHasChain, SDNPOutGlue]>;
141 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
142 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
144 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
145 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
148 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
149 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
151 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
152 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
153 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
154 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
156 def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
157 SDTypeProfile<0, 1, []>,
158 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
161 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
162 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
164 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
165 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
167 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
168 SDTypeProfile<1, 1, [SDTCisInt<0>,
170 [SDNPHasChain, SDNPSideEffect]>;
171 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
172 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
173 [SDNPHasChain, SDNPSideEffect]>;
175 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
176 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
177 [SDNPHasChain, SDNPSideEffect]>;
179 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
180 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
182 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
183 [SDNPHasChain, SDNPOptInGlue]>;
185 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
186 [SDNPHasChain, SDNPMayLoad]>;
187 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
188 [SDNPHasChain, SDNPMayStore]>;
190 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
191 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
192 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
193 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
194 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
196 // Instructions to support atomic operations
197 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
198 [SDNPHasChain, SDNPMayLoad]>;
199 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
200 [SDNPHasChain, SDNPMayStore]>;
202 // Instructions to support medium and large code model
203 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
204 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
205 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
208 // Instructions to support dynamic alloca.
209 def SDTDynOp : SDTypeProfile<1, 2, []>;
210 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
212 //===----------------------------------------------------------------------===//
213 // PowerPC specific transformation functions and pattern fragments.
216 def SHL32 : SDNodeXForm<imm, [{
217 // Transformation function: 31 - imm
218 return getI32Imm(31 - N->getZExtValue());
221 def SRL32 : SDNodeXForm<imm, [{
222 // Transformation function: 32 - imm
223 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
226 def LO16 : SDNodeXForm<imm, [{
227 // Transformation function: get the low 16 bits.
228 return getI32Imm((unsigned short)N->getZExtValue());
231 def HI16 : SDNodeXForm<imm, [{
232 // Transformation function: shift the immediate value down into the low bits.
233 return getI32Imm((unsigned)N->getZExtValue() >> 16);
236 def HA16 : SDNodeXForm<imm, [{
237 // Transformation function: shift the immediate value down into the low bits.
238 signed int Val = N->getZExtValue();
239 return getI32Imm((Val - (signed short)Val) >> 16);
241 def MB : SDNodeXForm<imm, [{
242 // Transformation function: get the start bit of a mask
244 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
245 return getI32Imm(mb);
248 def ME : SDNodeXForm<imm, [{
249 // Transformation function: get the end bit of a mask
251 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
252 return getI32Imm(me);
254 def maskimm32 : PatLeaf<(imm), [{
255 // maskImm predicate - True if immediate is a run of ones.
257 if (N->getValueType(0) == MVT::i32)
258 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
263 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
264 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
265 // sign extended field. Used by instructions like 'addi'.
266 return (int32_t)Imm == (short)Imm;
268 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
269 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
270 // sign extended field. Used by instructions like 'addi'.
271 return (int64_t)Imm == (short)Imm;
273 def immZExt16 : PatLeaf<(imm), [{
274 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
275 // field. Used by instructions like 'ori'.
276 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
279 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
280 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
281 // identical in 32-bit mode, but in 64-bit mode, they return true if the
282 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
284 def imm16ShiftedZExt : PatLeaf<(imm), [{
285 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
286 // immediate are set. Used by instructions like 'xoris'.
287 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
290 def imm16ShiftedSExt : PatLeaf<(imm), [{
291 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
292 // immediate are set. Used by instructions like 'addis'. Identical to
293 // imm16ShiftedZExt in 32-bit mode.
294 if (N->getZExtValue() & 0xFFFF) return false;
295 if (N->getValueType(0) == MVT::i32)
297 // For 64-bit, make sure it is sext right.
298 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
301 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
302 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
303 // zero extended field.
304 return isUInt<32>(Imm);
307 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
308 // restricted memrix (4-aligned) constants are alignment sensitive. If these
309 // offsets are hidden behind TOC entries than the values of the lower-order
310 // bits cannot be checked directly. As a result, we need to also incorporate
311 // an alignment check into the relevant patterns.
313 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
314 return cast<LoadSDNode>(N)->getAlignment() >= 4;
316 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
317 (store node:$val, node:$ptr), [{
318 return cast<StoreSDNode>(N)->getAlignment() >= 4;
320 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
321 return cast<LoadSDNode>(N)->getAlignment() >= 4;
323 def aligned4pre_store : PatFrag<
324 (ops node:$val, node:$base, node:$offset),
325 (pre_store node:$val, node:$base, node:$offset), [{
326 return cast<StoreSDNode>(N)->getAlignment() >= 4;
329 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
330 return cast<LoadSDNode>(N)->getAlignment() < 4;
332 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
333 (store node:$val, node:$ptr), [{
334 return cast<StoreSDNode>(N)->getAlignment() < 4;
336 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
337 return cast<LoadSDNode>(N)->getAlignment() < 4;
340 //===----------------------------------------------------------------------===//
341 // PowerPC Flag Definitions.
343 class isPPC64 { bit PPC64 = 1; }
344 class isDOT { bit RC = 1; }
346 class RegConstraint<string C> {
347 string Constraints = C;
349 class NoEncode<string E> {
350 string DisableEncoding = E;
354 //===----------------------------------------------------------------------===//
355 // PowerPC Operand Definitions.
357 // In the default PowerPC assembler syntax, registers are specified simply
358 // by number, so they cannot be distinguished from immediate values (without
359 // looking at the opcode). This means that the default operand matching logic
360 // for the asm parser does not work, and we need to specify custom matchers.
361 // Since those can only be specified with RegisterOperand classes and not
362 // directly on the RegisterClass, all instructions patterns used by the asm
363 // parser need to use a RegisterOperand (instead of a RegisterClass) for
364 // all their register operands.
365 // For this purpose, we define one RegisterOperand for each RegisterClass,
366 // using the same name as the class, just in lower case.
368 def PPCRegGPRCAsmOperand : AsmOperandClass {
369 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
371 def gprc : RegisterOperand<GPRC> {
372 let ParserMatchClass = PPCRegGPRCAsmOperand;
374 def PPCRegG8RCAsmOperand : AsmOperandClass {
375 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
377 def g8rc : RegisterOperand<G8RC> {
378 let ParserMatchClass = PPCRegG8RCAsmOperand;
380 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
381 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
383 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
384 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
386 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
387 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
389 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
390 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
392 def PPCRegF8RCAsmOperand : AsmOperandClass {
393 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
395 def f8rc : RegisterOperand<F8RC> {
396 let ParserMatchClass = PPCRegF8RCAsmOperand;
398 def PPCRegF4RCAsmOperand : AsmOperandClass {
399 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
401 def f4rc : RegisterOperand<F4RC> {
402 let ParserMatchClass = PPCRegF4RCAsmOperand;
404 def PPCRegVRRCAsmOperand : AsmOperandClass {
405 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
407 def vrrc : RegisterOperand<VRRC> {
408 let ParserMatchClass = PPCRegVRRCAsmOperand;
410 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
411 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
413 def crbitrc : RegisterOperand<CRBITRC> {
414 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
416 def PPCRegCRRCAsmOperand : AsmOperandClass {
417 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
419 def crrc : RegisterOperand<CRRC> {
420 let ParserMatchClass = PPCRegCRRCAsmOperand;
423 def PPCU2ImmAsmOperand : AsmOperandClass {
424 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
425 let RenderMethod = "addImmOperands";
427 def u2imm : Operand<i32> {
428 let PrintMethod = "printU2ImmOperand";
429 let ParserMatchClass = PPCU2ImmAsmOperand;
432 def PPCU4ImmAsmOperand : AsmOperandClass {
433 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
434 let RenderMethod = "addImmOperands";
436 def u4imm : Operand<i32> {
437 let PrintMethod = "printU4ImmOperand";
438 let ParserMatchClass = PPCU4ImmAsmOperand;
440 def PPCS5ImmAsmOperand : AsmOperandClass {
441 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
442 let RenderMethod = "addImmOperands";
444 def s5imm : Operand<i32> {
445 let PrintMethod = "printS5ImmOperand";
446 let ParserMatchClass = PPCS5ImmAsmOperand;
447 let DecoderMethod = "decodeSImmOperand<5>";
449 def PPCU5ImmAsmOperand : AsmOperandClass {
450 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
451 let RenderMethod = "addImmOperands";
453 def u5imm : Operand<i32> {
454 let PrintMethod = "printU5ImmOperand";
455 let ParserMatchClass = PPCU5ImmAsmOperand;
456 let DecoderMethod = "decodeUImmOperand<5>";
458 def PPCU6ImmAsmOperand : AsmOperandClass {
459 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
460 let RenderMethod = "addImmOperands";
462 def u6imm : Operand<i32> {
463 let PrintMethod = "printU6ImmOperand";
464 let ParserMatchClass = PPCU6ImmAsmOperand;
465 let DecoderMethod = "decodeUImmOperand<6>";
467 def PPCS16ImmAsmOperand : AsmOperandClass {
468 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
469 let RenderMethod = "addS16ImmOperands";
471 def s16imm : Operand<i32> {
472 let PrintMethod = "printS16ImmOperand";
473 let EncoderMethod = "getImm16Encoding";
474 let ParserMatchClass = PPCS16ImmAsmOperand;
475 let DecoderMethod = "decodeSImmOperand<16>";
477 def PPCU16ImmAsmOperand : AsmOperandClass {
478 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
479 let RenderMethod = "addU16ImmOperands";
481 def u16imm : Operand<i32> {
482 let PrintMethod = "printU16ImmOperand";
483 let EncoderMethod = "getImm16Encoding";
484 let ParserMatchClass = PPCU16ImmAsmOperand;
485 let DecoderMethod = "decodeUImmOperand<16>";
487 def PPCS17ImmAsmOperand : AsmOperandClass {
488 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
489 let RenderMethod = "addS16ImmOperands";
491 def s17imm : Operand<i32> {
492 // This operand type is used for addis/lis to allow the assembler parser
493 // to accept immediates in the range -65536..65535 for compatibility with
494 // the GNU assembler. The operand is treated as 16-bit otherwise.
495 let PrintMethod = "printS16ImmOperand";
496 let EncoderMethod = "getImm16Encoding";
497 let ParserMatchClass = PPCS17ImmAsmOperand;
498 let DecoderMethod = "decodeSImmOperand<16>";
500 def PPCDirectBrAsmOperand : AsmOperandClass {
501 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
502 let RenderMethod = "addBranchTargetOperands";
504 def directbrtarget : Operand<OtherVT> {
505 let PrintMethod = "printBranchOperand";
506 let EncoderMethod = "getDirectBrEncoding";
507 let ParserMatchClass = PPCDirectBrAsmOperand;
509 def absdirectbrtarget : Operand<OtherVT> {
510 let PrintMethod = "printAbsBranchOperand";
511 let EncoderMethod = "getAbsDirectBrEncoding";
512 let ParserMatchClass = PPCDirectBrAsmOperand;
514 def PPCCondBrAsmOperand : AsmOperandClass {
515 let Name = "CondBr"; let PredicateMethod = "isCondBr";
516 let RenderMethod = "addBranchTargetOperands";
518 def condbrtarget : Operand<OtherVT> {
519 let PrintMethod = "printBranchOperand";
520 let EncoderMethod = "getCondBrEncoding";
521 let ParserMatchClass = PPCCondBrAsmOperand;
523 def abscondbrtarget : Operand<OtherVT> {
524 let PrintMethod = "printAbsBranchOperand";
525 let EncoderMethod = "getAbsCondBrEncoding";
526 let ParserMatchClass = PPCCondBrAsmOperand;
528 def calltarget : Operand<iPTR> {
529 let PrintMethod = "printBranchOperand";
530 let EncoderMethod = "getDirectBrEncoding";
531 let ParserMatchClass = PPCDirectBrAsmOperand;
533 def abscalltarget : Operand<iPTR> {
534 let PrintMethod = "printAbsBranchOperand";
535 let EncoderMethod = "getAbsDirectBrEncoding";
536 let ParserMatchClass = PPCDirectBrAsmOperand;
538 def PPCCRBitMaskOperand : AsmOperandClass {
539 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
541 def crbitm: Operand<i8> {
542 let PrintMethod = "printcrbitm";
543 let EncoderMethod = "get_crbitm_encoding";
544 let DecoderMethod = "decodeCRBitMOperand";
545 let ParserMatchClass = PPCCRBitMaskOperand;
548 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
549 def PPCRegGxRCNoR0Operand : AsmOperandClass {
550 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
552 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
553 let ParserMatchClass = PPCRegGxRCNoR0Operand;
555 // A version of ptr_rc usable with the asm parser.
556 def PPCRegGxRCOperand : AsmOperandClass {
557 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
559 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
560 let ParserMatchClass = PPCRegGxRCOperand;
563 def PPCDispRIOperand : AsmOperandClass {
564 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
565 let RenderMethod = "addS16ImmOperands";
567 def dispRI : Operand<iPTR> {
568 let ParserMatchClass = PPCDispRIOperand;
570 def PPCDispRIXOperand : AsmOperandClass {
571 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
572 let RenderMethod = "addImmOperands";
574 def dispRIX : Operand<iPTR> {
575 let ParserMatchClass = PPCDispRIXOperand;
577 def PPCDispSPE8Operand : AsmOperandClass {
578 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
579 let RenderMethod = "addImmOperands";
581 def dispSPE8 : Operand<iPTR> {
582 let ParserMatchClass = PPCDispSPE8Operand;
584 def PPCDispSPE4Operand : AsmOperandClass {
585 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
586 let RenderMethod = "addImmOperands";
588 def dispSPE4 : Operand<iPTR> {
589 let ParserMatchClass = PPCDispSPE4Operand;
591 def PPCDispSPE2Operand : AsmOperandClass {
592 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
593 let RenderMethod = "addImmOperands";
595 def dispSPE2 : Operand<iPTR> {
596 let ParserMatchClass = PPCDispSPE2Operand;
599 def memri : Operand<iPTR> {
600 let PrintMethod = "printMemRegImm";
601 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
602 let EncoderMethod = "getMemRIEncoding";
603 let DecoderMethod = "decodeMemRIOperands";
605 def memrr : Operand<iPTR> {
606 let PrintMethod = "printMemRegReg";
607 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
609 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
610 let PrintMethod = "printMemRegImm";
611 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
612 let EncoderMethod = "getMemRIXEncoding";
613 let DecoderMethod = "decodeMemRIXOperands";
615 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
616 let PrintMethod = "printMemRegImm";
617 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
618 let EncoderMethod = "getSPE8DisEncoding";
620 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
621 let PrintMethod = "printMemRegImm";
622 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
623 let EncoderMethod = "getSPE4DisEncoding";
625 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
626 let PrintMethod = "printMemRegImm";
627 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
628 let EncoderMethod = "getSPE2DisEncoding";
631 // A single-register address. This is used with the SjLj
632 // pseudo-instructions.
633 def memr : Operand<iPTR> {
634 let MIOperandInfo = (ops ptr_rc:$ptrreg);
636 def PPCTLSRegOperand : AsmOperandClass {
637 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
638 let RenderMethod = "addTLSRegOperands";
640 def tlsreg32 : Operand<i32> {
641 let EncoderMethod = "getTLSRegEncoding";
642 let ParserMatchClass = PPCTLSRegOperand;
644 def tlsgd32 : Operand<i32> {}
645 def tlscall32 : Operand<i32> {
646 let PrintMethod = "printTLSCall";
647 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
648 let EncoderMethod = "getTLSCallEncoding";
651 // PowerPC Predicate operand.
652 def pred : Operand<OtherVT> {
653 let PrintMethod = "printPredicateOperand";
654 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
657 // Define PowerPC specific addressing mode.
658 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
659 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
660 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
661 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
663 // The address in a single register. This is used with the SjLj
664 // pseudo-instructions.
665 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
667 /// This is just the offset part of iaddr, used for preinc.
668 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
670 //===----------------------------------------------------------------------===//
671 // PowerPC Instruction Predicate Definitions.
672 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
673 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
674 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
675 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
676 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
677 def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
678 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
679 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
680 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
681 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
682 def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
683 //===----------------------------------------------------------------------===//
684 // PowerPC Multiclass Definitions.
686 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
687 string asmbase, string asmstr, InstrItinClass itin,
689 let BaseName = asmbase in {
690 def NAME : XForm_6<opcode, xo, OOL, IOL,
691 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
692 pattern>, RecFormRel;
694 def o : XForm_6<opcode, xo, OOL, IOL,
695 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
696 []>, isDOT, RecFormRel;
700 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
701 string asmbase, string asmstr, InstrItinClass itin,
703 let BaseName = asmbase in {
704 let Defs = [CARRY] in
705 def NAME : XForm_6<opcode, xo, OOL, IOL,
706 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
707 pattern>, RecFormRel;
708 let Defs = [CARRY, CR0] in
709 def o : XForm_6<opcode, xo, OOL, IOL,
710 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
711 []>, isDOT, RecFormRel;
715 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
716 string asmbase, string asmstr, InstrItinClass itin,
718 let BaseName = asmbase in {
719 let Defs = [CARRY] in
720 def NAME : XForm_10<opcode, xo, OOL, IOL,
721 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
722 pattern>, RecFormRel;
723 let Defs = [CARRY, CR0] in
724 def o : XForm_10<opcode, xo, OOL, IOL,
725 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
726 []>, isDOT, RecFormRel;
730 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
731 string asmbase, string asmstr, InstrItinClass itin,
733 let BaseName = asmbase in {
734 def NAME : XForm_11<opcode, xo, OOL, IOL,
735 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
736 pattern>, RecFormRel;
738 def o : XForm_11<opcode, xo, OOL, IOL,
739 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
740 []>, isDOT, RecFormRel;
744 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
745 string asmbase, string asmstr, InstrItinClass itin,
747 let BaseName = asmbase in {
748 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
749 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
750 pattern>, RecFormRel;
752 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
753 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
754 []>, isDOT, RecFormRel;
758 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
759 string asmbase, string asmstr, InstrItinClass itin,
761 let BaseName = asmbase in {
762 let Defs = [CARRY] in
763 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
764 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
765 pattern>, RecFormRel;
766 let Defs = [CARRY, CR0] in
767 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
768 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
769 []>, isDOT, RecFormRel;
773 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
774 string asmbase, string asmstr, InstrItinClass itin,
776 let BaseName = asmbase in {
777 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
778 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
779 pattern>, RecFormRel;
781 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
782 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
783 []>, isDOT, RecFormRel;
787 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
788 string asmbase, string asmstr, InstrItinClass itin,
790 let BaseName = asmbase in {
791 let Defs = [CARRY] in
792 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
793 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
794 pattern>, RecFormRel;
795 let Defs = [CARRY, CR0] in
796 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
797 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
798 []>, isDOT, RecFormRel;
802 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
803 string asmbase, string asmstr, InstrItinClass itin,
805 let BaseName = asmbase in {
806 def NAME : MForm_2<opcode, OOL, IOL,
807 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
808 pattern>, RecFormRel;
810 def o : MForm_2<opcode, OOL, IOL,
811 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
812 []>, isDOT, RecFormRel;
816 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
817 string asmbase, string asmstr, InstrItinClass itin,
819 let BaseName = asmbase in {
820 def NAME : MDForm_1<opcode, xo, OOL, IOL,
821 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
822 pattern>, RecFormRel;
824 def o : MDForm_1<opcode, xo, OOL, IOL,
825 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
826 []>, isDOT, RecFormRel;
830 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
831 string asmbase, string asmstr, InstrItinClass itin,
833 let BaseName = asmbase in {
834 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
835 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
836 pattern>, RecFormRel;
838 def o : MDSForm_1<opcode, xo, OOL, IOL,
839 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
840 []>, isDOT, RecFormRel;
844 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
845 string asmbase, string asmstr, InstrItinClass itin,
847 let BaseName = asmbase in {
848 let Defs = [CARRY] in
849 def NAME : XSForm_1<opcode, xo, OOL, IOL,
850 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
851 pattern>, RecFormRel;
852 let Defs = [CARRY, CR0] in
853 def o : XSForm_1<opcode, xo, OOL, IOL,
854 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
855 []>, isDOT, RecFormRel;
859 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
860 string asmbase, string asmstr, InstrItinClass itin,
862 let BaseName = asmbase in {
863 def NAME : XForm_26<opcode, xo, OOL, IOL,
864 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
865 pattern>, RecFormRel;
867 def o : XForm_26<opcode, xo, OOL, IOL,
868 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
869 []>, isDOT, RecFormRel;
873 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
874 string asmbase, string asmstr, InstrItinClass itin,
876 let BaseName = asmbase in {
877 def NAME : XForm_28<opcode, xo, OOL, IOL,
878 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
879 pattern>, RecFormRel;
881 def o : XForm_28<opcode, xo, OOL, IOL,
882 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
883 []>, isDOT, RecFormRel;
887 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
888 string asmbase, string asmstr, InstrItinClass itin,
890 let BaseName = asmbase in {
891 def NAME : AForm_1<opcode, xo, OOL, IOL,
892 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
893 pattern>, RecFormRel;
895 def o : AForm_1<opcode, xo, OOL, IOL,
896 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
897 []>, isDOT, RecFormRel;
901 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
902 string asmbase, string asmstr, InstrItinClass itin,
904 let BaseName = asmbase in {
905 def NAME : AForm_2<opcode, xo, OOL, IOL,
906 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
907 pattern>, RecFormRel;
909 def o : AForm_2<opcode, xo, OOL, IOL,
910 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
911 []>, isDOT, RecFormRel;
915 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
916 string asmbase, string asmstr, InstrItinClass itin,
918 let BaseName = asmbase in {
919 def NAME : AForm_3<opcode, xo, OOL, IOL,
920 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
921 pattern>, RecFormRel;
923 def o : AForm_3<opcode, xo, OOL, IOL,
924 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
925 []>, isDOT, RecFormRel;
929 //===----------------------------------------------------------------------===//
930 // PowerPC Instruction Definitions.
932 // Pseudo-instructions:
934 let hasCtrlDep = 1 in {
935 let Defs = [R1], Uses = [R1] in {
936 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
937 [(callseq_start timm:$amt)]>;
938 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
939 [(callseq_end timm:$amt1, timm:$amt2)]>;
942 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
943 "UPDATE_VRSAVE $rD, $rS", []>;
946 let Defs = [R1], Uses = [R1] in
947 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
949 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
951 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
952 // instruction selection into a branch sequence.
953 let usesCustomInserter = 1, // Expanded after instruction selection.
954 PPC970_Single = 1 in {
955 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
956 // because either operand might become the first operand in an isel, and
957 // that operand cannot be r0.
958 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
959 gprc_nor0:$T, gprc_nor0:$F,
960 i32imm:$BROPC), "#SELECT_CC_I4",
962 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
963 g8rc_nox0:$T, g8rc_nox0:$F,
964 i32imm:$BROPC), "#SELECT_CC_I8",
966 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
967 i32imm:$BROPC), "#SELECT_CC_F4",
969 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
970 i32imm:$BROPC), "#SELECT_CC_F8",
972 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
973 i32imm:$BROPC), "#SELECT_CC_VRRC",
976 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
977 // register bit directly.
978 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
979 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
980 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
981 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
982 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
983 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
984 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
985 f4rc:$T, f4rc:$F), "#SELECT_F4",
986 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
987 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
988 f8rc:$T, f8rc:$F), "#SELECT_F8",
989 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
990 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
991 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
993 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
996 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
997 // scavenge a register for it.
998 let mayStore = 1 in {
999 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1001 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1002 "#SPILL_CRBIT", []>;
1005 // RESTORE_CR - Indicate that we're restoring the CR register (previously
1006 // spilled), so we'll need to scavenge a register for it.
1007 let mayLoad = 1 in {
1008 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1010 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1011 "#RESTORE_CRBIT", []>;
1014 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1015 let isReturn = 1, Uses = [LR, RM] in
1016 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1017 [(retflag)]>, Requires<[In32BitMode]>;
1018 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1019 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1022 let isCodeGenOnly = 1 in {
1023 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1024 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1027 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1028 "bcctr 12, $bi, 0", IIC_BrB, []>;
1029 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1030 "bcctr 4, $bi, 0", IIC_BrB, []>;
1036 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1039 def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1042 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1043 let isBarrier = 1 in {
1044 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1047 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1048 "ba $dst", IIC_BrB, []>;
1051 // BCC represents an arbitrary conditional branch on a predicate.
1052 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1053 // a two-value operand where a dag node expects two operands. :(
1054 let isCodeGenOnly = 1 in {
1055 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1056 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1057 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1058 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1059 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1061 let isReturn = 1, Uses = [LR, RM] in
1062 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1063 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1066 let isCodeGenOnly = 1 in {
1067 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1068 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1069 "bc 12, $bi, $dst">;
1071 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1072 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1075 let isReturn = 1, Uses = [LR, RM] in
1076 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1077 "bclr 12, $bi, 0", IIC_BrB, []>;
1078 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1079 "bclr 4, $bi, 0", IIC_BrB, []>;
1082 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1083 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1084 "bdzlr", IIC_BrB, []>;
1085 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1086 "bdnzlr", IIC_BrB, []>;
1087 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1088 "bdzlr+", IIC_BrB, []>;
1089 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1090 "bdnzlr+", IIC_BrB, []>;
1091 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1092 "bdzlr-", IIC_BrB, []>;
1093 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1094 "bdnzlr-", IIC_BrB, []>;
1097 let Defs = [CTR], Uses = [CTR] in {
1098 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1100 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1102 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1104 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1106 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1108 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1110 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1112 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1114 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1116 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1118 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1120 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1125 // The unconditional BCL used by the SjLj setjmp code.
1126 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1127 let Defs = [LR], Uses = [RM] in {
1128 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1129 "bcl 20, 31, $dst">;
1133 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1134 // Convenient aliases for call instructions
1135 let Uses = [RM] in {
1136 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1137 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1138 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1139 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1141 let isCodeGenOnly = 1 in {
1142 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1143 "bl $func", IIC_BrB, []>;
1144 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1145 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1146 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1147 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1149 def BCL : BForm_4<16, 12, 0, 1, (outs),
1150 (ins crbitrc:$bi, condbrtarget:$dst),
1151 "bcl 12, $bi, $dst">;
1152 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1153 (ins crbitrc:$bi, condbrtarget:$dst),
1154 "bcl 4, $bi, $dst">;
1157 let Uses = [CTR, RM] in {
1158 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1159 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1160 Requires<[In32BitMode]>;
1162 let isCodeGenOnly = 1 in {
1163 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1164 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1167 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1168 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1169 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1170 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1173 let Uses = [LR, RM] in {
1174 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1175 "blrl", IIC_BrB, []>;
1177 let isCodeGenOnly = 1 in {
1178 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1179 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1182 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1183 "bclrl 12, $bi, 0", IIC_BrB, []>;
1184 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1185 "bclrl 4, $bi, 0", IIC_BrB, []>;
1188 let Defs = [CTR], Uses = [CTR, RM] in {
1189 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1191 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1193 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1195 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1197 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1199 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1201 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1203 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1205 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1207 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1209 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1211 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1214 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1215 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1216 "bdzlrl", IIC_BrB, []>;
1217 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1218 "bdnzlrl", IIC_BrB, []>;
1219 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1220 "bdzlrl+", IIC_BrB, []>;
1221 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1222 "bdnzlrl+", IIC_BrB, []>;
1223 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1224 "bdzlrl-", IIC_BrB, []>;
1225 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1226 "bdnzlrl-", IIC_BrB, []>;
1230 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1231 def TCRETURNdi :Pseudo< (outs),
1232 (ins calltarget:$dst, i32imm:$offset),
1233 "#TC_RETURNd $dst $offset",
1237 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1238 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1239 "#TC_RETURNa $func $offset",
1240 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1242 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1243 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1244 "#TC_RETURNr $dst $offset",
1248 let isCodeGenOnly = 1 in {
1250 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1251 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1252 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1253 []>, Requires<[In32BitMode]>;
1255 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1256 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1257 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1261 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1262 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1263 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1269 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1271 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1272 "#EH_SJLJ_SETJMP32",
1273 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1274 Requires<[In32BitMode]>;
1275 let isTerminator = 1 in
1276 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1277 "#EH_SJLJ_LONGJMP32",
1278 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1279 Requires<[In32BitMode]>;
1282 let isBranch = 1, isTerminator = 1 in {
1283 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1284 "#EH_SjLj_Setup\t$dst", []>;
1288 let PPC970_Unit = 7 in {
1289 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1290 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1293 // DCB* instructions.
1294 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1295 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1296 PPC970_DGroup_Single;
1297 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1298 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1299 PPC970_DGroup_Single;
1300 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1301 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1302 PPC970_DGroup_Single;
1303 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1304 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1305 PPC970_DGroup_Single;
1306 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1307 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1308 PPC970_DGroup_Single;
1309 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1310 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1311 PPC970_DGroup_Single;
1312 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1313 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1314 PPC970_DGroup_Single;
1315 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1316 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1317 PPC970_DGroup_Single;
1319 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1320 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1322 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1323 (DCBT xoaddr:$dst)>; // data prefetch for loads
1324 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1325 (DCBTST xoaddr:$dst)>; // data prefetch for stores
1326 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1327 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1329 // Atomic operations
1330 let usesCustomInserter = 1 in {
1331 let Defs = [CR0] in {
1332 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1333 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1334 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1335 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1336 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1337 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1338 def ATOMIC_LOAD_AND_I8 : Pseudo<
1339 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1340 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1341 def ATOMIC_LOAD_OR_I8 : Pseudo<
1342 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1343 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1344 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1345 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1346 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1347 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1348 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1349 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1350 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1351 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1352 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1353 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1354 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1355 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1356 def ATOMIC_LOAD_AND_I16 : Pseudo<
1357 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1358 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1359 def ATOMIC_LOAD_OR_I16 : Pseudo<
1360 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1361 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1362 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1363 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1364 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1365 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1366 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1367 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1368 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1369 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1370 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1371 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1372 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1373 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1374 def ATOMIC_LOAD_AND_I32 : Pseudo<
1375 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1376 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1377 def ATOMIC_LOAD_OR_I32 : Pseudo<
1378 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1379 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1380 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1381 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1382 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1383 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1384 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1385 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1387 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1388 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1389 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1390 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1391 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1392 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1393 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1394 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1395 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1397 def ATOMIC_SWAP_I8 : Pseudo<
1398 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1399 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1400 def ATOMIC_SWAP_I16 : Pseudo<
1401 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1402 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1403 def ATOMIC_SWAP_I32 : Pseudo<
1404 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1405 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1409 // Instructions to support atomic operations
1410 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1411 "lwarx $rD, $src", IIC_LdStLWARX,
1412 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1415 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1416 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1417 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1420 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1421 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1423 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1424 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1425 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1426 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1427 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1428 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1429 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1430 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1432 //===----------------------------------------------------------------------===//
1433 // PPC32 Load Instructions.
1436 // Unindexed (r+i) Loads.
1437 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1438 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1439 "lbz $rD, $src", IIC_LdStLoad,
1440 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1441 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1442 "lha $rD, $src", IIC_LdStLHA,
1443 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1444 PPC970_DGroup_Cracked;
1445 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1446 "lhz $rD, $src", IIC_LdStLoad,
1447 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1448 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1449 "lwz $rD, $src", IIC_LdStLoad,
1450 [(set i32:$rD, (load iaddr:$src))]>;
1452 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1453 "lfs $rD, $src", IIC_LdStLFD,
1454 [(set f32:$rD, (load iaddr:$src))]>;
1455 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1456 "lfd $rD, $src", IIC_LdStLFD,
1457 [(set f64:$rD, (load iaddr:$src))]>;
1460 // Unindexed (r+i) Loads with Update (preinc).
1461 let mayLoad = 1, hasSideEffects = 0 in {
1462 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1463 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1464 []>, RegConstraint<"$addr.reg = $ea_result">,
1465 NoEncode<"$ea_result">;
1467 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1468 "lhau $rD, $addr", IIC_LdStLHAU,
1469 []>, RegConstraint<"$addr.reg = $ea_result">,
1470 NoEncode<"$ea_result">;
1472 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1473 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1474 []>, RegConstraint<"$addr.reg = $ea_result">,
1475 NoEncode<"$ea_result">;
1477 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1478 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1479 []>, RegConstraint<"$addr.reg = $ea_result">,
1480 NoEncode<"$ea_result">;
1482 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1483 "lfsu $rD, $addr", IIC_LdStLFDU,
1484 []>, RegConstraint<"$addr.reg = $ea_result">,
1485 NoEncode<"$ea_result">;
1487 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1488 "lfdu $rD, $addr", IIC_LdStLFDU,
1489 []>, RegConstraint<"$addr.reg = $ea_result">,
1490 NoEncode<"$ea_result">;
1493 // Indexed (r+r) Loads with Update (preinc).
1494 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1496 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1497 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1498 NoEncode<"$ea_result">;
1500 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1502 "lhaux $rD, $addr", IIC_LdStLHAUX,
1503 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1504 NoEncode<"$ea_result">;
1506 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1508 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1509 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1510 NoEncode<"$ea_result">;
1512 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1514 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1515 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1516 NoEncode<"$ea_result">;
1518 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1520 "lfsux $rD, $addr", IIC_LdStLFDUX,
1521 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1522 NoEncode<"$ea_result">;
1524 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1526 "lfdux $rD, $addr", IIC_LdStLFDUX,
1527 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1528 NoEncode<"$ea_result">;
1532 // Indexed (r+r) Loads.
1534 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1535 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1536 "lbzx $rD, $src", IIC_LdStLoad,
1537 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1538 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1539 "lhax $rD, $src", IIC_LdStLHA,
1540 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1541 PPC970_DGroup_Cracked;
1542 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1543 "lhzx $rD, $src", IIC_LdStLoad,
1544 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1545 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1546 "lwzx $rD, $src", IIC_LdStLoad,
1547 [(set i32:$rD, (load xaddr:$src))]>;
1550 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1551 "lhbrx $rD, $src", IIC_LdStLoad,
1552 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1553 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1554 "lwbrx $rD, $src", IIC_LdStLoad,
1555 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1557 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1558 "lfsx $frD, $src", IIC_LdStLFD,
1559 [(set f32:$frD, (load xaddr:$src))]>;
1560 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1561 "lfdx $frD, $src", IIC_LdStLFD,
1562 [(set f64:$frD, (load xaddr:$src))]>;
1564 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1565 "lfiwax $frD, $src", IIC_LdStLFD,
1566 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1567 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1568 "lfiwzx $frD, $src", IIC_LdStLFD,
1569 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1573 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1574 "lmw $rD, $src", IIC_LdStLMW, []>;
1576 //===----------------------------------------------------------------------===//
1577 // PPC32 Store Instructions.
1580 // Unindexed (r+i) Stores.
1581 let PPC970_Unit = 2 in {
1582 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1583 "stb $rS, $src", IIC_LdStStore,
1584 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1585 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1586 "sth $rS, $src", IIC_LdStStore,
1587 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1588 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1589 "stw $rS, $src", IIC_LdStStore,
1590 [(store i32:$rS, iaddr:$src)]>;
1591 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1592 "stfs $rS, $dst", IIC_LdStSTFD,
1593 [(store f32:$rS, iaddr:$dst)]>;
1594 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1595 "stfd $rS, $dst", IIC_LdStSTFD,
1596 [(store f64:$rS, iaddr:$dst)]>;
1599 // Unindexed (r+i) Stores with Update (preinc).
1600 let PPC970_Unit = 2, mayStore = 1 in {
1601 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1602 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1603 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1604 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1605 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1606 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1607 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1608 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1609 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1610 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1611 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1612 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1613 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1614 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1615 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1618 // Patterns to match the pre-inc stores. We can't put the patterns on
1619 // the instruction definitions directly as ISel wants the address base
1620 // and offset to be separate operands, not a single complex operand.
1621 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1622 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1623 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1624 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1625 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1626 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1627 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1628 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1629 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1630 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1632 // Indexed (r+r) Stores.
1633 let PPC970_Unit = 2 in {
1634 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1635 "stbx $rS, $dst", IIC_LdStStore,
1636 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1637 PPC970_DGroup_Cracked;
1638 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1639 "sthx $rS, $dst", IIC_LdStStore,
1640 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1641 PPC970_DGroup_Cracked;
1642 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1643 "stwx $rS, $dst", IIC_LdStStore,
1644 [(store i32:$rS, xaddr:$dst)]>,
1645 PPC970_DGroup_Cracked;
1647 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1648 "sthbrx $rS, $dst", IIC_LdStStore,
1649 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1650 PPC970_DGroup_Cracked;
1651 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1652 "stwbrx $rS, $dst", IIC_LdStStore,
1653 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1654 PPC970_DGroup_Cracked;
1656 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1657 "stfiwx $frS, $dst", IIC_LdStSTFD,
1658 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1660 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1661 "stfsx $frS, $dst", IIC_LdStSTFD,
1662 [(store f32:$frS, xaddr:$dst)]>;
1663 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1664 "stfdx $frS, $dst", IIC_LdStSTFD,
1665 [(store f64:$frS, xaddr:$dst)]>;
1668 // Indexed (r+r) Stores with Update (preinc).
1669 let PPC970_Unit = 2, mayStore = 1 in {
1670 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1671 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1672 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1673 PPC970_DGroup_Cracked;
1674 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1675 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1676 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1677 PPC970_DGroup_Cracked;
1678 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1679 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1680 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1681 PPC970_DGroup_Cracked;
1682 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1683 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1684 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1685 PPC970_DGroup_Cracked;
1686 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1687 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1688 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1689 PPC970_DGroup_Cracked;
1692 // Patterns to match the pre-inc stores. We can't put the patterns on
1693 // the instruction definitions directly as ISel wants the address base
1694 // and offset to be separate operands, not a single complex operand.
1695 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1696 (STBUX $rS, $ptrreg, $ptroff)>;
1697 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1698 (STHUX $rS, $ptrreg, $ptroff)>;
1699 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1700 (STWUX $rS, $ptrreg, $ptroff)>;
1701 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1702 (STFSUX $rS, $ptrreg, $ptroff)>;
1703 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1704 (STFDUX $rS, $ptrreg, $ptroff)>;
1707 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1708 "stmw $rS, $dst", IIC_LdStLMW, []>;
1710 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1711 "sync $L", IIC_LdStSync, []>;
1713 let isCodeGenOnly = 1 in {
1714 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1715 "msync", IIC_LdStSync, []> {
1720 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>;
1721 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1722 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1723 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1725 //===----------------------------------------------------------------------===//
1726 // PPC32 Arithmetic Instructions.
1729 let PPC970_Unit = 1 in { // FXU Operations.
1730 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1731 "addi $rD, $rA, $imm", IIC_IntSimple,
1732 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1733 let BaseName = "addic" in {
1734 let Defs = [CARRY] in
1735 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1736 "addic $rD, $rA, $imm", IIC_IntGeneral,
1737 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1738 RecFormRel, PPC970_DGroup_Cracked;
1739 let Defs = [CARRY, CR0] in
1740 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1741 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1742 []>, isDOT, RecFormRel;
1744 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1745 "addis $rD, $rA, $imm", IIC_IntSimple,
1746 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1747 let isCodeGenOnly = 1 in
1748 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1749 "la $rD, $sym($rA)", IIC_IntGeneral,
1750 [(set i32:$rD, (add i32:$rA,
1751 (PPClo tglobaladdr:$sym, 0)))]>;
1752 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1753 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1754 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1755 let Defs = [CARRY] in
1756 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1757 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1758 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1760 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1761 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1762 "li $rD, $imm", IIC_IntSimple,
1763 [(set i32:$rD, imm32SExt16:$imm)]>;
1764 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1765 "lis $rD, $imm", IIC_IntSimple,
1766 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1770 let PPC970_Unit = 1 in { // FXU Operations.
1771 let Defs = [CR0] in {
1772 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1773 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1774 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1776 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1777 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1778 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1781 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1782 "ori $dst, $src1, $src2", IIC_IntSimple,
1783 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1784 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1785 "oris $dst, $src1, $src2", IIC_IntSimple,
1786 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1787 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1788 "xori $dst, $src1, $src2", IIC_IntSimple,
1789 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1790 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1791 "xoris $dst, $src1, $src2", IIC_IntSimple,
1792 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1794 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1796 let isCodeGenOnly = 1 in {
1797 // The POWER6 and POWER7 have special group-terminating nops.
1798 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1799 "ori 1, 1, 0", IIC_IntSimple, []>;
1800 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1801 "ori 2, 2, 0", IIC_IntSimple, []>;
1804 let isCompare = 1, hasSideEffects = 0 in {
1805 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1806 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1807 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1808 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1812 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
1813 let isCommutable = 1 in {
1814 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1815 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1816 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1817 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1818 "and", "$rA, $rS, $rB", IIC_IntSimple,
1819 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1821 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1822 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1823 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1824 let isCommutable = 1 in {
1825 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1826 "or", "$rA, $rS, $rB", IIC_IntSimple,
1827 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1828 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1829 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1830 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1832 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1833 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1834 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1835 let isCommutable = 1 in {
1836 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1837 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1838 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1839 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1840 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1841 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1843 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1844 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1845 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1846 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1847 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1848 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1849 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1850 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1851 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1854 let PPC970_Unit = 1 in { // FXU Operations.
1855 let hasSideEffects = 0 in {
1856 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1857 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1858 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1859 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1860 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1861 [(set i32:$rA, (ctlz i32:$rS))]>;
1862 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1863 "extsb", "$rA, $rS", IIC_IntSimple,
1864 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1865 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1866 "extsh", "$rA, $rS", IIC_IntSimple,
1867 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1869 let isCommutable = 1 in
1870 def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1871 "cmpb $rA, $rS, $rB", IIC_IntGeneral,
1872 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
1874 let isCompare = 1, hasSideEffects = 0 in {
1875 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1876 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1877 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1878 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1881 let PPC970_Unit = 3 in { // FPU Operations.
1882 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1883 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1884 let isCompare = 1, hasSideEffects = 0 in {
1885 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1886 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1887 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1888 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1889 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1892 let Uses = [RM] in {
1893 let hasSideEffects = 0 in {
1894 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1895 "fctiw", "$frD, $frB", IIC_FPGeneral,
1897 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1898 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1899 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1901 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1902 "frsp", "$frD, $frB", IIC_FPGeneral,
1903 [(set f32:$frD, (fround f64:$frB))]>;
1905 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1906 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1907 "frin", "$frD, $frB", IIC_FPGeneral,
1908 [(set f64:$frD, (frnd f64:$frB))]>;
1909 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1910 "frin", "$frD, $frB", IIC_FPGeneral,
1911 [(set f32:$frD, (frnd f32:$frB))]>;
1914 let hasSideEffects = 0 in {
1915 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1916 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1917 "frip", "$frD, $frB", IIC_FPGeneral,
1918 [(set f64:$frD, (fceil f64:$frB))]>;
1919 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1920 "frip", "$frD, $frB", IIC_FPGeneral,
1921 [(set f32:$frD, (fceil f32:$frB))]>;
1922 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1923 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1924 "friz", "$frD, $frB", IIC_FPGeneral,
1925 [(set f64:$frD, (ftrunc f64:$frB))]>;
1926 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1927 "friz", "$frD, $frB", IIC_FPGeneral,
1928 [(set f32:$frD, (ftrunc f32:$frB))]>;
1929 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1930 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1931 "frim", "$frD, $frB", IIC_FPGeneral,
1932 [(set f64:$frD, (ffloor f64:$frB))]>;
1933 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1934 "frim", "$frD, $frB", IIC_FPGeneral,
1935 [(set f32:$frD, (ffloor f32:$frB))]>;
1937 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1938 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1939 [(set f64:$frD, (fsqrt f64:$frB))]>;
1940 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1941 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1942 [(set f32:$frD, (fsqrt f32:$frB))]>;
1947 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1948 /// often coalesced away and we don't want the dispatch group builder to think
1949 /// that they will fill slots (which could cause the load of a LSU reject to
1950 /// sneak into a d-group with a store).
1951 let hasSideEffects = 0 in
1952 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1953 "fmr", "$frD, $frB", IIC_FPGeneral,
1954 []>, // (set f32:$frD, f32:$frB)
1957 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
1958 // These are artificially split into two different forms, for 4/8 byte FP.
1959 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1960 "fabs", "$frD, $frB", IIC_FPGeneral,
1961 [(set f32:$frD, (fabs f32:$frB))]>;
1962 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1963 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1964 "fabs", "$frD, $frB", IIC_FPGeneral,
1965 [(set f64:$frD, (fabs f64:$frB))]>;
1966 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1967 "fnabs", "$frD, $frB", IIC_FPGeneral,
1968 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1969 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1970 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1971 "fnabs", "$frD, $frB", IIC_FPGeneral,
1972 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1973 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1974 "fneg", "$frD, $frB", IIC_FPGeneral,
1975 [(set f32:$frD, (fneg f32:$frB))]>;
1976 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1977 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1978 "fneg", "$frD, $frB", IIC_FPGeneral,
1979 [(set f64:$frD, (fneg f64:$frB))]>;
1981 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1982 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1983 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1984 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1985 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1986 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1987 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1989 // Reciprocal estimates.
1990 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1991 "fre", "$frD, $frB", IIC_FPGeneral,
1992 [(set f64:$frD, (PPCfre f64:$frB))]>;
1993 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1994 "fres", "$frD, $frB", IIC_FPGeneral,
1995 [(set f32:$frD, (PPCfre f32:$frB))]>;
1996 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1997 "frsqrte", "$frD, $frB", IIC_FPGeneral,
1998 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1999 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2000 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2001 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2004 // XL-Form instructions. condition register logical ops.
2006 let hasSideEffects = 0 in
2007 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2008 "mcrf $BF, $BFA", IIC_BrMCR>,
2009 PPC970_DGroup_First, PPC970_Unit_CRU;
2011 // FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2012 // condition-register logical instructions have preferred forms. Specifically,
2013 // it is preferred that the bit specified by the BT field be in the same
2014 // condition register as that specified by the bit BB. We might want to account
2015 // for this via hinting the register allocator and anti-dep breakers, or we
2016 // could constrain the register class to force this constraint and then loosen
2017 // it during register allocation via convertToThreeAddress or some similar
2020 let isCommutable = 1 in {
2021 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
2022 (ins crbitrc:$CRA, crbitrc:$CRB),
2023 "crand $CRD, $CRA, $CRB", IIC_BrCR,
2024 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2026 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2027 (ins crbitrc:$CRA, crbitrc:$CRB),
2028 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2029 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2031 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
2032 (ins crbitrc:$CRA, crbitrc:$CRB),
2033 "cror $CRD, $CRA, $CRB", IIC_BrCR,
2034 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2036 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
2037 (ins crbitrc:$CRA, crbitrc:$CRB),
2038 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2039 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2041 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
2042 (ins crbitrc:$CRA, crbitrc:$CRB),
2043 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2044 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2046 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
2047 (ins crbitrc:$CRA, crbitrc:$CRB),
2048 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2049 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2052 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2053 (ins crbitrc:$CRA, crbitrc:$CRB),
2054 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2055 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2057 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
2058 (ins crbitrc:$CRA, crbitrc:$CRB),
2059 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2060 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2062 let isCodeGenOnly = 1 in {
2063 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2064 "creqv $dst, $dst, $dst", IIC_BrCR,
2065 [(set i1:$dst, 1)]>;
2067 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2068 "crxor $dst, $dst, $dst", IIC_BrCR,
2069 [(set i1:$dst, 0)]>;
2071 let Defs = [CR1EQ], CRD = 6 in {
2072 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2073 "creqv 6, 6, 6", IIC_BrCR,
2076 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2077 "crxor 6, 6, 6", IIC_BrCR,
2082 // XFX-Form instructions. Instructions that deal with SPRs.
2085 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2086 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2087 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2088 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2090 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2091 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2093 // A pseudo-instruction used to implement the read of the 64-bit cycle counter
2094 // on a 32-bit target.
2095 let hasSideEffects = 1, usesCustomInserter = 1 in
2096 def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2099 let Uses = [CTR] in {
2100 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2101 "mfctr $rT", IIC_SprMFSPR>,
2102 PPC970_DGroup_First, PPC970_Unit_FXU;
2104 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2105 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2106 "mtctr $rS", IIC_SprMTSPR>,
2107 PPC970_DGroup_First, PPC970_Unit_FXU;
2109 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2110 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2111 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2112 "mtctr $rS", IIC_SprMTSPR>,
2113 PPC970_DGroup_First, PPC970_Unit_FXU;
2116 let Defs = [LR] in {
2117 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2118 "mtlr $rS", IIC_SprMTSPR>,
2119 PPC970_DGroup_First, PPC970_Unit_FXU;
2121 let Uses = [LR] in {
2122 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2123 "mflr $rT", IIC_SprMFSPR>,
2124 PPC970_DGroup_First, PPC970_Unit_FXU;
2127 let isCodeGenOnly = 1 in {
2128 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2129 // like a GPR on the PPC970. As such, copies in and out have the same
2130 // performance characteristics as an OR instruction.
2131 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2132 "mtspr 256, $rS", IIC_IntGeneral>,
2133 PPC970_DGroup_Single, PPC970_Unit_FXU;
2134 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2135 "mfspr $rT, 256", IIC_IntGeneral>,
2136 PPC970_DGroup_First, PPC970_Unit_FXU;
2138 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2139 (outs VRSAVERC:$reg), (ins gprc:$rS),
2140 "mtspr 256, $rS", IIC_IntGeneral>,
2141 PPC970_DGroup_Single, PPC970_Unit_FXU;
2142 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2143 (ins VRSAVERC:$reg),
2144 "mfspr $rT, 256", IIC_IntGeneral>,
2145 PPC970_DGroup_First, PPC970_Unit_FXU;
2148 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2149 // so we'll need to scavenge a register for it.
2151 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2152 "#SPILL_VRSAVE", []>;
2154 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2155 // spilled), so we'll need to scavenge a register for it.
2157 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2158 "#RESTORE_VRSAVE", []>;
2160 let hasSideEffects = 0 in {
2161 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2162 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2163 PPC970_DGroup_First, PPC970_Unit_CRU;
2165 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2166 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2167 PPC970_MicroCode, PPC970_Unit_CRU;
2169 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2170 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2171 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2172 PPC970_DGroup_First, PPC970_Unit_CRU;
2174 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2175 "mfcr $rT", IIC_SprMFCR>,
2176 PPC970_MicroCode, PPC970_Unit_CRU;
2177 } // hasSideEffects = 0
2179 // Pseudo instruction to perform FADD in round-to-zero mode.
2180 let usesCustomInserter = 1, Uses = [RM] in {
2181 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2182 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2185 // The above pseudo gets expanded to make use of the following instructions
2186 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2187 let Uses = [RM], Defs = [RM] in {
2188 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2189 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2190 PPC970_DGroup_Single, PPC970_Unit_FPU;
2191 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2192 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2193 PPC970_DGroup_Single, PPC970_Unit_FPU;
2194 let isCodeGenOnly = 1 in
2195 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2196 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2197 PPC970_DGroup_Single, PPC970_Unit_FPU;
2199 let Uses = [RM] in {
2200 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2201 "mffs $rT", IIC_IntMFFS,
2202 [(set f64:$rT, (PPCmffs))]>,
2203 PPC970_DGroup_Single, PPC970_Unit_FPU;
2206 def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2207 "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2211 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
2212 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2213 let isCommutable = 1 in
2214 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2215 "add", "$rT, $rA, $rB", IIC_IntSimple,
2216 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2217 let isCodeGenOnly = 1 in
2218 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2219 "add $rT, $rA, $rB", IIC_IntSimple,
2220 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2221 let isCommutable = 1 in
2222 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2223 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2224 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2225 PPC970_DGroup_Cracked;
2227 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2228 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2229 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2230 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2231 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2232 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2233 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2234 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2235 let isCommutable = 1 in {
2236 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2237 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2238 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2239 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2240 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2241 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2242 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2243 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2244 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2246 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2247 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2248 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2249 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2250 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2251 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2252 PPC970_DGroup_Cracked;
2253 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2254 "neg", "$rT, $rA", IIC_IntSimple,
2255 [(set i32:$rT, (ineg i32:$rA))]>;
2256 let Uses = [CARRY] in {
2257 let isCommutable = 1 in
2258 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2259 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2260 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2261 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2262 "addme", "$rT, $rA", IIC_IntGeneral,
2263 [(set i32:$rT, (adde i32:$rA, -1))]>;
2264 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2265 "addze", "$rT, $rA", IIC_IntGeneral,
2266 [(set i32:$rT, (adde i32:$rA, 0))]>;
2267 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2268 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2269 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2270 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2271 "subfme", "$rT, $rA", IIC_IntGeneral,
2272 [(set i32:$rT, (sube -1, i32:$rA))]>;
2273 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2274 "subfze", "$rT, $rA", IIC_IntGeneral,
2275 [(set i32:$rT, (sube 0, i32:$rA))]>;
2279 // A-Form instructions. Most of the instructions executed in the FPU are of
2282 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2283 let Uses = [RM] in {
2284 let isCommutable = 1 in {
2285 defm FMADD : AForm_1r<63, 29,
2286 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2287 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2288 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2289 defm FMADDS : AForm_1r<59, 29,
2290 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2291 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2292 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2293 defm FMSUB : AForm_1r<63, 28,
2294 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2295 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2297 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2298 defm FMSUBS : AForm_1r<59, 28,
2299 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2300 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2302 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2303 defm FNMADD : AForm_1r<63, 31,
2304 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2305 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2307 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2308 defm FNMADDS : AForm_1r<59, 31,
2309 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2310 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2312 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2313 defm FNMSUB : AForm_1r<63, 30,
2314 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2315 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2316 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2317 (fneg f64:$FRB))))]>;
2318 defm FNMSUBS : AForm_1r<59, 30,
2319 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2320 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2321 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2322 (fneg f32:$FRB))))]>;
2325 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2326 // having 4 of these, force the comparison to always be an 8-byte double (code
2327 // should use an FMRSD if the input comparison value really wants to be a float)
2328 // and 4/8 byte forms for the result and operand type..
2329 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2330 defm FSELD : AForm_1r<63, 23,
2331 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2332 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2333 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2334 defm FSELS : AForm_1r<63, 23,
2335 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2336 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2337 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2338 let Uses = [RM] in {
2339 let isCommutable = 1 in {
2340 defm FADD : AForm_2r<63, 21,
2341 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2342 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2343 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2344 defm FADDS : AForm_2r<59, 21,
2345 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2346 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2347 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2349 defm FDIV : AForm_2r<63, 18,
2350 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2351 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2352 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2353 defm FDIVS : AForm_2r<59, 18,
2354 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2355 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2356 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2357 let isCommutable = 1 in {
2358 defm FMUL : AForm_3r<63, 25,
2359 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2360 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2361 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2362 defm FMULS : AForm_3r<59, 25,
2363 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2364 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2365 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2367 defm FSUB : AForm_2r<63, 20,
2368 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2369 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2370 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2371 defm FSUBS : AForm_2r<59, 20,
2372 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2373 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2374 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2378 let hasSideEffects = 0 in {
2379 let PPC970_Unit = 1 in { // FXU Operations.
2381 def ISEL : AForm_4<31, 15,
2382 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2383 "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
2387 let PPC970_Unit = 1 in { // FXU Operations.
2388 // M-Form instructions. rotate and mask instructions.
2390 let isCommutable = 1 in {
2391 // RLWIMI can be commuted if the rotate amount is zero.
2392 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2393 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2394 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2395 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2396 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2398 let BaseName = "rlwinm" in {
2399 def RLWINM : MForm_2<21,
2400 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2401 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2404 def RLWINMo : MForm_2<21,
2405 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2406 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2407 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2409 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2410 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2411 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2414 } // hasSideEffects = 0
2416 //===----------------------------------------------------------------------===//
2417 // PowerPC Instruction Patterns
2420 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2421 def : Pat<(i32 imm:$imm),
2422 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2424 // Implement the 'not' operation with the NOR instruction.
2425 def i32not : OutPatFrag<(ops node:$in),
2427 def : Pat<(not i32:$in),
2430 // ADD an arbitrary immediate.
2431 def : Pat<(add i32:$in, imm:$imm),
2432 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2433 // OR an arbitrary immediate.
2434 def : Pat<(or i32:$in, imm:$imm),
2435 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2436 // XOR an arbitrary immediate.
2437 def : Pat<(xor i32:$in, imm:$imm),
2438 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2440 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2441 (SUBFIC $in, imm:$imm)>;
2444 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2445 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2446 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2447 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2450 def : Pat<(rotl i32:$in, i32:$sh),
2451 (RLWNM $in, $sh, 0, 31)>;
2452 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2453 (RLWINM $in, imm:$imm, 0, 31)>;
2456 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2457 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2460 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2461 (BL tglobaladdr:$dst)>;
2462 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2463 (BL texternalsym:$dst)>;
2465 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2466 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2468 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2469 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2471 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2472 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2476 // Hi and Lo for Darwin Global Addresses.
2477 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2478 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2479 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2480 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2481 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2482 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2483 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2484 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2485 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2486 (ADDIS $in, tglobaltlsaddr:$g)>;
2487 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2488 (ADDI $in, tglobaltlsaddr:$g)>;
2489 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2490 (ADDIS $in, tglobaladdr:$g)>;
2491 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2492 (ADDIS $in, tconstpool:$g)>;
2493 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2494 (ADDIS $in, tjumptable:$g)>;
2495 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2496 (ADDIS $in, tblockaddress:$g)>;
2498 // Support for thread-local storage.
2499 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2500 [(set i32:$rD, (PPCppc32GOT))]>;
2502 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2503 // This uses two output registers, the first as the real output, the second as a
2504 // temporary register, used internally in code generation.
2505 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2506 []>, NoEncode<"$rT">;
2508 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2511 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2512 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2513 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2515 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2518 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2519 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2520 // explicitly defined when this op is created, so not mentioned here.
2521 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2522 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2523 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2526 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2527 // Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR
2528 // are true defines while the rest of the Defs are clobbers.
2529 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2530 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2531 def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2532 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2533 "#ADDItlsgdLADDR32",
2535 (PPCaddiTlsgdLAddr i32:$reg,
2536 tglobaltlsaddr:$disp,
2537 tglobaltlsaddr:$sym))]>;
2538 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2541 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2542 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2543 // explicitly defined when this op is created, so not mentioned here.
2544 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2545 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2546 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2549 (PPCgetTlsldAddr i32:$reg,
2550 tglobaltlsaddr:$sym))]>;
2551 // Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR
2552 // are true defines while the rest of the Defs are clobbers.
2553 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2554 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2555 def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2556 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2557 "#ADDItlsldLADDR32",
2559 (PPCaddiTlsldLAddr i32:$reg,
2560 tglobaltlsaddr:$disp,
2561 tglobaltlsaddr:$sym))]>;
2562 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2565 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2566 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2569 (PPCaddisDtprelHA i32:$reg,
2570 tglobaltlsaddr:$disp))]>;
2572 // Support for Position-independent code
2573 def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2576 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2577 // Get Global (GOT) Base Register offset, from the word immediately preceding
2578 // the function label.
2579 def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2582 // Standard shifts. These are represented separately from the real shifts above
2583 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2585 def : Pat<(sra i32:$rS, i32:$rB),
2587 def : Pat<(srl i32:$rS, i32:$rB),
2589 def : Pat<(shl i32:$rS, i32:$rB),
2592 def : Pat<(zextloadi1 iaddr:$src),
2594 def : Pat<(zextloadi1 xaddr:$src),
2596 def : Pat<(extloadi1 iaddr:$src),
2598 def : Pat<(extloadi1 xaddr:$src),
2600 def : Pat<(extloadi8 iaddr:$src),
2602 def : Pat<(extloadi8 xaddr:$src),
2604 def : Pat<(extloadi16 iaddr:$src),
2606 def : Pat<(extloadi16 xaddr:$src),
2608 def : Pat<(f64 (extloadf32 iaddr:$src)),
2609 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2610 def : Pat<(f64 (extloadf32 xaddr:$src)),
2611 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2613 def : Pat<(f64 (fextend f32:$src)),
2614 (COPY_TO_REGCLASS $src, F8RC)>;
2616 // Only seq_cst fences require the heavyweight sync (SYNC 0).
2617 // All others can use the lightweight sync (SYNC 1).
2618 // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2619 // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2620 // versions of Power.
2621 def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2622 def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2623 def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2624 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2626 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2627 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2628 (FNMSUB $A, $C, $B)>;
2629 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2630 (FNMSUB $A, $C, $B)>;
2631 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2632 (FNMSUBS $A, $C, $B)>;
2633 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2634 (FNMSUBS $A, $C, $B)>;
2636 // FCOPYSIGN's operand types need not agree.
2637 def : Pat<(fcopysign f64:$frB, f32:$frA),
2638 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2639 def : Pat<(fcopysign f32:$frB, f64:$frA),
2640 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2642 include "PPCInstrAltivec.td"
2643 include "PPCInstrSPE.td"
2644 include "PPCInstr64Bit.td"
2645 include "PPCInstrVSX.td"
2647 def crnot : OutPatFrag<(ops node:$in),
2649 def : Pat<(not i1:$in),
2652 // Patterns for arithmetic i1 operations.
2653 def : Pat<(add i1:$a, i1:$b),
2655 def : Pat<(sub i1:$a, i1:$b),
2657 def : Pat<(mul i1:$a, i1:$b),
2660 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2661 // (-1 is used to mean all bits set).
2662 def : Pat<(i1 -1), (CRSET)>;
2664 // i1 extensions, implemented in terms of isel.
2665 def : Pat<(i32 (zext i1:$in)),
2666 (SELECT_I4 $in, (LI 1), (LI 0))>;
2667 def : Pat<(i32 (sext i1:$in)),
2668 (SELECT_I4 $in, (LI -1), (LI 0))>;
2670 def : Pat<(i64 (zext i1:$in)),
2671 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2672 def : Pat<(i64 (sext i1:$in)),
2673 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2675 // FIXME: We should choose either a zext or a sext based on other constants
2677 def : Pat<(i32 (anyext i1:$in)),
2678 (SELECT_I4 $in, (LI 1), (LI 0))>;
2679 def : Pat<(i64 (anyext i1:$in)),
2680 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2682 // match setcc on i1 variables.
2683 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2685 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2687 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2689 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2691 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2693 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2695 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2697 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2699 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2701 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2704 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2705 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2706 // floating-point types.
2708 multiclass CRNotPat<dag pattern, dag result> {
2709 def : Pat<pattern, (crnot result)>;
2710 def : Pat<(not pattern), result>;
2712 // We can also fold the crnot into an extension:
2713 def : Pat<(i32 (zext pattern)),
2714 (SELECT_I4 result, (LI 0), (LI 1))>;
2715 def : Pat<(i32 (sext pattern)),
2716 (SELECT_I4 result, (LI 0), (LI -1))>;
2718 // We can also fold the crnot into an extension:
2719 def : Pat<(i64 (zext pattern)),
2720 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2721 def : Pat<(i64 (sext pattern)),
2722 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2724 // FIXME: We should choose either a zext or a sext based on other constants
2726 def : Pat<(i32 (anyext pattern)),
2727 (SELECT_I4 result, (LI 0), (LI 1))>;
2729 def : Pat<(i64 (anyext pattern)),
2730 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2733 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2734 // we need to write imm:$imm in the output patterns below, not just $imm, or
2735 // else the resulting matcher will not correctly add the immediate operand
2736 // (making it a register operand instead).
2739 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2740 OutPatFrag rfrag, OutPatFrag rfrag8> {
2741 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2743 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2745 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2746 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2747 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2748 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2750 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2752 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2754 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2755 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2756 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2757 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2760 // Note that we do all inversions below with i(32|64)not, instead of using
2761 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2762 // has 2-cycle latency.
2764 defm : ExtSetCCPat<SETEQ,
2765 PatFrag<(ops node:$in, node:$cc),
2766 (setcc $in, 0, $cc)>,
2767 OutPatFrag<(ops node:$in),
2768 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2769 OutPatFrag<(ops node:$in),
2770 (RLDICL (CNTLZD $in), 58, 63)> >;
2772 defm : ExtSetCCPat<SETNE,
2773 PatFrag<(ops node:$in, node:$cc),
2774 (setcc $in, 0, $cc)>,
2775 OutPatFrag<(ops node:$in),
2776 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2777 OutPatFrag<(ops node:$in),
2778 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2780 defm : ExtSetCCPat<SETLT,
2781 PatFrag<(ops node:$in, node:$cc),
2782 (setcc $in, 0, $cc)>,
2783 OutPatFrag<(ops node:$in),
2784 (RLWINM $in, 1, 31, 31)>,
2785 OutPatFrag<(ops node:$in),
2786 (RLDICL $in, 1, 63)> >;
2788 defm : ExtSetCCPat<SETGE,
2789 PatFrag<(ops node:$in, node:$cc),
2790 (setcc $in, 0, $cc)>,
2791 OutPatFrag<(ops node:$in),
2792 (RLWINM (i32not $in), 1, 31, 31)>,
2793 OutPatFrag<(ops node:$in),
2794 (RLDICL (i64not $in), 1, 63)> >;
2796 defm : ExtSetCCPat<SETGT,
2797 PatFrag<(ops node:$in, node:$cc),
2798 (setcc $in, 0, $cc)>,
2799 OutPatFrag<(ops node:$in),
2800 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2801 OutPatFrag<(ops node:$in),
2802 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2804 defm : ExtSetCCPat<SETLE,
2805 PatFrag<(ops node:$in, node:$cc),
2806 (setcc $in, 0, $cc)>,
2807 OutPatFrag<(ops node:$in),
2808 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2809 OutPatFrag<(ops node:$in),
2810 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2812 defm : ExtSetCCPat<SETLT,
2813 PatFrag<(ops node:$in, node:$cc),
2814 (setcc $in, -1, $cc)>,
2815 OutPatFrag<(ops node:$in),
2816 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2817 OutPatFrag<(ops node:$in),
2818 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2820 defm : ExtSetCCPat<SETGE,
2821 PatFrag<(ops node:$in, node:$cc),
2822 (setcc $in, -1, $cc)>,
2823 OutPatFrag<(ops node:$in),
2824 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2825 OutPatFrag<(ops node:$in),
2826 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2828 defm : ExtSetCCPat<SETGT,
2829 PatFrag<(ops node:$in, node:$cc),
2830 (setcc $in, -1, $cc)>,
2831 OutPatFrag<(ops node:$in),
2832 (RLWINM (i32not $in), 1, 31, 31)>,
2833 OutPatFrag<(ops node:$in),
2834 (RLDICL (i64not $in), 1, 63)> >;
2836 defm : ExtSetCCPat<SETLE,
2837 PatFrag<(ops node:$in, node:$cc),
2838 (setcc $in, -1, $cc)>,
2839 OutPatFrag<(ops node:$in),
2840 (RLWINM $in, 1, 31, 31)>,
2841 OutPatFrag<(ops node:$in),
2842 (RLDICL $in, 1, 63)> >;
2845 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2846 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2847 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2848 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2849 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2850 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2851 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2852 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2853 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2854 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2855 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2856 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2858 // For non-equality comparisons, the default code would materialize the
2859 // constant, then compare against it, like this:
2861 // ori r2, r2, 22136
2864 // Since we are just comparing for equality, we can emit this instead:
2865 // xoris r0,r3,0x1234
2866 // cmplwi cr0,r0,0x5678
2869 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2870 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2871 (LO16 imm:$imm)), sub_eq)>;
2873 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2874 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2875 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2876 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2877 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2878 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2879 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2880 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2881 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2882 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2883 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2884 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2886 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2887 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2888 (LO16 imm:$imm)), sub_eq)>;
2890 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
2891 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2892 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2893 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2894 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2895 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2896 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
2897 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2898 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2899 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2901 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2902 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2903 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
2904 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2905 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2906 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2907 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
2908 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2909 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2910 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2913 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
2914 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2915 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2916 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2917 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2918 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2919 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
2920 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2921 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
2922 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2923 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
2924 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2926 // For non-equality comparisons, the default code would materialize the
2927 // constant, then compare against it, like this:
2929 // ori r2, r2, 22136
2932 // Since we are just comparing for equality, we can emit this instead:
2933 // xoris r0,r3,0x1234
2934 // cmpldi cr0,r0,0x5678
2937 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
2938 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2939 (LO16 imm:$imm)), sub_eq)>;
2941 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
2942 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2943 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
2944 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2945 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
2946 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2947 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
2948 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2949 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
2950 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2951 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
2952 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2954 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
2955 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2956 (LO16 imm:$imm)), sub_eq)>;
2958 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
2959 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2960 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
2961 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2962 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
2963 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2964 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
2965 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2966 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
2967 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2969 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
2970 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2971 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
2972 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2973 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
2974 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2975 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
2976 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2977 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
2978 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2981 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
2982 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2983 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
2984 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2985 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
2986 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2987 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
2988 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2989 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
2990 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2991 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
2992 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2993 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
2994 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2996 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
2997 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2998 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
2999 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3000 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3001 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3002 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3003 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3004 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3005 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3006 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3007 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3008 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3009 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3012 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3013 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3014 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3015 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3016 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3017 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3018 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3019 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3020 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3021 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3022 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3023 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3024 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3025 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3027 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3028 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3029 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3030 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3031 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3032 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3033 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3034 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3035 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3036 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3037 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3038 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3039 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3040 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3042 // match select on i1 variables:
3043 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3044 (CROR (CRAND $cond , $tval),
3045 (CRAND (crnot $cond), $fval))>;
3047 // match selectcc on i1 variables:
3048 // select (lhs == rhs), tval, fval is:
3049 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3050 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3051 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3052 (CRAND (CRORC $lhs, $rhs), $fval))>;
3053 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3054 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
3055 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3056 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3057 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3058 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3059 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3060 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
3061 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3062 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3063 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3064 (CRAND (CRORC $rhs, $lhs), $fval))>;
3065 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3066 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3067 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3069 // match selectcc on i1 variables with non-i1 output.
3070 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3071 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3072 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3073 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3074 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3075 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3076 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3077 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3078 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3079 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3080 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3081 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3083 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3084 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3085 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3086 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3087 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3088 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3089 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3090 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3091 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3092 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3093 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3094 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3096 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3097 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3098 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3099 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3100 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3101 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3102 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3103 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3104 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3105 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3106 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3107 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3109 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3110 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3111 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3112 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3113 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3114 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3115 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3116 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3117 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3118 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3119 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3120 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3122 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3123 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3124 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3125 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3126 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3127 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3128 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3129 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3130 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3131 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3132 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3133 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3135 let usesCustomInserter = 1 in {
3136 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3138 [(set i1:$dst, (trunc (not i32:$in)))]>;
3139 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3141 [(set i1:$dst, (trunc i32:$in))]>;
3143 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3145 [(set i1:$dst, (trunc (not i64:$in)))]>;
3146 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3148 [(set i1:$dst, (trunc i64:$in))]>;
3151 def : Pat<(i1 (not (trunc i32:$in))),
3152 (ANDIo_1_EQ_BIT $in)>;
3153 def : Pat<(i1 (not (trunc i64:$in))),
3154 (ANDIo_1_EQ_BIT8 $in)>;
3156 //===----------------------------------------------------------------------===//
3157 // PowerPC Instructions used for assembler/disassembler only
3160 // FIXME: For B=0 or B > 8, the registers following RT are used.
3161 // WARNING: Do not add patterns for this instruction without fixing this.
3162 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3163 "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3165 // FIXME: For B=0 or B > 8, the registers following RT are used.
3166 // WARNING: Do not add patterns for this instruction without fixing this.
3167 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3168 "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3170 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3171 "isync", IIC_SprISYNC, []>;
3173 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3174 "icbi $src", IIC_LdStICBI, []>;
3176 // We used to have EIEIO as value but E[0-9A-Z] is a reserved name
3177 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3178 "eieio", IIC_LdStLoad, []>;
3180 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3181 "wait $L", IIC_LdStLoad, []>;
3183 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3184 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3186 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3187 "mtsr $SR, $RS", IIC_SprMTSR>;
3189 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3190 "mfsr $RS, $SR", IIC_SprMFSR>;
3192 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3193 "mtsrin $RS, $RB", IIC_SprMTSR>;
3195 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3196 "mfsrin $RS, $RB", IIC_SprMFSR>;
3198 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3199 "mtmsr $RS, $L", IIC_SprMTMSR>;
3201 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3202 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3206 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3207 Requires<[IsBookE]> {
3211 let Inst{21-30} = 163;
3214 def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3215 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3216 def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3217 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3219 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3220 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3221 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3222 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3224 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3225 "mfmsr $RT", IIC_SprMFMSR, []>;
3227 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3228 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3230 def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
3231 "mcrfs $BF, $BFA", IIC_BrMCR>;
3233 def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3234 "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
3236 def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3237 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
3239 def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
3240 def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
3242 def MTFSF : XFLForm_1<63, 711, (outs),
3243 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3244 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
3245 def MTFSFo : XFLForm_1<63, 711, (outs),
3246 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3247 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
3249 def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3250 def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3252 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3253 "slbie $RB", IIC_SprSLBIE, []>;
3255 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3256 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3258 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3259 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3261 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3263 def TLBIA : XForm_0<31, 370, (outs), (ins),
3264 "tlbia", IIC_SprTLBIA, []>;
3266 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3267 "tlbsync", IIC_SprTLBSYNC, []>;
3269 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3270 "tlbiel $RB", IIC_SprTLBIEL, []>;
3272 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3273 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3274 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3275 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3277 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3278 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3280 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3281 IIC_LdStLoad>, Requires<[IsBookE]>;
3283 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3284 IIC_LdStLoad>, Requires<[IsBookE]>;
3286 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3287 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3289 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3290 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3292 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3293 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3295 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3296 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3298 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3299 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3300 Requires<[IsPPC4xx]>;
3301 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3302 (ins gprc:$RST, gprc:$A, gprc:$B),
3303 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3304 Requires<[IsPPC4xx]>, isDOT;
3306 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3308 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3309 Requires<[IsBookE]>;
3310 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3311 Requires<[IsBookE]>;
3313 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3315 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3318 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3319 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3320 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3321 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3323 def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3325 def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3326 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3327 def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3328 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3329 def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3330 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3331 def LDCIX : XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3332 "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3334 def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3335 "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3336 def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3337 "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3338 def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3339 "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3340 def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3341 "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3343 //===----------------------------------------------------------------------===//
3344 // PowerPC Assembler Instruction Aliases
3347 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3348 // These are aliases that require C++ handling to convert to the target
3349 // instruction, while InstAliases can be handled directly by tblgen.
3350 class PPCAsmPseudo<string asm, dag iops>
3352 let Namespace = "PPC";
3353 bit PPC64 = 0; // Default value, override with isPPC64
3355 let OutOperandList = (outs);
3356 let InOperandList = iops;
3358 let AsmString = asm;
3359 let isAsmParserOnly = 1;
3363 def : InstAlias<"sc", (SC 0)>;
3365 def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3366 def : InstAlias<"msync", (SYNC 0)>, Requires<[HasSYNC]>;
3367 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3368 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3370 def : InstAlias<"wait", (WAIT 0)>;
3371 def : InstAlias<"waitrsv", (WAIT 1)>;
3372 def : InstAlias<"waitimpl", (WAIT 2)>;
3374 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3376 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3377 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3378 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3379 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3381 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3382 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3384 def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3385 def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3387 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3388 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3390 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3391 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3393 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3394 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3396 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3397 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3399 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3400 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3402 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3403 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3405 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3406 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3408 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3409 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3411 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3412 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3414 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3415 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3417 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3418 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3420 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3421 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3423 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3424 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3425 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3427 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3428 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3430 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3431 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3432 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3433 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3435 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3437 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3438 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3440 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3441 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3443 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3445 foreach BATR = 0-3 in {
3446 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3447 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3448 Requires<[IsPPC6xx]>;
3449 def : InstAlias<"mfdbatu $Rx, "#BATR,
3450 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3451 Requires<[IsPPC6xx]>;
3452 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3453 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3454 Requires<[IsPPC6xx]>;
3455 def : InstAlias<"mfdbatl $Rx, "#BATR,
3456 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3457 Requires<[IsPPC6xx]>;
3458 def : InstAlias<"mtibatu "#BATR#", $Rx",
3459 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3460 Requires<[IsPPC6xx]>;
3461 def : InstAlias<"mfibatu $Rx, "#BATR,
3462 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3463 Requires<[IsPPC6xx]>;
3464 def : InstAlias<"mtibatl "#BATR#", $Rx",
3465 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3466 Requires<[IsPPC6xx]>;
3467 def : InstAlias<"mfibatl $Rx, "#BATR,
3468 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3469 Requires<[IsPPC6xx]>;
3472 foreach BR = 0-7 in {
3473 def : InstAlias<"mfbr"#BR#" $Rx",
3474 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3475 Requires<[IsPPC4xx]>;
3476 def : InstAlias<"mtbr"#BR#" $Rx",
3477 (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3478 Requires<[IsPPC4xx]>;
3481 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3482 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3484 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3485 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3487 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3488 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3490 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3491 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3493 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3494 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3496 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3497 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3499 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3501 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3502 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3503 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3504 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3505 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3506 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3507 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3508 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3510 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3511 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3512 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3513 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3515 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3516 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3518 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3519 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3521 foreach SPRG = 0-3 in {
3522 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3523 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3524 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3525 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3527 foreach SPRG = 4-7 in {
3528 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3529 Requires<[IsBookE]>;
3530 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3531 Requires<[IsBookE]>;
3532 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3533 Requires<[IsBookE]>;
3534 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3535 Requires<[IsBookE]>;
3538 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3540 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3541 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3543 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3545 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3546 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3548 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3549 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3550 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3551 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3553 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3555 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3556 Requires<[IsPPC4xx]>;
3557 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3558 Requires<[IsPPC4xx]>;
3559 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3560 Requires<[IsPPC4xx]>;
3561 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3562 Requires<[IsPPC4xx]>;
3564 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3565 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3566 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3567 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3568 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3569 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3570 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3571 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3572 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3573 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3574 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3575 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3576 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3577 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3578 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3579 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3580 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3581 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3582 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3583 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3584 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3585 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3586 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3587 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3588 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3589 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3590 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3591 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3592 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3593 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3594 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3595 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3596 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3597 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3598 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3599 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3601 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3602 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3603 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3604 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3605 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3606 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3608 def : InstAlias<"cntlz $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
3609 def : InstAlias<"cntlz. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
3611 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3612 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3613 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3614 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3615 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3616 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3617 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3618 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3619 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3620 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3621 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3622 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3623 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3624 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3625 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3626 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3627 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3628 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3629 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3630 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3631 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3632 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3633 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3634 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3635 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3636 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3637 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3638 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3639 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3640 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3641 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3642 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3644 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3645 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3646 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3647 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3648 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3649 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3651 // These generic branch instruction forms are used for the assembler parser only.
3652 // Defs and Uses are conservative, since we don't know the BO value.
3653 let PPC970_Unit = 7 in {
3654 let Defs = [CTR], Uses = [CTR, RM] in {
3655 def gBC : BForm_3<16, 0, 0, (outs),
3656 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3657 "bc $bo, $bi, $dst">;
3658 def gBCA : BForm_3<16, 1, 0, (outs),
3659 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3660 "bca $bo, $bi, $dst">;
3662 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3663 def gBCL : BForm_3<16, 0, 1, (outs),
3664 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3665 "bcl $bo, $bi, $dst">;
3666 def gBCLA : BForm_3<16, 1, 1, (outs),
3667 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3668 "bcla $bo, $bi, $dst">;
3670 let Defs = [CTR], Uses = [CTR, LR, RM] in
3671 def gBCLR : XLForm_2<19, 16, 0, (outs),
3672 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3673 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3674 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3675 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3676 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3677 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3678 let Defs = [CTR], Uses = [CTR, LR, RM] in
3679 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3680 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3681 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3682 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3683 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3684 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3685 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3687 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3688 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3689 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3690 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3692 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3693 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3694 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3695 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3696 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3697 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3698 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3700 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3701 : BranchSimpleMnemonic1<name, pm, bo> {
3702 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3703 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3705 defm : BranchSimpleMnemonic2<"t", "", 12>;
3706 defm : BranchSimpleMnemonic2<"f", "", 4>;
3707 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3708 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3709 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3710 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3711 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3712 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3713 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3714 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3716 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3717 def : InstAlias<"b"#name#pm#" $cc, $dst",
3718 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3719 def : InstAlias<"b"#name#pm#" $dst",
3720 (BCC bibo, CR0, condbrtarget:$dst)>;
3722 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3723 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3724 def : InstAlias<"b"#name#"a"#pm#" $dst",
3725 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3727 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3728 (BCCLR bibo, crrc:$cc)>;
3729 def : InstAlias<"b"#name#"lr"#pm,
3732 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3733 (BCCCTR bibo, crrc:$cc)>;
3734 def : InstAlias<"b"#name#"ctr"#pm,
3735 (BCCCTR bibo, CR0)>;
3737 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3738 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3739 def : InstAlias<"b"#name#"l"#pm#" $dst",
3740 (BCCL bibo, CR0, condbrtarget:$dst)>;
3742 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3743 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3744 def : InstAlias<"b"#name#"la"#pm#" $dst",
3745 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3747 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3748 (BCCLRL bibo, crrc:$cc)>;
3749 def : InstAlias<"b"#name#"lrl"#pm,
3750 (BCCLRL bibo, CR0)>;
3752 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3753 (BCCCTRL bibo, crrc:$cc)>;
3754 def : InstAlias<"b"#name#"ctrl"#pm,
3755 (BCCCTRL bibo, CR0)>;
3757 multiclass BranchExtendedMnemonic<string name, int bibo> {
3758 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3759 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3760 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3762 defm : BranchExtendedMnemonic<"lt", 12>;
3763 defm : BranchExtendedMnemonic<"gt", 44>;
3764 defm : BranchExtendedMnemonic<"eq", 76>;
3765 defm : BranchExtendedMnemonic<"un", 108>;
3766 defm : BranchExtendedMnemonic<"so", 108>;
3767 defm : BranchExtendedMnemonic<"ge", 4>;
3768 defm : BranchExtendedMnemonic<"nl", 4>;
3769 defm : BranchExtendedMnemonic<"le", 36>;
3770 defm : BranchExtendedMnemonic<"ng", 36>;
3771 defm : BranchExtendedMnemonic<"ne", 68>;
3772 defm : BranchExtendedMnemonic<"nu", 100>;
3773 defm : BranchExtendedMnemonic<"ns", 100>;
3775 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3776 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3777 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3778 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3779 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3780 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3781 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3782 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3784 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3785 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3786 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3787 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3788 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3789 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3790 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3791 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3793 multiclass TrapExtendedMnemonic<string name, int to> {
3794 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3795 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3796 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3797 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3799 defm : TrapExtendedMnemonic<"lt", 16>;
3800 defm : TrapExtendedMnemonic<"le", 20>;
3801 defm : TrapExtendedMnemonic<"eq", 4>;
3802 defm : TrapExtendedMnemonic<"ge", 12>;
3803 defm : TrapExtendedMnemonic<"gt", 8>;
3804 defm : TrapExtendedMnemonic<"nl", 12>;
3805 defm : TrapExtendedMnemonic<"ne", 24>;
3806 defm : TrapExtendedMnemonic<"ng", 20>;
3807 defm : TrapExtendedMnemonic<"llt", 2>;
3808 defm : TrapExtendedMnemonic<"lle", 6>;
3809 defm : TrapExtendedMnemonic<"lge", 5>;
3810 defm : TrapExtendedMnemonic<"lgt", 1>;
3811 defm : TrapExtendedMnemonic<"lnl", 5>;
3812 defm : TrapExtendedMnemonic<"lng", 6>;
3813 defm : TrapExtendedMnemonic<"u", 31>;
3816 def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>;
3817 def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>;
3818 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>;
3819 def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>;
3820 def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
3821 def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
3824 def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>;
3825 def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>;
3826 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>;
3827 def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
3828 def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
3829 def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;