1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
28 def SDT_PPCvperm : SDTypeProfile<1, 3, [
29 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
32 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
33 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
36 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
37 SDTCisVT<1, i32>, SDTCisVT<2, OtherVT>
40 def SDT_PPClbrx : SDTypeProfile<1, 3, [
41 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
43 def SDT_PPCstbrx : SDTypeProfile<0, 4, [
44 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
47 //===----------------------------------------------------------------------===//
48 // PowerPC specific DAG Nodes.
51 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
52 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
53 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
54 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
56 def PPCfsel : SDNode<"PPCISD::FSEL",
57 // Type constraint for fsel.
58 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
59 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
61 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
62 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
63 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
64 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
66 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
68 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
69 // amounts. These nodes are generated by the multi-precision shift code.
70 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
71 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
72 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
74 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
75 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
77 // These are target-independent nodes, but have target-specific formats.
78 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,
79 [SDNPHasChain, SDNPOutFlag]>;
80 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,
81 [SDNPHasChain, SDNPOutFlag]>;
83 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
84 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
85 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
86 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
87 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
88 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTRet,
89 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
91 def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet,
92 [SDNPHasChain, SDNPOptInFlag]>;
94 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
95 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
97 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
98 [SDNPHasChain, SDNPOptInFlag]>;
100 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
101 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>;
103 //===----------------------------------------------------------------------===//
104 // PowerPC specific transformation functions and pattern fragments.
107 def SHL32 : SDNodeXForm<imm, [{
108 // Transformation function: 31 - imm
109 return getI32Imm(31 - N->getValue());
112 def SRL32 : SDNodeXForm<imm, [{
113 // Transformation function: 32 - imm
114 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
117 def LO16 : SDNodeXForm<imm, [{
118 // Transformation function: get the low 16 bits.
119 return getI32Imm((unsigned short)N->getValue());
122 def HI16 : SDNodeXForm<imm, [{
123 // Transformation function: shift the immediate value down into the low bits.
124 return getI32Imm((unsigned)N->getValue() >> 16);
127 def HA16 : SDNodeXForm<imm, [{
128 // Transformation function: shift the immediate value down into the low bits.
129 signed int Val = N->getValue();
130 return getI32Imm((Val - (signed short)Val) >> 16);
132 def MB : SDNodeXForm<imm, [{
133 // Transformation function: get the start bit of a mask
135 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
136 return getI32Imm(mb);
139 def ME : SDNodeXForm<imm, [{
140 // Transformation function: get the end bit of a mask
142 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
143 return getI32Imm(me);
145 def maskimm32 : PatLeaf<(imm), [{
146 // maskImm predicate - True if immediate is a run of ones.
148 if (N->getValueType(0) == MVT::i32)
149 return isRunOfOnes((unsigned)N->getValue(), mb, me);
154 def immSExt16 : PatLeaf<(imm), [{
155 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
156 // field. Used by instructions like 'addi'.
157 if (N->getValueType(0) == MVT::i32)
158 return (int32_t)N->getValue() == (short)N->getValue();
160 return (int64_t)N->getValue() == (short)N->getValue();
162 def immZExt16 : PatLeaf<(imm), [{
163 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
164 // field. Used by instructions like 'ori'.
165 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
168 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
169 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
170 // identical in 32-bit mode, but in 64-bit mode, they return true if the
171 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
173 def imm16ShiftedZExt : PatLeaf<(imm), [{
174 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
175 // immediate are set. Used by instructions like 'xoris'.
176 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
179 def imm16ShiftedSExt : PatLeaf<(imm), [{
180 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
181 // immediate are set. Used by instructions like 'addis'. Identical to
182 // imm16ShiftedZExt in 32-bit mode.
183 if (N->getValue() & 0xFFFF) return false;
184 if (N->getValueType(0) == MVT::i32)
186 // For 64-bit, make sure it is sext right.
187 return N->getValue() == (uint64_t)(int)N->getValue();
191 //===----------------------------------------------------------------------===//
192 // PowerPC Flag Definitions.
194 class isPPC64 { bit PPC64 = 1; }
196 list<Register> Defs = [CR0];
200 class RegConstraint<string C> {
201 string Constraints = C;
205 //===----------------------------------------------------------------------===//
206 // PowerPC Operand Definitions.
208 def s5imm : Operand<i32> {
209 let PrintMethod = "printS5ImmOperand";
211 def u5imm : Operand<i32> {
212 let PrintMethod = "printU5ImmOperand";
214 def u6imm : Operand<i32> {
215 let PrintMethod = "printU6ImmOperand";
217 def s16imm : Operand<i32> {
218 let PrintMethod = "printS16ImmOperand";
220 def u16imm : Operand<i32> {
221 let PrintMethod = "printU16ImmOperand";
223 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
224 let PrintMethod = "printS16X4ImmOperand";
226 def target : Operand<OtherVT> {
227 let PrintMethod = "printBranchOperand";
229 def calltarget : Operand<iPTR> {
230 let PrintMethod = "printCallOperand";
232 def aaddr : Operand<iPTR> {
233 let PrintMethod = "printAbsAddrOperand";
235 def piclabel: Operand<iPTR> {
236 let PrintMethod = "printPICLabel";
238 def symbolHi: Operand<i32> {
239 let PrintMethod = "printSymbolHi";
241 def symbolLo: Operand<i32> {
242 let PrintMethod = "printSymbolLo";
244 def crbitm: Operand<i8> {
245 let PrintMethod = "printcrbitm";
248 def memri : Operand<iPTR> {
249 let PrintMethod = "printMemRegImm";
250 let MIOperandInfo = (ops i32imm, ptr_rc);
252 def memrr : Operand<iPTR> {
253 let PrintMethod = "printMemRegReg";
254 let MIOperandInfo = (ops ptr_rc, ptr_rc);
256 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
257 let PrintMethod = "printMemRegImmShifted";
258 let MIOperandInfo = (ops i32imm, ptr_rc);
261 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
262 // that doesn't matter.
263 def pred : PredicateOperand<(ops imm, CRRC), (ops (i32 20), CR0)> {
264 let PrintMethod = "printPredicateOperand";
267 // Define PowerPC specific addressing mode.
268 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
269 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
270 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
271 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
273 //===----------------------------------------------------------------------===//
274 // PowerPC Instruction Predicate Definitions.
275 def FPContractions : Predicate<"!NoExcessFPPrecision">;
277 //===----------------------------------------------------------------------===//
278 // PowerPC Instruction Definitions.
280 // Pseudo-instructions:
282 let hasCtrlDep = 1 in {
283 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
284 "${:comment} ADJCALLSTACKDOWN",
285 [(callseq_start imm:$amt)]>, Imp<[R1],[R1]>;
286 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
287 "${:comment} ADJCALLSTACKUP",
288 [(callseq_end imm:$amt)]>, Imp<[R1],[R1]>;
290 def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
291 "UPDATE_VRSAVE $rD, $rS", []>;
293 def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD),"${:comment}IMPLICIT_DEF_GPRC $rD",
294 [(set GPRC:$rD, (undef))]>;
295 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "${:comment} IMPLICIT_DEF_F8 $rD",
296 [(set F8RC:$rD, (undef))]>;
297 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "${:comment} IMPLICIT_DEF_F4 $rD",
298 [(set F4RC:$rD, (undef))]>;
300 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
301 // scheduler into a branch sequence.
302 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
303 PPC970_Single = 1 in {
304 def SELECT_CC_I4 : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
305 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
307 def SELECT_CC_I8 : Pseudo<(ops G8RC:$dst, CRRC:$cond, G8RC:$T, G8RC:$F,
308 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
310 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
311 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
313 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
314 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
316 def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F,
317 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
321 let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
323 def BLR : XLForm_2_br<19, 16, 0,
325 "b${p:cc}lr ${p:reg}", BrB,
327 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
332 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
335 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
336 noResults = 1, PPC970_Unit = 7 in {
337 // COND_BRANCH is formed before branch selection, it is turned into Bcc below.
338 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
339 "${:comment} COND_BRANCH $crS, $opc, $dst",
340 [(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
341 let isBarrier = 1 in {
342 def B : IForm<18, 0, 0, (ops target:$dst),
347 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
348 "blt $crS, $block", BrB>;
349 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
350 "ble $crS, $block", BrB>;
351 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
352 "beq $crS, $block", BrB>;
353 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
354 "bge $crS, $block", BrB>;
355 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
356 "bgt $crS, $block", BrB>;
357 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
358 "bne $crS, $block", BrB>;
359 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
360 "bun $crS, $block", BrB>;
361 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
362 "bnu $crS, $block", BrB>;
365 let isCall = 1, noResults = 1, PPC970_Unit = 7,
366 // All calls clobber the non-callee saved registers...
367 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
368 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
369 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
371 CR0,CR1,CR5,CR6,CR7] in {
372 // Convenient aliases for call instructions
373 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
374 "bl $func", BrB, []>; // See Pat patterns below.
375 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
376 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
377 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB,
381 // DCB* instructions.
382 def DCBA : DCB_Form<758, 0, (ops memrr:$dst),
383 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
384 PPC970_DGroup_Single;
385 def DCBF : DCB_Form<86, 0, (ops memrr:$dst),
386 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
387 PPC970_DGroup_Single;
388 def DCBI : DCB_Form<470, 0, (ops memrr:$dst),
389 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
390 PPC970_DGroup_Single;
391 def DCBST : DCB_Form<54, 0, (ops memrr:$dst),
392 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
393 PPC970_DGroup_Single;
394 def DCBT : DCB_Form<278, 0, (ops memrr:$dst),
395 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
396 PPC970_DGroup_Single;
397 def DCBTST : DCB_Form<246, 0, (ops memrr:$dst),
398 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
399 PPC970_DGroup_Single;
400 def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
401 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
402 PPC970_DGroup_Single;
403 def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
404 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
405 PPC970_DGroup_Single;
407 // D-Form instructions. Most instructions that perform an operation on a
408 // register and an immediate are of this type.
410 let isLoad = 1, PPC970_Unit = 2 in {
411 def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
412 "lbz $rD, $src", LdStGeneral,
413 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
414 def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
415 "lha $rD, $src", LdStLHA,
416 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
417 PPC970_DGroup_Cracked;
418 def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
419 "lhz $rD, $src", LdStGeneral,
420 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
421 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
422 "lwz $rD, $src", LdStGeneral,
423 [(set GPRC:$rD, (load iaddr:$src))]>;
425 def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src),
426 "lfs $rD, $src", LdStLFDU,
427 [(set F4RC:$rD, (load iaddr:$src))]>;
428 def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src),
429 "lfd $rD, $src", LdStLFD,
430 [(set F8RC:$rD, (load iaddr:$src))]>;
432 // FIXME: PTRRC for Pointer regs for ppc64.
434 // 'Update' load forms.
435 def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$rA_result, i32imm:$disp,
437 "lbzu $rD, $disp($rA)", LdStGeneral,
438 []>, RegConstraint<"$rA = $rA_result">;
440 def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$rA_result, i32imm:$disp,
442 "lhau $rD, $disp($rA)", LdStGeneral,
443 []>, RegConstraint<"$rA = $rA_result">;
445 def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$rA_result, i32imm:$disp,
447 "lhzu $rD, $disp($rA)", LdStGeneral,
448 []>, RegConstraint<"$rA = $rA_result">;
450 def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$rA_result, i32imm:$disp,
452 "lwzu $rD, $disp($rA)", LdStGeneral,
453 []>, RegConstraint<"$rA = $rA_result">;
455 def LFSU : DForm_8<49, (ops F4RC:$rD, ptr_rc:$rA_result, i32imm:$disp,
457 "lfs $rD, $disp($rA)", LdStLFDU,
458 []>, RegConstraint<"$rA = $rA_result">;
459 def LFDU : DForm_8<51, (ops F8RC:$rD, ptr_rc:$rA_result, i32imm:$disp,
461 "lfd $rD, $disp($rA)", LdStLFD,
462 []>, RegConstraint<"$rA = $rA_result">;
466 let PPC970_Unit = 1 in { // FXU Operations.
467 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
468 "addi $rD, $rA, $imm", IntGeneral,
469 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
470 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
471 "addic $rD, $rA, $imm", IntGeneral,
472 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
473 PPC970_DGroup_Cracked;
474 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
475 "addic. $rD, $rA, $imm", IntGeneral,
477 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
478 "addis $rD, $rA, $imm", IntGeneral,
479 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
480 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
481 "la $rD, $sym($rA)", IntGeneral,
482 [(set GPRC:$rD, (add GPRC:$rA,
483 (PPClo tglobaladdr:$sym, 0)))]>;
484 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
485 "mulli $rD, $rA, $imm", IntMulLI,
486 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
487 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
488 "subfic $rD, $rA, $imm", IntGeneral,
489 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
490 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
491 "li $rD, $imm", IntGeneral,
492 [(set GPRC:$rD, immSExt16:$imm)]>;
493 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
494 "lis $rD, $imm", IntGeneral,
495 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
497 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
498 def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
499 "stb $rS, $src", LdStGeneral,
500 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
501 def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
502 "sth $rS, $src", LdStGeneral,
503 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
504 def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
505 "stw $rS, $src", LdStGeneral,
506 [(store GPRC:$rS, iaddr:$src)]>;
507 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
508 "stwu $rS, $disp($rA)", LdStGeneral,
511 let PPC970_Unit = 1 in { // FXU Operations.
512 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
513 "andi. $dst, $src1, $src2", IntGeneral,
514 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
516 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
517 "andis. $dst, $src1, $src2", IntGeneral,
518 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
520 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
521 "ori $dst, $src1, $src2", IntGeneral,
522 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
523 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
524 "oris $dst, $src1, $src2", IntGeneral,
525 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
526 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
527 "xori $dst, $src1, $src2", IntGeneral,
528 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
529 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
530 "xoris $dst, $src1, $src2", IntGeneral,
531 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
532 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
534 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
535 "cmpwi $crD, $rA, $imm", IntCompare>;
536 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
537 "cmplwi $dst, $src1, $src2", IntCompare>;
539 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
540 def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst),
541 "stfs $rS, $dst", LdStUX,
542 [(store F4RC:$rS, iaddr:$dst)]>;
543 def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst),
544 "stfd $rS, $dst", LdStUX,
545 [(store F8RC:$rS, iaddr:$dst)]>;
548 // X-Form instructions. Most instructions that perform an operation on a
549 // register and another register are of this type.
551 let isLoad = 1, PPC970_Unit = 2 in {
552 def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
553 "lbzx $rD, $src", LdStGeneral,
554 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
555 def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
556 "lhax $rD, $src", LdStLHA,
557 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
558 PPC970_DGroup_Cracked;
559 def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
560 "lhzx $rD, $src", LdStGeneral,
561 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
562 def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
563 "lwzx $rD, $src", LdStGeneral,
564 [(set GPRC:$rD, (load xaddr:$src))]>;
567 def LHBRX : XForm_1<31, 790, (ops GPRC:$rD, memrr:$src),
568 "lhbrx $rD, $src", LdStGeneral,
569 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
570 def LWBRX : XForm_1<31, 534, (ops GPRC:$rD, memrr:$src),
571 "lwbrx $rD, $src", LdStGeneral,
572 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
576 let PPC970_Unit = 1 in { // FXU Operations.
577 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
578 "nand $rA, $rS, $rB", IntGeneral,
579 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
580 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
581 "and $rA, $rS, $rB", IntGeneral,
582 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
583 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
584 "andc $rA, $rS, $rB", IntGeneral,
585 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
586 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
587 "or $rA, $rS, $rB", IntGeneral,
588 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
589 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
590 "nor $rA, $rS, $rB", IntGeneral,
591 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
592 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
593 "orc $rA, $rS, $rB", IntGeneral,
594 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
595 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
596 "eqv $rA, $rS, $rB", IntGeneral,
597 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
598 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
599 "xor $rA, $rS, $rB", IntGeneral,
600 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
601 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
602 "slw $rA, $rS, $rB", IntGeneral,
603 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
604 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
605 "srw $rA, $rS, $rB", IntGeneral,
606 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
607 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
608 "sraw $rA, $rS, $rB", IntShift,
609 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
611 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
612 def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
613 "stbx $rS, $dst", LdStGeneral,
614 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
615 PPC970_DGroup_Cracked;
616 def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
617 "sthx $rS, $dst", LdStGeneral,
618 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
619 PPC970_DGroup_Cracked;
620 def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
621 "stwx $rS, $dst", LdStGeneral,
622 [(store GPRC:$rS, xaddr:$dst)]>,
623 PPC970_DGroup_Cracked;
624 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
625 "stwux $rS, $rA, $rB", LdStGeneral,
627 def STHBRX: XForm_8<31, 918, (ops GPRC:$rS, memrr:$dst),
628 "sthbrx $rS, $dst", LdStGeneral,
629 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
630 PPC970_DGroup_Cracked;
631 def STWBRX: XForm_8<31, 662, (ops GPRC:$rS, memrr:$dst),
632 "stwbrx $rS, $dst", LdStGeneral,
633 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
634 PPC970_DGroup_Cracked;
636 let PPC970_Unit = 1 in { // FXU Operations.
637 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
638 "srawi $rA, $rS, $SH", IntShift,
639 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
640 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
641 "cntlzw $rA, $rS", IntGeneral,
642 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
643 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
644 "extsb $rA, $rS", IntGeneral,
645 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
646 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
647 "extsh $rA, $rS", IntGeneral,
648 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
650 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
651 "cmpw $crD, $rA, $rB", IntCompare>;
652 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
653 "cmplw $crD, $rA, $rB", IntCompare>;
655 let PPC970_Unit = 3 in { // FPU Operations.
656 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
657 // "fcmpo $crD, $fA, $fB", FPCompare>;
658 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
659 "fcmpu $crD, $fA, $fB", FPCompare>;
660 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
661 "fcmpu $crD, $fA, $fB", FPCompare>;
663 let isLoad = 1, PPC970_Unit = 2 in {
664 def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
665 "lfsx $frD, $src", LdStLFDU,
666 [(set F4RC:$frD, (load xaddr:$src))]>;
667 def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
668 "lfdx $frD, $src", LdStLFDU,
669 [(set F8RC:$frD, (load xaddr:$src))]>;
671 let PPC970_Unit = 3 in { // FPU Operations.
672 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
673 "fctiwz $frD, $frB", FPGeneral,
674 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
675 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
676 "frsp $frD, $frB", FPGeneral,
677 [(set F4RC:$frD, (fround F8RC:$frB))]>;
678 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
679 "fsqrt $frD, $frB", FPSqrt,
680 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
681 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
682 "fsqrts $frD, $frB", FPSqrt,
683 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
686 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
688 /// Note that these are defined as pseudo-ops on the PPC970 because they are
689 /// often coalesced away and we don't want the dispatch group builder to think
690 /// that they will fill slots (which could cause the load of a LSU reject to
691 /// sneak into a d-group with a store).
692 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
693 "fmr $frD, $frB", FPGeneral,
694 []>, // (set F4RC:$frD, F4RC:$frB)
696 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
697 "fmr $frD, $frB", FPGeneral,
698 []>, // (set F8RC:$frD, F8RC:$frB)
700 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
701 "fmr $frD, $frB", FPGeneral,
702 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
705 let PPC970_Unit = 3 in { // FPU Operations.
706 // These are artificially split into two different forms, for 4/8 byte FP.
707 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
708 "fabs $frD, $frB", FPGeneral,
709 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
710 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
711 "fabs $frD, $frB", FPGeneral,
712 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
713 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
714 "fnabs $frD, $frB", FPGeneral,
715 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
716 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
717 "fnabs $frD, $frB", FPGeneral,
718 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
719 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
720 "fneg $frD, $frB", FPGeneral,
721 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
722 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
723 "fneg $frD, $frB", FPGeneral,
724 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
727 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
728 def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst),
729 "stfiwx $frS, $dst", LdStUX,
730 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
731 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
732 "stfsx $frS, $dst", LdStUX,
733 [(store F4RC:$frS, xaddr:$dst)]>;
734 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
735 "stfdx $frS, $dst", LdStUX,
736 [(store F8RC:$frS, xaddr:$dst)]>;
739 // XL-Form instructions. condition register logical ops.
741 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
742 "mcrf $BF, $BFA", BrMCR>,
743 PPC970_DGroup_First, PPC970_Unit_CRU;
745 // XFX-Form instructions. Instructions that deal with SPRs.
747 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>,
748 PPC970_DGroup_First, PPC970_Unit_FXU;
749 let Pattern = [(PPCmtctr GPRC:$rS)] in {
750 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>,
751 PPC970_DGroup_First, PPC970_Unit_FXU;
754 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>,
755 PPC970_DGroup_First, PPC970_Unit_FXU;
756 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>,
757 PPC970_DGroup_First, PPC970_Unit_FXU;
759 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
760 // a GPR on the PPC970. As such, copies in and out have the same performance
761 // characteristics as an OR instruction.
762 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS),
763 "mtspr 256, $rS", IntGeneral>,
764 PPC970_DGroup_Single, PPC970_Unit_FXU;
765 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT),
766 "mfspr $rT, 256", IntGeneral>,
767 PPC970_DGroup_First, PPC970_Unit_FXU;
769 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
770 "mtcrf $FXM, $rS", BrMCRX>,
771 PPC970_MicroCode, PPC970_Unit_CRU;
772 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>,
773 PPC970_MicroCode, PPC970_Unit_CRU;
774 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
775 "mfcr $rT, $FXM", SprMFCR>,
776 PPC970_DGroup_First, PPC970_Unit_CRU;
778 let PPC970_Unit = 1 in { // FXU Operations.
780 // XO-Form instructions. Arithmetic instructions that can set overflow bit
782 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
783 "add $rT, $rA, $rB", IntGeneral,
784 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
785 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
786 "addc $rT, $rA, $rB", IntGeneral,
787 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
788 PPC970_DGroup_Cracked;
789 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
790 "adde $rT, $rA, $rB", IntGeneral,
791 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
792 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
793 "divw $rT, $rA, $rB", IntDivW,
794 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
795 PPC970_DGroup_First, PPC970_DGroup_Cracked;
796 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
797 "divwu $rT, $rA, $rB", IntDivW,
798 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
799 PPC970_DGroup_First, PPC970_DGroup_Cracked;
800 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
801 "mulhw $rT, $rA, $rB", IntMulHW,
802 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
803 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
804 "mulhwu $rT, $rA, $rB", IntMulHWU,
805 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
806 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
807 "mullw $rT, $rA, $rB", IntMulHW,
808 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
809 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
810 "subf $rT, $rA, $rB", IntGeneral,
811 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
812 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
813 "subfc $rT, $rA, $rB", IntGeneral,
814 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
815 PPC970_DGroup_Cracked;
816 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
817 "subfe $rT, $rA, $rB", IntGeneral,
818 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
819 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
820 "addme $rT, $rA", IntGeneral,
821 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
822 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
823 "addze $rT, $rA", IntGeneral,
824 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
825 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
826 "neg $rT, $rA", IntGeneral,
827 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
828 def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA),
829 "subfme $rT, $rA", IntGeneral,
830 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
831 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
832 "subfze $rT, $rA", IntGeneral,
833 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
836 // A-Form instructions. Most of the instructions executed in the FPU are of
839 let PPC970_Unit = 3 in { // FPU Operations.
840 def FMADD : AForm_1<63, 29,
841 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
842 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
843 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
845 Requires<[FPContractions]>;
846 def FMADDS : AForm_1<59, 29,
847 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
848 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
849 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
851 Requires<[FPContractions]>;
852 def FMSUB : AForm_1<63, 28,
853 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
854 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
855 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
857 Requires<[FPContractions]>;
858 def FMSUBS : AForm_1<59, 28,
859 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
860 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
861 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
863 Requires<[FPContractions]>;
864 def FNMADD : AForm_1<63, 31,
865 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
866 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
867 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
869 Requires<[FPContractions]>;
870 def FNMADDS : AForm_1<59, 31,
871 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
872 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
873 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
875 Requires<[FPContractions]>;
876 def FNMSUB : AForm_1<63, 30,
877 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
878 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
879 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
881 Requires<[FPContractions]>;
882 def FNMSUBS : AForm_1<59, 30,
883 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
884 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
885 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
887 Requires<[FPContractions]>;
888 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
889 // having 4 of these, force the comparison to always be an 8-byte double (code
890 // should use an FMRSD if the input comparison value really wants to be a float)
891 // and 4/8 byte forms for the result and operand type..
892 def FSELD : AForm_1<63, 23,
893 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
894 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
895 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
896 def FSELS : AForm_1<63, 23,
897 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
898 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
899 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
900 def FADD : AForm_2<63, 21,
901 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
902 "fadd $FRT, $FRA, $FRB", FPGeneral,
903 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
904 def FADDS : AForm_2<59, 21,
905 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
906 "fadds $FRT, $FRA, $FRB", FPGeneral,
907 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
908 def FDIV : AForm_2<63, 18,
909 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
910 "fdiv $FRT, $FRA, $FRB", FPDivD,
911 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
912 def FDIVS : AForm_2<59, 18,
913 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
914 "fdivs $FRT, $FRA, $FRB", FPDivS,
915 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
916 def FMUL : AForm_3<63, 25,
917 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
918 "fmul $FRT, $FRA, $FRB", FPFused,
919 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
920 def FMULS : AForm_3<59, 25,
921 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
922 "fmuls $FRT, $FRA, $FRB", FPGeneral,
923 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
924 def FSUB : AForm_2<63, 20,
925 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
926 "fsub $FRT, $FRA, $FRB", FPGeneral,
927 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
928 def FSUBS : AForm_2<59, 20,
929 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
930 "fsubs $FRT, $FRA, $FRB", FPGeneral,
931 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
934 let PPC970_Unit = 1 in { // FXU Operations.
935 // M-Form instructions. rotate and mask instructions.
937 let isTwoAddress = 1, isCommutable = 1 in {
938 // RLWIMI can be commuted if the rotate amount is zero.
939 def RLWIMI : MForm_2<20,
940 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
941 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
942 []>, PPC970_DGroup_Cracked;
944 def RLWINM : MForm_2<21,
945 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
946 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
948 def RLWINMo : MForm_2<21,
949 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
950 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
951 []>, isDOT, PPC970_DGroup_Cracked;
952 def RLWNM : MForm_2<23,
953 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
954 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
959 //===----------------------------------------------------------------------===//
960 // DWARF Pseudo Instructions
963 def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
964 "${:comment} .loc $file, $line, $col",
965 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
968 def DWARF_LABEL : Pseudo<(ops i32imm:$id),
969 "\n${:private}debug_loc$id:",
970 [(dwarf_label (i32 imm:$id))]>;
972 //===----------------------------------------------------------------------===//
973 // PowerPC Instruction Patterns
976 // Arbitrary immediate support. Implement in terms of LIS/ORI.
977 def : Pat<(i32 imm:$imm),
978 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
980 // Implement the 'not' operation with the NOR instruction.
981 def NOT : Pat<(not GPRC:$in),
982 (NOR GPRC:$in, GPRC:$in)>;
984 // ADD an arbitrary immediate.
985 def : Pat<(add GPRC:$in, imm:$imm),
986 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
987 // OR an arbitrary immediate.
988 def : Pat<(or GPRC:$in, imm:$imm),
989 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
990 // XOR an arbitrary immediate.
991 def : Pat<(xor GPRC:$in, imm:$imm),
992 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
994 def : Pat<(sub immSExt16:$imm, GPRC:$in),
995 (SUBFIC GPRC:$in, imm:$imm)>;
997 // Return void support.
998 def : Pat<(ret), (BLR)>;
1001 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1002 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1003 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1004 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1007 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1008 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1009 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1010 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1013 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1014 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1017 def : Pat<(PPCcall tglobaladdr:$dst),
1018 (BL tglobaladdr:$dst)>;
1019 def : Pat<(PPCcall texternalsym:$dst),
1020 (BL texternalsym:$dst)>;
1022 // Hi and Lo for Darwin Global Addresses.
1023 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1024 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1025 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1026 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1027 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1028 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1029 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1030 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1031 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1032 (ADDIS GPRC:$in, tconstpool:$g)>;
1033 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1034 (ADDIS GPRC:$in, tjumptable:$g)>;
1036 // Fused negative multiply subtract, alternate pattern
1037 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1038 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1039 Requires<[FPContractions]>;
1040 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1041 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1042 Requires<[FPContractions]>;
1044 // Standard shifts. These are represented separately from the real shifts above
1045 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1047 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1048 (SRAW GPRC:$rS, GPRC:$rB)>;
1049 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1050 (SRW GPRC:$rS, GPRC:$rB)>;
1051 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1052 (SLW GPRC:$rS, GPRC:$rB)>;
1054 def : Pat<(zextloadi1 iaddr:$src),
1056 def : Pat<(zextloadi1 xaddr:$src),
1058 def : Pat<(extloadi1 iaddr:$src),
1060 def : Pat<(extloadi1 xaddr:$src),
1062 def : Pat<(extloadi8 iaddr:$src),
1064 def : Pat<(extloadi8 xaddr:$src),
1066 def : Pat<(extloadi16 iaddr:$src),
1068 def : Pat<(extloadi16 xaddr:$src),
1070 def : Pat<(extloadf32 iaddr:$src),
1071 (FMRSD (LFS iaddr:$src))>;
1072 def : Pat<(extloadf32 xaddr:$src),
1073 (FMRSD (LFSX xaddr:$src))>;
1075 include "PPCInstrAltivec.td"
1076 include "PPCInstr64Bit.td"