1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
60 def tocentry32 : Operand<iPTR> {
61 let MIOperandInfo = (ops i32imm:$imm);
64 //===----------------------------------------------------------------------===//
65 // PowerPC specific DAG Nodes.
68 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
69 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
71 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
72 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
73 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
74 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
75 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
76 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
77 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
78 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
79 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
80 [SDNPHasChain, SDNPMayStore]>;
81 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
82 [SDNPHasChain, SDNPMayLoad]>;
83 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
84 [SDNPHasChain, SDNPMayLoad]>;
86 // Extract FPSCR (not modeled at the DAG level).
87 def PPCmffs : SDNode<"PPCISD::MFFS",
88 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
90 // Perform FADD in round-to-zero mode.
91 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
94 def PPCfsel : SDNode<"PPCISD::FSEL",
95 // Type constraint for fsel.
96 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
97 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
99 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
100 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
101 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
102 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
103 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
105 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
107 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
108 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
110 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
111 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
112 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
113 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
114 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
115 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
116 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
117 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
119 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
121 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
123 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
124 // amounts. These nodes are generated by the multi-precision shift code.
125 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
126 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
127 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
129 // These are target-independent nodes, but have target-specific formats.
130 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
131 [SDNPHasChain, SDNPOutGlue]>;
132 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
135 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
136 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
139 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
142 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
143 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
144 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
145 [SDNPHasChain, SDNPSideEffect,
146 SDNPInGlue, SDNPOutGlue]>;
147 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
149 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
150 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
153 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
154 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
156 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
157 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
159 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
160 SDTypeProfile<1, 1, [SDTCisInt<0>,
162 [SDNPHasChain, SDNPSideEffect]>;
163 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
164 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
165 [SDNPHasChain, SDNPSideEffect]>;
167 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
168 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
169 [SDNPHasChain, SDNPSideEffect]>;
171 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
172 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
174 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
175 [SDNPHasChain, SDNPOptInGlue]>;
177 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
178 [SDNPHasChain, SDNPMayLoad]>;
179 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
180 [SDNPHasChain, SDNPMayStore]>;
182 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
183 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
186 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
188 // Instructions to support atomic operations
189 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
190 [SDNPHasChain, SDNPMayLoad]>;
191 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
192 [SDNPHasChain, SDNPMayStore]>;
194 // Instructions to support medium and large code model
195 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
196 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
197 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
200 // Instructions to support dynamic alloca.
201 def SDTDynOp : SDTypeProfile<1, 2, []>;
202 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
204 //===----------------------------------------------------------------------===//
205 // PowerPC specific transformation functions and pattern fragments.
208 def SHL32 : SDNodeXForm<imm, [{
209 // Transformation function: 31 - imm
210 return getI32Imm(31 - N->getZExtValue());
213 def SRL32 : SDNodeXForm<imm, [{
214 // Transformation function: 32 - imm
215 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
218 def LO16 : SDNodeXForm<imm, [{
219 // Transformation function: get the low 16 bits.
220 return getI32Imm((unsigned short)N->getZExtValue());
223 def HI16 : SDNodeXForm<imm, [{
224 // Transformation function: shift the immediate value down into the low bits.
225 return getI32Imm((unsigned)N->getZExtValue() >> 16);
228 def HA16 : SDNodeXForm<imm, [{
229 // Transformation function: shift the immediate value down into the low bits.
230 signed int Val = N->getZExtValue();
231 return getI32Imm((Val - (signed short)Val) >> 16);
233 def MB : SDNodeXForm<imm, [{
234 // Transformation function: get the start bit of a mask
236 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
237 return getI32Imm(mb);
240 def ME : SDNodeXForm<imm, [{
241 // Transformation function: get the end bit of a mask
243 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
244 return getI32Imm(me);
246 def maskimm32 : PatLeaf<(imm), [{
247 // maskImm predicate - True if immediate is a run of ones.
249 if (N->getValueType(0) == MVT::i32)
250 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
255 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
256 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
257 // sign extended field. Used by instructions like 'addi'.
258 return (int32_t)Imm == (short)Imm;
260 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
261 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
262 // sign extended field. Used by instructions like 'addi'.
263 return (int64_t)Imm == (short)Imm;
265 def immZExt16 : PatLeaf<(imm), [{
266 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
267 // field. Used by instructions like 'ori'.
268 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
271 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
272 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
273 // identical in 32-bit mode, but in 64-bit mode, they return true if the
274 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
276 def imm16ShiftedZExt : PatLeaf<(imm), [{
277 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
278 // immediate are set. Used by instructions like 'xoris'.
279 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
282 def imm16ShiftedSExt : PatLeaf<(imm), [{
283 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
284 // immediate are set. Used by instructions like 'addis'. Identical to
285 // imm16ShiftedZExt in 32-bit mode.
286 if (N->getZExtValue() & 0xFFFF) return false;
287 if (N->getValueType(0) == MVT::i32)
289 // For 64-bit, make sure it is sext right.
290 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
293 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
294 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
295 // zero extended field.
296 return isUInt<32>(Imm);
299 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
300 // restricted memrix (4-aligned) constants are alignment sensitive. If these
301 // offsets are hidden behind TOC entries than the values of the lower-order
302 // bits cannot be checked directly. As a result, we need to also incorporate
303 // an alignment check into the relevant patterns.
305 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
306 return cast<LoadSDNode>(N)->getAlignment() >= 4;
308 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
309 (store node:$val, node:$ptr), [{
310 return cast<StoreSDNode>(N)->getAlignment() >= 4;
312 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
313 return cast<LoadSDNode>(N)->getAlignment() >= 4;
315 def aligned4pre_store : PatFrag<
316 (ops node:$val, node:$base, node:$offset),
317 (pre_store node:$val, node:$base, node:$offset), [{
318 return cast<StoreSDNode>(N)->getAlignment() >= 4;
321 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
322 return cast<LoadSDNode>(N)->getAlignment() < 4;
324 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
325 (store node:$val, node:$ptr), [{
326 return cast<StoreSDNode>(N)->getAlignment() < 4;
328 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
329 return cast<LoadSDNode>(N)->getAlignment() < 4;
332 //===----------------------------------------------------------------------===//
333 // PowerPC Flag Definitions.
335 class isPPC64 { bit PPC64 = 1; }
336 class isDOT { bit RC = 1; }
338 class RegConstraint<string C> {
339 string Constraints = C;
341 class NoEncode<string E> {
342 string DisableEncoding = E;
346 //===----------------------------------------------------------------------===//
347 // PowerPC Operand Definitions.
349 // In the default PowerPC assembler syntax, registers are specified simply
350 // by number, so they cannot be distinguished from immediate values (without
351 // looking at the opcode). This means that the default operand matching logic
352 // for the asm parser does not work, and we need to specify custom matchers.
353 // Since those can only be specified with RegisterOperand classes and not
354 // directly on the RegisterClass, all instructions patterns used by the asm
355 // parser need to use a RegisterOperand (instead of a RegisterClass) for
356 // all their register operands.
357 // For this purpose, we define one RegisterOperand for each RegisterClass,
358 // using the same name as the class, just in lower case.
360 def PPCRegGPRCAsmOperand : AsmOperandClass {
361 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
363 def gprc : RegisterOperand<GPRC> {
364 let ParserMatchClass = PPCRegGPRCAsmOperand;
366 def PPCRegG8RCAsmOperand : AsmOperandClass {
367 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
369 def g8rc : RegisterOperand<G8RC> {
370 let ParserMatchClass = PPCRegG8RCAsmOperand;
372 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
373 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
375 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
376 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
378 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
379 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
381 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
382 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
384 def PPCRegF8RCAsmOperand : AsmOperandClass {
385 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
387 def f8rc : RegisterOperand<F8RC> {
388 let ParserMatchClass = PPCRegF8RCAsmOperand;
390 def PPCRegF4RCAsmOperand : AsmOperandClass {
391 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
393 def f4rc : RegisterOperand<F4RC> {
394 let ParserMatchClass = PPCRegF4RCAsmOperand;
396 def PPCRegVRRCAsmOperand : AsmOperandClass {
397 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
399 def vrrc : RegisterOperand<VRRC> {
400 let ParserMatchClass = PPCRegVRRCAsmOperand;
402 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
403 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
405 def crbitrc : RegisterOperand<CRBITRC> {
406 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
408 def PPCRegCRRCAsmOperand : AsmOperandClass {
409 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
411 def crrc : RegisterOperand<CRRC> {
412 let ParserMatchClass = PPCRegCRRCAsmOperand;
415 def PPCU2ImmAsmOperand : AsmOperandClass {
416 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
417 let RenderMethod = "addImmOperands";
419 def u2imm : Operand<i32> {
420 let PrintMethod = "printU2ImmOperand";
421 let ParserMatchClass = PPCU2ImmAsmOperand;
424 def PPCU4ImmAsmOperand : AsmOperandClass {
425 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
426 let RenderMethod = "addImmOperands";
428 def u4imm : Operand<i32> {
429 let PrintMethod = "printU4ImmOperand";
430 let ParserMatchClass = PPCU4ImmAsmOperand;
432 def PPCS5ImmAsmOperand : AsmOperandClass {
433 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
434 let RenderMethod = "addImmOperands";
436 def s5imm : Operand<i32> {
437 let PrintMethod = "printS5ImmOperand";
438 let ParserMatchClass = PPCS5ImmAsmOperand;
439 let DecoderMethod = "decodeSImmOperand<5>";
441 def PPCU5ImmAsmOperand : AsmOperandClass {
442 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
443 let RenderMethod = "addImmOperands";
445 def u5imm : Operand<i32> {
446 let PrintMethod = "printU5ImmOperand";
447 let ParserMatchClass = PPCU5ImmAsmOperand;
448 let DecoderMethod = "decodeUImmOperand<5>";
450 def PPCU6ImmAsmOperand : AsmOperandClass {
451 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
452 let RenderMethod = "addImmOperands";
454 def u6imm : Operand<i32> {
455 let PrintMethod = "printU6ImmOperand";
456 let ParserMatchClass = PPCU6ImmAsmOperand;
457 let DecoderMethod = "decodeUImmOperand<6>";
459 def PPCS16ImmAsmOperand : AsmOperandClass {
460 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
461 let RenderMethod = "addImmOperands";
463 def s16imm : Operand<i32> {
464 let PrintMethod = "printS16ImmOperand";
465 let EncoderMethod = "getImm16Encoding";
466 let ParserMatchClass = PPCS16ImmAsmOperand;
467 let DecoderMethod = "decodeSImmOperand<16>";
469 def PPCU16ImmAsmOperand : AsmOperandClass {
470 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
471 let RenderMethod = "addImmOperands";
473 def u16imm : Operand<i32> {
474 let PrintMethod = "printU16ImmOperand";
475 let EncoderMethod = "getImm16Encoding";
476 let ParserMatchClass = PPCU16ImmAsmOperand;
477 let DecoderMethod = "decodeUImmOperand<16>";
479 def PPCS17ImmAsmOperand : AsmOperandClass {
480 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
481 let RenderMethod = "addImmOperands";
483 def s17imm : Operand<i32> {
484 // This operand type is used for addis/lis to allow the assembler parser
485 // to accept immediates in the range -65536..65535 for compatibility with
486 // the GNU assembler. The operand is treated as 16-bit otherwise.
487 let PrintMethod = "printS16ImmOperand";
488 let EncoderMethod = "getImm16Encoding";
489 let ParserMatchClass = PPCS17ImmAsmOperand;
490 let DecoderMethod = "decodeSImmOperand<16>";
492 def PPCDirectBrAsmOperand : AsmOperandClass {
493 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
494 let RenderMethod = "addBranchTargetOperands";
496 def directbrtarget : Operand<OtherVT> {
497 let PrintMethod = "printBranchOperand";
498 let EncoderMethod = "getDirectBrEncoding";
499 let ParserMatchClass = PPCDirectBrAsmOperand;
501 def absdirectbrtarget : Operand<OtherVT> {
502 let PrintMethod = "printAbsBranchOperand";
503 let EncoderMethod = "getAbsDirectBrEncoding";
504 let ParserMatchClass = PPCDirectBrAsmOperand;
506 def PPCCondBrAsmOperand : AsmOperandClass {
507 let Name = "CondBr"; let PredicateMethod = "isCondBr";
508 let RenderMethod = "addBranchTargetOperands";
510 def condbrtarget : Operand<OtherVT> {
511 let PrintMethod = "printBranchOperand";
512 let EncoderMethod = "getCondBrEncoding";
513 let ParserMatchClass = PPCCondBrAsmOperand;
515 def abscondbrtarget : Operand<OtherVT> {
516 let PrintMethod = "printAbsBranchOperand";
517 let EncoderMethod = "getAbsCondBrEncoding";
518 let ParserMatchClass = PPCCondBrAsmOperand;
520 def calltarget : Operand<iPTR> {
521 let PrintMethod = "printBranchOperand";
522 let EncoderMethod = "getDirectBrEncoding";
523 let ParserMatchClass = PPCDirectBrAsmOperand;
525 def abscalltarget : Operand<iPTR> {
526 let PrintMethod = "printAbsBranchOperand";
527 let EncoderMethod = "getAbsDirectBrEncoding";
528 let ParserMatchClass = PPCDirectBrAsmOperand;
530 def PPCCRBitMaskOperand : AsmOperandClass {
531 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
533 def crbitm: Operand<i8> {
534 let PrintMethod = "printcrbitm";
535 let EncoderMethod = "get_crbitm_encoding";
536 let DecoderMethod = "decodeCRBitMOperand";
537 let ParserMatchClass = PPCCRBitMaskOperand;
540 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
541 def PPCRegGxRCNoR0Operand : AsmOperandClass {
542 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
544 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
545 let ParserMatchClass = PPCRegGxRCNoR0Operand;
547 // A version of ptr_rc usable with the asm parser.
548 def PPCRegGxRCOperand : AsmOperandClass {
549 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
551 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
552 let ParserMatchClass = PPCRegGxRCOperand;
555 def PPCDispRIOperand : AsmOperandClass {
556 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
557 let RenderMethod = "addImmOperands";
559 def dispRI : Operand<iPTR> {
560 let ParserMatchClass = PPCDispRIOperand;
562 def PPCDispRIXOperand : AsmOperandClass {
563 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
564 let RenderMethod = "addImmOperands";
566 def dispRIX : Operand<iPTR> {
567 let ParserMatchClass = PPCDispRIXOperand;
570 def memri : Operand<iPTR> {
571 let PrintMethod = "printMemRegImm";
572 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
573 let EncoderMethod = "getMemRIEncoding";
574 let DecoderMethod = "decodeMemRIOperands";
576 def memrr : Operand<iPTR> {
577 let PrintMethod = "printMemRegReg";
578 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
580 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
581 let PrintMethod = "printMemRegImm";
582 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
583 let EncoderMethod = "getMemRIXEncoding";
584 let DecoderMethod = "decodeMemRIXOperands";
587 // A single-register address. This is used with the SjLj
588 // pseudo-instructions.
589 def memr : Operand<iPTR> {
590 let MIOperandInfo = (ops ptr_rc:$ptrreg);
592 def PPCTLSRegOperand : AsmOperandClass {
593 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
594 let RenderMethod = "addTLSRegOperands";
596 def tlsreg32 : Operand<i32> {
597 let EncoderMethod = "getTLSRegEncoding";
598 let ParserMatchClass = PPCTLSRegOperand;
600 def tlsgd32 : Operand<i32> {}
601 def tlscall32 : Operand<i32> {
602 let PrintMethod = "printTLSCall";
603 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
604 let EncoderMethod = "getTLSCallEncoding";
607 // PowerPC Predicate operand.
608 def pred : Operand<OtherVT> {
609 let PrintMethod = "printPredicateOperand";
610 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
613 // Define PowerPC specific addressing mode.
614 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
615 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
616 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
617 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
619 // The address in a single register. This is used with the SjLj
620 // pseudo-instructions.
621 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
623 /// This is just the offset part of iaddr, used for preinc.
624 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
626 //===----------------------------------------------------------------------===//
627 // PowerPC Instruction Predicate Definitions.
628 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
629 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
630 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
631 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
632 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
633 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
634 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
635 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
637 //===----------------------------------------------------------------------===//
638 // PowerPC Multiclass Definitions.
640 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
641 string asmbase, string asmstr, InstrItinClass itin,
643 let BaseName = asmbase in {
644 def NAME : XForm_6<opcode, xo, OOL, IOL,
645 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
646 pattern>, RecFormRel;
648 def o : XForm_6<opcode, xo, OOL, IOL,
649 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
650 []>, isDOT, RecFormRel;
654 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
655 string asmbase, string asmstr, InstrItinClass itin,
657 let BaseName = asmbase in {
658 let Defs = [CARRY] in
659 def NAME : XForm_6<opcode, xo, OOL, IOL,
660 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
661 pattern>, RecFormRel;
662 let Defs = [CARRY, CR0] in
663 def o : XForm_6<opcode, xo, OOL, IOL,
664 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
665 []>, isDOT, RecFormRel;
669 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
670 string asmbase, string asmstr, InstrItinClass itin,
672 let BaseName = asmbase in {
673 let Defs = [CARRY] in
674 def NAME : XForm_10<opcode, xo, OOL, IOL,
675 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
676 pattern>, RecFormRel;
677 let Defs = [CARRY, CR0] in
678 def o : XForm_10<opcode, xo, OOL, IOL,
679 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
680 []>, isDOT, RecFormRel;
684 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
685 string asmbase, string asmstr, InstrItinClass itin,
687 let BaseName = asmbase in {
688 def NAME : XForm_11<opcode, xo, OOL, IOL,
689 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
690 pattern>, RecFormRel;
692 def o : XForm_11<opcode, xo, OOL, IOL,
693 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
694 []>, isDOT, RecFormRel;
698 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
699 string asmbase, string asmstr, InstrItinClass itin,
701 let BaseName = asmbase in {
702 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
703 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
704 pattern>, RecFormRel;
706 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
707 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
708 []>, isDOT, RecFormRel;
712 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
713 string asmbase, string asmstr, InstrItinClass itin,
715 let BaseName = asmbase in {
716 let Defs = [CARRY] in
717 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
718 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
719 pattern>, RecFormRel;
720 let Defs = [CARRY, CR0] in
721 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
722 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
723 []>, isDOT, RecFormRel;
727 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
728 string asmbase, string asmstr, InstrItinClass itin,
730 let BaseName = asmbase in {
731 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
732 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
733 pattern>, RecFormRel;
735 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
736 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
737 []>, isDOT, RecFormRel;
741 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
742 string asmbase, string asmstr, InstrItinClass itin,
744 let BaseName = asmbase in {
745 let Defs = [CARRY] in
746 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
747 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
748 pattern>, RecFormRel;
749 let Defs = [CARRY, CR0] in
750 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
751 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
752 []>, isDOT, RecFormRel;
756 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
757 string asmbase, string asmstr, InstrItinClass itin,
759 let BaseName = asmbase in {
760 def NAME : MForm_2<opcode, OOL, IOL,
761 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
762 pattern>, RecFormRel;
764 def o : MForm_2<opcode, OOL, IOL,
765 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
766 []>, isDOT, RecFormRel;
770 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
771 string asmbase, string asmstr, InstrItinClass itin,
773 let BaseName = asmbase in {
774 def NAME : MDForm_1<opcode, xo, OOL, IOL,
775 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
776 pattern>, RecFormRel;
778 def o : MDForm_1<opcode, xo, OOL, IOL,
779 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
780 []>, isDOT, RecFormRel;
784 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
785 string asmbase, string asmstr, InstrItinClass itin,
787 let BaseName = asmbase in {
788 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
789 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
790 pattern>, RecFormRel;
792 def o : MDSForm_1<opcode, xo, OOL, IOL,
793 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
794 []>, isDOT, RecFormRel;
798 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
799 string asmbase, string asmstr, InstrItinClass itin,
801 let BaseName = asmbase in {
802 let Defs = [CARRY] in
803 def NAME : XSForm_1<opcode, xo, OOL, IOL,
804 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
805 pattern>, RecFormRel;
806 let Defs = [CARRY, CR0] in
807 def o : XSForm_1<opcode, xo, OOL, IOL,
808 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
809 []>, isDOT, RecFormRel;
813 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
814 string asmbase, string asmstr, InstrItinClass itin,
816 let BaseName = asmbase in {
817 def NAME : XForm_26<opcode, xo, OOL, IOL,
818 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
819 pattern>, RecFormRel;
821 def o : XForm_26<opcode, xo, OOL, IOL,
822 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
823 []>, isDOT, RecFormRel;
827 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
828 string asmbase, string asmstr, InstrItinClass itin,
830 let BaseName = asmbase in {
831 def NAME : XForm_28<opcode, xo, OOL, IOL,
832 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
833 pattern>, RecFormRel;
835 def o : XForm_28<opcode, xo, OOL, IOL,
836 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
837 []>, isDOT, RecFormRel;
841 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
842 string asmbase, string asmstr, InstrItinClass itin,
844 let BaseName = asmbase in {
845 def NAME : AForm_1<opcode, xo, OOL, IOL,
846 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
847 pattern>, RecFormRel;
849 def o : AForm_1<opcode, xo, OOL, IOL,
850 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
851 []>, isDOT, RecFormRel;
855 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
856 string asmbase, string asmstr, InstrItinClass itin,
858 let BaseName = asmbase in {
859 def NAME : AForm_2<opcode, xo, OOL, IOL,
860 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
861 pattern>, RecFormRel;
863 def o : AForm_2<opcode, xo, OOL, IOL,
864 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
865 []>, isDOT, RecFormRel;
869 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
870 string asmbase, string asmstr, InstrItinClass itin,
872 let BaseName = asmbase in {
873 def NAME : AForm_3<opcode, xo, OOL, IOL,
874 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
875 pattern>, RecFormRel;
877 def o : AForm_3<opcode, xo, OOL, IOL,
878 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
879 []>, isDOT, RecFormRel;
883 //===----------------------------------------------------------------------===//
884 // PowerPC Instruction Definitions.
886 // Pseudo-instructions:
888 let hasCtrlDep = 1 in {
889 let Defs = [R1], Uses = [R1] in {
890 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
891 [(callseq_start timm:$amt)]>;
892 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
893 [(callseq_end timm:$amt1, timm:$amt2)]>;
896 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
897 "UPDATE_VRSAVE $rD, $rS", []>;
900 let Defs = [R1], Uses = [R1] in
901 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
903 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
905 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
906 // instruction selection into a branch sequence.
907 let usesCustomInserter = 1, // Expanded after instruction selection.
908 PPC970_Single = 1 in {
909 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
910 // because either operand might become the first operand in an isel, and
911 // that operand cannot be r0.
912 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
913 gprc_nor0:$T, gprc_nor0:$F,
914 i32imm:$BROPC), "#SELECT_CC_I4",
916 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
917 g8rc_nox0:$T, g8rc_nox0:$F,
918 i32imm:$BROPC), "#SELECT_CC_I8",
920 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
921 i32imm:$BROPC), "#SELECT_CC_F4",
923 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
924 i32imm:$BROPC), "#SELECT_CC_F8",
926 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
927 i32imm:$BROPC), "#SELECT_CC_VRRC",
930 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
931 // register bit directly.
932 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
933 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
934 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
935 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
936 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
937 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
938 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
939 f4rc:$T, f4rc:$F), "#SELECT_F4",
940 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
941 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
942 f8rc:$T, f8rc:$F), "#SELECT_F8",
943 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
944 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
945 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
947 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
950 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
951 // scavenge a register for it.
952 let mayStore = 1 in {
953 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
955 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
959 // RESTORE_CR - Indicate that we're restoring the CR register (previously
960 // spilled), so we'll need to scavenge a register for it.
962 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
964 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
965 "#RESTORE_CRBIT", []>;
968 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
969 let isReturn = 1, Uses = [LR, RM] in
970 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
972 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
973 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
976 let isCodeGenOnly = 1 in {
977 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
978 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
981 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
982 "bcctr 12, $bi, 0", IIC_BrB, []>;
983 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
984 "bcctr 4, $bi, 0", IIC_BrB, []>;
990 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
993 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
994 let isBarrier = 1 in {
995 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
998 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
999 "ba $dst", IIC_BrB, []>;
1002 // BCC represents an arbitrary conditional branch on a predicate.
1003 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1004 // a two-value operand where a dag node expects two operands. :(
1005 let isCodeGenOnly = 1 in {
1006 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1007 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1008 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1009 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1010 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1012 let isReturn = 1, Uses = [LR, RM] in
1013 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1014 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1017 let isCodeGenOnly = 1 in {
1018 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1019 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1020 "bc 12, $bi, $dst">;
1022 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1023 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1026 let isReturn = 1, Uses = [LR, RM] in
1027 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1028 "bclr 12, $bi, 0", IIC_BrB, []>;
1029 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1030 "bclr 4, $bi, 0", IIC_BrB, []>;
1033 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1034 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1035 "bdzlr", IIC_BrB, []>;
1036 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1037 "bdnzlr", IIC_BrB, []>;
1038 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1039 "bdzlr+", IIC_BrB, []>;
1040 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1041 "bdnzlr+", IIC_BrB, []>;
1042 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1043 "bdzlr-", IIC_BrB, []>;
1044 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1045 "bdnzlr-", IIC_BrB, []>;
1048 let Defs = [CTR], Uses = [CTR] in {
1049 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1051 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1053 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1055 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1057 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1059 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1061 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1063 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1065 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1067 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1069 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1071 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1076 // The unconditional BCL used by the SjLj setjmp code.
1077 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1078 let Defs = [LR], Uses = [RM] in {
1079 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1080 "bcl 20, 31, $dst">;
1084 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1085 // Convenient aliases for call instructions
1086 let Uses = [RM] in {
1087 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1088 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1089 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1090 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1092 let isCodeGenOnly = 1 in {
1093 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1094 "bl $func", IIC_BrB, []>;
1095 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1096 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1097 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1098 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1100 def BCL : BForm_4<16, 12, 0, 1, (outs),
1101 (ins crbitrc:$bi, condbrtarget:$dst),
1102 "bcl 12, $bi, $dst">;
1103 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1104 (ins crbitrc:$bi, condbrtarget:$dst),
1105 "bcl 4, $bi, $dst">;
1108 let Uses = [CTR, RM] in {
1109 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1110 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1111 Requires<[In32BitMode]>;
1113 let isCodeGenOnly = 1 in {
1114 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1115 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1118 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1119 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1120 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1121 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1124 let Uses = [LR, RM] in {
1125 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1126 "blrl", IIC_BrB, []>;
1128 let isCodeGenOnly = 1 in {
1129 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1130 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1133 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1134 "bclrl 12, $bi, 0", IIC_BrB, []>;
1135 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1136 "bclrl 4, $bi, 0", IIC_BrB, []>;
1139 let Defs = [CTR], Uses = [CTR, RM] in {
1140 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1142 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1144 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1146 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1148 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1150 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1152 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1154 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1156 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1158 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1160 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1162 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1165 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1166 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1167 "bdzlrl", IIC_BrB, []>;
1168 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1169 "bdnzlrl", IIC_BrB, []>;
1170 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1171 "bdzlrl+", IIC_BrB, []>;
1172 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1173 "bdnzlrl+", IIC_BrB, []>;
1174 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1175 "bdzlrl-", IIC_BrB, []>;
1176 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1177 "bdnzlrl-", IIC_BrB, []>;
1181 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1182 def TCRETURNdi :Pseudo< (outs),
1183 (ins calltarget:$dst, i32imm:$offset),
1184 "#TC_RETURNd $dst $offset",
1188 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1189 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1190 "#TC_RETURNa $func $offset",
1191 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1193 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1194 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1195 "#TC_RETURNr $dst $offset",
1199 let isCodeGenOnly = 1 in {
1201 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1202 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1203 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1204 []>, Requires<[In32BitMode]>;
1206 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1207 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1208 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1212 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1213 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1214 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1220 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1222 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1223 "#EH_SJLJ_SETJMP32",
1224 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1225 Requires<[In32BitMode]>;
1226 let isTerminator = 1 in
1227 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1228 "#EH_SJLJ_LONGJMP32",
1229 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1230 Requires<[In32BitMode]>;
1233 let isBranch = 1, isTerminator = 1 in {
1234 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1235 "#EH_SjLj_Setup\t$dst", []>;
1239 let PPC970_Unit = 7 in {
1240 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1241 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1244 // DCB* instructions.
1245 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1246 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1247 PPC970_DGroup_Single;
1248 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1249 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1250 PPC970_DGroup_Single;
1251 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1252 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1253 PPC970_DGroup_Single;
1254 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1255 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1256 PPC970_DGroup_Single;
1257 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1258 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1259 PPC970_DGroup_Single;
1260 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1261 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1262 PPC970_DGroup_Single;
1263 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1264 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1265 PPC970_DGroup_Single;
1266 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1267 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1268 PPC970_DGroup_Single;
1270 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1271 (DCBT xoaddr:$dst)>;
1273 // Atomic operations
1274 let usesCustomInserter = 1 in {
1275 let Defs = [CR0] in {
1276 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1277 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1278 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1279 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1280 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1281 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1282 def ATOMIC_LOAD_AND_I8 : Pseudo<
1283 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1284 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1285 def ATOMIC_LOAD_OR_I8 : Pseudo<
1286 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1287 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1288 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1289 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1290 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1291 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1292 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1293 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1294 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1295 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1296 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1297 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1298 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1299 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1300 def ATOMIC_LOAD_AND_I16 : Pseudo<
1301 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1302 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1303 def ATOMIC_LOAD_OR_I16 : Pseudo<
1304 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1305 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1306 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1307 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1308 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1309 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1310 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1311 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1312 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1313 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1314 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1315 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1316 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1317 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1318 def ATOMIC_LOAD_AND_I32 : Pseudo<
1319 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1320 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1321 def ATOMIC_LOAD_OR_I32 : Pseudo<
1322 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1323 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1324 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1325 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1326 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1327 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1328 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1329 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1331 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1332 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1333 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1334 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1335 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1336 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1337 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1338 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1339 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1341 def ATOMIC_SWAP_I8 : Pseudo<
1342 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1343 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1344 def ATOMIC_SWAP_I16 : Pseudo<
1345 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1346 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1347 def ATOMIC_SWAP_I32 : Pseudo<
1348 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1349 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1353 // Instructions to support atomic operations
1354 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1355 "lwarx $rD, $src", IIC_LdStLWARX,
1356 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1359 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1360 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1361 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1364 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1365 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1367 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1368 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1369 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1370 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1371 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1372 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1373 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1374 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1376 //===----------------------------------------------------------------------===//
1377 // PPC32 Load Instructions.
1380 // Unindexed (r+i) Loads.
1381 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1382 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1383 "lbz $rD, $src", IIC_LdStLoad,
1384 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1385 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1386 "lha $rD, $src", IIC_LdStLHA,
1387 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1388 PPC970_DGroup_Cracked;
1389 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1390 "lhz $rD, $src", IIC_LdStLoad,
1391 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1392 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1393 "lwz $rD, $src", IIC_LdStLoad,
1394 [(set i32:$rD, (load iaddr:$src))]>;
1396 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1397 "lfs $rD, $src", IIC_LdStLFD,
1398 [(set f32:$rD, (load iaddr:$src))]>;
1399 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1400 "lfd $rD, $src", IIC_LdStLFD,
1401 [(set f64:$rD, (load iaddr:$src))]>;
1404 // Unindexed (r+i) Loads with Update (preinc).
1405 let mayLoad = 1, neverHasSideEffects = 1 in {
1406 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1407 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1408 []>, RegConstraint<"$addr.reg = $ea_result">,
1409 NoEncode<"$ea_result">;
1411 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1412 "lhau $rD, $addr", IIC_LdStLHAU,
1413 []>, RegConstraint<"$addr.reg = $ea_result">,
1414 NoEncode<"$ea_result">;
1416 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1417 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1418 []>, RegConstraint<"$addr.reg = $ea_result">,
1419 NoEncode<"$ea_result">;
1421 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1422 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1423 []>, RegConstraint<"$addr.reg = $ea_result">,
1424 NoEncode<"$ea_result">;
1426 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1427 "lfsu $rD, $addr", IIC_LdStLFDU,
1428 []>, RegConstraint<"$addr.reg = $ea_result">,
1429 NoEncode<"$ea_result">;
1431 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1432 "lfdu $rD, $addr", IIC_LdStLFDU,
1433 []>, RegConstraint<"$addr.reg = $ea_result">,
1434 NoEncode<"$ea_result">;
1437 // Indexed (r+r) Loads with Update (preinc).
1438 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1440 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1441 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1442 NoEncode<"$ea_result">;
1444 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1446 "lhaux $rD, $addr", IIC_LdStLHAUX,
1447 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1448 NoEncode<"$ea_result">;
1450 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1452 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1453 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1454 NoEncode<"$ea_result">;
1456 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1458 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1459 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1460 NoEncode<"$ea_result">;
1462 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1464 "lfsux $rD, $addr", IIC_LdStLFDUX,
1465 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1466 NoEncode<"$ea_result">;
1468 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1470 "lfdux $rD, $addr", IIC_LdStLFDUX,
1471 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1472 NoEncode<"$ea_result">;
1476 // Indexed (r+r) Loads.
1478 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1479 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1480 "lbzx $rD, $src", IIC_LdStLoad,
1481 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1482 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1483 "lhax $rD, $src", IIC_LdStLHA,
1484 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1485 PPC970_DGroup_Cracked;
1486 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1487 "lhzx $rD, $src", IIC_LdStLoad,
1488 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1489 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1490 "lwzx $rD, $src", IIC_LdStLoad,
1491 [(set i32:$rD, (load xaddr:$src))]>;
1494 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1495 "lhbrx $rD, $src", IIC_LdStLoad,
1496 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1497 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1498 "lwbrx $rD, $src", IIC_LdStLoad,
1499 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1501 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1502 "lfsx $frD, $src", IIC_LdStLFD,
1503 [(set f32:$frD, (load xaddr:$src))]>;
1504 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1505 "lfdx $frD, $src", IIC_LdStLFD,
1506 [(set f64:$frD, (load xaddr:$src))]>;
1508 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1509 "lfiwax $frD, $src", IIC_LdStLFD,
1510 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1511 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1512 "lfiwzx $frD, $src", IIC_LdStLFD,
1513 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1517 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1518 "lmw $rD, $src", IIC_LdStLMW, []>;
1520 //===----------------------------------------------------------------------===//
1521 // PPC32 Store Instructions.
1524 // Unindexed (r+i) Stores.
1525 let PPC970_Unit = 2 in {
1526 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1527 "stb $rS, $src", IIC_LdStStore,
1528 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1529 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1530 "sth $rS, $src", IIC_LdStStore,
1531 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1532 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1533 "stw $rS, $src", IIC_LdStStore,
1534 [(store i32:$rS, iaddr:$src)]>;
1535 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1536 "stfs $rS, $dst", IIC_LdStSTFD,
1537 [(store f32:$rS, iaddr:$dst)]>;
1538 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1539 "stfd $rS, $dst", IIC_LdStSTFD,
1540 [(store f64:$rS, iaddr:$dst)]>;
1543 // Unindexed (r+i) Stores with Update (preinc).
1544 let PPC970_Unit = 2, mayStore = 1 in {
1545 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1546 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1547 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1548 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1549 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1550 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1551 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1552 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1553 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1554 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1555 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1556 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1557 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1558 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1559 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1562 // Patterns to match the pre-inc stores. We can't put the patterns on
1563 // the instruction definitions directly as ISel wants the address base
1564 // and offset to be separate operands, not a single complex operand.
1565 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1566 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1567 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1568 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1569 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1570 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1571 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1572 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1573 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1574 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1576 // Indexed (r+r) Stores.
1577 let PPC970_Unit = 2 in {
1578 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1579 "stbx $rS, $dst", IIC_LdStStore,
1580 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1581 PPC970_DGroup_Cracked;
1582 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1583 "sthx $rS, $dst", IIC_LdStStore,
1584 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1585 PPC970_DGroup_Cracked;
1586 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1587 "stwx $rS, $dst", IIC_LdStStore,
1588 [(store i32:$rS, xaddr:$dst)]>,
1589 PPC970_DGroup_Cracked;
1591 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1592 "sthbrx $rS, $dst", IIC_LdStStore,
1593 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1594 PPC970_DGroup_Cracked;
1595 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1596 "stwbrx $rS, $dst", IIC_LdStStore,
1597 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1598 PPC970_DGroup_Cracked;
1600 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1601 "stfiwx $frS, $dst", IIC_LdStSTFD,
1602 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1604 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1605 "stfsx $frS, $dst", IIC_LdStSTFD,
1606 [(store f32:$frS, xaddr:$dst)]>;
1607 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1608 "stfdx $frS, $dst", IIC_LdStSTFD,
1609 [(store f64:$frS, xaddr:$dst)]>;
1612 // Indexed (r+r) Stores with Update (preinc).
1613 let PPC970_Unit = 2, mayStore = 1 in {
1614 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1615 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1616 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1617 PPC970_DGroup_Cracked;
1618 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1619 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1620 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1621 PPC970_DGroup_Cracked;
1622 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1623 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1624 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1625 PPC970_DGroup_Cracked;
1626 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1627 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1628 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1629 PPC970_DGroup_Cracked;
1630 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1631 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1632 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1633 PPC970_DGroup_Cracked;
1636 // Patterns to match the pre-inc stores. We can't put the patterns on
1637 // the instruction definitions directly as ISel wants the address base
1638 // and offset to be separate operands, not a single complex operand.
1639 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1640 (STBUX $rS, $ptrreg, $ptroff)>;
1641 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1642 (STHUX $rS, $ptrreg, $ptroff)>;
1643 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1644 (STWUX $rS, $ptrreg, $ptroff)>;
1645 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1646 (STFSUX $rS, $ptrreg, $ptroff)>;
1647 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1648 (STFDUX $rS, $ptrreg, $ptroff)>;
1651 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1652 "stmw $rS, $dst", IIC_LdStLMW, []>;
1654 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1655 "sync $L", IIC_LdStSync, []>, Requires<[IsNotBookE]>;
1657 let isCodeGenOnly = 1 in {
1658 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1659 "msync", IIC_LdStSync, []>, Requires<[IsBookE]> {
1664 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[IsNotBookE]>;
1665 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[IsBookE]>;
1667 //===----------------------------------------------------------------------===//
1668 // PPC32 Arithmetic Instructions.
1671 let PPC970_Unit = 1 in { // FXU Operations.
1672 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1673 "addi $rD, $rA, $imm", IIC_IntSimple,
1674 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1675 let BaseName = "addic" in {
1676 let Defs = [CARRY] in
1677 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1678 "addic $rD, $rA, $imm", IIC_IntGeneral,
1679 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1680 RecFormRel, PPC970_DGroup_Cracked;
1681 let Defs = [CARRY, CR0] in
1682 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1683 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1684 []>, isDOT, RecFormRel;
1686 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1687 "addis $rD, $rA, $imm", IIC_IntSimple,
1688 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1689 let isCodeGenOnly = 1 in
1690 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1691 "la $rD, $sym($rA)", IIC_IntGeneral,
1692 [(set i32:$rD, (add i32:$rA,
1693 (PPClo tglobaladdr:$sym, 0)))]>;
1694 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1695 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1696 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1697 let Defs = [CARRY] in
1698 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1699 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1700 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1702 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1703 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1704 "li $rD, $imm", IIC_IntSimple,
1705 [(set i32:$rD, imm32SExt16:$imm)]>;
1706 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1707 "lis $rD, $imm", IIC_IntSimple,
1708 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1712 let PPC970_Unit = 1 in { // FXU Operations.
1713 let Defs = [CR0] in {
1714 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1715 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1716 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1718 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1719 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1720 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1723 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1724 "ori $dst, $src1, $src2", IIC_IntSimple,
1725 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1726 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1727 "oris $dst, $src1, $src2", IIC_IntSimple,
1728 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1729 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1730 "xori $dst, $src1, $src2", IIC_IntSimple,
1731 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1732 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1733 "xoris $dst, $src1, $src2", IIC_IntSimple,
1734 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1736 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1738 let isCodeGenOnly = 1 in {
1739 // The POWER6 and POWER7 have special group-terminating nops.
1740 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1741 "ori 1, 1, 0", IIC_IntSimple, []>;
1742 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1743 "ori 2, 2, 0", IIC_IntSimple, []>;
1746 let isCompare = 1, neverHasSideEffects = 1 in {
1747 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1748 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1749 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1750 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1754 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1755 let isCommutable = 1 in {
1756 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1757 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1758 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1759 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1760 "and", "$rA, $rS, $rB", IIC_IntSimple,
1761 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1763 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1764 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1765 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1766 let isCommutable = 1 in {
1767 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1768 "or", "$rA, $rS, $rB", IIC_IntSimple,
1769 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1770 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1771 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1772 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1774 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1775 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1776 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1777 let isCommutable = 1 in {
1778 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1779 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1780 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1781 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1782 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1783 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1785 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1786 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1787 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1788 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1789 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1790 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1791 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1792 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1793 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1796 let PPC970_Unit = 1 in { // FXU Operations.
1797 let neverHasSideEffects = 1 in {
1798 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1799 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1800 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1801 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1802 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1803 [(set i32:$rA, (ctlz i32:$rS))]>;
1804 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1805 "extsb", "$rA, $rS", IIC_IntSimple,
1806 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1807 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1808 "extsh", "$rA, $rS", IIC_IntSimple,
1809 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1811 let isCompare = 1, neverHasSideEffects = 1 in {
1812 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1813 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1814 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1815 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1818 let PPC970_Unit = 3 in { // FPU Operations.
1819 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1820 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1821 let isCompare = 1, neverHasSideEffects = 1 in {
1822 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1823 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1824 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1825 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1826 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1829 let Uses = [RM] in {
1830 let neverHasSideEffects = 1 in {
1831 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1832 "fctiw", "$frD, $frB", IIC_FPGeneral,
1834 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1835 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1836 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1838 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1839 "frsp", "$frD, $frB", IIC_FPGeneral,
1840 [(set f32:$frD, (fround f64:$frB))]>;
1842 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1843 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1844 "frin", "$frD, $frB", IIC_FPGeneral,
1845 [(set f64:$frD, (frnd f64:$frB))]>;
1846 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1847 "frin", "$frD, $frB", IIC_FPGeneral,
1848 [(set f32:$frD, (frnd f32:$frB))]>;
1851 let neverHasSideEffects = 1 in {
1852 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1853 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1854 "frip", "$frD, $frB", IIC_FPGeneral,
1855 [(set f64:$frD, (fceil f64:$frB))]>;
1856 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1857 "frip", "$frD, $frB", IIC_FPGeneral,
1858 [(set f32:$frD, (fceil f32:$frB))]>;
1859 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1860 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1861 "friz", "$frD, $frB", IIC_FPGeneral,
1862 [(set f64:$frD, (ftrunc f64:$frB))]>;
1863 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1864 "friz", "$frD, $frB", IIC_FPGeneral,
1865 [(set f32:$frD, (ftrunc f32:$frB))]>;
1866 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1867 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1868 "frim", "$frD, $frB", IIC_FPGeneral,
1869 [(set f64:$frD, (ffloor f64:$frB))]>;
1870 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1871 "frim", "$frD, $frB", IIC_FPGeneral,
1872 [(set f32:$frD, (ffloor f32:$frB))]>;
1874 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1875 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1876 [(set f64:$frD, (fsqrt f64:$frB))]>;
1877 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1878 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1879 [(set f32:$frD, (fsqrt f32:$frB))]>;
1884 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1885 /// often coalesced away and we don't want the dispatch group builder to think
1886 /// that they will fill slots (which could cause the load of a LSU reject to
1887 /// sneak into a d-group with a store).
1888 let neverHasSideEffects = 1 in
1889 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1890 "fmr", "$frD, $frB", IIC_FPGeneral,
1891 []>, // (set f32:$frD, f32:$frB)
1894 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1895 // These are artificially split into two different forms, for 4/8 byte FP.
1896 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1897 "fabs", "$frD, $frB", IIC_FPGeneral,
1898 [(set f32:$frD, (fabs f32:$frB))]>;
1899 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1900 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1901 "fabs", "$frD, $frB", IIC_FPGeneral,
1902 [(set f64:$frD, (fabs f64:$frB))]>;
1903 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1904 "fnabs", "$frD, $frB", IIC_FPGeneral,
1905 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1906 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1907 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1908 "fnabs", "$frD, $frB", IIC_FPGeneral,
1909 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1910 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1911 "fneg", "$frD, $frB", IIC_FPGeneral,
1912 [(set f32:$frD, (fneg f32:$frB))]>;
1913 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1914 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1915 "fneg", "$frD, $frB", IIC_FPGeneral,
1916 [(set f64:$frD, (fneg f64:$frB))]>;
1918 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1919 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1920 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1921 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1922 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1923 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1924 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1926 // Reciprocal estimates.
1927 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1928 "fre", "$frD, $frB", IIC_FPGeneral,
1929 [(set f64:$frD, (PPCfre f64:$frB))]>;
1930 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1931 "fres", "$frD, $frB", IIC_FPGeneral,
1932 [(set f32:$frD, (PPCfre f32:$frB))]>;
1933 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1934 "frsqrte", "$frD, $frB", IIC_FPGeneral,
1935 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1936 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1937 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
1938 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1941 // XL-Form instructions. condition register logical ops.
1943 let neverHasSideEffects = 1 in
1944 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1945 "mcrf $BF, $BFA", IIC_BrMCR>,
1946 PPC970_DGroup_First, PPC970_Unit_CRU;
1948 let isCommutable = 1 in {
1949 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
1950 (ins crbitrc:$CRA, crbitrc:$CRB),
1951 "crand $CRD, $CRA, $CRB", IIC_BrCR,
1952 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
1954 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
1955 (ins crbitrc:$CRA, crbitrc:$CRB),
1956 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
1957 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
1959 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
1960 (ins crbitrc:$CRA, crbitrc:$CRB),
1961 "cror $CRD, $CRA, $CRB", IIC_BrCR,
1962 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
1964 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
1965 (ins crbitrc:$CRA, crbitrc:$CRB),
1966 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
1967 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
1969 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
1970 (ins crbitrc:$CRA, crbitrc:$CRB),
1971 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
1972 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
1974 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
1975 (ins crbitrc:$CRA, crbitrc:$CRB),
1976 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
1977 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
1980 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
1981 (ins crbitrc:$CRA, crbitrc:$CRB),
1982 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
1983 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
1985 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
1986 (ins crbitrc:$CRA, crbitrc:$CRB),
1987 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
1988 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
1990 let isCodeGenOnly = 1 in {
1991 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
1992 "creqv $dst, $dst, $dst", IIC_BrCR,
1993 [(set i1:$dst, 1)]>;
1995 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
1996 "crxor $dst, $dst, $dst", IIC_BrCR,
1997 [(set i1:$dst, 0)]>;
1999 let Defs = [CR1EQ], CRD = 6 in {
2000 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2001 "creqv 6, 6, 6", IIC_BrCR,
2004 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2005 "crxor 6, 6, 6", IIC_BrCR,
2010 // XFX-Form instructions. Instructions that deal with SPRs.
2013 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2014 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2015 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2016 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2018 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2019 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2021 let Uses = [CTR] in {
2022 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2023 "mfctr $rT", IIC_SprMFSPR>,
2024 PPC970_DGroup_First, PPC970_Unit_FXU;
2026 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2027 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2028 "mtctr $rS", IIC_SprMTSPR>,
2029 PPC970_DGroup_First, PPC970_Unit_FXU;
2031 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2032 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2033 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2034 "mtctr $rS", IIC_SprMTSPR>,
2035 PPC970_DGroup_First, PPC970_Unit_FXU;
2038 let Defs = [LR] in {
2039 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2040 "mtlr $rS", IIC_SprMTSPR>,
2041 PPC970_DGroup_First, PPC970_Unit_FXU;
2043 let Uses = [LR] in {
2044 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2045 "mflr $rT", IIC_SprMFSPR>,
2046 PPC970_DGroup_First, PPC970_Unit_FXU;
2049 let isCodeGenOnly = 1 in {
2050 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2051 // like a GPR on the PPC970. As such, copies in and out have the same
2052 // performance characteristics as an OR instruction.
2053 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2054 "mtspr 256, $rS", IIC_IntGeneral>,
2055 PPC970_DGroup_Single, PPC970_Unit_FXU;
2056 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2057 "mfspr $rT, 256", IIC_IntGeneral>,
2058 PPC970_DGroup_First, PPC970_Unit_FXU;
2060 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2061 (outs VRSAVERC:$reg), (ins gprc:$rS),
2062 "mtspr 256, $rS", IIC_IntGeneral>,
2063 PPC970_DGroup_Single, PPC970_Unit_FXU;
2064 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2065 (ins VRSAVERC:$reg),
2066 "mfspr $rT, 256", IIC_IntGeneral>,
2067 PPC970_DGroup_First, PPC970_Unit_FXU;
2070 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2071 // so we'll need to scavenge a register for it.
2073 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2074 "#SPILL_VRSAVE", []>;
2076 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2077 // spilled), so we'll need to scavenge a register for it.
2079 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2080 "#RESTORE_VRSAVE", []>;
2082 let neverHasSideEffects = 1 in {
2083 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2084 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2085 PPC970_DGroup_First, PPC970_Unit_CRU;
2087 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2088 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2089 PPC970_MicroCode, PPC970_Unit_CRU;
2091 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2092 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2093 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2094 PPC970_DGroup_First, PPC970_Unit_CRU;
2096 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2097 "mfcr $rT", IIC_SprMFCR>,
2098 PPC970_MicroCode, PPC970_Unit_CRU;
2099 } // neverHasSideEffects = 1
2101 // Pseudo instruction to perform FADD in round-to-zero mode.
2102 let usesCustomInserter = 1, Uses = [RM] in {
2103 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2104 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2107 // The above pseudo gets expanded to make use of the following instructions
2108 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2109 let Uses = [RM], Defs = [RM] in {
2110 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2111 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2112 PPC970_DGroup_Single, PPC970_Unit_FPU;
2113 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2114 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2115 PPC970_DGroup_Single, PPC970_Unit_FPU;
2116 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2117 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2118 PPC970_DGroup_Single, PPC970_Unit_FPU;
2120 let Uses = [RM] in {
2121 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2122 "mffs $rT", IIC_IntMFFS,
2123 [(set f64:$rT, (PPCmffs))]>,
2124 PPC970_DGroup_Single, PPC970_Unit_FPU;
2128 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
2129 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2130 let isCommutable = 1 in
2131 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2132 "add", "$rT, $rA, $rB", IIC_IntSimple,
2133 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2134 let isCodeGenOnly = 1 in
2135 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2136 "add $rT, $rA, $rB", IIC_IntSimple,
2137 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2138 let isCommutable = 1 in
2139 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2140 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2141 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2142 PPC970_DGroup_Cracked;
2144 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2145 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2146 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2147 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2148 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2149 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2150 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2151 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2152 let isCommutable = 1 in {
2153 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2154 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2155 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2156 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2157 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2158 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2159 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2160 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2161 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2163 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2164 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2165 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2166 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2167 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2168 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2169 PPC970_DGroup_Cracked;
2170 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2171 "neg", "$rT, $rA", IIC_IntSimple,
2172 [(set i32:$rT, (ineg i32:$rA))]>;
2173 let Uses = [CARRY] in {
2174 let isCommutable = 1 in
2175 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2176 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2177 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2178 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2179 "addme", "$rT, $rA", IIC_IntGeneral,
2180 [(set i32:$rT, (adde i32:$rA, -1))]>;
2181 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2182 "addze", "$rT, $rA", IIC_IntGeneral,
2183 [(set i32:$rT, (adde i32:$rA, 0))]>;
2184 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2185 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2186 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2187 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2188 "subfme", "$rT, $rA", IIC_IntGeneral,
2189 [(set i32:$rT, (sube -1, i32:$rA))]>;
2190 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2191 "subfze", "$rT, $rA", IIC_IntGeneral,
2192 [(set i32:$rT, (sube 0, i32:$rA))]>;
2196 // A-Form instructions. Most of the instructions executed in the FPU are of
2199 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
2200 let Uses = [RM] in {
2201 let isCommutable = 1 in {
2202 defm FMADD : AForm_1r<63, 29,
2203 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2204 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2205 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2206 defm FMADDS : AForm_1r<59, 29,
2207 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2208 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2209 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2210 defm FMSUB : AForm_1r<63, 28,
2211 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2212 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2214 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2215 defm FMSUBS : AForm_1r<59, 28,
2216 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2217 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2219 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2220 defm FNMADD : AForm_1r<63, 31,
2221 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2222 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2224 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2225 defm FNMADDS : AForm_1r<59, 31,
2226 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2227 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2229 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2230 defm FNMSUB : AForm_1r<63, 30,
2231 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2232 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2233 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2234 (fneg f64:$FRB))))]>;
2235 defm FNMSUBS : AForm_1r<59, 30,
2236 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2237 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2238 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2239 (fneg f32:$FRB))))]>;
2242 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2243 // having 4 of these, force the comparison to always be an 8-byte double (code
2244 // should use an FMRSD if the input comparison value really wants to be a float)
2245 // and 4/8 byte forms for the result and operand type..
2246 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2247 defm FSELD : AForm_1r<63, 23,
2248 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2249 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2250 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2251 defm FSELS : AForm_1r<63, 23,
2252 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2253 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2254 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2255 let Uses = [RM] in {
2256 let isCommutable = 1 in {
2257 defm FADD : AForm_2r<63, 21,
2258 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2259 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2260 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2261 defm FADDS : AForm_2r<59, 21,
2262 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2263 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2264 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2266 defm FDIV : AForm_2r<63, 18,
2267 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2268 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2269 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2270 defm FDIVS : AForm_2r<59, 18,
2271 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2272 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2273 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2274 let isCommutable = 1 in {
2275 defm FMUL : AForm_3r<63, 25,
2276 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2277 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2278 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2279 defm FMULS : AForm_3r<59, 25,
2280 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2281 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2282 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2284 defm FSUB : AForm_2r<63, 20,
2285 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2286 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2287 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2288 defm FSUBS : AForm_2r<59, 20,
2289 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2290 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2291 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2295 let neverHasSideEffects = 1 in {
2296 let PPC970_Unit = 1 in { // FXU Operations.
2298 def ISEL : AForm_4<31, 15,
2299 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2300 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
2304 let PPC970_Unit = 1 in { // FXU Operations.
2305 // M-Form instructions. rotate and mask instructions.
2307 let isCommutable = 1 in {
2308 // RLWIMI can be commuted if the rotate amount is zero.
2309 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2310 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2311 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2312 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2313 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2315 let BaseName = "rlwinm" in {
2316 def RLWINM : MForm_2<21,
2317 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2318 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2321 def RLWINMo : MForm_2<21,
2322 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2323 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2324 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2326 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2327 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2328 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2331 } // neverHasSideEffects = 1
2333 //===----------------------------------------------------------------------===//
2334 // PowerPC Instruction Patterns
2337 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2338 def : Pat<(i32 imm:$imm),
2339 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2341 // Implement the 'not' operation with the NOR instruction.
2342 def i32not : OutPatFrag<(ops node:$in),
2344 def : Pat<(not i32:$in),
2347 // ADD an arbitrary immediate.
2348 def : Pat<(add i32:$in, imm:$imm),
2349 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2350 // OR an arbitrary immediate.
2351 def : Pat<(or i32:$in, imm:$imm),
2352 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2353 // XOR an arbitrary immediate.
2354 def : Pat<(xor i32:$in, imm:$imm),
2355 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2357 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2358 (SUBFIC $in, imm:$imm)>;
2361 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2362 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2363 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2364 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2367 def : Pat<(rotl i32:$in, i32:$sh),
2368 (RLWNM $in, $sh, 0, 31)>;
2369 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2370 (RLWINM $in, imm:$imm, 0, 31)>;
2373 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2374 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2377 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2378 (BL tglobaladdr:$dst)>;
2379 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2380 (BL texternalsym:$dst)>;
2383 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2384 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2386 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2387 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2389 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2390 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2394 // Hi and Lo for Darwin Global Addresses.
2395 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2396 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2397 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2398 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2399 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2400 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2401 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2402 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2403 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2404 (ADDIS $in, tglobaltlsaddr:$g)>;
2405 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2406 (ADDI $in, tglobaltlsaddr:$g)>;
2407 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2408 (ADDIS $in, tglobaladdr:$g)>;
2409 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2410 (ADDIS $in, tconstpool:$g)>;
2411 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2412 (ADDIS $in, tjumptable:$g)>;
2413 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2414 (ADDIS $in, tblockaddress:$g)>;
2416 // Support for thread-local storage.
2417 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2418 [(set i32:$rD, (PPCppc32GOT))]>;
2420 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2421 // This uses two output registers, the first as the real output, the second as a
2422 // temporary register, used internally in code generation.
2423 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2424 []>, NoEncode<"$rT">;
2426 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2429 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2430 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2431 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2433 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2436 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2437 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2440 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2441 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2444 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2445 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2448 (PPCgetTlsldAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2449 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2452 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2453 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2456 (PPCaddisDtprelHA i32:$reg,
2457 tglobaltlsaddr:$disp))]>;
2459 // Support for Position-independent code
2460 def LWZtoc: Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2463 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2464 // Get Global (GOT) Base Register offset, from the word immediately preceding
2465 // the function label.
2466 def GetGBRO: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#GetGBRO", []>;
2467 // Update the Global(GOT) Base Register with the above offset.
2468 def UpdateGBR: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2471 // Standard shifts. These are represented separately from the real shifts above
2472 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2474 def : Pat<(sra i32:$rS, i32:$rB),
2476 def : Pat<(srl i32:$rS, i32:$rB),
2478 def : Pat<(shl i32:$rS, i32:$rB),
2481 def : Pat<(zextloadi1 iaddr:$src),
2483 def : Pat<(zextloadi1 xaddr:$src),
2485 def : Pat<(extloadi1 iaddr:$src),
2487 def : Pat<(extloadi1 xaddr:$src),
2489 def : Pat<(extloadi8 iaddr:$src),
2491 def : Pat<(extloadi8 xaddr:$src),
2493 def : Pat<(extloadi16 iaddr:$src),
2495 def : Pat<(extloadi16 xaddr:$src),
2497 def : Pat<(f64 (extloadf32 iaddr:$src)),
2498 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2499 def : Pat<(f64 (extloadf32 xaddr:$src)),
2500 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2502 def : Pat<(f64 (fextend f32:$src)),
2503 (COPY_TO_REGCLASS $src, F8RC)>;
2505 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[IsNotBookE]>;
2506 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[IsBookE]>;
2508 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2509 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2510 (FNMSUB $A, $C, $B)>;
2511 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2512 (FNMSUB $A, $C, $B)>;
2513 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2514 (FNMSUBS $A, $C, $B)>;
2515 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2516 (FNMSUBS $A, $C, $B)>;
2518 // FCOPYSIGN's operand types need not agree.
2519 def : Pat<(fcopysign f64:$frB, f32:$frA),
2520 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2521 def : Pat<(fcopysign f32:$frB, f64:$frA),
2522 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2524 include "PPCInstrAltivec.td"
2525 include "PPCInstrSPE.td"
2526 include "PPCInstr64Bit.td"
2527 include "PPCInstrVSX.td"
2529 def crnot : OutPatFrag<(ops node:$in),
2531 def : Pat<(not i1:$in),
2534 // Patterns for arithmetic i1 operations.
2535 def : Pat<(add i1:$a, i1:$b),
2537 def : Pat<(sub i1:$a, i1:$b),
2539 def : Pat<(mul i1:$a, i1:$b),
2542 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2543 // (-1 is used to mean all bits set).
2544 def : Pat<(i1 -1), (CRSET)>;
2546 // i1 extensions, implemented in terms of isel.
2547 def : Pat<(i32 (zext i1:$in)),
2548 (SELECT_I4 $in, (LI 1), (LI 0))>;
2549 def : Pat<(i32 (sext i1:$in)),
2550 (SELECT_I4 $in, (LI -1), (LI 0))>;
2552 def : Pat<(i64 (zext i1:$in)),
2553 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2554 def : Pat<(i64 (sext i1:$in)),
2555 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2557 // FIXME: We should choose either a zext or a sext based on other constants
2559 def : Pat<(i32 (anyext i1:$in)),
2560 (SELECT_I4 $in, (LI 1), (LI 0))>;
2561 def : Pat<(i64 (anyext i1:$in)),
2562 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2564 // match setcc on i1 variables.
2565 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2567 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2569 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2571 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2573 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2575 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2577 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2579 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2581 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2583 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2586 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2587 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2588 // floating-point types.
2590 multiclass CRNotPat<dag pattern, dag result> {
2591 def : Pat<pattern, (crnot result)>;
2592 def : Pat<(not pattern), result>;
2594 // We can also fold the crnot into an extension:
2595 def : Pat<(i32 (zext pattern)),
2596 (SELECT_I4 result, (LI 0), (LI 1))>;
2597 def : Pat<(i32 (sext pattern)),
2598 (SELECT_I4 result, (LI 0), (LI -1))>;
2600 // We can also fold the crnot into an extension:
2601 def : Pat<(i64 (zext pattern)),
2602 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2603 def : Pat<(i64 (sext pattern)),
2604 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2606 // FIXME: We should choose either a zext or a sext based on other constants
2608 def : Pat<(i32 (anyext pattern)),
2609 (SELECT_I4 result, (LI 0), (LI 1))>;
2611 def : Pat<(i64 (anyext pattern)),
2612 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2615 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2616 // we need to write imm:$imm in the output patterns below, not just $imm, or
2617 // else the resulting matcher will not correctly add the immediate operand
2618 // (making it a register operand instead).
2621 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2622 OutPatFrag rfrag, OutPatFrag rfrag8> {
2623 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2625 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2627 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2628 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2629 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2630 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2632 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2634 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2636 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2637 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2638 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2639 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2642 // Note that we do all inversions below with i(32|64)not, instead of using
2643 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2644 // has 2-cycle latency.
2646 defm : ExtSetCCPat<SETEQ,
2647 PatFrag<(ops node:$in, node:$cc),
2648 (setcc $in, 0, $cc)>,
2649 OutPatFrag<(ops node:$in),
2650 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2651 OutPatFrag<(ops node:$in),
2652 (RLDICL (CNTLZD $in), 58, 63)> >;
2654 defm : ExtSetCCPat<SETNE,
2655 PatFrag<(ops node:$in, node:$cc),
2656 (setcc $in, 0, $cc)>,
2657 OutPatFrag<(ops node:$in),
2658 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2659 OutPatFrag<(ops node:$in),
2660 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2662 defm : ExtSetCCPat<SETLT,
2663 PatFrag<(ops node:$in, node:$cc),
2664 (setcc $in, 0, $cc)>,
2665 OutPatFrag<(ops node:$in),
2666 (RLWINM $in, 1, 31, 31)>,
2667 OutPatFrag<(ops node:$in),
2668 (RLDICL $in, 1, 63)> >;
2670 defm : ExtSetCCPat<SETGE,
2671 PatFrag<(ops node:$in, node:$cc),
2672 (setcc $in, 0, $cc)>,
2673 OutPatFrag<(ops node:$in),
2674 (RLWINM (i32not $in), 1, 31, 31)>,
2675 OutPatFrag<(ops node:$in),
2676 (RLDICL (i64not $in), 1, 63)> >;
2678 defm : ExtSetCCPat<SETGT,
2679 PatFrag<(ops node:$in, node:$cc),
2680 (setcc $in, 0, $cc)>,
2681 OutPatFrag<(ops node:$in),
2682 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2683 OutPatFrag<(ops node:$in),
2684 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2686 defm : ExtSetCCPat<SETLE,
2687 PatFrag<(ops node:$in, node:$cc),
2688 (setcc $in, 0, $cc)>,
2689 OutPatFrag<(ops node:$in),
2690 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2691 OutPatFrag<(ops node:$in),
2692 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2694 defm : ExtSetCCPat<SETLT,
2695 PatFrag<(ops node:$in, node:$cc),
2696 (setcc $in, -1, $cc)>,
2697 OutPatFrag<(ops node:$in),
2698 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2699 OutPatFrag<(ops node:$in),
2700 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2702 defm : ExtSetCCPat<SETGE,
2703 PatFrag<(ops node:$in, node:$cc),
2704 (setcc $in, -1, $cc)>,
2705 OutPatFrag<(ops node:$in),
2706 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2707 OutPatFrag<(ops node:$in),
2708 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2710 defm : ExtSetCCPat<SETGT,
2711 PatFrag<(ops node:$in, node:$cc),
2712 (setcc $in, -1, $cc)>,
2713 OutPatFrag<(ops node:$in),
2714 (RLWINM (i32not $in), 1, 31, 31)>,
2715 OutPatFrag<(ops node:$in),
2716 (RLDICL (i64not $in), 1, 63)> >;
2718 defm : ExtSetCCPat<SETLE,
2719 PatFrag<(ops node:$in, node:$cc),
2720 (setcc $in, -1, $cc)>,
2721 OutPatFrag<(ops node:$in),
2722 (RLWINM $in, 1, 31, 31)>,
2723 OutPatFrag<(ops node:$in),
2724 (RLDICL $in, 1, 63)> >;
2727 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2728 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2729 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2730 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2731 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2732 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2733 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2734 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2735 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2736 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2737 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2738 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2740 // For non-equality comparisons, the default code would materialize the
2741 // constant, then compare against it, like this:
2743 // ori r2, r2, 22136
2746 // Since we are just comparing for equality, we can emit this instead:
2747 // xoris r0,r3,0x1234
2748 // cmplwi cr0,r0,0x5678
2751 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2752 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2753 (LO16 imm:$imm)), sub_eq)>;
2755 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2756 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2757 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2758 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2759 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2760 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2761 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2762 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2763 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2764 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2765 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2766 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2768 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2769 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2770 (LO16 imm:$imm)), sub_eq)>;
2772 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
2773 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2774 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2775 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2776 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2777 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2778 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
2779 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2780 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2781 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2783 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2784 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2785 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
2786 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2787 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2788 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2789 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
2790 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2791 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2792 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2795 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
2796 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2797 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2798 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2799 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2800 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2801 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
2802 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2803 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
2804 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2805 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
2806 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2808 // For non-equality comparisons, the default code would materialize the
2809 // constant, then compare against it, like this:
2811 // ori r2, r2, 22136
2814 // Since we are just comparing for equality, we can emit this instead:
2815 // xoris r0,r3,0x1234
2816 // cmpldi cr0,r0,0x5678
2819 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
2820 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2821 (LO16 imm:$imm)), sub_eq)>;
2823 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
2824 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2825 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
2826 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2827 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
2828 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2829 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
2830 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2831 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
2832 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2833 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
2834 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2836 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
2837 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2838 (LO16 imm:$imm)), sub_eq)>;
2840 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
2841 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2842 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
2843 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2844 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
2845 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2846 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
2847 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2848 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
2849 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2851 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
2852 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2853 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
2854 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2855 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
2856 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2857 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
2858 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2859 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
2860 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2863 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
2864 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2865 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
2866 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2867 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
2868 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2869 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
2870 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2871 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
2872 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2873 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
2874 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2875 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
2876 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2878 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
2879 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2880 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
2881 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2882 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
2883 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2884 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
2885 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2886 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
2887 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2888 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
2889 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2890 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
2891 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2894 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
2895 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2896 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
2897 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2898 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
2899 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2900 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
2901 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2902 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
2903 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2904 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
2905 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2906 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
2907 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2909 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
2910 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2911 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
2912 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2913 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
2914 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2915 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
2916 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2917 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
2918 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2919 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
2920 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2921 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
2922 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2924 // match select on i1 variables:
2925 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
2926 (CROR (CRAND $cond , $tval),
2927 (CRAND (crnot $cond), $fval))>;
2929 // match selectcc on i1 variables:
2930 // select (lhs == rhs), tval, fval is:
2931 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
2932 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
2933 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
2934 (CRAND (CRORC $lhs, $rhs), $fval))>;
2935 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
2936 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
2937 (CRAND (CRANDC $lhs, $rhs), $fval))>;
2938 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
2939 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
2940 (CRAND (CRXOR $lhs, $rhs), $fval))>;
2941 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
2942 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
2943 (CRAND (CRANDC $rhs, $lhs), $fval))>;
2944 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
2945 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
2946 (CRAND (CRORC $rhs, $lhs), $fval))>;
2947 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
2948 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
2949 (CRAND (CRXOR $lhs, $rhs), $tval))>;
2951 // match selectcc on i1 variables with non-i1 output.
2952 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
2953 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
2954 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
2955 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
2956 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
2957 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
2958 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
2959 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
2960 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
2961 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
2962 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
2963 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
2965 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
2966 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
2967 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
2968 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
2969 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
2970 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
2971 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
2972 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
2973 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
2974 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
2975 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
2976 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
2978 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
2979 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
2980 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
2981 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
2982 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
2983 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
2984 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
2985 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
2986 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
2987 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
2988 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
2989 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
2991 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
2992 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
2993 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
2994 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
2995 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
2996 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
2997 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
2998 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
2999 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3000 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3001 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3002 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3004 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3005 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3006 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3007 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3008 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3009 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3010 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3011 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3012 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3013 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3014 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3015 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3017 let usesCustomInserter = 1 in {
3018 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3020 [(set i1:$dst, (trunc (not i32:$in)))]>;
3021 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3023 [(set i1:$dst, (trunc i32:$in))]>;
3025 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3027 [(set i1:$dst, (trunc (not i64:$in)))]>;
3028 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3030 [(set i1:$dst, (trunc i64:$in))]>;
3033 def : Pat<(i1 (not (trunc i32:$in))),
3034 (ANDIo_1_EQ_BIT $in)>;
3035 def : Pat<(i1 (not (trunc i64:$in))),
3036 (ANDIo_1_EQ_BIT8 $in)>;
3038 //===----------------------------------------------------------------------===//
3039 // PowerPC Instructions used for assembler/disassembler only
3042 // FIXME: For B=0 or B > 8, the registers following RT are used.
3043 // WARNING: Do not add patterns for this instruction without fixing this.
3044 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3045 "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3047 // FIXME: For B=0 or B > 8, the registers following RT are used.
3048 // WARNING: Do not add patterns for this instruction without fixing this.
3049 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3050 "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3052 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3053 "isync", IIC_SprISYNC, []>;
3055 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3056 "icbi $src", IIC_LdStICBI, []>;
3058 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3059 "eieio", IIC_LdStLoad, []>;
3061 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3062 "wait $L", IIC_LdStLoad, []>;
3064 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3065 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3067 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3068 "mtsr $SR, $RS", IIC_SprMTSR>;
3070 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3071 "mfsr $RS, $SR", IIC_SprMFSR>;
3073 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3074 "mtsrin $RS, $RB", IIC_SprMTSR>;
3076 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3077 "mfsrin $RS, $RB", IIC_SprMFSR>;
3079 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3080 "mtmsr $RS, $L", IIC_SprMTMSR>;
3082 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3083 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3087 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3088 Requires<[IsBookE]> {
3092 let Inst{21-30} = 163;
3095 def DCI: I<31, (outs), (ins u4imm:$CT), "dci $CT", IIC_LdStLoad>,
3096 Requires<[IsPPC4xx]> {
3099 let Inst{7-10} = CT;
3100 let Inst{21-30} = 454;
3103 def ICI: I<31, (outs), (ins u4imm:$CT), "ici $CT", IIC_LdStLoad>,
3104 Requires<[IsPPC4xx]> {
3107 let Inst{7-10} = CT;
3108 let Inst{21-30} = 966;
3111 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3112 "mfmsr $RT", IIC_SprMFMSR, []>;
3114 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3115 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3117 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3118 "slbie $RB", IIC_SprSLBIE, []>;
3120 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3121 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3123 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3124 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3126 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3128 def TLBIA : XForm_0<31, 370, (outs), (ins),
3129 "tlbia", IIC_SprTLBIA, []>;
3131 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3132 "tlbsync", IIC_SprTLBSYNC, []>;
3134 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3135 "tlbiel $RB", IIC_SprTLBIEL, []>;
3137 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3138 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3139 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3140 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3142 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3143 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3145 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3146 IIC_LdStLoad>, Requires<[IsBookE]>;
3148 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3149 IIC_LdStLoad>, Requires<[IsBookE]>;
3151 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3152 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3154 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3155 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3157 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3158 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3160 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3161 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3163 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3164 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3165 Requires<[IsPPC4xx]>;
3166 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3167 (ins gprc:$RST, gprc:$A, gprc:$B),
3168 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3169 Requires<[IsPPC4xx]>, isDOT;
3171 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3173 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3174 Requires<[IsBookE]>;
3175 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3176 Requires<[IsBookE]>;
3178 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3180 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3183 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3184 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3185 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3186 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3188 //===----------------------------------------------------------------------===//
3189 // PowerPC Assembler Instruction Aliases
3192 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3193 // These are aliases that require C++ handling to convert to the target
3194 // instruction, while InstAliases can be handled directly by tblgen.
3195 class PPCAsmPseudo<string asm, dag iops>
3197 let Namespace = "PPC";
3198 bit PPC64 = 0; // Default value, override with isPPC64
3200 let OutOperandList = (outs);
3201 let InOperandList = iops;
3203 let AsmString = asm;
3204 let isAsmParserOnly = 1;
3208 def : InstAlias<"sc", (SC 0)>;
3210 def : InstAlias<"sync", (SYNC 0)>, Requires<[IsNotBookE]>;
3211 def : InstAlias<"msync", (SYNC 0)>, Requires<[IsNotBookE]>;
3212 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[IsNotBookE]>;
3213 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[IsNotBookE]>;
3215 def : InstAlias<"wait", (WAIT 0)>;
3216 def : InstAlias<"waitrsv", (WAIT 1)>;
3217 def : InstAlias<"waitimpl", (WAIT 2)>;
3219 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3221 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3222 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3223 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3224 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3226 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3227 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3229 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3230 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3232 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3233 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3235 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3236 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3238 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3239 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3241 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3242 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3244 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3245 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3247 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3248 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3250 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3251 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3253 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3254 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3256 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3257 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3259 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3260 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3262 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3263 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3265 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3266 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3267 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3269 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3270 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3272 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3273 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3274 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3275 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3277 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3279 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3280 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3282 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3283 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3285 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3287 foreach BATR = 0-3 in {
3288 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3289 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3290 Requires<[IsPPC6xx]>;
3291 def : InstAlias<"mfdbatu $Rx, "#BATR,
3292 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3293 Requires<[IsPPC6xx]>;
3294 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3295 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3296 Requires<[IsPPC6xx]>;
3297 def : InstAlias<"mfdbatl $Rx, "#BATR,
3298 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3299 Requires<[IsPPC6xx]>;
3300 def : InstAlias<"mtibatu "#BATR#", $Rx",
3301 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3302 Requires<[IsPPC6xx]>;
3303 def : InstAlias<"mfibatu $Rx, "#BATR,
3304 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3305 Requires<[IsPPC6xx]>;
3306 def : InstAlias<"mtibatl "#BATR#", $Rx",
3307 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3308 Requires<[IsPPC6xx]>;
3309 def : InstAlias<"mfibatl $Rx, "#BATR,
3310 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3311 Requires<[IsPPC6xx]>;
3314 foreach BR = 0-7 in {
3315 def : InstAlias<"mfbr"#BR#" $Rx",
3316 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3317 Requires<[IsPPC4xx]>;
3318 def : InstAlias<"mtbr"#BR#" $Rx",
3319 (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3320 Requires<[IsPPC4xx]>;
3323 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3324 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3326 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3327 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3329 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3330 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3332 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3333 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3335 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3336 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3338 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3339 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3341 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3343 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3344 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3345 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3346 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3347 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3348 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3349 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3350 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3352 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3353 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3354 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3355 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3357 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3358 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3360 foreach SPRG = 0-3 in {
3361 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3362 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3363 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3364 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3366 foreach SPRG = 4-7 in {
3367 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3368 Requires<[IsBookE]>;
3369 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3370 Requires<[IsBookE]>;
3371 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3372 Requires<[IsBookE]>;
3373 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3374 Requires<[IsBookE]>;
3377 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3379 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3380 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3382 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3384 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3385 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3387 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3388 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3389 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3390 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3392 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3394 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3395 Requires<[IsPPC4xx]>;
3396 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3397 Requires<[IsPPC4xx]>;
3398 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3399 Requires<[IsPPC4xx]>;
3400 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3401 Requires<[IsPPC4xx]>;
3403 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3404 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3405 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3406 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3407 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3408 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3409 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3410 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3411 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3412 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3413 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3414 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3415 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3416 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3417 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3418 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3419 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3420 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3421 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3422 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3423 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3424 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3425 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3426 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3427 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3428 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3429 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3430 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3431 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3432 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3433 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3434 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3435 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3436 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3437 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3438 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3440 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3441 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3442 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3443 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3444 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3445 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3447 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3448 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3449 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3450 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3451 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3452 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3453 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3454 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3455 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3456 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3457 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3458 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3459 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3460 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3461 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3462 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3463 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3464 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3465 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3466 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3467 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3468 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3469 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3470 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3471 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3472 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3473 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3474 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3475 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3476 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3477 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3478 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3480 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3481 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3482 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3483 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3484 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3485 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3487 // These generic branch instruction forms are used for the assembler parser only.
3488 // Defs and Uses are conservative, since we don't know the BO value.
3489 let PPC970_Unit = 7 in {
3490 let Defs = [CTR], Uses = [CTR, RM] in {
3491 def gBC : BForm_3<16, 0, 0, (outs),
3492 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3493 "bc $bo, $bi, $dst">;
3494 def gBCA : BForm_3<16, 1, 0, (outs),
3495 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3496 "bca $bo, $bi, $dst">;
3498 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3499 def gBCL : BForm_3<16, 0, 1, (outs),
3500 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3501 "bcl $bo, $bi, $dst">;
3502 def gBCLA : BForm_3<16, 1, 1, (outs),
3503 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3504 "bcla $bo, $bi, $dst">;
3506 let Defs = [CTR], Uses = [CTR, LR, RM] in
3507 def gBCLR : XLForm_2<19, 16, 0, (outs),
3508 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3509 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3510 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3511 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3512 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3513 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3514 let Defs = [CTR], Uses = [CTR, LR, RM] in
3515 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3516 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3517 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3518 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3519 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3520 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3521 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3523 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3524 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3525 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3526 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3528 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3529 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3530 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3531 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3532 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3533 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3534 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3536 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3537 : BranchSimpleMnemonic1<name, pm, bo> {
3538 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3539 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3541 defm : BranchSimpleMnemonic2<"t", "", 12>;
3542 defm : BranchSimpleMnemonic2<"f", "", 4>;
3543 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3544 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3545 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3546 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3547 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3548 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3549 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3550 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3552 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3553 def : InstAlias<"b"#name#pm#" $cc, $dst",
3554 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3555 def : InstAlias<"b"#name#pm#" $dst",
3556 (BCC bibo, CR0, condbrtarget:$dst)>;
3558 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3559 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3560 def : InstAlias<"b"#name#"a"#pm#" $dst",
3561 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3563 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3564 (BCCLR bibo, crrc:$cc)>;
3565 def : InstAlias<"b"#name#"lr"#pm,
3568 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3569 (BCCCTR bibo, crrc:$cc)>;
3570 def : InstAlias<"b"#name#"ctr"#pm,
3571 (BCCCTR bibo, CR0)>;
3573 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3574 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3575 def : InstAlias<"b"#name#"l"#pm#" $dst",
3576 (BCCL bibo, CR0, condbrtarget:$dst)>;
3578 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3579 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3580 def : InstAlias<"b"#name#"la"#pm#" $dst",
3581 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3583 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3584 (BCCLRL bibo, crrc:$cc)>;
3585 def : InstAlias<"b"#name#"lrl"#pm,
3586 (BCCLRL bibo, CR0)>;
3588 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3589 (BCCCTRL bibo, crrc:$cc)>;
3590 def : InstAlias<"b"#name#"ctrl"#pm,
3591 (BCCCTRL bibo, CR0)>;
3593 multiclass BranchExtendedMnemonic<string name, int bibo> {
3594 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3595 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3596 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3598 defm : BranchExtendedMnemonic<"lt", 12>;
3599 defm : BranchExtendedMnemonic<"gt", 44>;
3600 defm : BranchExtendedMnemonic<"eq", 76>;
3601 defm : BranchExtendedMnemonic<"un", 108>;
3602 defm : BranchExtendedMnemonic<"so", 108>;
3603 defm : BranchExtendedMnemonic<"ge", 4>;
3604 defm : BranchExtendedMnemonic<"nl", 4>;
3605 defm : BranchExtendedMnemonic<"le", 36>;
3606 defm : BranchExtendedMnemonic<"ng", 36>;
3607 defm : BranchExtendedMnemonic<"ne", 68>;
3608 defm : BranchExtendedMnemonic<"nu", 100>;
3609 defm : BranchExtendedMnemonic<"ns", 100>;
3611 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3612 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3613 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3614 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3615 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3616 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3617 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3618 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3620 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3621 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3622 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3623 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3624 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3625 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3626 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3627 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3629 multiclass TrapExtendedMnemonic<string name, int to> {
3630 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3631 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3632 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3633 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3635 defm : TrapExtendedMnemonic<"lt", 16>;
3636 defm : TrapExtendedMnemonic<"le", 20>;
3637 defm : TrapExtendedMnemonic<"eq", 4>;
3638 defm : TrapExtendedMnemonic<"ge", 12>;
3639 defm : TrapExtendedMnemonic<"gt", 8>;
3640 defm : TrapExtendedMnemonic<"nl", 12>;
3641 defm : TrapExtendedMnemonic<"ne", 24>;
3642 defm : TrapExtendedMnemonic<"ng", 20>;
3643 defm : TrapExtendedMnemonic<"llt", 2>;
3644 defm : TrapExtendedMnemonic<"lle", 6>;
3645 defm : TrapExtendedMnemonic<"lge", 5>;
3646 defm : TrapExtendedMnemonic<"lgt", 1>;
3647 defm : TrapExtendedMnemonic<"lnl", 5>;
3648 defm : TrapExtendedMnemonic<"lng", 6>;
3649 defm : TrapExtendedMnemonic<"u", 31>;