1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific DAG Nodes.
21 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
22 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
23 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
25 def PPCfsel : SDNode<"PPCISD::FSEL",
26 // Type constraint for fsel.
27 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
28 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
30 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
31 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
32 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
33 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
35 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
36 // amounts. These nodes are generated by the multi-precision shift code.
37 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
38 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
40 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
41 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
42 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
44 // These are target-independent nodes, but have target-specific formats.
45 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
46 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
47 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
49 def SDT_PPCRetFlag : SDTypeProfile<0, 1, [ SDTCisVT<0, FlagVT>]>;
50 def retflag : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag, [SDNPHasChain]>;
52 //===----------------------------------------------------------------------===//
53 // PowerPC specific transformation functions and pattern fragments.
56 def SHL32 : SDNodeXForm<imm, [{
57 // Transformation function: 31 - imm
58 return getI32Imm(31 - N->getValue());
61 def SHL64 : SDNodeXForm<imm, [{
62 // Transformation function: 63 - imm
63 return getI32Imm(63 - N->getValue());
66 def SRL32 : SDNodeXForm<imm, [{
67 // Transformation function: 32 - imm
68 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
71 def SRL64 : SDNodeXForm<imm, [{
72 // Transformation function: 64 - imm
73 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
76 def LO16 : SDNodeXForm<imm, [{
77 // Transformation function: get the low 16 bits.
78 return getI32Imm((unsigned short)N->getValue());
81 def HI16 : SDNodeXForm<imm, [{
82 // Transformation function: shift the immediate value down into the low bits.
83 return getI32Imm((unsigned)N->getValue() >> 16);
86 def HA16 : SDNodeXForm<imm, [{
87 // Transformation function: shift the immediate value down into the low bits.
88 signed int Val = N->getValue();
89 return getI32Imm((Val - (signed short)Val) >> 16);
93 def immSExt16 : PatLeaf<(imm), [{
94 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
95 // field. Used by instructions like 'addi'.
96 return (int)N->getValue() == (short)N->getValue();
98 def immZExt16 : PatLeaf<(imm), [{
99 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
100 // field. Used by instructions like 'ori'.
101 return (unsigned)N->getValue() == (unsigned short)N->getValue();
104 def imm16Shifted : PatLeaf<(imm), [{
105 // imm16Shifted predicate - True if only bits in the top 16-bits of the
106 // immediate are set. Used by instructions like 'addis'.
107 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
111 // Example of a legalize expander: Only for PPC64.
112 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
113 [(set f64:$tmp , (FCTIDZ f64:$src)),
114 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
115 (store f64:$tmp, i32:$tmpFI),
116 (set i64:$dst, (load i32:$tmpFI))],
120 //===----------------------------------------------------------------------===//
121 // PowerPC Flag Definitions.
123 class isPPC64 { bit PPC64 = 1; }
124 class isVMX { bit VMX = 1; }
126 list<Register> Defs = [CR0];
132 //===----------------------------------------------------------------------===//
133 // PowerPC Operand Definitions.
135 def u5imm : Operand<i32> {
136 let PrintMethod = "printU5ImmOperand";
138 def u6imm : Operand<i32> {
139 let PrintMethod = "printU6ImmOperand";
141 def s16imm : Operand<i32> {
142 let PrintMethod = "printS16ImmOperand";
144 def u16imm : Operand<i32> {
145 let PrintMethod = "printU16ImmOperand";
147 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
148 let PrintMethod = "printS16X4ImmOperand";
150 def target : Operand<OtherVT> {
151 let PrintMethod = "printBranchOperand";
153 def calltarget : Operand<i32> {
154 let PrintMethod = "printCallOperand";
156 def aaddr : Operand<i32> {
157 let PrintMethod = "printAbsAddrOperand";
159 def piclabel: Operand<i32> {
160 let PrintMethod = "printPICLabel";
162 def symbolHi: Operand<i32> {
163 let PrintMethod = "printSymbolHi";
165 def symbolLo: Operand<i32> {
166 let PrintMethod = "printSymbolLo";
168 def crbitm: Operand<i8> {
169 let PrintMethod = "printcrbitm";
172 def memri : Operand<i32> {
173 let PrintMethod = "printMemRegImm";
174 let NumMIOperands = 2;
175 let MIOperandInfo = (ops i32imm, GPRC);
177 def memrr : Operand<i32> {
178 let PrintMethod = "printMemRegReg";
179 let NumMIOperands = 2;
180 let MIOperandInfo = (ops GPRC, GPRC);
183 // Define X86 specific addressing mode.
184 def iaddr : ComplexPattern<i32, 2, "SelectAddrImm", []>;
185 def xaddr : ComplexPattern<i32, 2, "SelectAddrIdx", []>;
186 def xoaddr : ComplexPattern<i32, 2, "SelectAddrIdxOnly",[]>;
188 //===----------------------------------------------------------------------===//
189 // PowerPC Instruction Predicate Definitions.
190 def FPContractions : Predicate<"!NoExcessFPPrecision">;
192 //===----------------------------------------------------------------------===//
193 // PowerPC Instruction Definitions.
195 // Pseudo-instructions:
196 def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
198 let isLoad = 1, hasCtrlDep = 1 in {
199 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
200 "; ADJCALLSTACKDOWN",
201 [(callseq_start imm:$amt)]>;
202 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
204 [(callseq_end imm:$amt)]>;
206 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
207 [(set GPRC:$rD, (undef))]>;
208 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8",
209 [(set F8RC:$rD, (undef))]>;
210 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4",
211 [(set F4RC:$rD, (undef))]>;
213 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
214 // scheduler into a branch sequence.
215 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
216 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
217 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
218 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
219 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
220 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
221 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
225 let isTerminator = 1 in {
227 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(ret)]>;
228 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
232 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>;
234 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
235 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
236 target:$true, target:$false),
237 "; COND_BRANCH", []>;
238 def B : IForm<18, 0, 0, (ops target:$dst),
242 // FIXME: 4*CR# needs to be added to the BI field!
243 // This will only work for CR0 as it stands now
244 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
245 "blt $crS, $block", BrB>;
246 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
247 "ble $crS, $block", BrB>;
248 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
249 "beq $crS, $block", BrB>;
250 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
251 "bge $crS, $block", BrB>;
252 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
253 "bgt $crS, $block", BrB>;
254 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
255 "bne $crS, $block", BrB>;
256 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
257 "bun $crS, $block", BrB>;
258 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
259 "bnu $crS, $block", BrB>;
263 // All calls clobber the non-callee saved registers...
264 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
265 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
267 CR0,CR1,CR5,CR6,CR7] in {
268 // Convenient aliases for call instructions
269 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
270 "bl $func", BrB, []>;
271 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
272 "bla $func", BrB, []>;
273 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB,
277 // D-Form instructions. Most instructions that perform an operation on a
278 // register and an immediate are of this type.
281 def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
282 "lbz $rD, $src", LdStGeneral,
283 [(set GPRC:$rD, (zextload iaddr:$src, i8))]>;
284 def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
285 "lha $rD, $src", LdStLHA,
286 [(set GPRC:$rD, (sextload iaddr:$src, i16))]>;
287 def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
288 "lhz $rD, $src", LdStGeneral,
289 [(set GPRC:$rD, (zextload iaddr:$src, i16))]>;
290 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
291 "lmw $rD, $disp($rA)", LdStLMW,
293 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
294 "lwz $rD, $src", LdStGeneral,
295 [(set GPRC:$rD, (load iaddr:$src))]>;
296 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
297 "lwzu $rD, $disp($rA)", LdStGeneral,
300 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
301 "addi $rD, $rA, $imm", IntGeneral,
302 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
303 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
304 "addic $rD, $rA, $imm", IntGeneral,
306 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
307 "addic. $rD, $rA, $imm", IntGeneral,
309 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
310 "addis $rD, $rA, $imm", IntGeneral,
311 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
312 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
313 "la $rD, $sym($rA)", IntGeneral,
314 [(set GPRC:$rD, (add GPRC:$rA,
315 (PPClo tglobaladdr:$sym, 0)))]>;
316 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
317 "mulli $rD, $rA, $imm", IntMulLI,
318 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
319 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
320 "subfic $rD, $rA, $imm", IntGeneral,
321 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
322 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
323 "li $rD, $imm", IntGeneral,
324 [(set GPRC:$rD, immSExt16:$imm)]>;
325 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
326 "lis $rD, $imm", IntGeneral,
327 [(set GPRC:$rD, imm16Shifted:$imm)]>;
329 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
330 "stmw $rS, $disp($rA)", LdStLMW,
332 def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
333 "stb $rS, $src", LdStGeneral,
334 [(truncstore GPRC:$rS, iaddr:$src, i8)]>;
335 def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
336 "sth $rS, $src", LdStGeneral,
337 [(truncstore GPRC:$rS, iaddr:$src, i16)]>;
338 def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
339 "stw $rS, $src", LdStGeneral,
340 [(store GPRC:$rS, iaddr:$src)]>;
341 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
342 "stwu $rS, $disp($rA)", LdStGeneral,
345 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
346 "andi. $dst, $src1, $src2", IntGeneral,
348 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
349 "andis. $dst, $src1, $src2", IntGeneral,
351 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
352 "ori $dst, $src1, $src2", IntGeneral,
353 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
354 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
355 "oris $dst, $src1, $src2", IntGeneral,
356 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
357 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
358 "xori $dst, $src1, $src2", IntGeneral,
359 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
360 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
361 "xoris $dst, $src1, $src2", IntGeneral,
362 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
363 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
365 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
366 "cmpi $crD, $L, $rA, $imm", IntCompare>;
367 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
368 "cmpwi $crD, $rA, $imm", IntCompare>;
369 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
370 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
371 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
372 "cmpli $dst, $size, $src1, $src2", IntCompare>;
373 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
374 "cmplwi $dst, $src1, $src2", IntCompare>;
375 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
376 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
378 def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src),
379 "lfs $rD, $src", LdStLFDU,
380 [(set F4RC:$rD, (load iaddr:$src))]>;
381 def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src),
382 "lfd $rD, $src", LdStLFD,
383 [(set F8RC:$rD, (load iaddr:$src))]>;
386 def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst),
387 "stfs $rS, $dst", LdStUX,
388 [(store F4RC:$rS, iaddr:$dst)]>;
389 def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst),
390 "stfd $rS, $dst", LdStUX,
391 [(store F8RC:$rS, iaddr:$dst)]>;
394 // DS-Form instructions. Load/Store instructions available in PPC-64
397 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
398 "lwa $rT, $DS($rA)", LdStLWA,
400 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
401 "ld $rT, $DS($rA)", LdStLD,
405 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
406 "std $rT, $DS($rA)", LdStSTD,
408 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
409 "stdu $rT, $DS($rA)", LdStSTD,
413 // X-Form instructions. Most instructions that perform an operation on a
414 // register and another register are of this type.
417 def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
418 "lbzx $rD, $src", LdStGeneral,
419 [(set GPRC:$rD, (zextload xaddr:$src, i8))]>;
420 def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
421 "lhax $rD, $src", LdStLHA,
422 [(set GPRC:$rD, (sextload xaddr:$src, i16))]>;
423 def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
424 "lhzx $rD, $src", LdStGeneral,
425 [(set GPRC:$rD, (zextload xaddr:$src, i16))]>;
426 def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
427 "lwax $rD, $src", LdStLHA,
428 [(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64;
429 def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
430 "lwzx $rD, $src", LdStGeneral,
431 [(set GPRC:$rD, (load xaddr:$src))]>;
432 def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
433 "ldx $rD, $src", LdStLD,
434 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
435 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
436 "lvebx $vD, $base, $rA", LdStGeneral,
438 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
439 "lvehx $vD, $base, $rA", LdStGeneral,
441 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
442 "lvewx $vD, $base, $rA", LdStGeneral,
444 def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
445 "lvx $vD, $src", LdStGeneral,
446 [(set VRRC:$vD, (load xoaddr:$src))]>;
448 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
449 "lvsl $vD, $base, $rA", LdStGeneral,
451 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
452 "lvsl $vD, $base, $rA", LdStGeneral,
454 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
455 "nand $rA, $rS, $rB", IntGeneral,
456 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
457 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
458 "and $rA, $rS, $rB", IntGeneral,
459 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
460 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
461 "and. $rA, $rS, $rB", IntGeneral,
463 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
464 "andc $rA, $rS, $rB", IntGeneral,
465 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
466 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
467 "or $rA, $rS, $rB", IntGeneral,
468 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
469 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
470 "or $rA, $rS, $rB", IntGeneral,
471 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
472 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
473 "or $rA, $rS, $rB", IntGeneral,
475 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
476 "or $rA, $rS, $rB", IntGeneral,
478 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
479 "nor $rA, $rS, $rB", IntGeneral,
480 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
481 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
482 "or. $rA, $rS, $rB", IntGeneral,
484 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
485 "orc $rA, $rS, $rB", IntGeneral,
486 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
487 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
488 "eqv $rA, $rS, $rB", IntGeneral,
489 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
490 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
491 "xor $rA, $rS, $rB", IntGeneral,
492 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
493 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
494 "sld $rA, $rS, $rB", IntRotateD,
495 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
496 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
497 "slw $rA, $rS, $rB", IntGeneral,
498 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
499 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
500 "srd $rA, $rS, $rB", IntRotateD,
501 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
502 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
503 "srw $rA, $rS, $rB", IntGeneral,
504 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
505 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
506 "srad $rA, $rS, $rB", IntRotateD,
507 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
508 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
509 "sraw $rA, $rS, $rB", IntShift,
510 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
512 def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
513 "stbx $rS, $dst", LdStGeneral,
514 [(truncstore GPRC:$rS, xaddr:$dst, i8)]>;
515 def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
516 "sthx $rS, $dst", LdStGeneral,
517 [(truncstore GPRC:$rS, xaddr:$dst, i16)]>;
518 def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
519 "stwx $rS, $dst", LdStGeneral,
520 [(store GPRC:$rS, xaddr:$dst)]>;
521 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
522 "stwux $rS, $rA, $rB", LdStGeneral,
524 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
525 "stdx $rS, $rA, $rB", LdStSTD,
527 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
528 "stdux $rS, $rA, $rB", LdStSTD,
530 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
531 "stvebx $rS, $rA, $rB", LdStGeneral,
533 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
534 "stvehx $rS, $rA, $rB", LdStGeneral,
536 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
537 "stvewx $rS, $rA, $rB", LdStGeneral,
539 def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
540 "stvx $rS, $dst", LdStGeneral,
541 [(store VRRC:$rS, xoaddr:$dst)]>;
543 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
544 "srawi $rA, $rS, $SH", IntShift,
545 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
546 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
547 "cntlzw $rA, $rS", IntGeneral,
548 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
549 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
550 "extsb $rA, $rS", IntGeneral,
551 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
552 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
553 "extsh $rA, $rS", IntGeneral,
554 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
555 def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
556 "extsw $rA, $rS", IntGeneral,
557 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
558 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
559 "cmp $crD, $long, $rA, $rB", IntCompare>;
560 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
561 "cmpl $crD, $long, $rA, $rB", IntCompare>;
562 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
563 "cmpw $crD, $rA, $rB", IntCompare>;
564 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
565 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
566 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
567 "cmplw $crD, $rA, $rB", IntCompare>;
568 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
569 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
570 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
571 // "fcmpo $crD, $fA, $fB", FPCompare>;
572 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
573 "fcmpu $crD, $fA, $fB", FPCompare>;
574 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
575 "fcmpu $crD, $fA, $fB", FPCompare>;
578 def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
579 "lfsx $frD, $src", LdStLFDU,
580 [(set F4RC:$frD, (load xaddr:$src))]>;
581 def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
582 "lfdx $frD, $src", LdStLFDU,
583 [(set F8RC:$frD, (load xaddr:$src))]>;
585 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
586 "fcfid $frD, $frB", FPGeneral,
587 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
588 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
589 "fctidz $frD, $frB", FPGeneral,
590 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
591 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
592 "fctiwz $frD, $frB", FPGeneral,
593 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
594 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
595 "frsp $frD, $frB", FPGeneral,
596 [(set F4RC:$frD, (fround F8RC:$frB))]>;
597 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
598 "fsqrt $frD, $frB", FPSqrt,
599 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
600 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
601 "fsqrts $frD, $frB", FPSqrt,
602 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
604 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
605 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
606 "fmr $frD, $frB", FPGeneral,
607 []>; // (set F4RC:$frD, F4RC:$frB)
608 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
609 "fmr $frD, $frB", FPGeneral,
610 []>; // (set F8RC:$frD, F8RC:$frB)
611 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
612 "fmr $frD, $frB", FPGeneral,
613 [(set F8RC:$frD, (fextend F4RC:$frB))]>;
615 // These are artificially split into two different forms, for 4/8 byte FP.
616 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
617 "fabs $frD, $frB", FPGeneral,
618 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
619 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
620 "fabs $frD, $frB", FPGeneral,
621 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
622 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
623 "fnabs $frD, $frB", FPGeneral,
624 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
625 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
626 "fnabs $frD, $frB", FPGeneral,
627 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
628 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
629 "fneg $frD, $frB", FPGeneral,
630 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
631 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
632 "fneg $frD, $frB", FPGeneral,
633 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
637 def STFIWX: XForm_28<31, 983, (ops F4RC:$frS, memrr:$dst),
638 "stfiwx $frS, $dst", LdStUX,
640 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
641 "stfsx $frS, $dst", LdStUX,
642 [(store F4RC:$frS, xaddr:$dst)]>;
643 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
644 "stfdx $frS, $dst", LdStUX,
645 [(store F8RC:$frS, xaddr:$dst)]>;
648 // XL-Form instructions. condition register logical ops.
650 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
651 "mcrf $BF, $BFA", BrMCR>;
653 // XFX-Form instructions. Instructions that deal with SPRs
655 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
656 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
657 // which means the SPR value needs to be multiplied by a factor of 32.
658 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
659 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
660 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
661 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
662 "mtcrf $FXM, $rS", BrMCRX>;
663 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
664 "mfcr $rT, $FXM", SprMFCR>;
665 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
666 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
667 def MTSPR : XFXForm_7<31, 467, (ops GPRC:$rS, u16imm:$UIMM), "mtspr $UIMM, $rS",
670 // XS-Form instructions. Just 'sradi'
672 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
673 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
675 // XO-Form instructions. Arithmetic instructions that can set overflow bit
677 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
678 "add $rT, $rA, $rB", IntGeneral,
679 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
680 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
681 "add $rT, $rA, $rB", IntGeneral,
682 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
683 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
684 "addc $rT, $rA, $rB", IntGeneral,
686 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
687 "adde $rT, $rA, $rB", IntGeneral,
689 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
690 "divd $rT, $rA, $rB", IntDivD,
691 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
692 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
693 "divdu $rT, $rA, $rB", IntDivD,
694 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
695 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
696 "divw $rT, $rA, $rB", IntDivW,
697 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
698 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
699 "divwu $rT, $rA, $rB", IntDivW,
700 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
701 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
702 "mulhd $rT, $rA, $rB", IntMulHW,
703 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
704 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
705 "mulhdu $rT, $rA, $rB", IntMulHWU,
706 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
707 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
708 "mulhw $rT, $rA, $rB", IntMulHW,
709 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
710 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
711 "mulhwu $rT, $rA, $rB", IntMulHWU,
712 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
713 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
714 "mulld $rT, $rA, $rB", IntMulHD,
715 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
716 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
717 "mullw $rT, $rA, $rB", IntMulHW,
718 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
719 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
720 "subf $rT, $rA, $rB", IntGeneral,
721 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
722 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
723 "subfc $rT, $rA, $rB", IntGeneral,
725 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
726 "subfe $rT, $rA, $rB", IntGeneral,
728 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
729 "addme $rT, $rA", IntGeneral,
731 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
732 "addze $rT, $rA", IntGeneral,
734 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
735 "neg $rT, $rA", IntGeneral,
736 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
737 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
738 "subfze $rT, $rA", IntGeneral,
741 // A-Form instructions. Most of the instructions executed in the FPU are of
744 def FMADD : AForm_1<63, 29,
745 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
746 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
747 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
749 Requires<[FPContractions]>;
750 def FMADDS : AForm_1<59, 29,
751 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
752 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
753 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
755 Requires<[FPContractions]>;
756 def FMSUB : AForm_1<63, 28,
757 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
758 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
759 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
761 Requires<[FPContractions]>;
762 def FMSUBS : AForm_1<59, 28,
763 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
764 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
765 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
767 Requires<[FPContractions]>;
768 def FNMADD : AForm_1<63, 31,
769 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
770 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
771 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
773 Requires<[FPContractions]>;
774 def FNMADDS : AForm_1<59, 31,
775 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
776 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
777 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
779 Requires<[FPContractions]>;
780 def FNMSUB : AForm_1<63, 30,
781 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
782 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
783 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
785 Requires<[FPContractions]>;
786 def FNMSUBS : AForm_1<59, 30,
787 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
788 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
789 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
791 Requires<[FPContractions]>;
792 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
793 // having 4 of these, force the comparison to always be an 8-byte double (code
794 // should use an FMRSD if the input comparison value really wants to be a float)
795 // and 4/8 byte forms for the result and operand type..
796 def FSELD : AForm_1<63, 23,
797 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
798 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
799 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
800 def FSELS : AForm_1<63, 23,
801 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
802 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
803 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
804 def FADD : AForm_2<63, 21,
805 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
806 "fadd $FRT, $FRA, $FRB", FPGeneral,
807 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
808 def FADDS : AForm_2<59, 21,
809 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
810 "fadds $FRT, $FRA, $FRB", FPGeneral,
811 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
812 def FDIV : AForm_2<63, 18,
813 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
814 "fdiv $FRT, $FRA, $FRB", FPDivD,
815 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
816 def FDIVS : AForm_2<59, 18,
817 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
818 "fdivs $FRT, $FRA, $FRB", FPDivS,
819 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
820 def FMUL : AForm_3<63, 25,
821 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
822 "fmul $FRT, $FRA, $FRB", FPFused,
823 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
824 def FMULS : AForm_3<59, 25,
825 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
826 "fmuls $FRT, $FRA, $FRB", FPGeneral,
827 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
828 def FSUB : AForm_2<63, 20,
829 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
830 "fsub $FRT, $FRA, $FRB", FPGeneral,
831 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
832 def FSUBS : AForm_2<59, 20,
833 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
834 "fsubs $FRT, $FRA, $FRB", FPGeneral,
835 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
837 // M-Form instructions. rotate and mask instructions.
839 let isTwoAddress = 1, isCommutable = 1 in {
840 // RLWIMI can be commuted if the rotate amount is zero.
841 def RLWIMI : MForm_2<20,
842 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
843 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
845 def RLDIMI : MDForm_1<30, 3,
846 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
847 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
850 def RLWINM : MForm_2<21,
851 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
852 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
854 def RLWINMo : MForm_2<21,
855 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
856 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
858 def RLWNM : MForm_2<23,
859 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
860 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
863 // MD-Form instructions. 64 bit rotate instructions.
865 def RLDICL : MDForm_1<30, 0,
866 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
867 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
869 def RLDICR : MDForm_1<30, 1,
870 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
871 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
874 // VA-Form instructions. 3-input AltiVec ops.
875 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
876 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
877 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
879 Requires<[FPContractions]>;
880 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
881 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
882 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA,
885 Requires<[FPContractions]>;
887 // VX-Form instructions. AltiVec arithmetic ops.
888 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
889 "vaddfp $vD, $vA, $vB", VecFP,
890 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
891 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
892 "vcfsx $vD, $vB, $UIMM", VecFP,
894 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
895 "vcfux $vD, $vB, $UIMM", VecFP,
897 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
898 "vctsxs $vD, $vB, $UIMM", VecFP,
900 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
901 "vctuxs $vD, $vB, $UIMM", VecFP,
903 def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
904 "vexptefp $vD, $vB", VecFP,
906 def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
907 "vlogefp $vD, $vB", VecFP,
909 def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
910 "vmaxfp $vD, $vA, $vB", VecFP,
912 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
913 "vminfp $vD, $vA, $vB", VecFP,
915 def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
916 "vrefp $vD, $vB", VecFP,
918 def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
919 "vrfim $vD, $vB", VecFP,
921 def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
922 "vrfin $vD, $vB", VecFP,
924 def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
925 "vrfip $vD, $vB", VecFP,
927 def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
928 "vrfiz $vD, $vB", VecFP,
930 def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
931 "vrsqrtefp $vD, $vB", VecFP,
933 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
934 "vsubfp $vD, $vA, $vB", VecFP,
935 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
936 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
937 "vxor $vD, $vA, $vB", VecFP,
940 // VX-Form Pseudo Instructions
942 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
943 "vxor $vD, $vD, $vD", VecFP,
947 //===----------------------------------------------------------------------===//
948 // DWARF Pseudo Instructions
951 def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
952 "; .loc $file, $line, $col",
953 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
956 //===----------------------------------------------------------------------===//
957 // PowerPC Instruction Patterns
960 // Arbitrary immediate support. Implement in terms of LIS/ORI.
961 def : Pat<(i32 imm:$imm),
962 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
964 // Implement the 'not' operation with the NOR instruction.
965 def NOT : Pat<(not GPRC:$in),
966 (NOR GPRC:$in, GPRC:$in)>;
968 // ADD an arbitrary immediate.
969 def : Pat<(add GPRC:$in, imm:$imm),
970 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
971 // OR an arbitrary immediate.
972 def : Pat<(or GPRC:$in, imm:$imm),
973 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
974 // XOR an arbitrary immediate.
975 def : Pat<(xor GPRC:$in, imm:$imm),
976 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
977 def : Pat<(or (shl GPRC:$rS, GPRC:$rB),
978 (srl GPRC:$rS, (sub 32, GPRC:$rB))),
979 (RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
981 def : Pat<(i64 (zext GPRC:$in)),
982 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
983 def : Pat<(i64 (anyext GPRC:$in)),
984 (OR4To8 GPRC:$in, GPRC:$in)>;
985 def : Pat<(i32 (trunc G8RC:$in)),
986 (OR8To4 G8RC:$in, G8RC:$in)>;
989 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
990 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
991 def : Pat<(shl G8RC:$in, (i64 imm:$imm)),
992 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
994 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
995 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
996 def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
997 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
999 // Hi and Lo for Darwin Global Addresses.
1000 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1001 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1002 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1003 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1004 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1005 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1006 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1007 (ADDIS GPRC:$in, tconstpool:$g)>;
1009 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
1010 (VMADDFP VRRC:$vA, (V_SET0), VRRC:$vB)>;
1012 // Fused negative multiply subtract, alternate pattern
1013 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1014 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1015 Requires<[FPContractions]>;
1016 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1017 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1018 Requires<[FPContractions]>;
1020 // Fused multiply add and multiply sub for packed float. These are represented
1021 // separately from the real instructions above, for operations that must have
1022 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
1023 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
1024 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
1025 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
1026 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
1028 // Standard shifts. These are represented separately from the real shifts above
1029 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1031 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1032 (SRAW GPRC:$rS, GPRC:$rB)>;
1033 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1034 (SRW GPRC:$rS, GPRC:$rB)>;
1035 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1036 (SLW GPRC:$rS, GPRC:$rB)>;
1038 def : Pat<(i32 (zextload iaddr:$src, i1)),
1040 def : Pat<(i32 (zextload xaddr:$src, i1)),
1042 def : Pat<(i32 (extload iaddr:$src, i1)),
1044 def : Pat<(i32 (extload xaddr:$src, i1)),
1046 def : Pat<(i32 (extload iaddr:$src, i8)),
1048 def : Pat<(i32 (extload xaddr:$src, i8)),
1050 def : Pat<(i32 (extload iaddr:$src, i16)),
1052 def : Pat<(i32 (extload xaddr:$src, i16)),
1054 def : Pat<(f64 (extload iaddr:$src, f32)),
1055 (FMRSD (LFS iaddr:$src))>;
1056 def : Pat<(f64 (extload xaddr:$src, f32)),
1057 (FMRSD (LFSX xaddr:$src))>;
1059 def : Pat<(retflag FLAG), (BLR)>;
1061 // Same as above, but using a temporary. FIXME: implement temporaries :)
1063 def : Pattern<(xor GPRC:$in, imm:$imm),
1064 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
1065 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
1068 //===----------------------------------------------------------------------===//
1069 // PowerPCInstrInfo Definition
1071 def PowerPCInstrInfo : InstrInfo {
1074 let TSFlagsFields = [ "VMX", "PPC64" ];
1075 let TSFlagsShifts = [ 0, 1 ];
1077 let isLittleEndianEncoding = 1;