1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
28 def SDT_PPCvperm : SDTypeProfile<1, 3, [
29 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
32 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
33 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
36 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
37 SDTCisVT<1, i32>, SDTCisVT<2, OtherVT>
40 def SDT_PPClbrx : SDTypeProfile<1, 3, [
41 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
43 def SDT_PPCstbrx : SDTypeProfile<0, 4, [
44 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
47 //===----------------------------------------------------------------------===//
48 // PowerPC specific DAG Nodes.
51 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
52 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
53 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
54 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
56 def PPCfsel : SDNode<"PPCISD::FSEL",
57 // Type constraint for fsel.
58 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
59 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
61 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
62 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
63 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
64 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
66 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
68 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
69 // amounts. These nodes are generated by the multi-precision shift code.
70 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
71 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
72 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
74 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
75 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
77 // These are target-independent nodes, but have target-specific formats.
78 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,
79 [SDNPHasChain, SDNPOutFlag]>;
80 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,
81 [SDNPHasChain, SDNPOutFlag]>;
83 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
84 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
85 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
86 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
87 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
88 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTRet,
89 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
91 def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet,
92 [SDNPHasChain, SDNPOptInFlag]>;
94 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
95 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
97 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
98 [SDNPHasChain, SDNPOptInFlag]>;
100 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
101 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>;
103 //===----------------------------------------------------------------------===//
104 // PowerPC specific transformation functions and pattern fragments.
107 def SHL32 : SDNodeXForm<imm, [{
108 // Transformation function: 31 - imm
109 return getI32Imm(31 - N->getValue());
112 def SRL32 : SDNodeXForm<imm, [{
113 // Transformation function: 32 - imm
114 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
117 def LO16 : SDNodeXForm<imm, [{
118 // Transformation function: get the low 16 bits.
119 return getI32Imm((unsigned short)N->getValue());
122 def HI16 : SDNodeXForm<imm, [{
123 // Transformation function: shift the immediate value down into the low bits.
124 return getI32Imm((unsigned)N->getValue() >> 16);
127 def HA16 : SDNodeXForm<imm, [{
128 // Transformation function: shift the immediate value down into the low bits.
129 signed int Val = N->getValue();
130 return getI32Imm((Val - (signed short)Val) >> 16);
132 def MB : SDNodeXForm<imm, [{
133 // Transformation function: get the start bit of a mask
135 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
136 return getI32Imm(mb);
139 def ME : SDNodeXForm<imm, [{
140 // Transformation function: get the end bit of a mask
142 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
143 return getI32Imm(me);
145 def maskimm32 : PatLeaf<(imm), [{
146 // maskImm predicate - True if immediate is a run of ones.
148 if (N->getValueType(0) == MVT::i32)
149 return isRunOfOnes((unsigned)N->getValue(), mb, me);
154 def immSExt16 : PatLeaf<(imm), [{
155 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
156 // field. Used by instructions like 'addi'.
157 if (N->getValueType(0) == MVT::i32)
158 return (int32_t)N->getValue() == (short)N->getValue();
160 return (int64_t)N->getValue() == (short)N->getValue();
162 def immZExt16 : PatLeaf<(imm), [{
163 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
164 // field. Used by instructions like 'ori'.
165 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
168 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
169 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
170 // identical in 32-bit mode, but in 64-bit mode, they return true if the
171 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
173 def imm16ShiftedZExt : PatLeaf<(imm), [{
174 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
175 // immediate are set. Used by instructions like 'xoris'.
176 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
179 def imm16ShiftedSExt : PatLeaf<(imm), [{
180 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
181 // immediate are set. Used by instructions like 'addis'. Identical to
182 // imm16ShiftedZExt in 32-bit mode.
183 if (N->getValue() & 0xFFFF) return false;
184 if (N->getValueType(0) == MVT::i32)
186 // For 64-bit, make sure it is sext right.
187 return N->getValue() == (uint64_t)(int)N->getValue();
191 //===----------------------------------------------------------------------===//
192 // PowerPC Flag Definitions.
194 class isPPC64 { bit PPC64 = 1; }
196 list<Register> Defs = [CR0];
200 class RegConstraint<string C> {
201 string Constraints = C;
205 //===----------------------------------------------------------------------===//
206 // PowerPC Operand Definitions.
208 def s5imm : Operand<i32> {
209 let PrintMethod = "printS5ImmOperand";
211 def u5imm : Operand<i32> {
212 let PrintMethod = "printU5ImmOperand";
214 def u6imm : Operand<i32> {
215 let PrintMethod = "printU6ImmOperand";
217 def s16imm : Operand<i32> {
218 let PrintMethod = "printS16ImmOperand";
220 def u16imm : Operand<i32> {
221 let PrintMethod = "printU16ImmOperand";
223 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
224 let PrintMethod = "printS16X4ImmOperand";
226 def target : Operand<OtherVT> {
227 let PrintMethod = "printBranchOperand";
229 def calltarget : Operand<iPTR> {
230 let PrintMethod = "printCallOperand";
232 def aaddr : Operand<iPTR> {
233 let PrintMethod = "printAbsAddrOperand";
235 def piclabel: Operand<iPTR> {
236 let PrintMethod = "printPICLabel";
238 def symbolHi: Operand<i32> {
239 let PrintMethod = "printSymbolHi";
241 def symbolLo: Operand<i32> {
242 let PrintMethod = "printSymbolLo";
244 def crbitm: Operand<i8> {
245 let PrintMethod = "printcrbitm";
248 def memri : Operand<iPTR> {
249 let PrintMethod = "printMemRegImm";
250 let MIOperandInfo = (ops i32imm, ptr_rc);
252 def memrr : Operand<iPTR> {
253 let PrintMethod = "printMemRegReg";
254 let MIOperandInfo = (ops ptr_rc, ptr_rc);
256 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
257 let PrintMethod = "printMemRegImmShifted";
258 let MIOperandInfo = (ops i32imm, ptr_rc);
261 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
262 // that doesn't matter.
263 def pred : PredicateOperand<(ops imm, CRRC), (ops (i32 20), CR0)> {
264 let PrintMethod = "printPredicateOperand";
267 // Define PowerPC specific addressing mode.
268 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
269 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
270 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
271 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
273 //===----------------------------------------------------------------------===//
274 // PowerPC Instruction Predicate Definitions.
275 def FPContractions : Predicate<"!NoExcessFPPrecision">;
278 //===----------------------------------------------------------------------===//
279 // PowerPC Instruction Definitions.
281 // Pseudo-instructions:
283 let hasCtrlDep = 1 in {
284 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
285 "${:comment} ADJCALLSTACKDOWN",
286 [(callseq_start imm:$amt)]>, Imp<[R1],[R1]>;
287 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
288 "${:comment} ADJCALLSTACKUP",
289 [(callseq_end imm:$amt)]>, Imp<[R1],[R1]>;
291 def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
292 "UPDATE_VRSAVE $rD, $rS", []>;
294 def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD),"${:comment}IMPLICIT_DEF_GPRC $rD",
295 [(set GPRC:$rD, (undef))]>;
296 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "${:comment} IMPLICIT_DEF_F8 $rD",
297 [(set F8RC:$rD, (undef))]>;
298 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "${:comment} IMPLICIT_DEF_F4 $rD",
299 [(set F4RC:$rD, (undef))]>;
301 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
302 // scheduler into a branch sequence.
303 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
304 PPC970_Single = 1 in {
305 def SELECT_CC_I4 : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
306 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
308 def SELECT_CC_I8 : Pseudo<(ops G8RC:$dst, CRRC:$cond, G8RC:$T, G8RC:$F,
309 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
311 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
312 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
314 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
315 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
317 def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F,
318 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
322 let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
324 def BLR : XLForm_2_br<19, 16, 0,
326 "b${p:cc}lr ${p:reg}", BrB,
328 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
334 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
337 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
338 noResults = 1, PPC970_Unit = 7 in {
339 // COND_BRANCH is formed before branch selection, it is turned into Bcc below.
340 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
341 "${:comment} COND_BRANCH $crS, $opc, $dst",
342 [(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
343 let isBarrier = 1 in {
344 def B : IForm<18, 0, 0, (ops target:$dst),
349 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
350 "blt $crS, $block", BrB>;
351 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
352 "ble $crS, $block", BrB>;
353 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
354 "beq $crS, $block", BrB>;
355 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
356 "bge $crS, $block", BrB>;
357 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
358 "bgt $crS, $block", BrB>;
359 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
360 "bne $crS, $block", BrB>;
361 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
362 "bun $crS, $block", BrB>;
363 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
364 "bnu $crS, $block", BrB>;
367 let isCall = 1, noResults = 1, PPC970_Unit = 7,
368 // All calls clobber the non-callee saved registers...
369 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
370 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
371 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
373 CR0,CR1,CR5,CR6,CR7] in {
374 // Convenient aliases for call instructions
375 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
376 "bl $func", BrB, []>; // See Pat patterns below.
377 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
378 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
379 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB,
383 // DCB* instructions.
384 def DCBA : DCB_Form<758, 0, (ops memrr:$dst),
385 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
386 PPC970_DGroup_Single;
387 def DCBF : DCB_Form<86, 0, (ops memrr:$dst),
388 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
389 PPC970_DGroup_Single;
390 def DCBI : DCB_Form<470, 0, (ops memrr:$dst),
391 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
392 PPC970_DGroup_Single;
393 def DCBST : DCB_Form<54, 0, (ops memrr:$dst),
394 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
395 PPC970_DGroup_Single;
396 def DCBT : DCB_Form<278, 0, (ops memrr:$dst),
397 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
398 PPC970_DGroup_Single;
399 def DCBTST : DCB_Form<246, 0, (ops memrr:$dst),
400 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
401 PPC970_DGroup_Single;
402 def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
403 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
404 PPC970_DGroup_Single;
405 def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
406 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
407 PPC970_DGroup_Single;
409 // D-Form instructions. Most instructions that perform an operation on a
410 // register and an immediate are of this type.
412 let isLoad = 1, PPC970_Unit = 2 in {
413 def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
414 "lbz $rD, $src", LdStGeneral,
415 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
416 def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
417 "lha $rD, $src", LdStLHA,
418 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
419 PPC970_DGroup_Cracked;
420 def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
421 "lhz $rD, $src", LdStGeneral,
422 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
423 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
424 "lwz $rD, $src", LdStGeneral,
425 [(set GPRC:$rD, (load iaddr:$src))]>;
427 def LFS : DForm_1<48, (ops F4RC:$rD, memri:$src),
428 "lfs $rD, $src", LdStLFDU,
429 [(set F4RC:$rD, (load iaddr:$src))]>;
430 def LFD : DForm_1<50, (ops F8RC:$rD, memri:$src),
431 "lfd $rD, $src", LdStLFD,
432 [(set F8RC:$rD, (load iaddr:$src))]>;
434 // FIXME: PTRRC for Pointer regs for ppc64.
436 // 'Update' load forms.
437 def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
439 "lbzu $rD, $disp($rA)", LdStGeneral,
440 []>, RegConstraint<"$rA = $rA_result">;
442 def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
444 "lhau $rD, $disp($rA)", LdStGeneral,
445 []>, RegConstraint<"$rA = $rA_result">;
447 def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
449 "lhzu $rD, $disp($rA)", LdStGeneral,
450 []>, RegConstraint<"$rA = $rA_result">;
452 def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
454 "lwzu $rD, $disp($rA)", LdStGeneral,
455 []>, RegConstraint<"$rA = $rA_result">;
457 def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
459 "lfs $rD, $disp($rA)", LdStLFDU,
460 []>, RegConstraint<"$rA = $rA_result">;
461 def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
463 "lfd $rD, $disp($rA)", LdStLFD,
464 []>, RegConstraint<"$rA = $rA_result">;
468 let PPC970_Unit = 1 in { // FXU Operations.
469 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
470 "addi $rD, $rA, $imm", IntGeneral,
471 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
472 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
473 "addic $rD, $rA, $imm", IntGeneral,
474 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
475 PPC970_DGroup_Cracked;
476 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
477 "addic. $rD, $rA, $imm", IntGeneral,
479 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
480 "addis $rD, $rA, $imm", IntGeneral,
481 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
482 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
483 "la $rD, $sym($rA)", IntGeneral,
484 [(set GPRC:$rD, (add GPRC:$rA,
485 (PPClo tglobaladdr:$sym, 0)))]>;
486 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
487 "mulli $rD, $rA, $imm", IntMulLI,
488 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
489 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
490 "subfic $rD, $rA, $imm", IntGeneral,
491 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
492 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
493 "li $rD, $imm", IntGeneral,
494 [(set GPRC:$rD, immSExt16:$imm)]>;
495 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
496 "lis $rD, $imm", IntGeneral,
497 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
499 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
500 def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
501 "stb $rS, $src", LdStGeneral,
502 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
503 def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
504 "sth $rS, $src", LdStGeneral,
505 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
506 def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
507 "stw $rS, $src", LdStGeneral,
508 [(store GPRC:$rS, iaddr:$src)]>;
509 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
510 "stwu $rS, $disp($rA)", LdStGeneral,
513 let PPC970_Unit = 1 in { // FXU Operations.
514 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
515 "andi. $dst, $src1, $src2", IntGeneral,
516 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
518 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
519 "andis. $dst, $src1, $src2", IntGeneral,
520 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
522 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
523 "ori $dst, $src1, $src2", IntGeneral,
524 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
525 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
526 "oris $dst, $src1, $src2", IntGeneral,
527 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
528 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
529 "xori $dst, $src1, $src2", IntGeneral,
530 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
531 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
532 "xoris $dst, $src1, $src2", IntGeneral,
533 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
534 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
536 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
537 "cmpwi $crD, $rA, $imm", IntCompare>;
538 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
539 "cmplwi $dst, $src1, $src2", IntCompare>;
541 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
542 def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst),
543 "stfs $rS, $dst", LdStUX,
544 [(store F4RC:$rS, iaddr:$dst)]>;
545 def STFD : DForm_1<54, (ops F8RC:$rS, memri:$dst),
546 "stfd $rS, $dst", LdStUX,
547 [(store F8RC:$rS, iaddr:$dst)]>;
550 // X-Form instructions. Most instructions that perform an operation on a
551 // register and another register are of this type.
553 let isLoad = 1, PPC970_Unit = 2 in {
554 def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
555 "lbzx $rD, $src", LdStGeneral,
556 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
557 def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
558 "lhax $rD, $src", LdStLHA,
559 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
560 PPC970_DGroup_Cracked;
561 def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
562 "lhzx $rD, $src", LdStGeneral,
563 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
564 def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
565 "lwzx $rD, $src", LdStGeneral,
566 [(set GPRC:$rD, (load xaddr:$src))]>;
569 def LHBRX : XForm_1<31, 790, (ops GPRC:$rD, memrr:$src),
570 "lhbrx $rD, $src", LdStGeneral,
571 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
572 def LWBRX : XForm_1<31, 534, (ops GPRC:$rD, memrr:$src),
573 "lwbrx $rD, $src", LdStGeneral,
574 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
578 let PPC970_Unit = 1 in { // FXU Operations.
579 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
580 "nand $rA, $rS, $rB", IntGeneral,
581 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
582 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
583 "and $rA, $rS, $rB", IntGeneral,
584 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
585 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
586 "andc $rA, $rS, $rB", IntGeneral,
587 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
588 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
589 "or $rA, $rS, $rB", IntGeneral,
590 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
591 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
592 "nor $rA, $rS, $rB", IntGeneral,
593 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
594 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
595 "orc $rA, $rS, $rB", IntGeneral,
596 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
597 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
598 "eqv $rA, $rS, $rB", IntGeneral,
599 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
600 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
601 "xor $rA, $rS, $rB", IntGeneral,
602 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
603 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
604 "slw $rA, $rS, $rB", IntGeneral,
605 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
606 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
607 "srw $rA, $rS, $rB", IntGeneral,
608 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
609 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
610 "sraw $rA, $rS, $rB", IntShift,
611 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
613 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
614 def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
615 "stbx $rS, $dst", LdStGeneral,
616 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
617 PPC970_DGroup_Cracked;
618 def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
619 "sthx $rS, $dst", LdStGeneral,
620 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
621 PPC970_DGroup_Cracked;
622 def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
623 "stwx $rS, $dst", LdStGeneral,
624 [(store GPRC:$rS, xaddr:$dst)]>,
625 PPC970_DGroup_Cracked;
626 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
627 "stwux $rS, $rA, $rB", LdStGeneral,
629 def STHBRX: XForm_8<31, 918, (ops GPRC:$rS, memrr:$dst),
630 "sthbrx $rS, $dst", LdStGeneral,
631 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
632 PPC970_DGroup_Cracked;
633 def STWBRX: XForm_8<31, 662, (ops GPRC:$rS, memrr:$dst),
634 "stwbrx $rS, $dst", LdStGeneral,
635 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
636 PPC970_DGroup_Cracked;
638 let PPC970_Unit = 1 in { // FXU Operations.
639 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
640 "srawi $rA, $rS, $SH", IntShift,
641 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
642 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
643 "cntlzw $rA, $rS", IntGeneral,
644 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
645 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
646 "extsb $rA, $rS", IntGeneral,
647 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
648 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
649 "extsh $rA, $rS", IntGeneral,
650 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
652 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
653 "cmpw $crD, $rA, $rB", IntCompare>;
654 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
655 "cmplw $crD, $rA, $rB", IntCompare>;
657 let PPC970_Unit = 3 in { // FPU Operations.
658 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
659 // "fcmpo $crD, $fA, $fB", FPCompare>;
660 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
661 "fcmpu $crD, $fA, $fB", FPCompare>;
662 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
663 "fcmpu $crD, $fA, $fB", FPCompare>;
665 let isLoad = 1, PPC970_Unit = 2 in {
666 def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
667 "lfsx $frD, $src", LdStLFDU,
668 [(set F4RC:$frD, (load xaddr:$src))]>;
669 def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
670 "lfdx $frD, $src", LdStLFDU,
671 [(set F8RC:$frD, (load xaddr:$src))]>;
673 let PPC970_Unit = 3 in { // FPU Operations.
674 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
675 "fctiwz $frD, $frB", FPGeneral,
676 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
677 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
678 "frsp $frD, $frB", FPGeneral,
679 [(set F4RC:$frD, (fround F8RC:$frB))]>;
680 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
681 "fsqrt $frD, $frB", FPSqrt,
682 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
683 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
684 "fsqrts $frD, $frB", FPSqrt,
685 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
688 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
690 /// Note that these are defined as pseudo-ops on the PPC970 because they are
691 /// often coalesced away and we don't want the dispatch group builder to think
692 /// that they will fill slots (which could cause the load of a LSU reject to
693 /// sneak into a d-group with a store).
694 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
695 "fmr $frD, $frB", FPGeneral,
696 []>, // (set F4RC:$frD, F4RC:$frB)
698 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
699 "fmr $frD, $frB", FPGeneral,
700 []>, // (set F8RC:$frD, F8RC:$frB)
702 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
703 "fmr $frD, $frB", FPGeneral,
704 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
707 let PPC970_Unit = 3 in { // FPU Operations.
708 // These are artificially split into two different forms, for 4/8 byte FP.
709 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
710 "fabs $frD, $frB", FPGeneral,
711 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
712 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
713 "fabs $frD, $frB", FPGeneral,
714 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
715 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
716 "fnabs $frD, $frB", FPGeneral,
717 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
718 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
719 "fnabs $frD, $frB", FPGeneral,
720 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
721 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
722 "fneg $frD, $frB", FPGeneral,
723 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
724 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
725 "fneg $frD, $frB", FPGeneral,
726 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
729 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
730 def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst),
731 "stfiwx $frS, $dst", LdStUX,
732 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
733 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
734 "stfsx $frS, $dst", LdStUX,
735 [(store F4RC:$frS, xaddr:$dst)]>;
736 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
737 "stfdx $frS, $dst", LdStUX,
738 [(store F8RC:$frS, xaddr:$dst)]>;
741 // XL-Form instructions. condition register logical ops.
743 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
744 "mcrf $BF, $BFA", BrMCR>,
745 PPC970_DGroup_First, PPC970_Unit_CRU;
747 // XFX-Form instructions. Instructions that deal with SPRs.
749 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>,
750 PPC970_DGroup_First, PPC970_Unit_FXU;
751 let Pattern = [(PPCmtctr GPRC:$rS)] in {
752 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>,
753 PPC970_DGroup_First, PPC970_Unit_FXU;
756 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>,
757 PPC970_DGroup_First, PPC970_Unit_FXU;
758 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>,
759 PPC970_DGroup_First, PPC970_Unit_FXU;
761 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
762 // a GPR on the PPC970. As such, copies in and out have the same performance
763 // characteristics as an OR instruction.
764 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS),
765 "mtspr 256, $rS", IntGeneral>,
766 PPC970_DGroup_Single, PPC970_Unit_FXU;
767 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT),
768 "mfspr $rT, 256", IntGeneral>,
769 PPC970_DGroup_First, PPC970_Unit_FXU;
771 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
772 "mtcrf $FXM, $rS", BrMCRX>,
773 PPC970_MicroCode, PPC970_Unit_CRU;
774 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>,
775 PPC970_MicroCode, PPC970_Unit_CRU;
776 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
777 "mfcr $rT, $FXM", SprMFCR>,
778 PPC970_DGroup_First, PPC970_Unit_CRU;
780 let PPC970_Unit = 1 in { // FXU Operations.
782 // XO-Form instructions. Arithmetic instructions that can set overflow bit
784 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
785 "add $rT, $rA, $rB", IntGeneral,
786 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
787 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
788 "addc $rT, $rA, $rB", IntGeneral,
789 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
790 PPC970_DGroup_Cracked;
791 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
792 "adde $rT, $rA, $rB", IntGeneral,
793 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
794 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
795 "divw $rT, $rA, $rB", IntDivW,
796 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
797 PPC970_DGroup_First, PPC970_DGroup_Cracked;
798 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
799 "divwu $rT, $rA, $rB", IntDivW,
800 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
801 PPC970_DGroup_First, PPC970_DGroup_Cracked;
802 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
803 "mulhw $rT, $rA, $rB", IntMulHW,
804 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
805 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
806 "mulhwu $rT, $rA, $rB", IntMulHWU,
807 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
808 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
809 "mullw $rT, $rA, $rB", IntMulHW,
810 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
811 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
812 "subf $rT, $rA, $rB", IntGeneral,
813 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
814 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
815 "subfc $rT, $rA, $rB", IntGeneral,
816 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
817 PPC970_DGroup_Cracked;
818 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
819 "subfe $rT, $rA, $rB", IntGeneral,
820 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
821 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
822 "addme $rT, $rA", IntGeneral,
823 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
824 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
825 "addze $rT, $rA", IntGeneral,
826 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
827 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
828 "neg $rT, $rA", IntGeneral,
829 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
830 def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA),
831 "subfme $rT, $rA", IntGeneral,
832 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
833 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
834 "subfze $rT, $rA", IntGeneral,
835 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
838 // A-Form instructions. Most of the instructions executed in the FPU are of
841 let PPC970_Unit = 3 in { // FPU Operations.
842 def FMADD : AForm_1<63, 29,
843 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
844 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
845 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
847 Requires<[FPContractions]>;
848 def FMADDS : AForm_1<59, 29,
849 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
850 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
851 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
853 Requires<[FPContractions]>;
854 def FMSUB : AForm_1<63, 28,
855 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
856 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
857 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
859 Requires<[FPContractions]>;
860 def FMSUBS : AForm_1<59, 28,
861 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
862 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
863 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
865 Requires<[FPContractions]>;
866 def FNMADD : AForm_1<63, 31,
867 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
868 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
869 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
871 Requires<[FPContractions]>;
872 def FNMADDS : AForm_1<59, 31,
873 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
874 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
875 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
877 Requires<[FPContractions]>;
878 def FNMSUB : AForm_1<63, 30,
879 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
880 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
881 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
883 Requires<[FPContractions]>;
884 def FNMSUBS : AForm_1<59, 30,
885 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
886 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
887 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
889 Requires<[FPContractions]>;
890 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
891 // having 4 of these, force the comparison to always be an 8-byte double (code
892 // should use an FMRSD if the input comparison value really wants to be a float)
893 // and 4/8 byte forms for the result and operand type..
894 def FSELD : AForm_1<63, 23,
895 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
896 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
897 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
898 def FSELS : AForm_1<63, 23,
899 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
900 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
901 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
902 def FADD : AForm_2<63, 21,
903 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
904 "fadd $FRT, $FRA, $FRB", FPGeneral,
905 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
906 def FADDS : AForm_2<59, 21,
907 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
908 "fadds $FRT, $FRA, $FRB", FPGeneral,
909 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
910 def FDIV : AForm_2<63, 18,
911 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
912 "fdiv $FRT, $FRA, $FRB", FPDivD,
913 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
914 def FDIVS : AForm_2<59, 18,
915 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
916 "fdivs $FRT, $FRA, $FRB", FPDivS,
917 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
918 def FMUL : AForm_3<63, 25,
919 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
920 "fmul $FRT, $FRA, $FRB", FPFused,
921 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
922 def FMULS : AForm_3<59, 25,
923 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
924 "fmuls $FRT, $FRA, $FRB", FPGeneral,
925 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
926 def FSUB : AForm_2<63, 20,
927 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
928 "fsub $FRT, $FRA, $FRB", FPGeneral,
929 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
930 def FSUBS : AForm_2<59, 20,
931 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
932 "fsubs $FRT, $FRA, $FRB", FPGeneral,
933 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
936 let PPC970_Unit = 1 in { // FXU Operations.
937 // M-Form instructions. rotate and mask instructions.
939 let isTwoAddress = 1, isCommutable = 1 in {
940 // RLWIMI can be commuted if the rotate amount is zero.
941 def RLWIMI : MForm_2<20,
942 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
943 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
944 []>, PPC970_DGroup_Cracked;
946 def RLWINM : MForm_2<21,
947 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
948 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
950 def RLWINMo : MForm_2<21,
951 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
952 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
953 []>, isDOT, PPC970_DGroup_Cracked;
954 def RLWNM : MForm_2<23,
955 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
956 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
961 //===----------------------------------------------------------------------===//
962 // DWARF Pseudo Instructions
965 def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
966 "${:comment} .loc $file, $line, $col",
967 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
970 def DWARF_LABEL : Pseudo<(ops i32imm:$id),
971 "\n${:private}debug_loc$id:",
972 [(dwarf_label (i32 imm:$id))]>;
974 //===----------------------------------------------------------------------===//
975 // PowerPC Instruction Patterns
978 // Arbitrary immediate support. Implement in terms of LIS/ORI.
979 def : Pat<(i32 imm:$imm),
980 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
982 // Implement the 'not' operation with the NOR instruction.
983 def NOT : Pat<(not GPRC:$in),
984 (NOR GPRC:$in, GPRC:$in)>;
986 // ADD an arbitrary immediate.
987 def : Pat<(add GPRC:$in, imm:$imm),
988 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
989 // OR an arbitrary immediate.
990 def : Pat<(or GPRC:$in, imm:$imm),
991 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
992 // XOR an arbitrary immediate.
993 def : Pat<(xor GPRC:$in, imm:$imm),
994 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
996 def : Pat<(sub immSExt16:$imm, GPRC:$in),
997 (SUBFIC GPRC:$in, imm:$imm)>;
999 // Return void support.
1000 def : Pat<(ret), (BLR)>;
1003 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1004 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1005 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1006 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1009 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1010 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1011 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1012 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1015 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1016 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1019 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
1020 (BL tglobaladdr:$dst)>;
1021 def : Pat<(PPCcall (i32 texternalsym:$dst)),
1022 (BL texternalsym:$dst)>;
1024 // Hi and Lo for Darwin Global Addresses.
1025 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1026 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1027 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1028 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1029 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1030 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1031 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1032 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1033 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1034 (ADDIS GPRC:$in, tconstpool:$g)>;
1035 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1036 (ADDIS GPRC:$in, tjumptable:$g)>;
1038 // Fused negative multiply subtract, alternate pattern
1039 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1040 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1041 Requires<[FPContractions]>;
1042 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1043 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1044 Requires<[FPContractions]>;
1046 // Standard shifts. These are represented separately from the real shifts above
1047 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1049 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1050 (SRAW GPRC:$rS, GPRC:$rB)>;
1051 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1052 (SRW GPRC:$rS, GPRC:$rB)>;
1053 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1054 (SLW GPRC:$rS, GPRC:$rB)>;
1056 def : Pat<(zextloadi1 iaddr:$src),
1058 def : Pat<(zextloadi1 xaddr:$src),
1060 def : Pat<(extloadi1 iaddr:$src),
1062 def : Pat<(extloadi1 xaddr:$src),
1064 def : Pat<(extloadi8 iaddr:$src),
1066 def : Pat<(extloadi8 xaddr:$src),
1068 def : Pat<(extloadi16 iaddr:$src),
1070 def : Pat<(extloadi16 xaddr:$src),
1072 def : Pat<(extloadf32 iaddr:$src),
1073 (FMRSD (LFS iaddr:$src))>;
1074 def : Pat<(extloadf32 xaddr:$src),
1075 (FMRSD (LFSX xaddr:$src))>;
1077 include "PPCInstrAltivec.td"
1078 include "PPCInstr64Bit.td"