1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
60 def tocentry32 : Operand<iPTR> {
61 let MIOperandInfo = (ops i32imm:$imm);
64 //===----------------------------------------------------------------------===//
65 // PowerPC specific DAG Nodes.
68 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
69 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
71 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
72 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
73 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
74 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
75 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
76 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
77 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
78 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
79 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
80 [SDNPHasChain, SDNPMayStore]>;
81 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
82 [SDNPHasChain, SDNPMayLoad]>;
83 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
84 [SDNPHasChain, SDNPMayLoad]>;
86 // Extract FPSCR (not modeled at the DAG level).
87 def PPCmffs : SDNode<"PPCISD::MFFS",
88 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
90 // Perform FADD in round-to-zero mode.
91 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
94 def PPCfsel : SDNode<"PPCISD::FSEL",
95 // Type constraint for fsel.
96 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
97 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
99 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
100 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
101 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
102 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
103 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
105 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
107 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
108 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
110 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
111 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
112 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
113 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
114 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
115 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
117 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
119 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
121 def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
123 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
124 // amounts. These nodes are generated by the multi-precision shift code.
125 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
126 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
127 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
129 // These are target-independent nodes, but have target-specific formats.
130 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
131 [SDNPHasChain, SDNPOutGlue]>;
132 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
135 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
136 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
139 def PPCcall_tls : SDNode<"PPCISD::CALL_TLS", SDT_PPCCall,
140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
142 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
143 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
145 def PPCcall_nop_tls : SDNode<"PPCISD::CALL_NOP_TLS", SDT_PPCCall,
146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
148 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
149 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
150 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
151 [SDNPHasChain, SDNPSideEffect,
152 SDNPInGlue, SDNPOutGlue]>;
153 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
154 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
155 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
156 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
158 def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
159 SDTypeProfile<0, 1, []>,
160 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
163 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
164 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
166 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
167 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
169 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
170 SDTypeProfile<1, 1, [SDTCisInt<0>,
172 [SDNPHasChain, SDNPSideEffect]>;
173 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
174 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
175 [SDNPHasChain, SDNPSideEffect]>;
177 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
178 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
179 [SDNPHasChain, SDNPSideEffect]>;
181 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
182 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
184 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
185 [SDNPHasChain, SDNPOptInGlue]>;
187 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
188 [SDNPHasChain, SDNPMayLoad]>;
189 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
190 [SDNPHasChain, SDNPMayStore]>;
192 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
193 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
194 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
195 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
196 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
198 // Instructions to support atomic operations
199 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
200 [SDNPHasChain, SDNPMayLoad]>;
201 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
202 [SDNPHasChain, SDNPMayStore]>;
204 // Instructions to support medium and large code model
205 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
206 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
207 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
210 // Instructions to support dynamic alloca.
211 def SDTDynOp : SDTypeProfile<1, 2, []>;
212 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
214 //===----------------------------------------------------------------------===//
215 // PowerPC specific transformation functions and pattern fragments.
218 def SHL32 : SDNodeXForm<imm, [{
219 // Transformation function: 31 - imm
220 return getI32Imm(31 - N->getZExtValue());
223 def SRL32 : SDNodeXForm<imm, [{
224 // Transformation function: 32 - imm
225 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
228 def LO16 : SDNodeXForm<imm, [{
229 // Transformation function: get the low 16 bits.
230 return getI32Imm((unsigned short)N->getZExtValue());
233 def HI16 : SDNodeXForm<imm, [{
234 // Transformation function: shift the immediate value down into the low bits.
235 return getI32Imm((unsigned)N->getZExtValue() >> 16);
238 def HA16 : SDNodeXForm<imm, [{
239 // Transformation function: shift the immediate value down into the low bits.
240 signed int Val = N->getZExtValue();
241 return getI32Imm((Val - (signed short)Val) >> 16);
243 def MB : SDNodeXForm<imm, [{
244 // Transformation function: get the start bit of a mask
246 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
247 return getI32Imm(mb);
250 def ME : SDNodeXForm<imm, [{
251 // Transformation function: get the end bit of a mask
253 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
254 return getI32Imm(me);
256 def maskimm32 : PatLeaf<(imm), [{
257 // maskImm predicate - True if immediate is a run of ones.
259 if (N->getValueType(0) == MVT::i32)
260 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
265 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
266 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
267 // sign extended field. Used by instructions like 'addi'.
268 return (int32_t)Imm == (short)Imm;
270 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
271 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
272 // sign extended field. Used by instructions like 'addi'.
273 return (int64_t)Imm == (short)Imm;
275 def immZExt16 : PatLeaf<(imm), [{
276 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
277 // field. Used by instructions like 'ori'.
278 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
281 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
282 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
283 // identical in 32-bit mode, but in 64-bit mode, they return true if the
284 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
286 def imm16ShiftedZExt : PatLeaf<(imm), [{
287 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
288 // immediate are set. Used by instructions like 'xoris'.
289 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
292 def imm16ShiftedSExt : PatLeaf<(imm), [{
293 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
294 // immediate are set. Used by instructions like 'addis'. Identical to
295 // imm16ShiftedZExt in 32-bit mode.
296 if (N->getZExtValue() & 0xFFFF) return false;
297 if (N->getValueType(0) == MVT::i32)
299 // For 64-bit, make sure it is sext right.
300 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
303 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
304 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
305 // zero extended field.
306 return isUInt<32>(Imm);
309 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
310 // restricted memrix (4-aligned) constants are alignment sensitive. If these
311 // offsets are hidden behind TOC entries than the values of the lower-order
312 // bits cannot be checked directly. As a result, we need to also incorporate
313 // an alignment check into the relevant patterns.
315 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
316 return cast<LoadSDNode>(N)->getAlignment() >= 4;
318 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
319 (store node:$val, node:$ptr), [{
320 return cast<StoreSDNode>(N)->getAlignment() >= 4;
322 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
323 return cast<LoadSDNode>(N)->getAlignment() >= 4;
325 def aligned4pre_store : PatFrag<
326 (ops node:$val, node:$base, node:$offset),
327 (pre_store node:$val, node:$base, node:$offset), [{
328 return cast<StoreSDNode>(N)->getAlignment() >= 4;
331 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
332 return cast<LoadSDNode>(N)->getAlignment() < 4;
334 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
335 (store node:$val, node:$ptr), [{
336 return cast<StoreSDNode>(N)->getAlignment() < 4;
338 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
339 return cast<LoadSDNode>(N)->getAlignment() < 4;
342 //===----------------------------------------------------------------------===//
343 // PowerPC Flag Definitions.
345 class isPPC64 { bit PPC64 = 1; }
346 class isDOT { bit RC = 1; }
348 class RegConstraint<string C> {
349 string Constraints = C;
351 class NoEncode<string E> {
352 string DisableEncoding = E;
356 //===----------------------------------------------------------------------===//
357 // PowerPC Operand Definitions.
359 // In the default PowerPC assembler syntax, registers are specified simply
360 // by number, so they cannot be distinguished from immediate values (without
361 // looking at the opcode). This means that the default operand matching logic
362 // for the asm parser does not work, and we need to specify custom matchers.
363 // Since those can only be specified with RegisterOperand classes and not
364 // directly on the RegisterClass, all instructions patterns used by the asm
365 // parser need to use a RegisterOperand (instead of a RegisterClass) for
366 // all their register operands.
367 // For this purpose, we define one RegisterOperand for each RegisterClass,
368 // using the same name as the class, just in lower case.
370 def PPCRegGPRCAsmOperand : AsmOperandClass {
371 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
373 def gprc : RegisterOperand<GPRC> {
374 let ParserMatchClass = PPCRegGPRCAsmOperand;
376 def PPCRegG8RCAsmOperand : AsmOperandClass {
377 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
379 def g8rc : RegisterOperand<G8RC> {
380 let ParserMatchClass = PPCRegG8RCAsmOperand;
382 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
383 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
385 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
386 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
388 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
389 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
391 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
392 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
394 def PPCRegF8RCAsmOperand : AsmOperandClass {
395 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
397 def f8rc : RegisterOperand<F8RC> {
398 let ParserMatchClass = PPCRegF8RCAsmOperand;
400 def PPCRegF4RCAsmOperand : AsmOperandClass {
401 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
403 def f4rc : RegisterOperand<F4RC> {
404 let ParserMatchClass = PPCRegF4RCAsmOperand;
406 def PPCRegVRRCAsmOperand : AsmOperandClass {
407 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
409 def vrrc : RegisterOperand<VRRC> {
410 let ParserMatchClass = PPCRegVRRCAsmOperand;
412 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
413 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
415 def crbitrc : RegisterOperand<CRBITRC> {
416 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
418 def PPCRegCRRCAsmOperand : AsmOperandClass {
419 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
421 def crrc : RegisterOperand<CRRC> {
422 let ParserMatchClass = PPCRegCRRCAsmOperand;
425 def PPCU2ImmAsmOperand : AsmOperandClass {
426 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
427 let RenderMethod = "addImmOperands";
429 def u2imm : Operand<i32> {
430 let PrintMethod = "printU2ImmOperand";
431 let ParserMatchClass = PPCU2ImmAsmOperand;
434 def PPCU4ImmAsmOperand : AsmOperandClass {
435 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
436 let RenderMethod = "addImmOperands";
438 def u4imm : Operand<i32> {
439 let PrintMethod = "printU4ImmOperand";
440 let ParserMatchClass = PPCU4ImmAsmOperand;
442 def PPCS5ImmAsmOperand : AsmOperandClass {
443 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
444 let RenderMethod = "addImmOperands";
446 def s5imm : Operand<i32> {
447 let PrintMethod = "printS5ImmOperand";
448 let ParserMatchClass = PPCS5ImmAsmOperand;
449 let DecoderMethod = "decodeSImmOperand<5>";
451 def PPCU5ImmAsmOperand : AsmOperandClass {
452 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
453 let RenderMethod = "addImmOperands";
455 def u5imm : Operand<i32> {
456 let PrintMethod = "printU5ImmOperand";
457 let ParserMatchClass = PPCU5ImmAsmOperand;
458 let DecoderMethod = "decodeUImmOperand<5>";
460 def PPCU6ImmAsmOperand : AsmOperandClass {
461 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
462 let RenderMethod = "addImmOperands";
464 def u6imm : Operand<i32> {
465 let PrintMethod = "printU6ImmOperand";
466 let ParserMatchClass = PPCU6ImmAsmOperand;
467 let DecoderMethod = "decodeUImmOperand<6>";
469 def PPCS16ImmAsmOperand : AsmOperandClass {
470 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
471 let RenderMethod = "addS16ImmOperands";
473 def s16imm : Operand<i32> {
474 let PrintMethod = "printS16ImmOperand";
475 let EncoderMethod = "getImm16Encoding";
476 let ParserMatchClass = PPCS16ImmAsmOperand;
477 let DecoderMethod = "decodeSImmOperand<16>";
479 def PPCU16ImmAsmOperand : AsmOperandClass {
480 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
481 let RenderMethod = "addU16ImmOperands";
483 def u16imm : Operand<i32> {
484 let PrintMethod = "printU16ImmOperand";
485 let EncoderMethod = "getImm16Encoding";
486 let ParserMatchClass = PPCU16ImmAsmOperand;
487 let DecoderMethod = "decodeUImmOperand<16>";
489 def PPCS17ImmAsmOperand : AsmOperandClass {
490 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
491 let RenderMethod = "addS16ImmOperands";
493 def s17imm : Operand<i32> {
494 // This operand type is used for addis/lis to allow the assembler parser
495 // to accept immediates in the range -65536..65535 for compatibility with
496 // the GNU assembler. The operand is treated as 16-bit otherwise.
497 let PrintMethod = "printS16ImmOperand";
498 let EncoderMethod = "getImm16Encoding";
499 let ParserMatchClass = PPCS17ImmAsmOperand;
500 let DecoderMethod = "decodeSImmOperand<16>";
502 def PPCDirectBrAsmOperand : AsmOperandClass {
503 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
504 let RenderMethod = "addBranchTargetOperands";
506 def directbrtarget : Operand<OtherVT> {
507 let PrintMethod = "printBranchOperand";
508 let EncoderMethod = "getDirectBrEncoding";
509 let ParserMatchClass = PPCDirectBrAsmOperand;
511 def absdirectbrtarget : Operand<OtherVT> {
512 let PrintMethod = "printAbsBranchOperand";
513 let EncoderMethod = "getAbsDirectBrEncoding";
514 let ParserMatchClass = PPCDirectBrAsmOperand;
516 def PPCCondBrAsmOperand : AsmOperandClass {
517 let Name = "CondBr"; let PredicateMethod = "isCondBr";
518 let RenderMethod = "addBranchTargetOperands";
520 def condbrtarget : Operand<OtherVT> {
521 let PrintMethod = "printBranchOperand";
522 let EncoderMethod = "getCondBrEncoding";
523 let ParserMatchClass = PPCCondBrAsmOperand;
525 def abscondbrtarget : Operand<OtherVT> {
526 let PrintMethod = "printAbsBranchOperand";
527 let EncoderMethod = "getAbsCondBrEncoding";
528 let ParserMatchClass = PPCCondBrAsmOperand;
530 def calltarget : Operand<iPTR> {
531 let PrintMethod = "printBranchOperand";
532 let EncoderMethod = "getDirectBrEncoding";
533 let ParserMatchClass = PPCDirectBrAsmOperand;
535 def abscalltarget : Operand<iPTR> {
536 let PrintMethod = "printAbsBranchOperand";
537 let EncoderMethod = "getAbsDirectBrEncoding";
538 let ParserMatchClass = PPCDirectBrAsmOperand;
540 def PPCCRBitMaskOperand : AsmOperandClass {
541 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
543 def crbitm: Operand<i8> {
544 let PrintMethod = "printcrbitm";
545 let EncoderMethod = "get_crbitm_encoding";
546 let DecoderMethod = "decodeCRBitMOperand";
547 let ParserMatchClass = PPCCRBitMaskOperand;
550 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
551 def PPCRegGxRCNoR0Operand : AsmOperandClass {
552 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
554 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
555 let ParserMatchClass = PPCRegGxRCNoR0Operand;
557 // A version of ptr_rc usable with the asm parser.
558 def PPCRegGxRCOperand : AsmOperandClass {
559 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
561 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
562 let ParserMatchClass = PPCRegGxRCOperand;
565 def PPCDispRIOperand : AsmOperandClass {
566 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
567 let RenderMethod = "addS16ImmOperands";
569 def dispRI : Operand<iPTR> {
570 let ParserMatchClass = PPCDispRIOperand;
572 def PPCDispRIXOperand : AsmOperandClass {
573 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
574 let RenderMethod = "addImmOperands";
576 def dispRIX : Operand<iPTR> {
577 let ParserMatchClass = PPCDispRIXOperand;
579 def PPCDispSPE8Operand : AsmOperandClass {
580 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
581 let RenderMethod = "addImmOperands";
583 def dispSPE8 : Operand<iPTR> {
584 let ParserMatchClass = PPCDispSPE8Operand;
586 def PPCDispSPE4Operand : AsmOperandClass {
587 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
588 let RenderMethod = "addImmOperands";
590 def dispSPE4 : Operand<iPTR> {
591 let ParserMatchClass = PPCDispSPE4Operand;
593 def PPCDispSPE2Operand : AsmOperandClass {
594 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
595 let RenderMethod = "addImmOperands";
597 def dispSPE2 : Operand<iPTR> {
598 let ParserMatchClass = PPCDispSPE2Operand;
601 def memri : Operand<iPTR> {
602 let PrintMethod = "printMemRegImm";
603 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
604 let EncoderMethod = "getMemRIEncoding";
605 let DecoderMethod = "decodeMemRIOperands";
607 def memrr : Operand<iPTR> {
608 let PrintMethod = "printMemRegReg";
609 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
611 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
612 let PrintMethod = "printMemRegImm";
613 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
614 let EncoderMethod = "getMemRIXEncoding";
615 let DecoderMethod = "decodeMemRIXOperands";
617 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
618 let PrintMethod = "printMemRegImm";
619 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
620 let EncoderMethod = "getSPE8DisEncoding";
622 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
623 let PrintMethod = "printMemRegImm";
624 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
625 let EncoderMethod = "getSPE4DisEncoding";
627 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
628 let PrintMethod = "printMemRegImm";
629 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
630 let EncoderMethod = "getSPE2DisEncoding";
633 // A single-register address. This is used with the SjLj
634 // pseudo-instructions.
635 def memr : Operand<iPTR> {
636 let MIOperandInfo = (ops ptr_rc:$ptrreg);
638 def PPCTLSRegOperand : AsmOperandClass {
639 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
640 let RenderMethod = "addTLSRegOperands";
642 def tlsreg32 : Operand<i32> {
643 let EncoderMethod = "getTLSRegEncoding";
644 let ParserMatchClass = PPCTLSRegOperand;
646 def tlsgd32 : Operand<i32> {}
647 def tlscall32 : Operand<i32> {
648 let PrintMethod = "printTLSCall";
649 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
650 let EncoderMethod = "getTLSCallEncoding";
653 // PowerPC Predicate operand.
654 def pred : Operand<OtherVT> {
655 let PrintMethod = "printPredicateOperand";
656 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
659 // Define PowerPC specific addressing mode.
660 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
661 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
662 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
663 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
665 // The address in a single register. This is used with the SjLj
666 // pseudo-instructions.
667 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
669 /// This is just the offset part of iaddr, used for preinc.
670 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
672 //===----------------------------------------------------------------------===//
673 // PowerPC Instruction Predicate Definitions.
674 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
675 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
676 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
677 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
678 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
679 def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
680 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
681 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
682 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
683 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
685 //===----------------------------------------------------------------------===//
686 // PowerPC Multiclass Definitions.
688 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
689 string asmbase, string asmstr, InstrItinClass itin,
691 let BaseName = asmbase in {
692 def NAME : XForm_6<opcode, xo, OOL, IOL,
693 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
694 pattern>, RecFormRel;
696 def o : XForm_6<opcode, xo, OOL, IOL,
697 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
698 []>, isDOT, RecFormRel;
702 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
703 string asmbase, string asmstr, InstrItinClass itin,
705 let BaseName = asmbase in {
706 let Defs = [CARRY] in
707 def NAME : XForm_6<opcode, xo, OOL, IOL,
708 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
709 pattern>, RecFormRel;
710 let Defs = [CARRY, CR0] in
711 def o : XForm_6<opcode, xo, OOL, IOL,
712 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
713 []>, isDOT, RecFormRel;
717 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
718 string asmbase, string asmstr, InstrItinClass itin,
720 let BaseName = asmbase in {
721 let Defs = [CARRY] in
722 def NAME : XForm_10<opcode, xo, OOL, IOL,
723 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
724 pattern>, RecFormRel;
725 let Defs = [CARRY, CR0] in
726 def o : XForm_10<opcode, xo, OOL, IOL,
727 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
728 []>, isDOT, RecFormRel;
732 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
733 string asmbase, string asmstr, InstrItinClass itin,
735 let BaseName = asmbase in {
736 def NAME : XForm_11<opcode, xo, OOL, IOL,
737 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
738 pattern>, RecFormRel;
740 def o : XForm_11<opcode, xo, OOL, IOL,
741 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
742 []>, isDOT, RecFormRel;
746 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
747 string asmbase, string asmstr, InstrItinClass itin,
749 let BaseName = asmbase in {
750 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
751 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
752 pattern>, RecFormRel;
754 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
755 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
756 []>, isDOT, RecFormRel;
760 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
761 string asmbase, string asmstr, InstrItinClass itin,
763 let BaseName = asmbase in {
764 let Defs = [CARRY] in
765 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
766 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
767 pattern>, RecFormRel;
768 let Defs = [CARRY, CR0] in
769 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
770 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
771 []>, isDOT, RecFormRel;
775 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
776 string asmbase, string asmstr, InstrItinClass itin,
778 let BaseName = asmbase in {
779 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
780 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
781 pattern>, RecFormRel;
783 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
784 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
785 []>, isDOT, RecFormRel;
789 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
790 string asmbase, string asmstr, InstrItinClass itin,
792 let BaseName = asmbase in {
793 let Defs = [CARRY] in
794 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
795 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
796 pattern>, RecFormRel;
797 let Defs = [CARRY, CR0] in
798 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
799 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
800 []>, isDOT, RecFormRel;
804 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
805 string asmbase, string asmstr, InstrItinClass itin,
807 let BaseName = asmbase in {
808 def NAME : MForm_2<opcode, OOL, IOL,
809 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
810 pattern>, RecFormRel;
812 def o : MForm_2<opcode, OOL, IOL,
813 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
814 []>, isDOT, RecFormRel;
818 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
819 string asmbase, string asmstr, InstrItinClass itin,
821 let BaseName = asmbase in {
822 def NAME : MDForm_1<opcode, xo, OOL, IOL,
823 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
824 pattern>, RecFormRel;
826 def o : MDForm_1<opcode, xo, OOL, IOL,
827 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
828 []>, isDOT, RecFormRel;
832 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
833 string asmbase, string asmstr, InstrItinClass itin,
835 let BaseName = asmbase in {
836 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
837 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
838 pattern>, RecFormRel;
840 def o : MDSForm_1<opcode, xo, OOL, IOL,
841 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
842 []>, isDOT, RecFormRel;
846 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
847 string asmbase, string asmstr, InstrItinClass itin,
849 let BaseName = asmbase in {
850 let Defs = [CARRY] in
851 def NAME : XSForm_1<opcode, xo, OOL, IOL,
852 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
853 pattern>, RecFormRel;
854 let Defs = [CARRY, CR0] in
855 def o : XSForm_1<opcode, xo, OOL, IOL,
856 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
857 []>, isDOT, RecFormRel;
861 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
862 string asmbase, string asmstr, InstrItinClass itin,
864 let BaseName = asmbase in {
865 def NAME : XForm_26<opcode, xo, OOL, IOL,
866 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
867 pattern>, RecFormRel;
869 def o : XForm_26<opcode, xo, OOL, IOL,
870 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
871 []>, isDOT, RecFormRel;
875 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
876 string asmbase, string asmstr, InstrItinClass itin,
878 let BaseName = asmbase in {
879 def NAME : XForm_28<opcode, xo, OOL, IOL,
880 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
881 pattern>, RecFormRel;
883 def o : XForm_28<opcode, xo, OOL, IOL,
884 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
885 []>, isDOT, RecFormRel;
889 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
890 string asmbase, string asmstr, InstrItinClass itin,
892 let BaseName = asmbase in {
893 def NAME : AForm_1<opcode, xo, OOL, IOL,
894 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
895 pattern>, RecFormRel;
897 def o : AForm_1<opcode, xo, OOL, IOL,
898 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
899 []>, isDOT, RecFormRel;
903 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
904 string asmbase, string asmstr, InstrItinClass itin,
906 let BaseName = asmbase in {
907 def NAME : AForm_2<opcode, xo, OOL, IOL,
908 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
909 pattern>, RecFormRel;
911 def o : AForm_2<opcode, xo, OOL, IOL,
912 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
913 []>, isDOT, RecFormRel;
917 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
918 string asmbase, string asmstr, InstrItinClass itin,
920 let BaseName = asmbase in {
921 def NAME : AForm_3<opcode, xo, OOL, IOL,
922 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
923 pattern>, RecFormRel;
925 def o : AForm_3<opcode, xo, OOL, IOL,
926 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
927 []>, isDOT, RecFormRel;
931 //===----------------------------------------------------------------------===//
932 // PowerPC Instruction Definitions.
934 // Pseudo-instructions:
936 let hasCtrlDep = 1 in {
937 let Defs = [R1], Uses = [R1] in {
938 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
939 [(callseq_start timm:$amt)]>;
940 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
941 [(callseq_end timm:$amt1, timm:$amt2)]>;
944 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
945 "UPDATE_VRSAVE $rD, $rS", []>;
948 let Defs = [R1], Uses = [R1] in
949 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
951 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
953 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
954 // instruction selection into a branch sequence.
955 let usesCustomInserter = 1, // Expanded after instruction selection.
956 PPC970_Single = 1 in {
957 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
958 // because either operand might become the first operand in an isel, and
959 // that operand cannot be r0.
960 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
961 gprc_nor0:$T, gprc_nor0:$F,
962 i32imm:$BROPC), "#SELECT_CC_I4",
964 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
965 g8rc_nox0:$T, g8rc_nox0:$F,
966 i32imm:$BROPC), "#SELECT_CC_I8",
968 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
969 i32imm:$BROPC), "#SELECT_CC_F4",
971 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
972 i32imm:$BROPC), "#SELECT_CC_F8",
974 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
975 i32imm:$BROPC), "#SELECT_CC_VRRC",
978 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
979 // register bit directly.
980 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
981 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
982 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
983 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
984 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
985 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
986 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
987 f4rc:$T, f4rc:$F), "#SELECT_F4",
988 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
989 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
990 f8rc:$T, f8rc:$F), "#SELECT_F8",
991 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
992 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
993 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
995 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
998 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
999 // scavenge a register for it.
1000 let mayStore = 1 in {
1001 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1003 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1004 "#SPILL_CRBIT", []>;
1007 // RESTORE_CR - Indicate that we're restoring the CR register (previously
1008 // spilled), so we'll need to scavenge a register for it.
1009 let mayLoad = 1 in {
1010 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1012 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1013 "#RESTORE_CRBIT", []>;
1016 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1017 let isReturn = 1, Uses = [LR, RM] in
1018 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1020 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1021 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1024 let isCodeGenOnly = 1 in {
1025 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1026 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1029 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1030 "bcctr 12, $bi, 0", IIC_BrB, []>;
1031 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1032 "bcctr 4, $bi, 0", IIC_BrB, []>;
1038 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1041 def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1044 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1045 let isBarrier = 1 in {
1046 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1049 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1050 "ba $dst", IIC_BrB, []>;
1053 // BCC represents an arbitrary conditional branch on a predicate.
1054 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1055 // a two-value operand where a dag node expects two operands. :(
1056 let isCodeGenOnly = 1 in {
1057 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1058 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1059 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1060 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1061 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1063 let isReturn = 1, Uses = [LR, RM] in
1064 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1065 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1068 let isCodeGenOnly = 1 in {
1069 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1070 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1071 "bc 12, $bi, $dst">;
1073 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1074 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1077 let isReturn = 1, Uses = [LR, RM] in
1078 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1079 "bclr 12, $bi, 0", IIC_BrB, []>;
1080 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1081 "bclr 4, $bi, 0", IIC_BrB, []>;
1084 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1085 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1086 "bdzlr", IIC_BrB, []>;
1087 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1088 "bdnzlr", IIC_BrB, []>;
1089 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1090 "bdzlr+", IIC_BrB, []>;
1091 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1092 "bdnzlr+", IIC_BrB, []>;
1093 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1094 "bdzlr-", IIC_BrB, []>;
1095 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1096 "bdnzlr-", IIC_BrB, []>;
1099 let Defs = [CTR], Uses = [CTR] in {
1100 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1102 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1104 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1106 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1108 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1110 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1112 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1114 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1116 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1118 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1120 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1122 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1127 // The unconditional BCL used by the SjLj setjmp code.
1128 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1129 let Defs = [LR], Uses = [RM] in {
1130 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1131 "bcl 20, 31, $dst">;
1135 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1136 // Convenient aliases for call instructions
1137 let Uses = [RM] in {
1138 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1139 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1140 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1141 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1143 let isCodeGenOnly = 1 in {
1144 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1145 "bl $func", IIC_BrB, []>;
1146 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1147 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1148 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1149 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1151 def BCL : BForm_4<16, 12, 0, 1, (outs),
1152 (ins crbitrc:$bi, condbrtarget:$dst),
1153 "bcl 12, $bi, $dst">;
1154 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1155 (ins crbitrc:$bi, condbrtarget:$dst),
1156 "bcl 4, $bi, $dst">;
1159 let Uses = [CTR, RM] in {
1160 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1161 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1162 Requires<[In32BitMode]>;
1164 let isCodeGenOnly = 1 in {
1165 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1166 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1169 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1170 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1171 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1172 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1175 let Uses = [LR, RM] in {
1176 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1177 "blrl", IIC_BrB, []>;
1179 let isCodeGenOnly = 1 in {
1180 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1181 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1184 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1185 "bclrl 12, $bi, 0", IIC_BrB, []>;
1186 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1187 "bclrl 4, $bi, 0", IIC_BrB, []>;
1190 let Defs = [CTR], Uses = [CTR, RM] in {
1191 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1193 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1195 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1197 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1199 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1201 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1203 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1205 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1207 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1209 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1211 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1213 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1216 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1217 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1218 "bdzlrl", IIC_BrB, []>;
1219 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1220 "bdnzlrl", IIC_BrB, []>;
1221 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1222 "bdzlrl+", IIC_BrB, []>;
1223 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1224 "bdnzlrl+", IIC_BrB, []>;
1225 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1226 "bdzlrl-", IIC_BrB, []>;
1227 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1228 "bdnzlrl-", IIC_BrB, []>;
1232 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1233 def TCRETURNdi :Pseudo< (outs),
1234 (ins calltarget:$dst, i32imm:$offset),
1235 "#TC_RETURNd $dst $offset",
1239 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1240 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1241 "#TC_RETURNa $func $offset",
1242 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1244 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1245 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1246 "#TC_RETURNr $dst $offset",
1250 let isCodeGenOnly = 1 in {
1252 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1253 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1254 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1255 []>, Requires<[In32BitMode]>;
1257 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1258 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1259 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1263 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1264 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1265 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1271 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1273 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1274 "#EH_SJLJ_SETJMP32",
1275 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1276 Requires<[In32BitMode]>;
1277 let isTerminator = 1 in
1278 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1279 "#EH_SJLJ_LONGJMP32",
1280 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1281 Requires<[In32BitMode]>;
1284 let isBranch = 1, isTerminator = 1 in {
1285 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1286 "#EH_SjLj_Setup\t$dst", []>;
1290 let PPC970_Unit = 7 in {
1291 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1292 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1295 // DCB* instructions.
1296 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1297 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1298 PPC970_DGroup_Single;
1299 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1300 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1301 PPC970_DGroup_Single;
1302 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1303 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1304 PPC970_DGroup_Single;
1305 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1306 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1307 PPC970_DGroup_Single;
1308 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1309 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1310 PPC970_DGroup_Single;
1311 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1312 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1313 PPC970_DGroup_Single;
1314 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1315 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1316 PPC970_DGroup_Single;
1317 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1318 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1319 PPC970_DGroup_Single;
1321 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1322 "icbt $CT, $src", IIC_LdStLoad>, Requires<[IsBookE]>;
1324 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1325 (DCBT xoaddr:$dst)>; // data prefetch for loads
1326 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1327 (DCBTST xoaddr:$dst)>; // data prefetch for stores
1328 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1329 (ICBT 0, xoaddr:$dst)>; // inst prefetch (for read)
1331 // Atomic operations
1332 let usesCustomInserter = 1 in {
1333 let Defs = [CR0] in {
1334 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1335 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1336 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1337 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1338 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1339 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1340 def ATOMIC_LOAD_AND_I8 : Pseudo<
1341 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1342 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1343 def ATOMIC_LOAD_OR_I8 : Pseudo<
1344 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1345 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1346 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1347 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1348 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1349 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1350 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1351 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1352 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1353 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1354 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1355 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1356 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1357 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1358 def ATOMIC_LOAD_AND_I16 : Pseudo<
1359 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1360 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1361 def ATOMIC_LOAD_OR_I16 : Pseudo<
1362 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1363 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1364 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1365 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1366 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1367 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1368 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1369 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1370 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1371 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1372 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1373 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1374 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1375 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1376 def ATOMIC_LOAD_AND_I32 : Pseudo<
1377 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1378 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1379 def ATOMIC_LOAD_OR_I32 : Pseudo<
1380 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1381 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1382 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1383 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1384 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1385 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1386 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1387 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1389 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1390 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1391 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1392 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1393 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1394 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1395 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1396 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1397 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1399 def ATOMIC_SWAP_I8 : Pseudo<
1400 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1401 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1402 def ATOMIC_SWAP_I16 : Pseudo<
1403 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1404 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1405 def ATOMIC_SWAP_I32 : Pseudo<
1406 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1407 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1411 // Instructions to support atomic operations
1412 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1413 "lwarx $rD, $src", IIC_LdStLWARX,
1414 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1417 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1418 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1419 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1422 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1423 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1425 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1426 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1427 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1428 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1429 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1430 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1431 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1432 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1434 //===----------------------------------------------------------------------===//
1435 // PPC32 Load Instructions.
1438 // Unindexed (r+i) Loads.
1439 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1440 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1441 "lbz $rD, $src", IIC_LdStLoad,
1442 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1443 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1444 "lha $rD, $src", IIC_LdStLHA,
1445 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1446 PPC970_DGroup_Cracked;
1447 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1448 "lhz $rD, $src", IIC_LdStLoad,
1449 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1450 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1451 "lwz $rD, $src", IIC_LdStLoad,
1452 [(set i32:$rD, (load iaddr:$src))]>;
1454 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1455 "lfs $rD, $src", IIC_LdStLFD,
1456 [(set f32:$rD, (load iaddr:$src))]>;
1457 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1458 "lfd $rD, $src", IIC_LdStLFD,
1459 [(set f64:$rD, (load iaddr:$src))]>;
1462 // Unindexed (r+i) Loads with Update (preinc).
1463 let mayLoad = 1, hasSideEffects = 0 in {
1464 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1465 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1466 []>, RegConstraint<"$addr.reg = $ea_result">,
1467 NoEncode<"$ea_result">;
1469 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1470 "lhau $rD, $addr", IIC_LdStLHAU,
1471 []>, RegConstraint<"$addr.reg = $ea_result">,
1472 NoEncode<"$ea_result">;
1474 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1475 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1476 []>, RegConstraint<"$addr.reg = $ea_result">,
1477 NoEncode<"$ea_result">;
1479 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1480 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1481 []>, RegConstraint<"$addr.reg = $ea_result">,
1482 NoEncode<"$ea_result">;
1484 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1485 "lfsu $rD, $addr", IIC_LdStLFDU,
1486 []>, RegConstraint<"$addr.reg = $ea_result">,
1487 NoEncode<"$ea_result">;
1489 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1490 "lfdu $rD, $addr", IIC_LdStLFDU,
1491 []>, RegConstraint<"$addr.reg = $ea_result">,
1492 NoEncode<"$ea_result">;
1495 // Indexed (r+r) Loads with Update (preinc).
1496 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1498 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1499 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1500 NoEncode<"$ea_result">;
1502 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1504 "lhaux $rD, $addr", IIC_LdStLHAUX,
1505 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1506 NoEncode<"$ea_result">;
1508 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1510 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1511 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1512 NoEncode<"$ea_result">;
1514 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1516 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1517 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1518 NoEncode<"$ea_result">;
1520 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1522 "lfsux $rD, $addr", IIC_LdStLFDUX,
1523 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1524 NoEncode<"$ea_result">;
1526 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1528 "lfdux $rD, $addr", IIC_LdStLFDUX,
1529 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1530 NoEncode<"$ea_result">;
1534 // Indexed (r+r) Loads.
1536 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1537 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1538 "lbzx $rD, $src", IIC_LdStLoad,
1539 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1540 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1541 "lhax $rD, $src", IIC_LdStLHA,
1542 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1543 PPC970_DGroup_Cracked;
1544 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1545 "lhzx $rD, $src", IIC_LdStLoad,
1546 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1547 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1548 "lwzx $rD, $src", IIC_LdStLoad,
1549 [(set i32:$rD, (load xaddr:$src))]>;
1552 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1553 "lhbrx $rD, $src", IIC_LdStLoad,
1554 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1555 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1556 "lwbrx $rD, $src", IIC_LdStLoad,
1557 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1559 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1560 "lfsx $frD, $src", IIC_LdStLFD,
1561 [(set f32:$frD, (load xaddr:$src))]>;
1562 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1563 "lfdx $frD, $src", IIC_LdStLFD,
1564 [(set f64:$frD, (load xaddr:$src))]>;
1566 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1567 "lfiwax $frD, $src", IIC_LdStLFD,
1568 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1569 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1570 "lfiwzx $frD, $src", IIC_LdStLFD,
1571 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1575 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1576 "lmw $rD, $src", IIC_LdStLMW, []>;
1578 //===----------------------------------------------------------------------===//
1579 // PPC32 Store Instructions.
1582 // Unindexed (r+i) Stores.
1583 let PPC970_Unit = 2 in {
1584 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1585 "stb $rS, $src", IIC_LdStStore,
1586 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1587 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1588 "sth $rS, $src", IIC_LdStStore,
1589 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1590 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1591 "stw $rS, $src", IIC_LdStStore,
1592 [(store i32:$rS, iaddr:$src)]>;
1593 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1594 "stfs $rS, $dst", IIC_LdStSTFD,
1595 [(store f32:$rS, iaddr:$dst)]>;
1596 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1597 "stfd $rS, $dst", IIC_LdStSTFD,
1598 [(store f64:$rS, iaddr:$dst)]>;
1601 // Unindexed (r+i) Stores with Update (preinc).
1602 let PPC970_Unit = 2, mayStore = 1 in {
1603 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1604 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1605 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1606 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1607 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1608 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1609 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1610 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1611 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1612 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1613 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1614 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1615 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1616 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1617 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1620 // Patterns to match the pre-inc stores. We can't put the patterns on
1621 // the instruction definitions directly as ISel wants the address base
1622 // and offset to be separate operands, not a single complex operand.
1623 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1624 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1625 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1626 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1627 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1628 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1629 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1630 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1631 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1632 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1634 // Indexed (r+r) Stores.
1635 let PPC970_Unit = 2 in {
1636 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1637 "stbx $rS, $dst", IIC_LdStStore,
1638 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1639 PPC970_DGroup_Cracked;
1640 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1641 "sthx $rS, $dst", IIC_LdStStore,
1642 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1643 PPC970_DGroup_Cracked;
1644 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1645 "stwx $rS, $dst", IIC_LdStStore,
1646 [(store i32:$rS, xaddr:$dst)]>,
1647 PPC970_DGroup_Cracked;
1649 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1650 "sthbrx $rS, $dst", IIC_LdStStore,
1651 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1652 PPC970_DGroup_Cracked;
1653 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1654 "stwbrx $rS, $dst", IIC_LdStStore,
1655 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1656 PPC970_DGroup_Cracked;
1658 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1659 "stfiwx $frS, $dst", IIC_LdStSTFD,
1660 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1662 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1663 "stfsx $frS, $dst", IIC_LdStSTFD,
1664 [(store f32:$frS, xaddr:$dst)]>;
1665 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1666 "stfdx $frS, $dst", IIC_LdStSTFD,
1667 [(store f64:$frS, xaddr:$dst)]>;
1670 // Indexed (r+r) Stores with Update (preinc).
1671 let PPC970_Unit = 2, mayStore = 1 in {
1672 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1673 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1674 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1675 PPC970_DGroup_Cracked;
1676 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1677 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1678 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1679 PPC970_DGroup_Cracked;
1680 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1681 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1682 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1683 PPC970_DGroup_Cracked;
1684 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1685 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1686 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1687 PPC970_DGroup_Cracked;
1688 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1689 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1690 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1691 PPC970_DGroup_Cracked;
1694 // Patterns to match the pre-inc stores. We can't put the patterns on
1695 // the instruction definitions directly as ISel wants the address base
1696 // and offset to be separate operands, not a single complex operand.
1697 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1698 (STBUX $rS, $ptrreg, $ptroff)>;
1699 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1700 (STHUX $rS, $ptrreg, $ptroff)>;
1701 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1702 (STWUX $rS, $ptrreg, $ptroff)>;
1703 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1704 (STFSUX $rS, $ptrreg, $ptroff)>;
1705 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1706 (STFDUX $rS, $ptrreg, $ptroff)>;
1709 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1710 "stmw $rS, $dst", IIC_LdStLMW, []>;
1712 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1713 "sync $L", IIC_LdStSync, []>;
1715 let isCodeGenOnly = 1 in {
1716 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1717 "msync", IIC_LdStSync, []> {
1722 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>;
1723 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1724 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1725 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1727 //===----------------------------------------------------------------------===//
1728 // PPC32 Arithmetic Instructions.
1731 let PPC970_Unit = 1 in { // FXU Operations.
1732 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1733 "addi $rD, $rA, $imm", IIC_IntSimple,
1734 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1735 let BaseName = "addic" in {
1736 let Defs = [CARRY] in
1737 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1738 "addic $rD, $rA, $imm", IIC_IntGeneral,
1739 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1740 RecFormRel, PPC970_DGroup_Cracked;
1741 let Defs = [CARRY, CR0] in
1742 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1743 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1744 []>, isDOT, RecFormRel;
1746 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1747 "addis $rD, $rA, $imm", IIC_IntSimple,
1748 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1749 let isCodeGenOnly = 1 in
1750 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1751 "la $rD, $sym($rA)", IIC_IntGeneral,
1752 [(set i32:$rD, (add i32:$rA,
1753 (PPClo tglobaladdr:$sym, 0)))]>;
1754 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1755 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1756 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1757 let Defs = [CARRY] in
1758 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1759 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1760 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1762 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1763 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1764 "li $rD, $imm", IIC_IntSimple,
1765 [(set i32:$rD, imm32SExt16:$imm)]>;
1766 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1767 "lis $rD, $imm", IIC_IntSimple,
1768 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1772 let PPC970_Unit = 1 in { // FXU Operations.
1773 let Defs = [CR0] in {
1774 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1775 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1776 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1778 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1779 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1780 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1783 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1784 "ori $dst, $src1, $src2", IIC_IntSimple,
1785 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1786 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1787 "oris $dst, $src1, $src2", IIC_IntSimple,
1788 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1789 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1790 "xori $dst, $src1, $src2", IIC_IntSimple,
1791 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1792 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1793 "xoris $dst, $src1, $src2", IIC_IntSimple,
1794 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1796 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1798 let isCodeGenOnly = 1 in {
1799 // The POWER6 and POWER7 have special group-terminating nops.
1800 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1801 "ori 1, 1, 0", IIC_IntSimple, []>;
1802 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1803 "ori 2, 2, 0", IIC_IntSimple, []>;
1806 let isCompare = 1, hasSideEffects = 0 in {
1807 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1808 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1809 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1810 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1814 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
1815 let isCommutable = 1 in {
1816 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1817 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1818 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1819 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1820 "and", "$rA, $rS, $rB", IIC_IntSimple,
1821 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1823 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1824 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1825 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1826 let isCommutable = 1 in {
1827 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1828 "or", "$rA, $rS, $rB", IIC_IntSimple,
1829 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1830 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1831 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1832 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1834 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1835 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1836 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1837 let isCommutable = 1 in {
1838 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1839 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1840 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1841 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1842 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1843 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1845 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1846 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1847 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1848 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1849 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1850 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1851 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1852 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1853 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1856 let PPC970_Unit = 1 in { // FXU Operations.
1857 let hasSideEffects = 0 in {
1858 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1859 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1860 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1861 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1862 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1863 [(set i32:$rA, (ctlz i32:$rS))]>;
1864 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1865 "extsb", "$rA, $rS", IIC_IntSimple,
1866 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1867 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1868 "extsh", "$rA, $rS", IIC_IntSimple,
1869 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1871 let isCommutable = 1 in
1872 def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1873 "cmpb $rA, $rS, $rB", IIC_IntGeneral,
1874 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
1876 let isCompare = 1, hasSideEffects = 0 in {
1877 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1878 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1879 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1880 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1883 let PPC970_Unit = 3 in { // FPU Operations.
1884 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1885 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1886 let isCompare = 1, hasSideEffects = 0 in {
1887 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1888 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1889 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1890 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1891 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1894 let Uses = [RM] in {
1895 let hasSideEffects = 0 in {
1896 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1897 "fctiw", "$frD, $frB", IIC_FPGeneral,
1899 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1900 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1901 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1903 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1904 "frsp", "$frD, $frB", IIC_FPGeneral,
1905 [(set f32:$frD, (fround f64:$frB))]>;
1907 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1908 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1909 "frin", "$frD, $frB", IIC_FPGeneral,
1910 [(set f64:$frD, (frnd f64:$frB))]>;
1911 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1912 "frin", "$frD, $frB", IIC_FPGeneral,
1913 [(set f32:$frD, (frnd f32:$frB))]>;
1916 let hasSideEffects = 0 in {
1917 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1918 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1919 "frip", "$frD, $frB", IIC_FPGeneral,
1920 [(set f64:$frD, (fceil f64:$frB))]>;
1921 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1922 "frip", "$frD, $frB", IIC_FPGeneral,
1923 [(set f32:$frD, (fceil f32:$frB))]>;
1924 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1925 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1926 "friz", "$frD, $frB", IIC_FPGeneral,
1927 [(set f64:$frD, (ftrunc f64:$frB))]>;
1928 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1929 "friz", "$frD, $frB", IIC_FPGeneral,
1930 [(set f32:$frD, (ftrunc f32:$frB))]>;
1931 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1932 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1933 "frim", "$frD, $frB", IIC_FPGeneral,
1934 [(set f64:$frD, (ffloor f64:$frB))]>;
1935 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1936 "frim", "$frD, $frB", IIC_FPGeneral,
1937 [(set f32:$frD, (ffloor f32:$frB))]>;
1939 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1940 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1941 [(set f64:$frD, (fsqrt f64:$frB))]>;
1942 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1943 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1944 [(set f32:$frD, (fsqrt f32:$frB))]>;
1949 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1950 /// often coalesced away and we don't want the dispatch group builder to think
1951 /// that they will fill slots (which could cause the load of a LSU reject to
1952 /// sneak into a d-group with a store).
1953 let hasSideEffects = 0 in
1954 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1955 "fmr", "$frD, $frB", IIC_FPGeneral,
1956 []>, // (set f32:$frD, f32:$frB)
1959 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
1960 // These are artificially split into two different forms, for 4/8 byte FP.
1961 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1962 "fabs", "$frD, $frB", IIC_FPGeneral,
1963 [(set f32:$frD, (fabs f32:$frB))]>;
1964 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1965 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1966 "fabs", "$frD, $frB", IIC_FPGeneral,
1967 [(set f64:$frD, (fabs f64:$frB))]>;
1968 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1969 "fnabs", "$frD, $frB", IIC_FPGeneral,
1970 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1971 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1972 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1973 "fnabs", "$frD, $frB", IIC_FPGeneral,
1974 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1975 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1976 "fneg", "$frD, $frB", IIC_FPGeneral,
1977 [(set f32:$frD, (fneg f32:$frB))]>;
1978 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1979 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1980 "fneg", "$frD, $frB", IIC_FPGeneral,
1981 [(set f64:$frD, (fneg f64:$frB))]>;
1983 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1984 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1985 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1986 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1987 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1988 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1989 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1991 // Reciprocal estimates.
1992 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1993 "fre", "$frD, $frB", IIC_FPGeneral,
1994 [(set f64:$frD, (PPCfre f64:$frB))]>;
1995 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1996 "fres", "$frD, $frB", IIC_FPGeneral,
1997 [(set f32:$frD, (PPCfre f32:$frB))]>;
1998 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1999 "frsqrte", "$frD, $frB", IIC_FPGeneral,
2000 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2001 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2002 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2003 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2006 // XL-Form instructions. condition register logical ops.
2008 let hasSideEffects = 0 in
2009 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2010 "mcrf $BF, $BFA", IIC_BrMCR>,
2011 PPC970_DGroup_First, PPC970_Unit_CRU;
2013 // FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2014 // condition-register logical instructions have preferred forms. Specifically,
2015 // it is preferred that the bit specified by the BT field be in the same
2016 // condition register as that specified by the bit BB. We might want to account
2017 // for this via hinting the register allocator and anti-dep breakers, or we
2018 // could constrain the register class to force this constraint and then loosen
2019 // it during register allocation via convertToThreeAddress or some similar
2022 let isCommutable = 1 in {
2023 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
2024 (ins crbitrc:$CRA, crbitrc:$CRB),
2025 "crand $CRD, $CRA, $CRB", IIC_BrCR,
2026 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2028 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2029 (ins crbitrc:$CRA, crbitrc:$CRB),
2030 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2031 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2033 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
2034 (ins crbitrc:$CRA, crbitrc:$CRB),
2035 "cror $CRD, $CRA, $CRB", IIC_BrCR,
2036 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2038 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
2039 (ins crbitrc:$CRA, crbitrc:$CRB),
2040 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2041 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2043 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
2044 (ins crbitrc:$CRA, crbitrc:$CRB),
2045 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2046 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2048 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
2049 (ins crbitrc:$CRA, crbitrc:$CRB),
2050 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2051 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2054 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2055 (ins crbitrc:$CRA, crbitrc:$CRB),
2056 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2057 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2059 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
2060 (ins crbitrc:$CRA, crbitrc:$CRB),
2061 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2062 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2064 let isCodeGenOnly = 1 in {
2065 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2066 "creqv $dst, $dst, $dst", IIC_BrCR,
2067 [(set i1:$dst, 1)]>;
2069 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2070 "crxor $dst, $dst, $dst", IIC_BrCR,
2071 [(set i1:$dst, 0)]>;
2073 let Defs = [CR1EQ], CRD = 6 in {
2074 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2075 "creqv 6, 6, 6", IIC_BrCR,
2078 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2079 "crxor 6, 6, 6", IIC_BrCR,
2084 // XFX-Form instructions. Instructions that deal with SPRs.
2087 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2088 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2089 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2090 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2092 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2093 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2095 // A pseudo-instruction used to implement the read of the 64-bit cycle counter
2096 // on a 32-bit target.
2097 let hasSideEffects = 1, usesCustomInserter = 1 in
2098 def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2101 let Uses = [CTR] in {
2102 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2103 "mfctr $rT", IIC_SprMFSPR>,
2104 PPC970_DGroup_First, PPC970_Unit_FXU;
2106 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2107 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2108 "mtctr $rS", IIC_SprMTSPR>,
2109 PPC970_DGroup_First, PPC970_Unit_FXU;
2111 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2112 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2113 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2114 "mtctr $rS", IIC_SprMTSPR>,
2115 PPC970_DGroup_First, PPC970_Unit_FXU;
2118 let Defs = [LR] in {
2119 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2120 "mtlr $rS", IIC_SprMTSPR>,
2121 PPC970_DGroup_First, PPC970_Unit_FXU;
2123 let Uses = [LR] in {
2124 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2125 "mflr $rT", IIC_SprMFSPR>,
2126 PPC970_DGroup_First, PPC970_Unit_FXU;
2129 let isCodeGenOnly = 1 in {
2130 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2131 // like a GPR on the PPC970. As such, copies in and out have the same
2132 // performance characteristics as an OR instruction.
2133 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2134 "mtspr 256, $rS", IIC_IntGeneral>,
2135 PPC970_DGroup_Single, PPC970_Unit_FXU;
2136 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2137 "mfspr $rT, 256", IIC_IntGeneral>,
2138 PPC970_DGroup_First, PPC970_Unit_FXU;
2140 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2141 (outs VRSAVERC:$reg), (ins gprc:$rS),
2142 "mtspr 256, $rS", IIC_IntGeneral>,
2143 PPC970_DGroup_Single, PPC970_Unit_FXU;
2144 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2145 (ins VRSAVERC:$reg),
2146 "mfspr $rT, 256", IIC_IntGeneral>,
2147 PPC970_DGroup_First, PPC970_Unit_FXU;
2150 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2151 // so we'll need to scavenge a register for it.
2153 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2154 "#SPILL_VRSAVE", []>;
2156 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2157 // spilled), so we'll need to scavenge a register for it.
2159 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2160 "#RESTORE_VRSAVE", []>;
2162 let hasSideEffects = 0 in {
2163 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2164 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2165 PPC970_DGroup_First, PPC970_Unit_CRU;
2167 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2168 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2169 PPC970_MicroCode, PPC970_Unit_CRU;
2171 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2172 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2173 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2174 PPC970_DGroup_First, PPC970_Unit_CRU;
2176 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2177 "mfcr $rT", IIC_SprMFCR>,
2178 PPC970_MicroCode, PPC970_Unit_CRU;
2179 } // hasSideEffects = 0
2181 // Pseudo instruction to perform FADD in round-to-zero mode.
2182 let usesCustomInserter = 1, Uses = [RM] in {
2183 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2184 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2187 // The above pseudo gets expanded to make use of the following instructions
2188 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2189 let Uses = [RM], Defs = [RM] in {
2190 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2191 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2192 PPC970_DGroup_Single, PPC970_Unit_FPU;
2193 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2194 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2195 PPC970_DGroup_Single, PPC970_Unit_FPU;
2196 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2197 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2198 PPC970_DGroup_Single, PPC970_Unit_FPU;
2200 let Uses = [RM] in {
2201 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2202 "mffs $rT", IIC_IntMFFS,
2203 [(set f64:$rT, (PPCmffs))]>,
2204 PPC970_DGroup_Single, PPC970_Unit_FPU;
2208 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
2209 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2210 let isCommutable = 1 in
2211 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2212 "add", "$rT, $rA, $rB", IIC_IntSimple,
2213 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2214 let isCodeGenOnly = 1 in
2215 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2216 "add $rT, $rA, $rB", IIC_IntSimple,
2217 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2218 let isCommutable = 1 in
2219 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2220 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2221 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2222 PPC970_DGroup_Cracked;
2224 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2225 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2226 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2227 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2228 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2229 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2230 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2231 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2232 let isCommutable = 1 in {
2233 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2234 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2235 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2236 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2237 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2238 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2239 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2240 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2241 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2243 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2244 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2245 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2246 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2247 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2248 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2249 PPC970_DGroup_Cracked;
2250 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2251 "neg", "$rT, $rA", IIC_IntSimple,
2252 [(set i32:$rT, (ineg i32:$rA))]>;
2253 let Uses = [CARRY] in {
2254 let isCommutable = 1 in
2255 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2256 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2257 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2258 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2259 "addme", "$rT, $rA", IIC_IntGeneral,
2260 [(set i32:$rT, (adde i32:$rA, -1))]>;
2261 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2262 "addze", "$rT, $rA", IIC_IntGeneral,
2263 [(set i32:$rT, (adde i32:$rA, 0))]>;
2264 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2265 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2266 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2267 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2268 "subfme", "$rT, $rA", IIC_IntGeneral,
2269 [(set i32:$rT, (sube -1, i32:$rA))]>;
2270 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2271 "subfze", "$rT, $rA", IIC_IntGeneral,
2272 [(set i32:$rT, (sube 0, i32:$rA))]>;
2276 // A-Form instructions. Most of the instructions executed in the FPU are of
2279 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2280 let Uses = [RM] in {
2281 let isCommutable = 1 in {
2282 defm FMADD : AForm_1r<63, 29,
2283 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2284 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2285 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2286 defm FMADDS : AForm_1r<59, 29,
2287 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2288 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2289 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2290 defm FMSUB : AForm_1r<63, 28,
2291 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2292 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2294 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2295 defm FMSUBS : AForm_1r<59, 28,
2296 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2297 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2299 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2300 defm FNMADD : AForm_1r<63, 31,
2301 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2302 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2304 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2305 defm FNMADDS : AForm_1r<59, 31,
2306 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2307 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2309 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2310 defm FNMSUB : AForm_1r<63, 30,
2311 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2312 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2313 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2314 (fneg f64:$FRB))))]>;
2315 defm FNMSUBS : AForm_1r<59, 30,
2316 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2317 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2318 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2319 (fneg f32:$FRB))))]>;
2322 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2323 // having 4 of these, force the comparison to always be an 8-byte double (code
2324 // should use an FMRSD if the input comparison value really wants to be a float)
2325 // and 4/8 byte forms for the result and operand type..
2326 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2327 defm FSELD : AForm_1r<63, 23,
2328 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2329 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2330 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2331 defm FSELS : AForm_1r<63, 23,
2332 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2333 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2334 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2335 let Uses = [RM] in {
2336 let isCommutable = 1 in {
2337 defm FADD : AForm_2r<63, 21,
2338 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2339 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2340 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2341 defm FADDS : AForm_2r<59, 21,
2342 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2343 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2344 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2346 defm FDIV : AForm_2r<63, 18,
2347 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2348 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2349 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2350 defm FDIVS : AForm_2r<59, 18,
2351 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2352 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2353 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2354 let isCommutable = 1 in {
2355 defm FMUL : AForm_3r<63, 25,
2356 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2357 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2358 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2359 defm FMULS : AForm_3r<59, 25,
2360 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2361 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2362 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2364 defm FSUB : AForm_2r<63, 20,
2365 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2366 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2367 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2368 defm FSUBS : AForm_2r<59, 20,
2369 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2370 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2371 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2375 let hasSideEffects = 0 in {
2376 let PPC970_Unit = 1 in { // FXU Operations.
2378 def ISEL : AForm_4<31, 15,
2379 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2380 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
2384 let PPC970_Unit = 1 in { // FXU Operations.
2385 // M-Form instructions. rotate and mask instructions.
2387 let isCommutable = 1 in {
2388 // RLWIMI can be commuted if the rotate amount is zero.
2389 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2390 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2391 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2392 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2393 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2395 let BaseName = "rlwinm" in {
2396 def RLWINM : MForm_2<21,
2397 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2398 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2401 def RLWINMo : MForm_2<21,
2402 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2403 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2404 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2406 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2407 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2408 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2411 } // hasSideEffects = 0
2413 //===----------------------------------------------------------------------===//
2414 // PowerPC Instruction Patterns
2417 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2418 def : Pat<(i32 imm:$imm),
2419 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2421 // Implement the 'not' operation with the NOR instruction.
2422 def i32not : OutPatFrag<(ops node:$in),
2424 def : Pat<(not i32:$in),
2427 // ADD an arbitrary immediate.
2428 def : Pat<(add i32:$in, imm:$imm),
2429 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2430 // OR an arbitrary immediate.
2431 def : Pat<(or i32:$in, imm:$imm),
2432 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2433 // XOR an arbitrary immediate.
2434 def : Pat<(xor i32:$in, imm:$imm),
2435 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2437 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2438 (SUBFIC $in, imm:$imm)>;
2441 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2442 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2443 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2444 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2447 def : Pat<(rotl i32:$in, i32:$sh),
2448 (RLWNM $in, $sh, 0, 31)>;
2449 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2450 (RLWINM $in, imm:$imm, 0, 31)>;
2453 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2454 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2457 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2458 (BL tglobaladdr:$dst)>;
2459 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2460 (BL texternalsym:$dst)>;
2462 def : Pat<(PPCcall_tls texternalsym:$func, tglobaltlsaddr:$sym),
2463 (BL_TLS texternalsym:$func, tglobaltlsaddr:$sym)>;
2465 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2466 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2468 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2469 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2471 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2472 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2476 // Hi and Lo for Darwin Global Addresses.
2477 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2478 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2479 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2480 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2481 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2482 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2483 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2484 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2485 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2486 (ADDIS $in, tglobaltlsaddr:$g)>;
2487 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2488 (ADDI $in, tglobaltlsaddr:$g)>;
2489 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2490 (ADDIS $in, tglobaladdr:$g)>;
2491 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2492 (ADDIS $in, tconstpool:$g)>;
2493 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2494 (ADDIS $in, tjumptable:$g)>;
2495 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2496 (ADDIS $in, tblockaddress:$g)>;
2498 // Support for thread-local storage.
2499 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2500 [(set i32:$rD, (PPCppc32GOT))]>;
2502 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2503 // This uses two output registers, the first as the real output, the second as a
2504 // temporary register, used internally in code generation.
2505 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2506 []>, NoEncode<"$rT">;
2508 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2511 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2512 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2513 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2515 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2518 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2519 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2522 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2523 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2526 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2527 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2530 (PPCaddisDtprelHA i32:$reg,
2531 tglobaltlsaddr:$disp))]>;
2533 // Support for Position-independent code
2534 def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2537 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2538 // Get Global (GOT) Base Register offset, from the word immediately preceding
2539 // the function label.
2540 def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2543 // Standard shifts. These are represented separately from the real shifts above
2544 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2546 def : Pat<(sra i32:$rS, i32:$rB),
2548 def : Pat<(srl i32:$rS, i32:$rB),
2550 def : Pat<(shl i32:$rS, i32:$rB),
2553 def : Pat<(zextloadi1 iaddr:$src),
2555 def : Pat<(zextloadi1 xaddr:$src),
2557 def : Pat<(extloadi1 iaddr:$src),
2559 def : Pat<(extloadi1 xaddr:$src),
2561 def : Pat<(extloadi8 iaddr:$src),
2563 def : Pat<(extloadi8 xaddr:$src),
2565 def : Pat<(extloadi16 iaddr:$src),
2567 def : Pat<(extloadi16 xaddr:$src),
2569 def : Pat<(f64 (extloadf32 iaddr:$src)),
2570 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2571 def : Pat<(f64 (extloadf32 xaddr:$src)),
2572 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2574 def : Pat<(f64 (fextend f32:$src)),
2575 (COPY_TO_REGCLASS $src, F8RC)>;
2577 // Only seq_cst fences require the heavyweight sync (SYNC 0).
2578 // All others can use the lightweight sync (SYNC 1).
2579 // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2580 // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2581 // versions of Power.
2582 def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2583 def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2584 def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2585 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2587 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2588 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2589 (FNMSUB $A, $C, $B)>;
2590 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2591 (FNMSUB $A, $C, $B)>;
2592 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2593 (FNMSUBS $A, $C, $B)>;
2594 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2595 (FNMSUBS $A, $C, $B)>;
2597 // FCOPYSIGN's operand types need not agree.
2598 def : Pat<(fcopysign f64:$frB, f32:$frA),
2599 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2600 def : Pat<(fcopysign f32:$frB, f64:$frA),
2601 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2603 include "PPCInstrAltivec.td"
2604 include "PPCInstrSPE.td"
2605 include "PPCInstr64Bit.td"
2606 include "PPCInstrVSX.td"
2608 def crnot : OutPatFrag<(ops node:$in),
2610 def : Pat<(not i1:$in),
2613 // Patterns for arithmetic i1 operations.
2614 def : Pat<(add i1:$a, i1:$b),
2616 def : Pat<(sub i1:$a, i1:$b),
2618 def : Pat<(mul i1:$a, i1:$b),
2621 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2622 // (-1 is used to mean all bits set).
2623 def : Pat<(i1 -1), (CRSET)>;
2625 // i1 extensions, implemented in terms of isel.
2626 def : Pat<(i32 (zext i1:$in)),
2627 (SELECT_I4 $in, (LI 1), (LI 0))>;
2628 def : Pat<(i32 (sext i1:$in)),
2629 (SELECT_I4 $in, (LI -1), (LI 0))>;
2631 def : Pat<(i64 (zext i1:$in)),
2632 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2633 def : Pat<(i64 (sext i1:$in)),
2634 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2636 // FIXME: We should choose either a zext or a sext based on other constants
2638 def : Pat<(i32 (anyext i1:$in)),
2639 (SELECT_I4 $in, (LI 1), (LI 0))>;
2640 def : Pat<(i64 (anyext i1:$in)),
2641 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2643 // match setcc on i1 variables.
2644 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2646 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2648 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2650 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2652 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2654 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2656 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2658 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2660 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2662 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2665 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2666 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2667 // floating-point types.
2669 multiclass CRNotPat<dag pattern, dag result> {
2670 def : Pat<pattern, (crnot result)>;
2671 def : Pat<(not pattern), result>;
2673 // We can also fold the crnot into an extension:
2674 def : Pat<(i32 (zext pattern)),
2675 (SELECT_I4 result, (LI 0), (LI 1))>;
2676 def : Pat<(i32 (sext pattern)),
2677 (SELECT_I4 result, (LI 0), (LI -1))>;
2679 // We can also fold the crnot into an extension:
2680 def : Pat<(i64 (zext pattern)),
2681 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2682 def : Pat<(i64 (sext pattern)),
2683 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2685 // FIXME: We should choose either a zext or a sext based on other constants
2687 def : Pat<(i32 (anyext pattern)),
2688 (SELECT_I4 result, (LI 0), (LI 1))>;
2690 def : Pat<(i64 (anyext pattern)),
2691 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2694 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2695 // we need to write imm:$imm in the output patterns below, not just $imm, or
2696 // else the resulting matcher will not correctly add the immediate operand
2697 // (making it a register operand instead).
2700 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2701 OutPatFrag rfrag, OutPatFrag rfrag8> {
2702 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2704 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2706 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2707 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2708 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2709 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2711 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2713 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2715 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2716 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2717 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2718 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2721 // Note that we do all inversions below with i(32|64)not, instead of using
2722 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2723 // has 2-cycle latency.
2725 defm : ExtSetCCPat<SETEQ,
2726 PatFrag<(ops node:$in, node:$cc),
2727 (setcc $in, 0, $cc)>,
2728 OutPatFrag<(ops node:$in),
2729 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2730 OutPatFrag<(ops node:$in),
2731 (RLDICL (CNTLZD $in), 58, 63)> >;
2733 defm : ExtSetCCPat<SETNE,
2734 PatFrag<(ops node:$in, node:$cc),
2735 (setcc $in, 0, $cc)>,
2736 OutPatFrag<(ops node:$in),
2737 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2738 OutPatFrag<(ops node:$in),
2739 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2741 defm : ExtSetCCPat<SETLT,
2742 PatFrag<(ops node:$in, node:$cc),
2743 (setcc $in, 0, $cc)>,
2744 OutPatFrag<(ops node:$in),
2745 (RLWINM $in, 1, 31, 31)>,
2746 OutPatFrag<(ops node:$in),
2747 (RLDICL $in, 1, 63)> >;
2749 defm : ExtSetCCPat<SETGE,
2750 PatFrag<(ops node:$in, node:$cc),
2751 (setcc $in, 0, $cc)>,
2752 OutPatFrag<(ops node:$in),
2753 (RLWINM (i32not $in), 1, 31, 31)>,
2754 OutPatFrag<(ops node:$in),
2755 (RLDICL (i64not $in), 1, 63)> >;
2757 defm : ExtSetCCPat<SETGT,
2758 PatFrag<(ops node:$in, node:$cc),
2759 (setcc $in, 0, $cc)>,
2760 OutPatFrag<(ops node:$in),
2761 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2762 OutPatFrag<(ops node:$in),
2763 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2765 defm : ExtSetCCPat<SETLE,
2766 PatFrag<(ops node:$in, node:$cc),
2767 (setcc $in, 0, $cc)>,
2768 OutPatFrag<(ops node:$in),
2769 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2770 OutPatFrag<(ops node:$in),
2771 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2773 defm : ExtSetCCPat<SETLT,
2774 PatFrag<(ops node:$in, node:$cc),
2775 (setcc $in, -1, $cc)>,
2776 OutPatFrag<(ops node:$in),
2777 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2778 OutPatFrag<(ops node:$in),
2779 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2781 defm : ExtSetCCPat<SETGE,
2782 PatFrag<(ops node:$in, node:$cc),
2783 (setcc $in, -1, $cc)>,
2784 OutPatFrag<(ops node:$in),
2785 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2786 OutPatFrag<(ops node:$in),
2787 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2789 defm : ExtSetCCPat<SETGT,
2790 PatFrag<(ops node:$in, node:$cc),
2791 (setcc $in, -1, $cc)>,
2792 OutPatFrag<(ops node:$in),
2793 (RLWINM (i32not $in), 1, 31, 31)>,
2794 OutPatFrag<(ops node:$in),
2795 (RLDICL (i64not $in), 1, 63)> >;
2797 defm : ExtSetCCPat<SETLE,
2798 PatFrag<(ops node:$in, node:$cc),
2799 (setcc $in, -1, $cc)>,
2800 OutPatFrag<(ops node:$in),
2801 (RLWINM $in, 1, 31, 31)>,
2802 OutPatFrag<(ops node:$in),
2803 (RLDICL $in, 1, 63)> >;
2806 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2807 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2808 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2809 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2810 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2811 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2812 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2813 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2814 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2815 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2816 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2817 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2819 // For non-equality comparisons, the default code would materialize the
2820 // constant, then compare against it, like this:
2822 // ori r2, r2, 22136
2825 // Since we are just comparing for equality, we can emit this instead:
2826 // xoris r0,r3,0x1234
2827 // cmplwi cr0,r0,0x5678
2830 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2831 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2832 (LO16 imm:$imm)), sub_eq)>;
2834 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2835 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2836 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2837 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2838 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2839 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2840 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2841 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2842 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2843 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2844 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2845 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2847 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2848 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2849 (LO16 imm:$imm)), sub_eq)>;
2851 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
2852 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2853 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2854 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2855 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2856 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2857 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
2858 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2859 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2860 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2862 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2863 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2864 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
2865 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2866 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2867 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2868 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
2869 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2870 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2871 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2874 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
2875 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2876 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2877 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2878 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2879 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2880 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
2881 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2882 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
2883 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2884 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
2885 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2887 // For non-equality comparisons, the default code would materialize the
2888 // constant, then compare against it, like this:
2890 // ori r2, r2, 22136
2893 // Since we are just comparing for equality, we can emit this instead:
2894 // xoris r0,r3,0x1234
2895 // cmpldi cr0,r0,0x5678
2898 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
2899 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2900 (LO16 imm:$imm)), sub_eq)>;
2902 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
2903 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2904 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
2905 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2906 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
2907 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2908 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
2909 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2910 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
2911 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2912 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
2913 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2915 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
2916 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2917 (LO16 imm:$imm)), sub_eq)>;
2919 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
2920 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2921 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
2922 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2923 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
2924 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2925 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
2926 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2927 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
2928 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2930 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
2931 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2932 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
2933 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2934 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
2935 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2936 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
2937 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2938 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
2939 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2942 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
2943 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2944 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
2945 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2946 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
2947 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2948 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
2949 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2950 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
2951 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2952 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
2953 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2954 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
2955 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2957 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
2958 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2959 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
2960 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2961 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
2962 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2963 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
2964 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2965 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
2966 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2967 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
2968 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2969 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
2970 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2973 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
2974 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2975 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
2976 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2977 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
2978 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2979 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
2980 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2981 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
2982 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2983 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
2984 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2985 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
2986 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2988 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
2989 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2990 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
2991 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2992 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
2993 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2994 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
2995 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2996 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
2997 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2998 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
2999 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3000 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3001 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3003 // match select on i1 variables:
3004 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3005 (CROR (CRAND $cond , $tval),
3006 (CRAND (crnot $cond), $fval))>;
3008 // match selectcc on i1 variables:
3009 // select (lhs == rhs), tval, fval is:
3010 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3011 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3012 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3013 (CRAND (CRORC $lhs, $rhs), $fval))>;
3014 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3015 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
3016 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3017 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3018 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3019 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3020 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3021 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
3022 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3023 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3024 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3025 (CRAND (CRORC $rhs, $lhs), $fval))>;
3026 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3027 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3028 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3030 // match selectcc on i1 variables with non-i1 output.
3031 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3032 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3033 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3034 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3035 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3036 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3037 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3038 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3039 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3040 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3041 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3042 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3044 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3045 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3046 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3047 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3048 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3049 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3050 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3051 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3052 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3053 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3054 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3055 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3057 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3058 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3059 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3060 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3061 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3062 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3063 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3064 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3065 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3066 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3067 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3068 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3070 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3071 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3072 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3073 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3074 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3075 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3076 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3077 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3078 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3079 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3080 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3081 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3083 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3084 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3085 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3086 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3087 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3088 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3089 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3090 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3091 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3092 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3093 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3094 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3096 let usesCustomInserter = 1 in {
3097 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3099 [(set i1:$dst, (trunc (not i32:$in)))]>;
3100 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3102 [(set i1:$dst, (trunc i32:$in))]>;
3104 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3106 [(set i1:$dst, (trunc (not i64:$in)))]>;
3107 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3109 [(set i1:$dst, (trunc i64:$in))]>;
3112 def : Pat<(i1 (not (trunc i32:$in))),
3113 (ANDIo_1_EQ_BIT $in)>;
3114 def : Pat<(i1 (not (trunc i64:$in))),
3115 (ANDIo_1_EQ_BIT8 $in)>;
3117 //===----------------------------------------------------------------------===//
3118 // PowerPC Instructions used for assembler/disassembler only
3121 // FIXME: For B=0 or B > 8, the registers following RT are used.
3122 // WARNING: Do not add patterns for this instruction without fixing this.
3123 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3124 "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3126 // FIXME: For B=0 or B > 8, the registers following RT are used.
3127 // WARNING: Do not add patterns for this instruction without fixing this.
3128 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3129 "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3131 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3132 "isync", IIC_SprISYNC, []>;
3134 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3135 "icbi $src", IIC_LdStICBI, []>;
3137 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3138 "eieio", IIC_LdStLoad, []>;
3140 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3141 "wait $L", IIC_LdStLoad, []>;
3143 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3144 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3146 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3147 "mtsr $SR, $RS", IIC_SprMTSR>;
3149 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3150 "mfsr $RS, $SR", IIC_SprMFSR>;
3152 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3153 "mtsrin $RS, $RB", IIC_SprMTSR>;
3155 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3156 "mfsrin $RS, $RB", IIC_SprMFSR>;
3158 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3159 "mtmsr $RS, $L", IIC_SprMTMSR>;
3161 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3162 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3166 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3167 Requires<[IsBookE]> {
3171 let Inst{21-30} = 163;
3174 def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3175 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3176 def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3177 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3179 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3180 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3181 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3182 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3184 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3185 "mfmsr $RT", IIC_SprMFMSR, []>;
3187 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3188 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3190 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3191 "slbie $RB", IIC_SprSLBIE, []>;
3193 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3194 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3196 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3197 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3199 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3201 def TLBIA : XForm_0<31, 370, (outs), (ins),
3202 "tlbia", IIC_SprTLBIA, []>;
3204 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3205 "tlbsync", IIC_SprTLBSYNC, []>;
3207 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3208 "tlbiel $RB", IIC_SprTLBIEL, []>;
3210 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3211 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3212 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3213 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3215 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3216 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3218 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3219 IIC_LdStLoad>, Requires<[IsBookE]>;
3221 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3222 IIC_LdStLoad>, Requires<[IsBookE]>;
3224 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3225 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3227 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3228 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3230 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3231 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3233 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3234 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3236 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3237 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3238 Requires<[IsPPC4xx]>;
3239 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3240 (ins gprc:$RST, gprc:$A, gprc:$B),
3241 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3242 Requires<[IsPPC4xx]>, isDOT;
3244 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3246 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3247 Requires<[IsBookE]>;
3248 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3249 Requires<[IsBookE]>;
3251 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3253 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3256 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3257 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3258 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3259 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3261 def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3263 def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3264 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3265 def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3266 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3267 def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3268 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3269 def LDCIX : XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3270 "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3272 def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3273 "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3274 def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3275 "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3276 def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3277 "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3278 def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3279 "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3281 //===----------------------------------------------------------------------===//
3282 // PowerPC Assembler Instruction Aliases
3285 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3286 // These are aliases that require C++ handling to convert to the target
3287 // instruction, while InstAliases can be handled directly by tblgen.
3288 class PPCAsmPseudo<string asm, dag iops>
3290 let Namespace = "PPC";
3291 bit PPC64 = 0; // Default value, override with isPPC64
3293 let OutOperandList = (outs);
3294 let InOperandList = iops;
3296 let AsmString = asm;
3297 let isAsmParserOnly = 1;
3301 def : InstAlias<"sc", (SC 0)>;
3303 def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3304 def : InstAlias<"msync", (SYNC 0)>, Requires<[HasSYNC]>;
3305 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3306 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3308 def : InstAlias<"wait", (WAIT 0)>;
3309 def : InstAlias<"waitrsv", (WAIT 1)>;
3310 def : InstAlias<"waitimpl", (WAIT 2)>;
3312 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3314 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3315 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3316 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3317 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3319 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3320 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3322 def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3323 def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3325 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3326 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3328 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3329 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3331 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3332 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3334 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3335 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3337 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3338 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3340 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3341 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3343 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3344 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3346 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3347 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3349 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3350 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3352 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3353 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3355 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3356 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3358 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3359 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3361 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3362 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3363 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3365 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3366 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3368 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3369 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3370 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3371 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3373 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3375 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3376 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3378 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3379 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3381 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3383 foreach BATR = 0-3 in {
3384 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3385 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3386 Requires<[IsPPC6xx]>;
3387 def : InstAlias<"mfdbatu $Rx, "#BATR,
3388 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3389 Requires<[IsPPC6xx]>;
3390 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3391 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3392 Requires<[IsPPC6xx]>;
3393 def : InstAlias<"mfdbatl $Rx, "#BATR,
3394 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3395 Requires<[IsPPC6xx]>;
3396 def : InstAlias<"mtibatu "#BATR#", $Rx",
3397 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3398 Requires<[IsPPC6xx]>;
3399 def : InstAlias<"mfibatu $Rx, "#BATR,
3400 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3401 Requires<[IsPPC6xx]>;
3402 def : InstAlias<"mtibatl "#BATR#", $Rx",
3403 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3404 Requires<[IsPPC6xx]>;
3405 def : InstAlias<"mfibatl $Rx, "#BATR,
3406 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3407 Requires<[IsPPC6xx]>;
3410 foreach BR = 0-7 in {
3411 def : InstAlias<"mfbr"#BR#" $Rx",
3412 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3413 Requires<[IsPPC4xx]>;
3414 def : InstAlias<"mtbr"#BR#" $Rx",
3415 (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3416 Requires<[IsPPC4xx]>;
3419 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3420 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3422 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3423 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3425 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3426 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3428 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3429 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3431 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3432 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3434 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3435 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3437 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3439 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3440 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3441 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3442 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3443 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3444 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3445 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3446 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3448 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3449 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3450 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3451 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3453 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3454 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3456 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3457 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3459 foreach SPRG = 0-3 in {
3460 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3461 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3462 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3463 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3465 foreach SPRG = 4-7 in {
3466 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3467 Requires<[IsBookE]>;
3468 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3469 Requires<[IsBookE]>;
3470 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3471 Requires<[IsBookE]>;
3472 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3473 Requires<[IsBookE]>;
3476 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3478 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3479 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3481 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3483 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3484 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3486 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3487 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3488 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3489 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3491 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3493 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3494 Requires<[IsPPC4xx]>;
3495 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3496 Requires<[IsPPC4xx]>;
3497 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3498 Requires<[IsPPC4xx]>;
3499 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3500 Requires<[IsPPC4xx]>;
3502 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3503 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3504 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3505 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3506 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3507 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3508 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3509 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3510 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3511 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3512 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3513 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3514 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3515 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3516 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3517 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3518 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3519 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3520 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3521 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3522 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3523 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3524 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3525 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3526 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3527 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3528 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3529 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3530 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3531 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3532 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3533 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3534 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3535 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3536 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3537 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3539 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3540 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3541 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3542 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3543 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3544 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3546 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3547 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3548 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3549 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3550 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3551 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3552 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3553 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3554 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3555 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3556 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3557 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3558 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3559 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3560 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3561 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3562 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3563 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3564 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3565 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3566 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3567 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3568 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3569 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3570 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3571 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3572 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3573 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3574 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3575 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3576 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3577 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3579 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3580 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3581 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3582 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3583 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3584 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3586 // These generic branch instruction forms are used for the assembler parser only.
3587 // Defs and Uses are conservative, since we don't know the BO value.
3588 let PPC970_Unit = 7 in {
3589 let Defs = [CTR], Uses = [CTR, RM] in {
3590 def gBC : BForm_3<16, 0, 0, (outs),
3591 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3592 "bc $bo, $bi, $dst">;
3593 def gBCA : BForm_3<16, 1, 0, (outs),
3594 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3595 "bca $bo, $bi, $dst">;
3597 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3598 def gBCL : BForm_3<16, 0, 1, (outs),
3599 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3600 "bcl $bo, $bi, $dst">;
3601 def gBCLA : BForm_3<16, 1, 1, (outs),
3602 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3603 "bcla $bo, $bi, $dst">;
3605 let Defs = [CTR], Uses = [CTR, LR, RM] in
3606 def gBCLR : XLForm_2<19, 16, 0, (outs),
3607 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3608 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3609 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3610 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3611 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3612 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3613 let Defs = [CTR], Uses = [CTR, LR, RM] in
3614 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3615 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3616 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3617 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3618 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3619 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3620 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3622 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3623 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3624 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3625 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3627 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3628 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3629 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3630 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3631 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3632 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3633 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3635 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3636 : BranchSimpleMnemonic1<name, pm, bo> {
3637 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3638 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3640 defm : BranchSimpleMnemonic2<"t", "", 12>;
3641 defm : BranchSimpleMnemonic2<"f", "", 4>;
3642 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3643 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3644 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3645 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3646 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3647 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3648 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3649 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3651 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3652 def : InstAlias<"b"#name#pm#" $cc, $dst",
3653 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3654 def : InstAlias<"b"#name#pm#" $dst",
3655 (BCC bibo, CR0, condbrtarget:$dst)>;
3657 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3658 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3659 def : InstAlias<"b"#name#"a"#pm#" $dst",
3660 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3662 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3663 (BCCLR bibo, crrc:$cc)>;
3664 def : InstAlias<"b"#name#"lr"#pm,
3667 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3668 (BCCCTR bibo, crrc:$cc)>;
3669 def : InstAlias<"b"#name#"ctr"#pm,
3670 (BCCCTR bibo, CR0)>;
3672 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3673 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3674 def : InstAlias<"b"#name#"l"#pm#" $dst",
3675 (BCCL bibo, CR0, condbrtarget:$dst)>;
3677 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3678 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3679 def : InstAlias<"b"#name#"la"#pm#" $dst",
3680 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3682 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3683 (BCCLRL bibo, crrc:$cc)>;
3684 def : InstAlias<"b"#name#"lrl"#pm,
3685 (BCCLRL bibo, CR0)>;
3687 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3688 (BCCCTRL bibo, crrc:$cc)>;
3689 def : InstAlias<"b"#name#"ctrl"#pm,
3690 (BCCCTRL bibo, CR0)>;
3692 multiclass BranchExtendedMnemonic<string name, int bibo> {
3693 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3694 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3695 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3697 defm : BranchExtendedMnemonic<"lt", 12>;
3698 defm : BranchExtendedMnemonic<"gt", 44>;
3699 defm : BranchExtendedMnemonic<"eq", 76>;
3700 defm : BranchExtendedMnemonic<"un", 108>;
3701 defm : BranchExtendedMnemonic<"so", 108>;
3702 defm : BranchExtendedMnemonic<"ge", 4>;
3703 defm : BranchExtendedMnemonic<"nl", 4>;
3704 defm : BranchExtendedMnemonic<"le", 36>;
3705 defm : BranchExtendedMnemonic<"ng", 36>;
3706 defm : BranchExtendedMnemonic<"ne", 68>;
3707 defm : BranchExtendedMnemonic<"nu", 100>;
3708 defm : BranchExtendedMnemonic<"ns", 100>;
3710 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3711 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3712 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3713 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3714 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3715 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3716 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3717 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3719 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3720 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3721 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3722 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3723 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3724 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3725 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3726 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3728 multiclass TrapExtendedMnemonic<string name, int to> {
3729 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3730 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3731 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3732 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3734 defm : TrapExtendedMnemonic<"lt", 16>;
3735 defm : TrapExtendedMnemonic<"le", 20>;
3736 defm : TrapExtendedMnemonic<"eq", 4>;
3737 defm : TrapExtendedMnemonic<"ge", 12>;
3738 defm : TrapExtendedMnemonic<"gt", 8>;
3739 defm : TrapExtendedMnemonic<"nl", 12>;
3740 defm : TrapExtendedMnemonic<"ne", 24>;
3741 defm : TrapExtendedMnemonic<"ng", 20>;
3742 defm : TrapExtendedMnemonic<"llt", 2>;
3743 defm : TrapExtendedMnemonic<"lle", 6>;
3744 defm : TrapExtendedMnemonic<"lge", 5>;
3745 defm : TrapExtendedMnemonic<"lgt", 1>;
3746 defm : TrapExtendedMnemonic<"lnl", 5>;
3747 defm : TrapExtendedMnemonic<"lng", 6>;
3748 defm : TrapExtendedMnemonic<"u", 31>;
3751 def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>;
3752 def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>;
3753 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>;
3754 def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>;
3755 def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
3756 def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
3759 def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>;
3760 def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>;
3761 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>;
3762 def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
3763 def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
3764 def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;